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external_coex: add extern coex wire 4

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This commit is contained in:
muhaidong 2023-04-11 21:45:46 +08:00
parent ef805e64a2
commit 2c70cda9b6
4 changed files with 43 additions and 7 deletions
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2
components/esp_coex/Kconfig
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@ -17,7 +17,7 @@ menu "Wireless Coexistence"
config ESP_COEX_EXTERNAL_COEXIST_ENABLE
bool "External Coexistence"
default n
depends on (!(BT_ENABLED||NIMBLE_ENABLED)&&(!IDF_TARGET_ESP32))
depends on (!(BT_ENABLED||NIMBLE_ENABLED)&&(!IDF_TARGET_ESP32)&&(!IDF_TARGET_ESP32C6)) #JIRA FCC52
help
If enabled, HW External coexistence arbitration is managed by GPIO pins.
It can support three types of wired combinations so far which are 1-wired/2-wired/3-wired.

1
components/esp_coex/include/esp_coexist.h
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@ -28,6 +28,7 @@ typedef enum {
EXTERN_COEX_WIRE_1 = 0,
EXTERN_COEX_WIRE_2,
EXTERN_COEX_WIRE_3,
EXTERN_COEX_WIRE_4,
EXTERN_COEX_WIRE_NUM,
} external_coex_wire_t;

43
components/esp_coex/src/coexist.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -17,11 +17,11 @@
#include "soc/gpio_struct.h"
#include "esp_attr.h"
#ifdef CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/gpio.h"
#include "esp_rom/include/esp32s3/rom/gpio.h"
#endif
#endif
static const char* TAG = "coexist";
//static const char* TAG = "coexist";
const char *esp_coex_version_get(void)
{
@ -246,6 +246,41 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
switch (wire_type)
{
#ifndef SOC_EXTERNAL_COEX_ADVANCE
case EXTERN_COEX_WIRE_4:
{
/*Input gpio pin setup --> GPIO_BT_PRIORITY_IDX：GPIO_BT_ACTIVE_IDX*/
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.in_pin0], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.in_pin0, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(gpio_pin.in_pin0, GPIO_BT_ACTIVE_IDX, false);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.in_pin1], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.in_pin1, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(gpio_pin.in_pin1, GPIO_BT_PRIORITY_IDX, false);
/*Output gpio pin setup --> GPIO_WLAN_ACTIVE_IDX: 1 BT, 0 WiFi*/
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.out_pin0], PIN_FUNC_GPIO);
gpio_set_direction(gpio_pin.out_pin0, GPIO_MODE_OUTPUT);
REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.out_pin0));
esp_rom_gpio_connect_out_signal(gpio_pin.out_pin0, GPIO_WLAN_ACTIVE_IDX, false, false);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC1_BYPASS, 2);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC2_BYPASS, 2);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin1), GPIO_PIN1_SYNC1_BYPASS, 2);
REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin1), GPIO_PIN1_SYNC2_BYPASS, 2);
esp_extern_coex_register_txline(gpio_pin.out_pin1);
int ret = esp_coex_external_set(EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_HIGH);
if (ESP_OK != ret) {
return ESP_FAIL;
}
break;
}
#endif
case EXTERN_COEX_WIRE_3:
{
#if SOC_EXTERNAL_COEX_ADVANCE
@ -424,7 +459,7 @@ esp_err_t esp_extern_coex_register_txline(uint32_t pin)
ESP_LOGI(TAG, "external coex select output io %d as txline", esp_extern_coex_outpin);
gpio_matrix_out(esp_extern_coex_outpin, BB_DIAG9_IDX, false, false);
esp_rom_gpio_matrix_out(esp_extern_coex_outpin, BB_DIAG9_IDX, false, false);
return ESP_OK;
}

4
examples/wifi/iperf/main/cmd_wifi.c
View File

@ -182,8 +182,8 @@ void initialise_wifi(void)
gpio_pin.in_pin0 = 1;
gpio_pin.in_pin1 = 2;
gpio_pin.out_pin0 = 3;
ESP_ERROR_CHECK( esp_enable_extern_coex_gpio_pin(EXTERN_COEX_WIRE_3, gpio_pin) );
ESP_ERROR_CHECK( esp_extern_coex_register_txline(4) );
gpio_pin.out_pin1 = 4;
ESP_ERROR_CHECK( esp_enable_extern_coex_gpio_pin(EXTERN_COEX_WIRE_4, gpio_pin) );
#endif
#endif