change(fpga): added bypass rng configuration

components/esp_hw_support/Kconfig

@@ -341,6 +341,16 @@ menu "Hardware Settings"
             clock support isn't done yet. So with this option,
             we use xtal on FPGA as the clock source.
 
+    # Invisible bringup bypass options for esp_hw_support component
+    config ESP_BRINGUP_BYPASS_RANDOM_SETTING
+        bool
+        default y if !SOC_RNG_SUPPORTED
+        default n
+        help
+            This option is only used for new chip bringup, when
+            RNG isn't done yet. So with this option, we use 0x5A
+            to fill the random buffers
+
     config ESP_SPI_BUS_LOCK_ISR_FUNCS_IN_IRAM
         bool
         default n

components/esp_system/CMakeLists.txt

@@ -13,7 +13,11 @@ endif()
 set(srcs "esp_err.c")
 
 if(CONFIG_IDF_ENV_FPGA OR CONFIG_ESP_BRINGUP_BYPASS_CPU_CLK_SETTING)
-    list(APPEND srcs "fpga_overrides.c")
+    list(APPEND srcs "fpga_overrides_clk.c")
+endif()
+
+if(CONFIG_IDF_ENV_FPGA OR CONFIG_ESP_BRINGUP_BYPASS_RANDOM_SETTING)
+    list(APPEND srcs "fpga_overrides_rng.c")
 endif()
 
 if(BOOTLOADER_BUILD)
@@ -91,7 +95,12 @@ endif()
 
 if(CONFIG_IDF_ENV_FPGA OR CONFIG_ESP_BRINGUP_BYPASS_CPU_CLK_SETTING)
     # Forces the linker to include fpga stubs from this component
-    target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_common_include_fpga_overrides")
+    target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_common_include_fpga_overrides_clk")
+endif()
+
+if(CONFIG_IDF_ENV_FPGA OR CONFIG_ESP_BRINGUP_BYPASS_RANDOM_SETTING)
+    # Forces the linker to include fpga stubs from this component
+    target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_common_include_fpga_overrides_rng")
 endif()
 
 # Force linking UBSAN hooks. If UBSAN is not enabled, the hooks will ultimately be removed

components/esp_system/fpga_overrides_clk.c

@@ -31,13 +31,12 @@
 #include "esp_log.h"
 #include "esp_rom_sys.h"
 #include "esp_rom_uart.h"
-#include "esp_attr.h"
 
-static const char *TAG = "fpga";
+static const char *TAG = "fpga_clk";
 
 static void s_warn(void)
 {
-    ESP_EARLY_LOGW(TAG, "Project configuration is for internal FPGA use, not all functions will work");
+    ESP_EARLY_LOGE(TAG, "Project configuration is for internal FPGA use, clock functions will not work");
 }
 
 void bootloader_clock_configure(void)
@@ -58,15 +57,6 @@ void bootloader_clock_configure(void)
     REG_WRITE(RTC_XTAL_FREQ_REG, (xtal_freq_mhz) | ((xtal_freq_mhz) << 16));
 }
 
-/* Placed in IRAM since test_apps expects it to be */
-void IRAM_ATTR bootloader_fill_random(void *buffer, size_t length)
-{
-    uint8_t *buffer_bytes = (uint8_t *)buffer;
-    for (int i = 0; i < length; i++) {
-        buffer_bytes[i] = 0x5A;
-    }
-}
-
 void esp_clk_init(void)
 {
     s_warn();
@@ -83,6 +73,6 @@ void esp_perip_clk_init(void)
  * @brief No-op function, used to force linking this file
  *
  */
-void esp_common_include_fpga_overrides(void)
+void esp_common_include_fpga_overrides_clk(void)
 {
 }

components/esp_system/fpga_overrides_rng.c

@@ -0,0 +1,29 @@
+/*
+ * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stddef.h>
+#include "esp_log.h"
+#include "esp_attr.h"
+
+static const char *TAG = "fpga_rng";
+
+/* Placed in IRAM since test_apps expects it to be */
+void IRAM_ATTR bootloader_fill_random(void *buffer, size_t length)
+{
+    ESP_EARLY_LOGE(TAG, "Project configuration is for internal FPGA use, RNG will not work");
+
+    uint8_t *buffer_bytes = (uint8_t *)buffer;
+    for (int i = 0; i < length; i++) {
+        buffer_bytes[i] = 0x5A;
+    }
+}
+
+/**
+ * @brief No-op function, used to force linking this file
+ *
+ */
+void esp_common_include_fpga_overrides_rng(void)
+{
+}

components/soc/esp32/include/soc/Kconfig.soc_caps.in

@@ -167,6 +167,10 @@ config SOC_SPI_FLASH_SUPPORTED
     bool
     default y
 
+config SOC_RNG_SUPPORTED
+    bool
+    default y
+
 config SOC_DPORT_WORKAROUND_DIS_INTERRUPT_LVL
     int
     default 5

components/soc/esp32/include/soc/soc_caps.h

@@ -99,6 +99,7 @@
 #define SOC_MPU_SUPPORTED           1
 #define SOC_WDT_SUPPORTED           1
 #define SOC_SPI_FLASH_SUPPORTED     1
+#define SOC_RNG_SUPPORTED           1
 
 #if SOC_CAPS_ECO_VER < 200
 #define SOC_DPORT_WORKAROUND                   1

components/soc/esp32c2/include/soc/Kconfig.soc_caps.in

@@ -111,6 +111,10 @@ config SOC_SPI_FLASH_SUPPORTED
     bool
     default y
 
+config SOC_RNG_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_26M
     bool
     default y

components/soc/esp32c2/include/soc/soc_caps.h

@@ -49,6 +49,7 @@
 #define SOC_ASSIST_DEBUG_SUPPORTED      1
 #define SOC_WDT_SUPPORTED               1
 #define SOC_SPI_FLASH_SUPPORTED         1
+#define SOC_RNG_SUPPORTED               1
 
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_26M            1

components/soc/esp32c3/include/soc/Kconfig.soc_caps.in

@@ -163,6 +163,10 @@ config SOC_SPI_FLASH_SUPPORTED
     bool
     default y
 
+config SOC_RNG_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_40M
     bool
     default y

components/soc/esp32c3/include/soc/soc_caps.h

@@ -65,6 +65,7 @@
 #define SOC_ASSIST_DEBUG_SUPPORTED      1
 #define SOC_WDT_SUPPORTED               1
 #define SOC_SPI_FLASH_SUPPORTED         1
+#define SOC_RNG_SUPPORTED               1
 
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -219,6 +219,10 @@ config SOC_SPI_FLASH_SUPPORTED
     bool
     default y
 
+config SOC_RNG_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_40M
     bool
     default y

components/soc/esp32c6/include/soc/soc_caps.h

@@ -76,6 +76,7 @@
 #define SOC_ASSIST_DEBUG_SUPPORTED      1
 #define SOC_WDT_SUPPORTED               1
 #define SOC_SPI_FLASH_SUPPORTED         1
+#define SOC_RNG_SUPPORTED               1
 
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -203,6 +203,10 @@ config SOC_SPI_FLASH_SUPPORTED
     bool
     default y
 
+config SOC_RNG_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_32M
     bool
     default y

components/soc/esp32h2/include/soc/soc_caps.h

@@ -73,6 +73,7 @@
 #define SOC_ASSIST_DEBUG_SUPPORTED      1
 #define SOC_WDT_SUPPORTED               1
 #define SOC_SPI_FLASH_SUPPORTED         1
+#define SOC_RNG_SUPPORTED               1
 
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_32M            1

components/soc/esp32p4/include/soc/soc_caps.h

@@ -82,6 +82,7 @@
 #define SOC_WDT_SUPPORTED               1
 #define SOC_SPI_FLASH_SUPPORTED         1
 // #define SOC_TOUCH_SENSOR_SUPPORTED      1  //TODO: IDF-7477
+// #define SOC_RNG_SUPPORTED               1  //TODO: IDF-6522
 
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1

components/soc/esp32s2/include/soc/Kconfig.soc_caps.in

@@ -191,6 +191,10 @@ config SOC_SPI_FLASH_SUPPORTED
     bool
     default y
 
+config SOC_RNG_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_40M
     bool
     default y

components/soc/esp32s2/include/soc/soc_caps.h

@@ -84,6 +84,7 @@
 #define SOC_MPU_SUPPORTED               1
 #define SOC_WDT_SUPPORTED               1
 #define SOC_SPI_FLASH_SUPPORTED         1
+#define SOC_RNG_SUPPORTED               1
 
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1

components/soc/esp32s3/include/soc/Kconfig.soc_caps.in

@@ -231,6 +231,10 @@ config SOC_SPI_FLASH_SUPPORTED
     bool
     default y
 
+config SOC_RNG_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_40M
     bool
     default y

components/soc/esp32s3/include/soc/soc_caps.h

@@ -74,6 +74,7 @@
 #define SOC_MPU_SUPPORTED               1
 #define SOC_WDT_SUPPORTED               1
 #define SOC_SPI_FLASH_SUPPORTED         1
+#define SOC_RNG_SUPPORTED               1
 
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1