diff --git a/components/driver/spi_master.c b/components/driver/spi_master.c
index ed4cba4108..411ae39e10 100644
--- a/components/driver/spi_master.c
+++ b/components/driver/spi_master.c
@@ -120,6 +120,7 @@ We have two bits to control the interrupt:
 #include "soc/soc_memory_layout.h"
 #include "driver/gpio.h"
 #include "hal/spi_hal.h"
+#include "hal/spi_ll.h"
 #include "esp_heap_caps.h"
 //Temporarily include esp_clk.h, will be replaced by clock tree API
 #include "esp_private/esp_clk.h"
@@ -725,6 +726,14 @@ static SPI_MASTER_ISR_ATTR esp_err_t check_trans_valid(spi_device_handle_t handl
     //Dummy phase is not available when both data out and in are enabled, regardless of FD or HD mode.
     SPI_CHECK(!tx_enabled || !rx_enabled || !dummy_enabled || !extra_dummy_enabled, "Dummy phase is not available when both data out and in are enabled", ESP_ERR_INVALID_ARG);
 
+    if (bus_attr->dma_enabled) {
+        SPI_CHECK(trans_desc->length <= SPI_LL_DMA_MAX_BIT_LEN, "txdata transfer > hardware max supported len", ESP_ERR_INVALID_ARG);
+        SPI_CHECK(trans_desc->rxlength <= SPI_LL_DMA_MAX_BIT_LEN, "rxdata transfer > hardware max supported len", ESP_ERR_INVALID_ARG);
+    } else {
+        SPI_CHECK(trans_desc->length <= SPI_LL_CPU_MAX_BIT_LEN, "txdata transfer > hardware max supported len", ESP_ERR_INVALID_ARG);
+        SPI_CHECK(trans_desc->rxlength <= SPI_LL_CPU_MAX_BIT_LEN, "rxdata transfer > hardware max supported len", ESP_ERR_INVALID_ARG);
+    }
+
     return ESP_OK;
 }
 
diff --git a/components/hal/esp32/include/hal/spi_ll.h b/components/hal/esp32/include/hal/spi_ll.h
index cf09b6e94f..77caebea37 100644
--- a/components/hal/esp32/include/hal/spi_ll.h
+++ b/components/hal/esp32/include/hal/spi_ll.h
@@ -41,7 +41,8 @@ extern "C" {
 #define SPI_LL_PERIPH_CLK_FREQ (80 * 1000000)
 #define SPI_LL_GET_HW(ID) ((ID)==0? &SPI1:((ID)==1? &SPI2 : &SPI3))
 
-#define SPI_LL_DATA_MAX_BIT_LEN (1 << 24)
+#define SPI_LL_DMA_MAX_BIT_LEN    (1 << 24)    //reg len: 24 bits
+#define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 
 /**
  * The data structure holding calculated clock configuration. Since the
diff --git a/components/hal/esp32c2/include/hal/spi_ll.h b/components/hal/esp32c2/include/hal/spi_ll.h
index ca67e3960a..657625080a 100644
--- a/components/hal/esp32c2/include/hal/spi_ll.h
+++ b/components/hal/esp32c2/include/hal/spi_ll.h
@@ -40,7 +40,8 @@ extern "C" {
 #define SPI_LL_PERIPH_CLK_FREQ (80 * 1000000)
 #define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):&GPSPI2)
 
-#define SPI_LL_DATA_MAX_BIT_LEN (1 << 18)
+#define SPI_LL_DMA_MAX_BIT_LEN    (1 << 18)    //reg len: 18 bits
+#define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 
 /**
  * The data structure holding calculated clock configuration. Since the
diff --git a/components/hal/esp32c3/include/hal/spi_ll.h b/components/hal/esp32c3/include/hal/spi_ll.h
index 78b58de6c4..03f52b56cd 100644
--- a/components/hal/esp32c3/include/hal/spi_ll.h
+++ b/components/hal/esp32c3/include/hal/spi_ll.h
@@ -40,7 +40,8 @@ extern "C" {
 #define SPI_LL_PERIPH_CLK_FREQ (80 * 1000000)
 #define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):&GPSPI2)
 
-#define SPI_LL_DATA_MAX_BIT_LEN (1 << 18)
+#define SPI_LL_DMA_MAX_BIT_LEN    (1 << 18)    //reg len: 18 bits
+#define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 
 /**
  * The data structure holding calculated clock configuration. Since the
diff --git a/components/hal/esp32h2/include/hal/spi_ll.h b/components/hal/esp32h2/include/hal/spi_ll.h
index 2881407dd9..9606c4adaf 100644
--- a/components/hal/esp32h2/include/hal/spi_ll.h
+++ b/components/hal/esp32h2/include/hal/spi_ll.h
@@ -40,7 +40,8 @@ extern "C" {
 #define SPI_LL_PERIPH_CLK_FREQ (80 * 1000000)
 #define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):&GPSPI2)
 
-#define SPI_LL_DATA_MAX_BIT_LEN (1 << 18)
+#define SPI_LL_DMA_MAX_BIT_LEN    (1 << 18)    //reg len: 18 bits
+#define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 
 /**
  * The data structure holding calculated clock configuration. Since the
diff --git a/components/hal/esp32s2/include/hal/spi_ll.h b/components/hal/esp32s2/include/hal/spi_ll.h
index 65084c8d23..0220d3c7eb 100644
--- a/components/hal/esp32s2/include/hal/spi_ll.h
+++ b/components/hal/esp32s2/include/hal/spi_ll.h
@@ -43,7 +43,8 @@ extern "C" {
 #define SPI_LL_PERIPH_CLK_FREQ (80 * 1000000)
 #define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):((ID)==1? &GPSPI2 : &GPSPI3))
 
-#define SPI_LL_DATA_MAX_BIT_LEN (1 << 23)
+#define SPI_LL_DMA_MAX_BIT_LEN    (1 << 23)    //reg len: 23 bits
+#define SPI_LL_CPU_MAX_BIT_LEN    (18 * 32)    //Fifo len: 18 words
 
 /**
  * The data structure holding calculated clock configuration. Since the
diff --git a/components/hal/esp32s3/include/hal/spi_ll.h b/components/hal/esp32s3/include/hal/spi_ll.h
index e210a76f8e..c45f370bf5 100644
--- a/components/hal/esp32s3/include/hal/spi_ll.h
+++ b/components/hal/esp32s3/include/hal/spi_ll.h
@@ -42,7 +42,8 @@ extern "C" {
 #define SPI_LL_PERIPH_CLK_FREQ (80 * 1000000)
 #define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):((ID)==1? &GPSPI2 : &GPSPI3))
 
-#define SPI_LL_DATA_MAX_BIT_LEN (1 << 18)
+#define SPI_LL_DMA_MAX_BIT_LEN    (1 << 18)    //reg len: 18 bits
+#define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 
 /**
  * The data structure holding calculated clock configuration. Since the