Merge branch 'feat/bss_in_psram_p4' into 'master'

psram: bss in psram p4

Closes IDF-7557

See merge request espressif/esp-idf!32018

components/esp_common/test_apps/.build-test-rules.yml

@@ -3,6 +3,6 @@
 components/esp_common/test_apps/esp_common:
   disable:
     - if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1
-    - if: CONFIG_NAME == "psram" and IDF_TARGET in ["esp32p4", "esp32c5"]
+    - if: CONFIG_NAME == "psram" and IDF_TARGET in ["esp32c5"]
       temporary: true
-      reason: esp32p4/c5 is not supported yet # TODO: IDF-7557
+      reason: esp32c5 is not supported yet # TODO: IDF-8689

components/esp_common/test_apps/esp_common/pytest_esp_common.py

@@ -1,6 +1,5 @@
-# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: CC0-1.0
-
 import pytest
 from pytest_embedded import Dut
 
@@ -51,6 +50,7 @@ def run_multiple_stages(dut: Dut, test_case_num: int, stages: int) -> None:
 @pytest.mark.esp32
 @pytest.mark.esp32s2
 @pytest.mark.esp32s3
+@pytest.mark.esp32p4
 @pytest.mark.generic
 @pytest.mark.parametrize(
     'config',
@@ -89,3 +89,17 @@ def test_esp_attr_xip_psram_esp32s2(dut: Dut) -> None:
 )
 def test_esp_attr_xip_psram_esp32s3(dut: Dut) -> None:
     dut.run_all_single_board_cases()
+
+
+# psram attr tests with xip_psram
+@pytest.mark.esp32p4
+@pytest.mark.generic
+@pytest.mark.parametrize(
+    'config',
+    [
+        'xip_psram_esp32p4'
+    ],
+    indirect=True,
+)
+def test_esp_attr_xip_psram_esp32p4(dut: Dut) -> None:
+    dut.run_all_single_board_cases()

components/esp_common/test_apps/esp_common/sdkconfig.xip_psram_esp32p4

@@ -0,0 +1,6 @@
+# For XiP PSRAM EXT_RAM_BSS_ATTR
+
+CONFIG_IDF_TARGET="esp32p4"
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_XIP_FROM_PSRAM=y
+CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y

components/esp_psram/esp_psram.c

@@ -11,6 +11,7 @@
  * When we add more types of external RAM memory, this can be made into a more intelligent dispatcher.
  *----------------------------------------------------------------------------------------------------*/
 #include <sys/param.h>
+#include <string.h>
 #include "sdkconfig.h"
 #include "esp_attr.h"
 #include "esp_err.h"
@@ -521,3 +522,11 @@ bool esp_psram_extram_test(void)
 
     return true;
 }
+
+void esp_psram_bss_init(void)
+{
+#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
+    size_t size = (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start);
+    memset(&_ext_ram_bss_start, 0, size);
+#endif
+}

components/esp_psram/include/esp_private/esp_psram_extram.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -55,6 +55,11 @@ esp_err_t esp_psram_extram_reserve_dma_pool(size_t size);
  */
 bool esp_psram_extram_test(void);
 
+/**
+ * @brief Init .bss on psram
+ */
+void esp_psram_bss_init(void);
+
 #if CONFIG_IDF_TARGET_ESP32
 /**
  * @brief Force a writeback of the data in the PSRAM cache. This is to be called whenever

components/esp_system/ld/esp32p4/memory.ld.in

@@ -103,6 +103,9 @@ MEMORY
      This segment is placed at the beginning of LP RAM, as the end of LP RAM is occupied by LP ROM stack/data
   */
   lp_reserved_seg(RW) :        org = 0x50108000, len = RESERVE_RTC_MEM
+
+  /* PSRAM seg */
+  extern_ram_seg(RWX) :        org = 0x48000000, len = IDROM_SEG_SIZE
 }
 
 /* Heap ends at top of dram0_0_seg */
@@ -135,6 +138,12 @@ REGION_ALIAS("rtc_reserved_seg", lp_reserved_seg );
   REGION_ALIAS("rodata_seg_high", sram_high);
 #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
 
+#if CONFIG_SPIRAM_XIP_FROM_PSRAM
+  REGION_ALIAS("ext_ram_seg", drom_seg);
+#else
+  REGION_ALIAS("ext_ram_seg", extern_ram_seg);
+#endif //#if CONFIG_SPIRAM_XIP_FROM_PSRAM
+
 /**
  *  If rodata default segment is placed in `drom_seg`, then flash's first rodata section must
  *  also be first in the segment.

components/esp_system/ld/esp32p4/sections.ld.in

@@ -475,6 +475,28 @@ SECTIONS
     mapping[rodata_noload]
   } > rodata_seg_low
 
+#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
+#if CONFIG_SPIRAM_XIP_FROM_PSRAM
+  /**
+   * This section is required to skip flash sections, because `extern_ram_seg`
+   * and `drom_seg` / `irom_seg` are on the same bus when xip on psram
+   */
+  .ext_ram.dummy (NOLOAD):
+  {
+    . = ORIGIN(ext_ram_seg) + (_rodata_reserved_end - _flash_rodata_dummy_start);
+    . = ALIGN (0x10000);
+  } > ext_ram_seg
+#endif  //CONFIG_SPIRAM_XIP_FROM_PSRAM
+
+  /* This section holds .ext_ram.bss data, and will be put in PSRAM */
+  .ext_ram.bss (NOLOAD) :
+  {
+    _ext_ram_bss_start = ABSOLUTE(.);
+    mapping[extern_ram]
+    ALIGNED_SYMBOL(4, _ext_ram_bss_end)
+  } > ext_ram_seg
+#endif  //CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
+
   .dram0.bss (NOLOAD) :
   {
     ALIGNED_SYMBOL(4, _bss_start_low)

components/esp_system/port/cpu_start.c

@@ -148,11 +148,6 @@ extern int _mtvt_table;
 
 static const char *TAG = "cpu_start";
 
-#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
-extern int _ext_ram_bss_start;
-extern int _ext_ram_bss_end;
-#endif
-
 #ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
 extern int _iram_bss_start;
 extern int _iram_bss_end;
@@ -683,7 +678,7 @@ void IRAM_ATTR call_start_cpu0(void)
 #endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
 
 #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
-    memset(&_ext_ram_bss_start, 0, (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start));
+    esp_psram_bss_init();
 #endif
 
 //Enable trace memory and immediately start trace.