From 29accf2533fa7f1c0ed8d3d60d93e80bbbb04202 Mon Sep 17 00:00:00 2001 From: SalimTerryLi Date: Fri, 8 Oct 2021 11:10:55 +0800 Subject: [PATCH] soc/ll: workaround compiler bug that generate 8/16 bits inst instead of 32 bits one Note: on ESP32 UART rxfifo seems to be read as u8 instead of u32 to make it work --- .gitignore | 3 + components/hal/esp32/include/hal/adc_ll.h | 32 +- components/hal/esp32/include/hal/dac_ll.h | 9 +- components/hal/esp32/include/hal/gpio_ll.h | 16 +- components/hal/esp32/include/hal/i2c_ll.h | 4 +- components/hal/esp32/include/hal/i2s_ll.h | 4 +- components/hal/esp32/include/hal/ledc_ll.h | 2 + components/hal/esp32/include/hal/mcpwm_ll.h | 4 +- components/hal/esp32/include/hal/mwdt_ll.h | 4 +- components/hal/esp32/include/hal/pcnt_ll.h | 2 + components/hal/esp32/include/hal/rmt_ll.h | 1 + components/hal/esp32/include/hal/rtc_io_ll.h | 1 + components/hal/esp32/include/hal/rwdt_ll.h | 1 + .../hal/esp32/include/hal/sigmadelta_ll.h | 1 + .../hal/esp32/include/hal/spi_flash_ll.h | 4 +- components/hal/esp32/include/hal/spi_ll.h | 8 +- components/hal/esp32/include/hal/timer_ll.h | 1 + .../hal/esp32/include/hal/touch_sensor_ll.h | 14 +- components/hal/esp32/include/hal/twai_ll.h | 8 +- components/hal/esp32/include/hal/uart_ll.h | 26 +- components/hal/esp32c3/include/hal/adc_ll.h | 15 +- components/hal/esp32c3/include/hal/gpio_ll.h | 1 + .../hal/esp32c3/include/hal/gpspi_flash_ll.h | 4 +- components/hal/esp32c3/include/hal/i2c_ll.h | 6 +- components/hal/esp32c3/include/hal/i2s_ll.h | 2 + components/hal/esp32c3/include/hal/ledc_ll.h | 1 + components/hal/esp32c3/include/hal/mwdt_ll.h | 4 +- components/hal/esp32c3/include/hal/rmt_ll.h | 3 +- components/hal/esp32c3/include/hal/rwdt_ll.h | 4 +- .../hal/esp32c3/include/hal/sigmadelta_ll.h | 1 + .../hal/esp32c3/include/hal/spi_flash_ll.h | 1 + components/hal/esp32c3/include/hal/spi_ll.h | 7 +- .../hal/esp32c3/include/hal/spimem_flash_ll.h | 12 +- components/hal/esp32c3/include/hal/timer_ll.h | 1 + components/hal/esp32c3/include/hal/twai_ll.h | 14 +- components/hal/esp32c3/include/hal/uart_ll.h | 26 +- components/hal/esp32s2/include/hal/adc_ll.h | 30 +- components/hal/esp32s2/include/hal/dac_ll.h | 9 +- .../hal/esp32s2/include/hal/dedic_gpio_ll.h | 5 +- components/hal/esp32s2/include/hal/gpio_ll.h | 2 + .../hal/esp32s2/include/hal/gpspi_flash_ll.h | 4 +- components/hal/esp32s2/include/hal/i2c_ll.h | 1 + components/hal/esp32s2/include/hal/i2s_ll.h | 4 +- components/hal/esp32s2/include/hal/ledc_ll.h | 1 + components/hal/esp32s2/include/hal/mwdt_ll.h | 4 +- components/hal/esp32s2/include/hal/pcnt_ll.h | 1 + .../hal/esp32s2/include/hal/rtc_io_ll.h | 2 + components/hal/esp32s2/include/hal/rwdt_ll.h | 4 +- .../hal/esp32s2/include/hal/sigmadelta_ll.h | 1 + .../hal/esp32s2/include/hal/spi_flash_ll.h | 1 + components/hal/esp32s2/include/hal/spi_ll.h | 21 +- .../hal/esp32s2/include/hal/spimem_flash_ll.h | 10 +- components/hal/esp32s2/include/hal/timer_ll.h | 1 + .../hal/esp32s2/include/hal/touch_sensor_ll.h | 26 +- components/hal/esp32s2/include/hal/twai_ll.h | 14 +- components/hal/esp32s2/include/hal/uart_ll.h | 22 +- components/hal/esp32s2/include/hal/usb_ll.h | 1 + components/hal/esp32s2/include/hal/usbh_ll.h | 11 +- components/hal/include/hal/hal_defs.h | 41 ++ .../soc/esp32/include/soc/emac_dma_struct.h | 2 +- .../soc/esp32/include/soc/emac_ext_struct.h | 2 +- .../soc/esp32/include/soc/emac_mac_struct.h | 2 +- components/soc/esp32/include/soc/i2c_struct.h | 4 +- .../soc/esp32/include/soc/pcnt_struct.h | 2 +- components/soc/esp32/include/soc/rmt_struct.h | 6 +- .../soc/esp32/include/soc/sdmmc_struct.h | 37 +- .../esp32/include/soc/timer_group_struct.h | 2 +- .../soc/esp32/include/soc/twai_struct.h | 2 +- .../soc/esp32/include/soc/uart_struct.h | 3 +- .../soc/esp32/include/soc/uhci_struct.h | 2 +- .../soc/esp32c3/include/soc/apb_ctrl_struct.h | 2 +- .../esp32c3/include/soc/apb_saradc_struct.h | 2 +- .../soc/esp32c3/include/soc/efuse_struct.h | 2 +- .../soc/esp32c3/include/soc/gdma_struct.h | 2 +- .../soc/esp32c3/include/soc/gpio_sd_struct.h | 2 +- .../soc/esp32c3/include/soc/gpio_struct.h | 2 +- .../soc/esp32c3/include/soc/i2c_struct.h | 2 +- .../soc/esp32c3/include/soc/i2s_struct.h | 2 +- .../soc/esp32c3/include/soc/ledc_struct.h | 2 +- .../soc/esp32c3/include/soc/rmt_struct.h | 8 +- .../soc/esp32c3/include/soc/rtc_cntl_struct.h | 2 +- .../soc/esp32c3/include/soc/rtc_i2c_struct.h | 2 +- .../esp32c3/include/soc/sensitive_struct.h | 5 +- .../soc/esp32c3/include/soc/spi_mem_struct.h | 2 +- .../soc/esp32c3/include/soc/spi_struct.h | 2 +- .../soc/esp32c3/include/soc/syscon_struct.h | 2 +- .../soc/esp32c3/include/soc/system_struct.h | 2 +- .../soc/esp32c3/include/soc/systimer_struct.h | 2 +- .../esp32c3/include/soc/timer_group_struct.h | 2 +- .../soc/esp32c3/include/soc/twai_struct.h | 2 +- .../soc/esp32c3/include/soc/uart_struct.h | 2 +- .../soc/esp32c3/include/soc/uhci_struct.h | 2 +- .../soc/esp32s2/include/soc/apb_ctrl_struct.h | 2 +- .../esp32s2/include/soc/apb_saradc_struct.h | 2 +- .../soc/esp32s2/include/soc/cp_dma_struct.h | 6 + .../esp32s2/include/soc/dedic_gpio_struct.h | 12 + .../soc/esp32s2/include/soc/efuse_struct.h | 2 +- .../soc/esp32s2/include/soc/gpio_sd_struct.h | 2 +- .../soc/esp32s2/include/soc/gpio_struct.h | 2 +- .../soc/esp32s2/include/soc/i2c_struct.h | 2 +- .../soc/esp32s2/include/soc/i2s_struct.h | 2 +- .../soc/esp32s2/include/soc/ledc_struct.h | 2 +- .../soc/esp32s2/include/soc/pcnt_struct.h | 2 +- .../soc/esp32s2/include/soc/rmt_struct.h | 19 +- .../soc/esp32s2/include/soc/rtc_cntl_struct.h | 2 +- .../soc/esp32s2/include/soc/rtc_i2c_struct.h | 2 +- .../soc/esp32s2/include/soc/rtc_io_struct.h | 2 +- .../soc/esp32s2/include/soc/sdmmc_struct.h | 377 ------------------ .../soc/esp32s2/include/soc/sens_struct.h | 2 +- .../soc/esp32s2/include/soc/syscon_struct.h | 2 +- .../esp32s2/include/soc/timer_group_struct.h | 2 +- .../soc/esp32s2/include/soc/twai_struct.h | 2 +- .../soc/esp32s2/include/soc/uart_struct.h | 2 +- .../soc/esp32s2/include/soc/uhci_struct.h | 2 +- .../soc/esp32s2/include/soc/usb_wrap_struct.h | 1 + .../soc/esp32s2/include/soc/usbh_struct.h | 2 +- 116 files changed, 403 insertions(+), 630 deletions(-) delete mode 100644 components/soc/esp32s2/include/soc/sdmmc_struct.h diff --git a/.gitignore b/.gitignore index 61e02dae70..38ebd38bef 100644 --- a/.gitignore +++ b/.gitignore @@ -88,3 +88,6 @@ build # lock files for examples and components dependencies.lock + +# managed_components for examples +managed_components diff --git a/components/hal/esp32/include/hal/adc_ll.h b/components/hal/esp32/include/hal/adc_ll.h index 587d7e7a34..4b43e48374 100644 --- a/components/hal/esp32/include/hal/adc_ll.h +++ b/components/hal/esp32/include/hal/adc_ll.h @@ -3,6 +3,10 @@ #include "soc/adc_periph.h" #include "hal/adc_types.h" #include "soc/rtc_io_struct.h" +#include "soc/syscon_struct.h" +#include "soc/sens_struct.h" +#include "soc/rtc_cntl_struct.h" +#include "hal/hal_defs.h" #include #ifdef __cplusplus @@ -52,11 +56,11 @@ typedef enum { static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait) { // Internal FSM reset wait time - SYSCON.saradc_fsm.rstb_wait = rst_wait; + HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, rstb_wait, rst_wait); // Internal FSM start wait time - SYSCON.saradc_fsm.start_wait = start_wait; + HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, start_wait, start_wait); // Internal FSM standby wait time - SYSCON.saradc_fsm.standby_wait = standby_wait; + HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, standby_wait, standby_wait); } /** @@ -67,7 +71,7 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa */ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle) { - SYSCON.saradc_fsm.sample_cycle = sample_cycle; + HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, sample_cycle, sample_cycle); } /** @@ -78,7 +82,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle) static inline void adc_ll_digi_set_clk_div(uint32_t div) { /* ADC clock divided from APB clk, e.g. 80 / 2 = 40Mhz, */ - SYSCON.saradc_ctrl.sar_clk_div = div; + HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_ctrl, sar_clk_div, div); } /** @@ -99,7 +103,7 @@ static inline void adc_ll_digi_set_output_format(adc_digi_output_format_t format */ static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num) { - SYSCON.saradc_ctrl2.max_meas_num = meas_num; + HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_ctrl2, max_meas_num, meas_num); } /** @@ -320,7 +324,7 @@ static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n) static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel) { if (adc_n == ADC_NUM_1) { - while (SENS.sar_slave_addr1.meas_status != 0); + while (HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_slave_addr1, meas_status) != 0) {} SENS.sar_meas_start1.meas1_start_sar = 0; SENS.sar_meas_start1.meas1_start_sar = 1; } else { // adc_n == ADC_NUM_2 @@ -359,9 +363,9 @@ static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n) { int ret_val = 0; if (adc_n == ADC_NUM_1) { - ret_val = SENS.sar_meas_start1.meas1_data_sar; + ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas_start1, meas1_data_sar); } else { // adc_n == ADC_NUM_2 - ret_val = SENS.sar_meas_start2.meas2_data_sar; + ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas_start2, meas2_data_sar); } return ret_val; } @@ -444,9 +448,9 @@ static inline adc_ll_power_t adc_ll_get_power_manage(void) static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div) { if (adc_n == ADC_NUM_1) { - SENS.sar_read_ctrl.sar1_clk_div = div; + HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl, sar1_clk_div, div); } else { // adc_n == ADC_NUM_2 - SENS.sar_read_ctrl2.sar2_clk_div = div; + HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl2, sar2_clk_div, div); } } @@ -563,9 +567,9 @@ static inline void adc_ll_amp_disable(void) SENS.sar_meas_ctrl.amp_rst_fb_fsm = 0; SENS.sar_meas_ctrl.amp_short_ref_fsm = 0; SENS.sar_meas_ctrl.amp_short_ref_gnd_fsm = 0; - SENS.sar_meas_wait1.sar_amp_wait1 = 1; - SENS.sar_meas_wait1.sar_amp_wait2 = 1; - SENS.sar_meas_wait2.sar_amp_wait3 = 1; + HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_meas_wait1, sar_amp_wait1, 1); + HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_meas_wait1, sar_amp_wait2, 1); + HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_meas_wait2, sar_amp_wait3, 1); } /*--------------------------------------------------------------- diff --git a/components/hal/esp32/include/hal/dac_ll.h b/components/hal/esp32/include/hal/dac_ll.h index 5ea4da8978..7eb4955705 100644 --- a/components/hal/esp32/include/hal/dac_ll.h +++ b/components/hal/esp32/include/hal/dac_ll.h @@ -22,7 +22,10 @@ #include #include "soc/dac_periph.h" +#include "soc/rtc_io_struct.h" +#include "soc/sens_struct.h" #include "hal/dac_types.h" +#include "hal/hal_defs.h" #ifdef __cplusplus extern "C" { @@ -124,7 +127,7 @@ static inline void dac_ll_cw_set_channel(dac_channel_t channel, bool enable) static inline void dac_ll_cw_set_freq(uint32_t freq) { uint32_t sw_freq = freq * 0xFFFF / RTC_FAST_CLK_FREQ_APPROX; - SENS.sar_dac_ctrl1.sw_fstep = (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq; + HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl1, sw_fstep, (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq); } /** @@ -171,12 +174,12 @@ static inline void dac_ll_cw_set_dc_offset(dac_channel_t channel, int8_t offset) if (SENS.sar_dac_ctrl2.dac_inv1 == DAC_CW_PHASE_180) { offset = 0 - offset; } - SENS.sar_dac_ctrl2.dac_dc1 = offset ? offset : (-128 - offset); + HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc1, offset ? offset : (-128 - offset)); } else if (channel == DAC_CHANNEL_2) { if (SENS.sar_dac_ctrl2.dac_inv2 == DAC_CW_PHASE_180) { offset = 0 - offset; } - SENS.sar_dac_ctrl2.dac_dc2 = offset ? offset : (-128 - offset); + HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc2, offset ? offset : (-128 - offset)); } } diff --git a/components/hal/esp32/include/hal/gpio_ll.h b/components/hal/esp32/include/hal/gpio_ll.h index 8c1acb3a1c..2d3cee2763 100644 --- a/components/hal/esp32/include/hal/gpio_ll.h +++ b/components/hal/esp32/include/hal/gpio_ll.h @@ -27,7 +27,9 @@ #include "soc/gpio_periph.h" #include "soc/rtc_cntl_reg.h" #include "soc/rtc_io_reg.h" +#include "soc/gpio_struct.h" #include "hal/gpio_types.h" +#include "hal/hal_defs.h" #ifdef __cplusplus extern "C" { @@ -245,7 +247,7 @@ static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uin */ static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) { - *status = (core_id == 0) ? hw->pcpu_int1.intr : hw->acpu_int1.intr; + *status = (core_id == 0) ? HAL_FORCE_READ_U32_REG_FIELD(hw->pcpu_int1, intr) : HAL_FORCE_READ_U32_REG_FIELD(hw->acpu_int1, intr); } /** @@ -267,7 +269,7 @@ static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask) */ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask) { - hw->status1_w1tc.intr_st = mask; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->status1_w1tc, intr_st, mask); } /** @@ -330,7 +332,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num) if (gpio_num < 32) { hw->enable_w1tc = (0x1 << gpio_num); } else { - hw->enable1_w1tc.data = (0x1 << (gpio_num - 32)); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->enable1_w1tc, data, (0x1 << (gpio_num - 32))); } // Ensure no other output signal is routed via GPIO matrix to this pin @@ -349,7 +351,7 @@ static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) if (gpio_num < 32) { hw->enable_w1ts = (0x1 << gpio_num); } else { - hw->enable1_w1ts.data = (0x1 << (gpio_num - 32)); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->enable1_w1ts, data, (0x1 << (gpio_num - 32))); } } @@ -432,13 +434,13 @@ static inline void gpio_ll_set_level(gpio_dev_t *hw, gpio_num_t gpio_num, uint32 if (gpio_num < 32) { hw->out_w1ts = (1 << gpio_num); } else { - hw->out1_w1ts.data = (1 << (gpio_num - 32)); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->out1_w1ts, data, (1 << (gpio_num - 32))); } } else { if (gpio_num < 32) { hw->out_w1tc = (1 << gpio_num); } else { - hw->out1_w1tc.data = (1 << (gpio_num - 32)); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->out1_w1tc, data, (1 << (gpio_num - 32))); } } } @@ -460,7 +462,7 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num) if (gpio_num < 32) { return (hw->in >> gpio_num) & 0x1; } else { - return (hw->in1.data >> (gpio_num - 32)) & 0x1; + return (HAL_FORCE_READ_U32_REG_FIELD(hw->in1, data) >> (gpio_num - 32)) & 0x1; } } diff --git a/components/hal/esp32/include/hal/i2c_ll.h b/components/hal/esp32/include/hal/i2c_ll.h index 557b563b07..fdac702f67 100644 --- a/components/hal/esp32/include/hal/i2c_ll.h +++ b/components/hal/esp32/include/hal/i2c_ll.h @@ -16,7 +16,9 @@ #pragma once #include "soc/i2c_periph.h" +#include "soc/i2c_struct.h" #include "hal/i2c_types.h" +#include "hal/hal_defs.h" #ifdef __cplusplus extern "C" { @@ -555,7 +557,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) { for(int i = 0; i < len; i++) { - ptr[i] = hw->fifo_data.data; + ptr[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->fifo_data, data); } } diff --git a/components/hal/esp32/include/hal/i2s_ll.h b/components/hal/esp32/include/hal/i2s_ll.h index 96d4a3f8ec..22d6cb90b3 100644 --- a/components/hal/esp32/include/hal/i2s_ll.h +++ b/components/hal/esp32/include/hal/i2s_ll.h @@ -27,7 +27,9 @@ #include "soc/rtc.h" #include "soc/efuse_periph.h" #include "soc/i2s_periph.h" +#include "soc/i2s_struct.h" #include "hal/i2s_types.h" +#include "hal/hal_defs.h" #ifdef __cplusplus extern "C" { @@ -398,7 +400,7 @@ static inline void i2s_ll_set_rx_eof_num(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_clkm_div_num(i2s_dev_t *hw, uint32_t val) { - hw->clkm_conf.clkm_div_num = val; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clkm_conf, clkm_div_num, val); } /** diff --git a/components/hal/esp32/include/hal/ledc_ll.h b/components/hal/esp32/include/hal/ledc_ll.h index f7331872b6..9e6c0c219e 100644 --- a/components/hal/esp32/include/hal/ledc_ll.h +++ b/components/hal/esp32/include/hal/ledc_ll.h @@ -19,6 +19,8 @@ #include "hal/ledc_types.h" #include "soc/ledc_periph.h" +#include "soc/ledc_struct.h" +#include "hal/hal_defs.h" #define LEDC_LL_GET_HW() &LEDC diff --git a/components/hal/esp32/include/hal/mcpwm_ll.h b/components/hal/esp32/include/hal/mcpwm_ll.h index 9f39626a1a..15f70c2f98 100644 --- a/components/hal/esp32/include/hal/mcpwm_ll.h +++ b/components/hal/esp32/include/hal/mcpwm_ll.h @@ -23,8 +23,8 @@ #pragma once #include "soc/soc_caps.h" -#include #include "soc/mcpwm_periph.h" +#include "soc/mcpwm_struct.h" #include "hal/mcpwm_types.h" #include "hal/hal_defs.h" @@ -61,7 +61,7 @@ static inline void mcpwm_ll_init(mcpwm_dev_t *mcpwm) */ static inline void mcpwm_ll_set_clock_prescale(mcpwm_dev_t *mcpwm, int prescale) { - mcpwm->clk_cfg.prescale = prescale; + HAL_FORCE_MODIFY_U32_REG_FIELD(mcpwm->clk_cfg, prescale, prescale); } STATIC_HAL_REG_CHECK(MCPWM, MCPWM_LL_INTR_CAP0, MCPWM_CAP0_INT_RAW); diff --git a/components/hal/esp32/include/hal/mwdt_ll.h b/components/hal/esp32/include/hal/mwdt_ll.h index 9a981c6855..85cf41ff36 100644 --- a/components/hal/esp32/include/hal/mwdt_ll.h +++ b/components/hal/esp32/include/hal/mwdt_ll.h @@ -24,8 +24,10 @@ extern "C" { #include #include #include "soc/timer_periph.h" +#include "soc/timer_group_struct.h" #include "hal/wdt_types.h" #include "esp_attr.h" +#include "hal/hal_defs.h" //Type check wdt_stage_action_t _Static_assert(WDT_STAGE_ACTION_OFF == TIMG_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t"); @@ -201,7 +203,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t* hw, bool enable) */ FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler) { - hw->wdt_config1.clk_prescale = prescaler; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdt_config1, clk_prescale, prescaler); } /** diff --git a/components/hal/esp32/include/hal/pcnt_ll.h b/components/hal/esp32/include/hal/pcnt_ll.h index b5b20ff49d..1176ce265f 100644 --- a/components/hal/esp32/include/hal/pcnt_ll.h +++ b/components/hal/esp32/include/hal/pcnt_ll.h @@ -23,7 +23,9 @@ #pragma once #include "soc/pcnt_periph.h" +#include "soc/pcnt_struct.h" #include "hal/pcnt_types.h" +#include "hal/hal_defs.h" #ifdef __cplusplus extern "C" { diff --git a/components/hal/esp32/include/hal/rmt_ll.h b/components/hal/esp32/include/hal/rmt_ll.h index e6435f18eb..676ce21ad3 100644 --- a/components/hal/esp32/include/hal/rmt_ll.h +++ b/components/hal/esp32/include/hal/rmt_ll.h @@ -20,6 +20,7 @@ extern "C" { #include #include "soc/rmt_struct.h" #include "soc/soc_caps.h" +#include "hal/hal_defs.h" #define RMT_LL_HW_BASE (&RMT) #define RMT_LL_MEM_BASE (&RMTMEM) diff --git a/components/hal/esp32/include/hal/rtc_io_ll.h b/components/hal/esp32/include/hal/rtc_io_ll.h index 3e5a1af8ff..f96452532e 100644 --- a/components/hal/esp32/include/hal/rtc_io_ll.h +++ b/components/hal/esp32/include/hal/rtc_io_ll.h @@ -22,6 +22,7 @@ #include #include "soc/rtc_io_periph.h" +#include "soc/rtc_io_struct.h" #include "hal/rtc_io_types.h" #include "hal/gpio_types.h" diff --git a/components/hal/esp32/include/hal/rwdt_ll.h b/components/hal/esp32/include/hal/rwdt_ll.h index c1d2d60607..e409eeaa8b 100644 --- a/components/hal/esp32/include/hal/rwdt_ll.h +++ b/components/hal/esp32/include/hal/rwdt_ll.h @@ -25,6 +25,7 @@ extern "C" { #include #include "hal/wdt_types.h" #include "soc/rtc_cntl_periph.h" +#include "soc/rtc_cntl_struct.h" #include "esp_attr.h" //Type check wdt_stage_action_t diff --git a/components/hal/esp32/include/hal/sigmadelta_ll.h b/components/hal/esp32/include/hal/sigmadelta_ll.h index 929546fe0c..c8f1f80723 100644 --- a/components/hal/esp32/include/hal/sigmadelta_ll.h +++ b/components/hal/esp32/include/hal/sigmadelta_ll.h @@ -23,6 +23,7 @@ #include #include "soc/sigmadelta_periph.h" +#include "soc/gpio_sd_struct.h" #include "hal/sigmadelta_types.h" #ifdef __cplusplus diff --git a/components/hal/esp32/include/hal/spi_flash_ll.h b/components/hal/esp32/include/hal/spi_flash_ll.h index 7c0862eddc..ad1cb88a0a 100644 --- a/components/hal/esp32/include/hal/spi_flash_ll.h +++ b/components/hal/esp32/include/hal/spi_flash_ll.h @@ -24,7 +24,9 @@ #include #include "soc/spi_periph.h" +#include "soc/spi_struct.h" #include "hal/spi_types.h" +#include "hal/hal_defs.h" #include "hal/spi_flash_types.h" #include // For MIN/MAX #include @@ -393,7 +395,7 @@ static inline void spi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr) static inline void spi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - dev->user1.usr_dummy_cyclelen = dummy_n - 1; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); } static inline void spi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n) diff --git a/components/hal/esp32/include/hal/spi_ll.h b/components/hal/esp32/include/hal/spi_ll.h index cacffe0a05..942eecd428 100644 --- a/components/hal/esp32/include/hal/spi_ll.h +++ b/components/hal/esp32/include/hal/spi_ll.h @@ -24,9 +24,11 @@ #include "hal/hal_defs.h" #include "soc/spi_periph.h" +#include "soc/spi_struct.h" #include "esp32/rom/lldesc.h" #include #include +#include "hal/hal_defs.h" #include //for abs() #ifdef __cplusplus @@ -681,7 +683,7 @@ static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int dela static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) { hw->user.usr_dummy = dummy_n ? 1 : 0; - hw->user1.usr_dummy_cyclelen = dummy_n - 1; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); } /** @@ -839,13 +841,13 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b { if (lsbfirst) { // The output command start from bit0 to bit 15, kept as is. - hw->user2.usr_command_value = cmd; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, cmd); } else { /* Output command will be sent from bit 7 to 0 of command_value, and * then bit 15 to 8 of the same register field. Shift and swap to send * more straightly. */ - hw->user2.usr_command_value = HAL_SPI_SWAP_DATA_TX(cmd, cmdlen); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, HAL_SPI_SWAP_DATA_TX(cmd, cmdlen)); } } diff --git a/components/hal/esp32/include/hal/timer_ll.h b/components/hal/esp32/include/hal/timer_ll.h index 447f3fded9..4ff9c68866 100644 --- a/components/hal/esp32/include/hal/timer_ll.h +++ b/components/hal/esp32/include/hal/timer_ll.h @@ -24,6 +24,7 @@ extern "C" { #include #include "hal/timer_types.h" #include "soc/timer_periph.h" +#include "soc/timer_group_struct.h" _Static_assert(TIMER_INTR_T0 == TIMG_T0_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t"); _Static_assert(TIMER_INTR_T1 == TIMG_T1_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t"); diff --git a/components/hal/esp32/include/hal/touch_sensor_ll.h b/components/hal/esp32/include/hal/touch_sensor_ll.h index 0b876039b0..0291724234 100644 --- a/components/hal/esp32/include/hal/touch_sensor_ll.h +++ b/components/hal/esp32/include/hal/touch_sensor_ll.h @@ -25,7 +25,11 @@ #include #include #include "soc/touch_sensor_periph.h" +#include "soc/rtc_io_struct.h" +#include "soc/rtc_cntl_struct.h" +#include "soc/sens_struct.h" #include "hal/touch_sensor_types.h" +#include "hal/hal_defs.h" #ifdef __cplusplus @@ -60,9 +64,9 @@ static inline touch_pad_t touch_ll_num_wrap(touch_pad_t touch_num) static inline void touch_ll_set_meas_time(uint16_t meas_time) { //touch sensor measure time= meas_cycle / 8Mhz - SENS.sar_touch_ctrl1.touch_meas_delay = meas_time; + HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_touch_ctrl1, touch_meas_delay, meas_time); //the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD - SENS.sar_touch_ctrl1.touch_xpd_wait = SOC_TOUCH_PAD_MEASURE_WAIT_MAX; + HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_touch_ctrl1, touch_xpd_wait, SOC_TOUCH_PAD_MEASURE_WAIT_MAX); } /** @@ -72,7 +76,7 @@ static inline void touch_ll_set_meas_time(uint16_t meas_time) */ static inline void touch_ll_get_meas_time(uint16_t *meas_time) { - *meas_time = SENS.sar_touch_ctrl1.touch_meas_delay; + *meas_time = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_ctrl1, touch_meas_delay); } /** @@ -86,7 +90,7 @@ static inline void touch_ll_get_meas_time(uint16_t *meas_time) static inline void touch_ll_set_sleep_time(uint16_t sleep_time) { //touch sensor sleep cycle Time = sleep_cycle / RTC_SLOW_CLK( can be 150k or 32k depending on the options) - SENS.sar_touch_ctrl2.touch_sleep_cycles = sleep_time; + HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_touch_ctrl2, touch_sleep_cycles, sleep_time); } /** @@ -96,7 +100,7 @@ static inline void touch_ll_set_sleep_time(uint16_t sleep_time) */ static inline void touch_ll_get_sleep_time(uint16_t *sleep_time) { - *sleep_time = SENS.sar_touch_ctrl1.touch_meas_delay; + *sleep_time = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_ctrl1, touch_meas_delay); } /** diff --git a/components/hal/esp32/include/hal/twai_ll.h b/components/hal/esp32/include/hal/twai_ll.h index b0d8968712..869759258a 100644 --- a/components/hal/esp32/include/hal/twai_ll.h +++ b/components/hal/esp32/include/hal/twai_ll.h @@ -31,6 +31,8 @@ extern "C" { #include "sdkconfig.h" #include "hal/twai_types.h" #include "soc/twai_periph.h" +#include "soc/twai_struct.h" +#include "hal/hal_defs.h" /* ------------------------- Defines and Typedefs --------------------------- */ @@ -490,7 +492,7 @@ static inline void twai_ll_parse_err_code_cap(twai_dev_t *hw, */ static inline void twai_ll_set_err_warn_lim(twai_dev_t *hw, uint32_t ewl) { - hw->error_warning_limit_reg.ewl = ewl; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->error_warning_limit_reg, ewl, ewl); } /** @@ -530,7 +532,7 @@ static inline uint32_t twai_ll_get_rec(twai_dev_t *hw) */ static inline void twai_ll_set_rec(twai_dev_t *hw, uint32_t rec) { - hw->rx_error_counter_reg.rxerr = rec; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_error_counter_reg, rxerr, rec); } /* ------------------------ TX Error Count Register ------------------------- */ @@ -558,7 +560,7 @@ static inline uint32_t twai_ll_get_tec(twai_dev_t *hw) */ static inline void twai_ll_set_tec(twai_dev_t *hw, uint32_t tec) { - hw->tx_error_counter_reg.txerr = tec; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_error_counter_reg, txerr, tec); } /* ---------------------- Acceptance Filter Registers ----------------------- */ diff --git a/components/hal/esp32/include/hal/uart_ll.h b/components/hal/esp32/include/hal/uart_ll.h index c740849360..98af78fbe2 100644 --- a/components/hal/esp32/include/hal/uart_ll.h +++ b/components/hal/esp32/include/hal/uart_ll.h @@ -19,7 +19,9 @@ #pragma once #include "esp_attr.h" #include "soc/uart_periph.h" +#include "soc/uart_struct.h" #include "hal/uart_types.h" +#include "hal/hal_defs.h" #ifdef __cplusplus extern "C" { @@ -249,7 +251,7 @@ FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw) //Get the UART APB fifo addr uint32_t fifo_addr = (hw == &UART0) ? UART_FIFO_REG(0) : (hw == &UART1) ? UART_FIFO_REG(1) : UART_FIFO_REG(2); do { - fifo_cnt = hw->status.rxfifo_cnt; + fifo_cnt = HAL_FORCE_READ_U32_REG_FIELD(hw->status, rxfifo_cnt); rxmem_sta.val = hw->mem_rx_status.val; if(fifo_cnt != 0 || (rxmem_sta.rd_addr != rxmem_sta.wr_addr)) { READ_PERI_REG(fifo_addr); @@ -287,7 +289,7 @@ FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw) */ FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) { - uint32_t fifo_cnt = hw->status.rxfifo_cnt; + uint32_t fifo_cnt = HAL_FORCE_READ_U32_REG_FIELD(hw->status, rxfifo_cnt); typeof(hw->mem_rx_status) rx_status = hw->mem_rx_status; uint32_t len = 0; @@ -313,7 +315,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) */ FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw) { - return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt; + return UART_LL_FIFO_DEF_LEN - HAL_FORCE_READ_U32_REG_FIELD(hw->status, txfifo_cnt); } /** @@ -453,7 +455,7 @@ FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num) { if(break_num > 0) { - hw->idle_conf.tx_brk_num = break_num; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->idle_conf, tx_brk_num, break_num); hw->conf0.txd_brk = 1; } else { hw->conf0.txd_brk = 0; @@ -518,10 +520,10 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl if(sw_flow_ctrl_en) { hw->flow_conf.xonoff_del = 1; hw->flow_conf.sw_flow_con_en = 1; - hw->swfc_conf.xon_threshold = flow_ctrl->xon_thrd; - hw->swfc_conf.xoff_threshold = flow_ctrl->xoff_thrd; - hw->swfc_conf.xon_char = flow_ctrl->xon_char; - hw->swfc_conf.xoff_char = flow_ctrl->xoff_char; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xon_threshold, flow_ctrl->xon_thrd); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xoff_threshold, flow_ctrl->xoff_thrd); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xon_char, flow_ctrl->xon_char); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xoff_char, flow_ctrl->xoff_char); } else { hw->flow_conf.sw_flow_con_en = 0; hw->flow_conf.xonoff_del = 0; @@ -543,8 +545,8 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl */ FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char) { - hw->at_cmd_char.data = cmd_char->cmd_char; - hw->at_cmd_char.char_num = cmd_char->char_num; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num); hw->at_cmd_postcnt.post_idle_num = cmd_char->post_idle; hw->at_cmd_precnt.pre_idle_num = cmd_char->pre_idle; hw->at_cmd_gaptout.rx_gap_tout = cmd_char->gap_tout; @@ -729,8 +731,8 @@ FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) */ FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num) { - *cmd_char = hw->at_cmd_char.data; - *char_num = hw->at_cmd_char.char_num; + *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, data); + *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, char_num); } /** diff --git a/components/hal/esp32c3/include/hal/adc_ll.h b/components/hal/esp32c3/include/hal/adc_ll.h index a2fd21f2b5..eab29e1e97 100644 --- a/components/hal/esp32c3/include/hal/adc_ll.h +++ b/components/hal/esp32c3/include/hal/adc_ll.h @@ -24,6 +24,7 @@ #include "soc/apb_saradc_reg.h" #include "soc/rtc_cntl_struct.h" #include "soc/rtc_cntl_reg.h" +#include "hal/hal_defs.h" #ifdef __cplusplus extern "C" { @@ -94,11 +95,11 @@ typedef enum { static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait) { // Internal FSM reset wait time - APB_SARADC.fsm_wait.rstb_wait = rst_wait; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, rstb_wait, rst_wait); // Internal FSM start wait time - APB_SARADC.fsm_wait.xpd_wait = start_wait; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, xpd_wait, start_wait); // Internal FSM standby wait time - APB_SARADC.fsm_wait.standby_wait = standby_wait; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, standby_wait, standby_wait); } /** @@ -124,7 +125,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle) static inline void adc_ll_digi_set_clk_div(uint32_t div) { /* ADC clock devided from digital controller clock clk */ - APB_SARADC.ctrl.sar_clk_div = div; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl, sar_clk_div, div); } /** @@ -135,7 +136,7 @@ static inline void adc_ll_digi_set_clk_div(uint32_t div) */ static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num) { - APB_SARADC.ctrl2.max_meas_num = meas_num; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl2, max_meas_num, meas_num); } /** @@ -267,7 +268,7 @@ static inline void adc_ll_digi_trigger_disable(void) */ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a) { - APB_SARADC.apb_adc_clkm_conf.clkm_div_num = div_num; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.apb_adc_clkm_conf, clkm_div_num, div_num); APB_SARADC.apb_adc_clkm_conf.clkm_div_b = div_b; APB_SARADC.apb_adc_clkm_conf.clkm_div_a = div_a; } @@ -404,7 +405,7 @@ static inline void adc_ll_digi_monitor_disable(adc_digi_monitor_idx_t idx) */ static inline void adc_ll_digi_dma_set_eof_num(uint32_t num) { - APB_SARADC.dma_conf.apb_adc_eof_num = num; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, num); } /** diff --git a/components/hal/esp32c3/include/hal/gpio_ll.h b/components/hal/esp32c3/include/hal/gpio_ll.h index da61aa198c..6214bc06e3 100644 --- a/components/hal/esp32c3/include/hal/gpio_ll.h +++ b/components/hal/esp32c3/include/hal/gpio_ll.h @@ -24,6 +24,7 @@ #include "soc/soc.h" #include "soc/gpio_periph.h" +#include "soc/gpio_struct.h" #include "soc/rtc_cntl_reg.h" #include "hal/gpio_types.h" #include "stdlib.h" diff --git a/components/hal/esp32c3/include/hal/gpspi_flash_ll.h b/components/hal/esp32c3/include/hal/gpspi_flash_ll.h index f80fc83b26..2d55ab9003 100644 --- a/components/hal/esp32c3/include/hal/gpspi_flash_ll.h +++ b/components/hal/esp32c3/include/hal/gpspi_flash_ll.h @@ -24,8 +24,10 @@ #include #include "soc/spi_periph.h" +#include "soc/spi_struct.h" #include "hal/spi_types.h" #include "hal/spi_flash_types.h" +#include "hal/hal_defs.h" #include // For MIN/MAX #include #include @@ -354,7 +356,7 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr) static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - dev->user1.usr_dummy_cyclelen = dummy_n - 1; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); } /** diff --git a/components/hal/esp32c3/include/hal/i2c_ll.h b/components/hal/esp32c3/include/hal/i2c_ll.h index 9abe26d513..41facaf158 100644 --- a/components/hal/esp32c3/include/hal/i2c_ll.h +++ b/components/hal/esp32c3/include/hal/i2c_ll.h @@ -16,10 +16,12 @@ #pragma once #include "soc/i2c_periph.h" +#include "soc/i2c_struct.h" #include "soc/soc_caps.h" #include "hal/i2c_types.h" #include "soc/rtc_cntl_reg.h" #include "esp_rom_sys.h" +#include "hal/hal_defs.h" #ifdef __cplusplus extern "C" { @@ -152,7 +154,7 @@ static inline void i2c_ll_update(i2c_dev_t *hw) */ static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_clk_cal_t *bus_cfg) { - hw->clk_conf.sclk_div_num = bus_cfg->clkm_div - 1; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, bus_cfg->clkm_div - 1); //scl period hw->scl_low_period.period = bus_cfg->scl_low - 1; hw->scl_high_period.period = bus_cfg->scl_high; @@ -590,7 +592,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) { for(int i = 0; i < len; i++) { - ptr[i] = hw->fifo_data.data; + ptr[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->fifo_data, data); } } diff --git a/components/hal/esp32c3/include/hal/i2s_ll.h b/components/hal/esp32c3/include/hal/i2s_ll.h index 4a6042cf12..2962699aae 100644 --- a/components/hal/esp32c3/include/hal/i2s_ll.h +++ b/components/hal/esp32c3/include/hal/i2s_ll.h @@ -25,7 +25,9 @@ #include #include #include "soc/i2s_periph.h" +#include "soc/i2s_struct.h" #include "hal/i2s_types.h" +#include "hal/hal_defs.h" #ifdef __cplusplus extern "C" { diff --git a/components/hal/esp32c3/include/hal/ledc_ll.h b/components/hal/esp32c3/include/hal/ledc_ll.h index eafae904ba..fb495b0319 100644 --- a/components/hal/esp32c3/include/hal/ledc_ll.h +++ b/components/hal/esp32c3/include/hal/ledc_ll.h @@ -19,6 +19,7 @@ #include "hal/ledc_types.h" #include "soc/ledc_periph.h" +#include "soc/ledc_struct.h" #ifdef __cplusplus extern "C" { diff --git a/components/hal/esp32c3/include/hal/mwdt_ll.h b/components/hal/esp32c3/include/hal/mwdt_ll.h index c1fd5be9d6..85ec1d7796 100644 --- a/components/hal/esp32c3/include/hal/mwdt_ll.h +++ b/components/hal/esp32c3/include/hal/mwdt_ll.h @@ -24,7 +24,9 @@ extern "C" { #include #include #include "soc/timer_periph.h" +#include "soc/timer_group_struct.h" #include "hal/wdt_types.h" +#include "hal/hal_defs.h" #include "esp_attr.h" //Type check wdt_stage_action_t @@ -189,7 +191,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable) */ FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler) { - hw->wdt_config1.clk_prescale = prescaler; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdt_config1, clk_prescale, prescaler); //Config registers are updated asynchronously hw->wdt_config0.conf_update_en = 1; } diff --git a/components/hal/esp32c3/include/hal/rmt_ll.h b/components/hal/esp32c3/include/hal/rmt_ll.h index 5e8c64c28a..731d74c363 100644 --- a/components/hal/esp32c3/include/hal/rmt_ll.h +++ b/components/hal/esp32c3/include/hal/rmt_ll.h @@ -21,6 +21,7 @@ extern "C" { #include #include "soc/rmt_struct.h" #include "soc/soc_caps.h" +#include "hal/hal_defs.h" #define RMT_LL_HW_BASE (&RMT) #define RMT_LL_MEM_BASE (&RMTMEM) @@ -58,7 +59,7 @@ static inline void rmt_ll_set_counter_clock_src(rmt_dev_t *dev, uint32_t channel // Formula: rmt_sclk = module_clock_src / (1 + div_num + div_a / div_b) dev->sys_conf.sclk_active = 0; dev->sys_conf.sclk_sel = src; - dev->sys_conf.sclk_div_num = div_num; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->sys_conf, sclk_div_num, div_num); dev->sys_conf.sclk_div_a = div_a; dev->sys_conf.sclk_div_b = div_b; dev->sys_conf.sclk_active = 1; diff --git a/components/hal/esp32c3/include/hal/rwdt_ll.h b/components/hal/esp32c3/include/hal/rwdt_ll.h index 87ae4f7294..8a2eba272b 100644 --- a/components/hal/esp32c3/include/hal/rwdt_ll.h +++ b/components/hal/esp32c3/include/hal/rwdt_ll.h @@ -25,6 +25,8 @@ extern "C" { #include #include "hal/wdt_types.h" #include "soc/rtc_cntl_periph.h" +#include "soc/rtc_cntl_struct.h" +#include "hal/hal_defs.h" #include "soc/efuse_reg.h" #include "esp_attr.h" @@ -239,7 +241,7 @@ FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_en(rtc_cntl_dev_t *hw, bool enable */ FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_width(rtc_cntl_dev_t *hw, uint32_t width) { - hw->wdt_config0.chip_reset_width = width; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdt_config0, chip_reset_width, width); } /** diff --git a/components/hal/esp32c3/include/hal/sigmadelta_ll.h b/components/hal/esp32c3/include/hal/sigmadelta_ll.h index 87f75dab9e..0a559dfb52 100644 --- a/components/hal/esp32c3/include/hal/sigmadelta_ll.h +++ b/components/hal/esp32c3/include/hal/sigmadelta_ll.h @@ -23,6 +23,7 @@ #include #include "soc/sigmadelta_periph.h" +#include "soc/gpio_sd_struct.h" #include "hal/sigmadelta_types.h" #ifdef __cplusplus diff --git a/components/hal/esp32c3/include/hal/spi_flash_ll.h b/components/hal/esp32c3/include/hal/spi_flash_ll.h index 5508d161e0..ba2afb7aa9 100644 --- a/components/hal/esp32c3/include/hal/spi_flash_ll.h +++ b/components/hal/esp32c3/include/hal/spi_flash_ll.h @@ -24,6 +24,7 @@ #include "gpspi_flash_ll.h" #include "spimem_flash_ll.h" +#include "hal/hal_defs.h" #ifdef __cplusplus extern "C" { diff --git a/components/hal/esp32c3/include/hal/spi_ll.h b/components/hal/esp32c3/include/hal/spi_ll.h index 5527ee1eb7..316f2e93a5 100644 --- a/components/hal/esp32c3/include/hal/spi_ll.h +++ b/components/hal/esp32c3/include/hal/spi_ll.h @@ -27,6 +27,7 @@ #include "hal/hal_defs.h" #include "esp_types.h" #include "soc/spi_periph.h" +#include "soc/spi_struct.h" #include "esp32c3/rom/lldesc.h" #include "esp_attr.h" @@ -905,13 +906,13 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b { if (lsbfirst) { // The output command start from bit0 to bit 15, kept as is. - hw->user2.usr_command_value = cmd; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, cmd); } else { /* Output command will be sent from bit 7 to 0 of command_value, and * then bit 15 to 8 of the same register field. Shift and swap to send * more straightly. */ - hw->user2.usr_command_value = HAL_SPI_SWAP_DATA_TX(cmd, cmdlen); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, HAL_SPI_SWAP_DATA_TX(cmd, cmdlen)); } } @@ -927,7 +928,7 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) { hw->user.usr_dummy = dummy_n ? 1 : 0; - hw->user1.usr_dummy_cyclelen = dummy_n - 1; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); } /** diff --git a/components/hal/esp32c3/include/hal/spimem_flash_ll.h b/components/hal/esp32c3/include/hal/spimem_flash_ll.h index 7641c3d723..2d576f437d 100644 --- a/components/hal/esp32c3/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32c3/include/hal/spimem_flash_ll.h @@ -28,8 +28,10 @@ #include #include "soc/spi_periph.h" +#include "soc/spi_mem_struct.h" #include "hal/spi_types.h" #include "hal/spi_flash_types.h" +#include "hal/hal_defs.h" #ifdef __cplusplus extern "C" { @@ -157,7 +159,7 @@ static inline void spimem_flash_ll_auto_resume_init(spi_mem_dev_t *dev, bool aut */ static inline void spimem_flash_ll_suspend_cmd_setup(spi_mem_dev_t *dev, uint32_t sus_cmd) { - dev->flash_sus_cmd.flash_pes_command = sus_cmd; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, flash_pes_command, sus_cmd); } /** @@ -169,7 +171,7 @@ static inline void spimem_flash_ll_suspend_cmd_setup(spi_mem_dev_t *dev, uint32_ */ static inline void spimem_flash_ll_resume_cmd_setup(spi_mem_dev_t *dev, uint32_t res_cmd) { - dev->flash_sus_cmd.flash_per_command = res_cmd; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, flash_per_command, res_cmd); } /** @@ -181,7 +183,7 @@ static inline void spimem_flash_ll_resume_cmd_setup(spi_mem_dev_t *dev, uint32_t */ static inline void spimem_flash_ll_rd_sus_cmd_setup(spi_mem_dev_t *dev, uint32_t pesr_cmd) { - dev->flash_sus_cmd.wait_pesr_command = pesr_cmd; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, wait_pesr_command, pesr_cmd); } /** @@ -218,7 +220,7 @@ static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, bool static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint32_t sus_conf) { dev->flash_sus_ctrl.frd_sus_2b = 0; - dev->flash_sus_ctrl.pesr_end_msk = sus_conf; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, pesr_end_msk, sus_conf); } /** @@ -229,7 +231,7 @@ static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint3 */ static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool auto_waiti) { - dev->flash_waiti_ctrl.waiti_cmd = 0x05; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_waiti_ctrl, waiti_cmd, 0x05); dev->flash_sus_ctrl.flash_per_wait_en = auto_waiti; dev->flash_sus_ctrl.flash_pes_wait_en = auto_waiti; } diff --git a/components/hal/esp32c3/include/hal/timer_ll.h b/components/hal/esp32c3/include/hal/timer_ll.h index edadee14e3..b17667e7de 100644 --- a/components/hal/esp32c3/include/hal/timer_ll.h +++ b/components/hal/esp32c3/include/hal/timer_ll.h @@ -24,6 +24,7 @@ extern "C" { #include #include "hal/timer_types.h" #include "soc/timer_periph.h" +#include "soc/timer_group_struct.h" _Static_assert(TIMER_INTR_T0 == TIMG_T0_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t"); _Static_assert(TIMER_INTR_WDT == TIMG_WDT_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t"); diff --git a/components/hal/esp32c3/include/hal/twai_ll.h b/components/hal/esp32c3/include/hal/twai_ll.h index 6c9ae1b9fd..68df4cf7e2 100644 --- a/components/hal/esp32c3/include/hal/twai_ll.h +++ b/components/hal/esp32c3/include/hal/twai_ll.h @@ -30,6 +30,8 @@ extern "C" { #include #include "hal/twai_types.h" #include "soc/twai_periph.h" +#include "soc/twai_struct.h" +#include "hal/hal_defs.h" /* ------------------------- Defines and Typedefs --------------------------- */ @@ -398,7 +400,7 @@ static inline void twai_ll_clear_err_code_cap(twai_dev_t *hw) */ static inline void twai_ll_set_err_warn_lim(twai_dev_t *hw, uint32_t ewl) { - hw->error_warning_limit_reg.ewl = ewl; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->error_warning_limit_reg, ewl, ewl); } /** @@ -438,7 +440,7 @@ static inline uint32_t twai_ll_get_rec(twai_dev_t *hw) */ static inline void twai_ll_set_rec(twai_dev_t *hw, uint32_t rec) { - hw->rx_error_counter_reg.rxerr = rec; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_error_counter_reg, rxerr, rec); } /* ------------------------ TX Error Count Register ------------------------- */ @@ -466,7 +468,7 @@ static inline uint32_t twai_ll_get_tec(twai_dev_t *hw) */ static inline void twai_ll_set_tec(twai_dev_t *hw, uint32_t tec) { - hw->tx_error_counter_reg.txerr = tec; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_error_counter_reg, txerr, tec); } /* ---------------------- Acceptance Filter Registers ----------------------- */ @@ -651,14 +653,14 @@ static inline void twai_ll_set_clkout(twai_dev_t *hw, uint32_t divider) { if (divider >= 2 && divider <= 490) { hw->clock_divider_reg.co = 0; - hw->clock_divider_reg.cd = (divider / 2) - 1; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, (divider / 2) - 1); } else if (divider == 1) { //Setting the divider reg to max value (255) means a divider of 1 hw->clock_divider_reg.co = 0; - hw->clock_divider_reg.cd = 255; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 255); } else { hw->clock_divider_reg.co = 1; - hw->clock_divider_reg.cd = 0; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 0); } } diff --git a/components/hal/esp32c3/include/hal/uart_ll.h b/components/hal/esp32c3/include/hal/uart_ll.h index a917caadcb..9bc63503b0 100644 --- a/components/hal/esp32c3/include/hal/uart_ll.h +++ b/components/hal/esp32c3/include/hal/uart_ll.h @@ -19,6 +19,8 @@ #pragma once #include "hal/uart_types.h" #include "soc/uart_periph.h" +#include "soc/uart_struct.h" +#include "hal/hal_defs.h" #ifdef __cplusplus extern "C" { @@ -163,7 +165,7 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud) // an integer part and a fractional part. hw->clk_div.div_int = clk_div >> 4; hw->clk_div.div_frag = clk_div & 0xf; - hw->clk_conf.sclk_div_num = sclk_div - 1; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1); #undef DIV_UP } @@ -178,7 +180,7 @@ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw) { uint32_t sclk_freq = uart_ll_get_sclk_freq(hw); typeof(hw->clk_div) div_reg = hw->clk_div; - return ((sclk_freq << 4)) / (((div_reg.div_int << 4) | div_reg.div_frag) * (hw->clk_conf.sclk_div_num + 1)); + return ((sclk_freq << 4)) / (((div_reg.div_int << 4) | div_reg.div_frag) * (HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1)); } /** @@ -451,7 +453,7 @@ static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num) static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num) { if (break_num > 0) { - hw->txbrk_conf.tx_brk_num = break_num; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf, tx_brk_num, break_num); hw->conf0.txd_brk = 1; } else { hw->conf0.txd_brk = 0; @@ -518,8 +520,8 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t * hw->flow_conf.sw_flow_con_en = 1; hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd; hw->swfc_conf0.xoff_threshold = flow_ctrl->xoff_thrd; - hw->swfc_conf1.xon_char = flow_ctrl->xon_char; - hw->swfc_conf0.xoff_char = flow_ctrl->xoff_char; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_char, flow_ctrl->xon_char); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0, xoff_char, flow_ctrl->xoff_char); } else { hw->flow_conf.sw_flow_con_en = 0; hw->flow_conf.xonoff_del = 0; @@ -541,11 +543,11 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t * */ static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char) { - hw->at_cmd_char.data = cmd_char->cmd_char; - hw->at_cmd_char.char_num = cmd_char->char_num; - hw->at_cmd_postcnt.post_idle_num = cmd_char->post_idle; - hw->at_cmd_precnt.pre_idle_num = cmd_char->pre_idle; - hw->at_cmd_gaptout.rx_gap_tout = cmd_char->gap_tout; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt, post_idle_num, cmd_char->post_idle); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt, pre_idle_num, cmd_char->pre_idle); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout, rx_gap_tout, cmd_char->gap_tout); } /** @@ -734,8 +736,8 @@ static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) */ static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num) { - *cmd_char = hw->at_cmd_char.data; - *char_num = hw->at_cmd_char.char_num; + *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, data); + *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, char_num); } /** diff --git a/components/hal/esp32s2/include/hal/adc_ll.h b/components/hal/esp32s2/include/hal/adc_ll.h index ffad47a5c3..0ffe3b1a65 100644 --- a/components/hal/esp32s2/include/hal/adc_ll.h +++ b/components/hal/esp32s2/include/hal/adc_ll.h @@ -4,10 +4,12 @@ #include "soc/adc_periph.h" #include "hal/adc_types.h" #include "soc/apb_saradc_struct.h" +#include "soc/sens_struct.h" #include "soc/apb_saradc_reg.h" #include "soc/rtc_cntl_struct.h" #include "soc/rtc_cntl_reg.h" #include "regi2c_ctrl.h" +#include "hal/hal_defs.h" #ifdef __cplusplus extern "C" { @@ -83,11 +85,11 @@ typedef enum { static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait) { // Internal FSM reset wait time - APB_SARADC.fsm_wait.rstb_wait = rst_wait; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, rstb_wait, rst_wait); // Internal FSM start wait time - APB_SARADC.fsm_wait.xpd_wait = start_wait; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, xpd_wait, start_wait); // Internal FSM standby wait time - APB_SARADC.fsm_wait.standby_wait = standby_wait; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, standby_wait, standby_wait); } /** @@ -115,7 +117,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle) static inline void adc_ll_digi_set_clk_div(uint32_t div) { /* ADC clock devided from digital controller clock clk */ - APB_SARADC.ctrl.sar_clk_div = div; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl, sar_clk_div, div); } /** @@ -136,7 +138,7 @@ static inline void adc_ll_digi_set_output_format(adc_digi_output_format_t format */ static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num) { - APB_SARADC.ctrl2.max_meas_num = meas_num; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl2, max_meas_num, meas_num); } /** @@ -307,7 +309,7 @@ static inline void adc_ll_digi_trigger_disable(void) */ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a) { - APB_SARADC.apb_adc_clkm_conf.clkm_div_num = div_num; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.apb_adc_clkm_conf, clkm_div_num, div_num); APB_SARADC.apb_adc_clkm_conf.clkm_div_b = div_b; APB_SARADC.apb_adc_clkm_conf.clkm_div_a = div_a; } @@ -427,9 +429,9 @@ static inline void adc_ll_digi_filter_enable(adc_ll_num_t adc_n, bool enable) static inline uint32_t adc_ll_digi_filter_read_data(adc_ll_num_t adc_n) { if (adc_n == ADC_NUM_1) { - return APB_SARADC.filter_status.adc1_filter_data; + return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.filter_status, adc1_filter_data); } else { // adc_n == ADC_NUM_2 - return APB_SARADC.filter_status.adc2_filter_data; + return HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.filter_status, adc2_filter_data); } } @@ -595,7 +597,7 @@ static inline uint32_t adc_ll_digi_get_intr_status(adc_ll_num_t adc_n) */ static inline void adc_ll_digi_dma_set_eof_num(uint32_t num) { - APB_SARADC.dma_conf.apb_adc_eof_num = num; + HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, num); } /** @@ -710,7 +712,7 @@ static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n) static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel) { if (adc_n == ADC_NUM_1) { - while (SENS.sar_slave_addr1.meas_status != 0); + while (HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_slave_addr1, meas_status) != 0); SENS.sar_meas1_ctrl2.meas1_start_sar = 0; SENS.sar_meas1_ctrl2.meas1_start_sar = 1; } else { // adc_n == ADC_NUM_2 @@ -749,9 +751,9 @@ static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n) { int ret_val = 0; if (adc_n == ADC_NUM_1) { - ret_val = SENS.sar_meas1_ctrl2.meas1_data_sar; + ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas1_ctrl2, meas1_data_sar); } else { // adc_n == ADC_NUM_2 - ret_val = SENS.sar_meas2_ctrl2.meas2_data_sar; + ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas2_ctrl2, meas2_data_sar); } return ret_val; } @@ -906,9 +908,9 @@ static inline adc_ll_power_t adc_ll_get_power_manage(void) static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div) { if (adc_n == ADC_NUM_1) { - SENS.sar_reader1_ctrl.sar1_clk_div = div; + HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader1_ctrl, sar1_clk_div, div); } else { // adc_n == ADC_NUM_2 - SENS.sar_reader2_ctrl.sar2_clk_div = div; + HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader2_ctrl, sar2_clk_div, div); } } diff --git a/components/hal/esp32s2/include/hal/dac_ll.h b/components/hal/esp32s2/include/hal/dac_ll.h index 11f3284f11..deb50ce35f 100644 --- a/components/hal/esp32s2/include/hal/dac_ll.h +++ b/components/hal/esp32s2/include/hal/dac_ll.h @@ -24,7 +24,10 @@ #include "soc/dac_periph.h" #include "hal/dac_types.h" #include "soc/apb_saradc_struct.h" +#include "soc/rtc_io_struct.h" +#include "soc/sens_struct.h" #include "soc/apb_saradc_reg.h" +#include "hal/hal_defs.h" #ifdef __cplusplus extern "C" { @@ -145,7 +148,7 @@ static inline void dac_ll_cw_set_channel(dac_channel_t channel, bool enable) static inline void dac_ll_cw_set_freq(uint32_t freq) { uint32_t sw_freq = freq * 0xFFFF / RTC_FAST_CLK_FREQ_APPROX; - SENS.sar_dac_ctrl1.sw_fstep = (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq; + HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl1, sw_fstep, (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq); } /** @@ -192,12 +195,12 @@ static inline void dac_ll_cw_set_dc_offset(dac_channel_t channel, int8_t offset) if (SENS.sar_dac_ctrl2.dac_inv1 == DAC_CW_PHASE_180) { offset = 0 - offset; } - SENS.sar_dac_ctrl2.dac_dc1 = offset ? offset : (-128 - offset); + HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc1, offset ? offset : (-128 - offset)); } else if (channel == DAC_CHANNEL_2) { if (SENS.sar_dac_ctrl2.dac_inv2 == DAC_CW_PHASE_180) { offset = 0 - offset; } - SENS.sar_dac_ctrl2.dac_dc2 = offset ? offset : (-128 - offset); + HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc2, offset ? offset : (-128 - offset)); } } diff --git a/components/hal/esp32s2/include/hal/dedic_gpio_ll.h b/components/hal/esp32s2/include/hal/dedic_gpio_ll.h index 3cbf29b7bb..e763ae1ebb 100644 --- a/components/hal/esp32s2/include/hal/dedic_gpio_ll.h +++ b/components/hal/esp32s2/include/hal/dedic_gpio_ll.h @@ -20,6 +20,7 @@ extern "C" { #include #include #include "soc/dedic_gpio_struct.h" +#include "hal/hal_defs.h" static inline void dedic_gpio_ll_enable_instruction_access_out(dedic_dev_t *dev, uint32_t channel_mask, bool enable) { @@ -61,12 +62,12 @@ static inline void dedic_gpio_ll_toggle_channel(dedic_dev_t *dev, uint32_t chann static inline uint32_t dedic_gpio_ll_read_out_all(dedic_dev_t *dev) { - return dev->gpio_out_scan.gpio_out_status; + return HAL_FORCE_READ_U32_REG_FIELD(dev->gpio_out_scan, gpio_out_status); } static inline uint32_t dedic_gpio_ll_read_in_all(dedic_dev_t *dev) { - return dev->gpio_in_scan.gpio_in_status; + return HAL_FORCE_READ_U32_REG_FIELD(dev->gpio_in_scan, gpio_in_status); } static inline void dedic_gpio_ll_set_input_delay(dedic_dev_t *dev, uint32_t channel, uint32_t delay_cpu_clks) diff --git a/components/hal/esp32s2/include/hal/gpio_ll.h b/components/hal/esp32s2/include/hal/gpio_ll.h index d6330db630..12fafe6062 100644 --- a/components/hal/esp32s2/include/hal/gpio_ll.h +++ b/components/hal/esp32s2/include/hal/gpio_ll.h @@ -24,7 +24,9 @@ #include "soc/soc.h" #include "soc/gpio_periph.h" +#include "soc/gpio_struct.h" #include "soc/rtc_cntl_reg.h" +#include "soc/rtc_cntl_struct.h" #include "soc/rtc_io_reg.h" #include "hal/gpio_types.h" diff --git a/components/hal/esp32s2/include/hal/gpspi_flash_ll.h b/components/hal/esp32s2/include/hal/gpspi_flash_ll.h index 44612385b3..71126b9848 100644 --- a/components/hal/esp32s2/include/hal/gpspi_flash_ll.h +++ b/components/hal/esp32s2/include/hal/gpspi_flash_ll.h @@ -24,7 +24,9 @@ #include #include "soc/spi_periph.h" +#include "soc/spi_struct.h" #include "hal/spi_types.h" +#include "hal/hal_defs.h" #include "hal/spi_flash_types.h" #include // For MIN/MAX #include @@ -347,7 +349,7 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr) static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - dev->user1.usr_dummy_cyclelen = dummy_n - 1; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); } /** diff --git a/components/hal/esp32s2/include/hal/i2c_ll.h b/components/hal/esp32s2/include/hal/i2c_ll.h index 8152557ced..dc246020b2 100644 --- a/components/hal/esp32s2/include/hal/i2c_ll.h +++ b/components/hal/esp32s2/include/hal/i2c_ll.h @@ -16,6 +16,7 @@ #pragma once #include "soc/i2c_periph.h" +#include "soc/i2c_struct.h" #include "hal/i2c_types.h" #ifdef __cplusplus diff --git a/components/hal/esp32s2/include/hal/i2s_ll.h b/components/hal/esp32s2/include/hal/i2s_ll.h index 3e0a7eeb20..ff0a97a7b1 100644 --- a/components/hal/esp32s2/include/hal/i2s_ll.h +++ b/components/hal/esp32s2/include/hal/i2s_ll.h @@ -24,7 +24,9 @@ #include #include "soc/i2s_periph.h" +#include "soc/i2s_struct.h" #include "hal/i2s_types.h" +#include "hal/hal_defs.h" #ifdef __cplusplus extern "C" { @@ -416,7 +418,7 @@ static inline void i2s_ll_set_rx_eof_num(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_clkm_div_num(i2s_dev_t *hw, uint32_t val) { - hw->clkm_conf.clkm_div_num = val; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clkm_conf, clkm_div_num, val); } /** diff --git a/components/hal/esp32s2/include/hal/ledc_ll.h b/components/hal/esp32s2/include/hal/ledc_ll.h index 19d61f127f..677a2e36d3 100644 --- a/components/hal/esp32s2/include/hal/ledc_ll.h +++ b/components/hal/esp32s2/include/hal/ledc_ll.h @@ -19,6 +19,7 @@ #include "hal/ledc_types.h" #include "soc/ledc_periph.h" +#include "soc/ledc_struct.h" #ifdef __cplusplus extern "C" { diff --git a/components/hal/esp32s2/include/hal/mwdt_ll.h b/components/hal/esp32s2/include/hal/mwdt_ll.h index f909678b39..3d887129d9 100644 --- a/components/hal/esp32s2/include/hal/mwdt_ll.h +++ b/components/hal/esp32s2/include/hal/mwdt_ll.h @@ -24,7 +24,9 @@ extern "C" { #include #include #include "soc/timer_periph.h" +#include "soc/timer_group_struct.h" #include "hal/wdt_types.h" +#include "hal/hal_defs.h" #include "esp_attr.h" //Type check wdt_stage_action_t @@ -201,7 +203,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t* hw, bool enable) */ FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler) { - hw->wdt_config1.clk_prescale = prescaler; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdt_config1, clk_prescale, prescaler); } /** diff --git a/components/hal/esp32s2/include/hal/pcnt_ll.h b/components/hal/esp32s2/include/hal/pcnt_ll.h index 11dad5cf35..7aefe7faf8 100644 --- a/components/hal/esp32s2/include/hal/pcnt_ll.h +++ b/components/hal/esp32s2/include/hal/pcnt_ll.h @@ -23,6 +23,7 @@ #pragma once #include "soc/pcnt_periph.h" +#include "soc/pcnt_struct.h" #include "hal/pcnt_types.h" #ifdef __cplusplus diff --git a/components/hal/esp32s2/include/hal/rtc_io_ll.h b/components/hal/esp32s2/include/hal/rtc_io_ll.h index c519f70030..cdd19466b6 100644 --- a/components/hal/esp32s2/include/hal/rtc_io_ll.h +++ b/components/hal/esp32s2/include/hal/rtc_io_ll.h @@ -22,6 +22,8 @@ #include #include "soc/rtc_io_periph.h" +#include "soc/rtc_io_struct.h" +#include "soc/sens_struct.h" #include "hal/rtc_io_types.h" #include "hal/gpio_types.h" diff --git a/components/hal/esp32s2/include/hal/rwdt_ll.h b/components/hal/esp32s2/include/hal/rwdt_ll.h index 681c2fdf4f..148921836e 100644 --- a/components/hal/esp32s2/include/hal/rwdt_ll.h +++ b/components/hal/esp32s2/include/hal/rwdt_ll.h @@ -25,6 +25,8 @@ extern "C" { #include #include "hal/wdt_types.h" #include "soc/rtc_cntl_periph.h" +#include "soc/rtc_cntl_struct.h" +#include "hal/hal_defs.h" #include "soc/efuse_reg.h" #include "esp_attr.h" @@ -239,7 +241,7 @@ FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_en(rtc_cntl_dev_t* hw, bool enable */ FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_width(rtc_cntl_dev_t *hw, uint32_t width) { - hw->wdt_config0.chip_reset_width = width; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdt_config0, chip_reset_width, width); } /** diff --git a/components/hal/esp32s2/include/hal/sigmadelta_ll.h b/components/hal/esp32s2/include/hal/sigmadelta_ll.h index e06464a5ff..e0124b0df2 100644 --- a/components/hal/esp32s2/include/hal/sigmadelta_ll.h +++ b/components/hal/esp32s2/include/hal/sigmadelta_ll.h @@ -23,6 +23,7 @@ #include #include "soc/sigmadelta_periph.h" +#include "soc/gpio_sd_struct.h" #include "hal/sigmadelta_types.h" #ifdef __cplusplus diff --git a/components/hal/esp32s2/include/hal/spi_flash_ll.h b/components/hal/esp32s2/include/hal/spi_flash_ll.h index 000a2fcc0d..e0db83cbb5 100644 --- a/components/hal/esp32s2/include/hal/spi_flash_ll.h +++ b/components/hal/esp32s2/include/hal/spi_flash_ll.h @@ -24,6 +24,7 @@ #include "gpspi_flash_ll.h" #include "spimem_flash_ll.h" +#include "hal/hal_defs.h" #ifdef __cplusplus extern "C" { diff --git a/components/hal/esp32s2/include/hal/spi_ll.h b/components/hal/esp32s2/include/hal/spi_ll.h index d11fbcd98a..6b728503a3 100644 --- a/components/hal/esp32s2/include/hal/spi_ll.h +++ b/components/hal/esp32s2/include/hal/spi_ll.h @@ -27,6 +27,7 @@ #include "hal/hal_defs.h" #include "esp_types.h" #include "soc/spi_periph.h" +#include "soc/spi_struct.h" #include "esp32s2/rom/lldesc.h" #include "esp_attr.h" @@ -512,10 +513,10 @@ static inline void spi_ll_set_sio_mode(spi_dev_t *hw, int sio_mode) static inline void spi_ll_master_set_io_mode(spi_dev_t *hw, spi_ll_io_mode_t io_mode) { if (io_mode == SPI_LL_IO_MODE_DIO || io_mode == SPI_LL_IO_MODE_DUAL) { - hw->ctrl.fcmd_dual= (io_mode == SPI_LL_IO_MODE_DIO) ? 1 : 0; - hw->ctrl.faddr_dual= (io_mode == SPI_LL_IO_MODE_DIO) ? 1 : 0; - hw->ctrl.fread_dual=1; - hw->user.fwrite_dual=1; + hw->ctrl.fcmd_dual = (io_mode == SPI_LL_IO_MODE_DIO) ? 1 : 0; + hw->ctrl.faddr_dual = (io_mode == SPI_LL_IO_MODE_DIO) ? 1 : 0; + hw->ctrl.fread_dual = 1; + hw->user.fwrite_dual = 1; hw->ctrl.fcmd_quad = 0; hw->ctrl.faddr_quad = 0; hw->ctrl.fread_quad = 0; @@ -523,8 +524,8 @@ static inline void spi_ll_master_set_io_mode(spi_dev_t *hw, spi_ll_io_mode_t io_ } else if (io_mode == SPI_LL_IO_MODE_QIO || io_mode == SPI_LL_IO_MODE_QUAD) { hw->ctrl.fcmd_quad = (io_mode == SPI_LL_IO_MODE_QIO) ? 1 : 0; hw->ctrl.faddr_quad = (io_mode == SPI_LL_IO_MODE_QIO) ? 1 : 0; - hw->ctrl.fread_quad=1; - hw->user.fwrite_quad=1; + hw->ctrl.fread_quad = 1; + hw->user.fwrite_quad = 1; hw->ctrl.fcmd_dual = 0; hw->ctrl.faddr_dual = 0; hw->ctrl.fread_dual = 0; @@ -732,7 +733,7 @@ static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int dela static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n) { hw->user.usr_dummy = dummy_n ? 1 : 0; - hw->user1.usr_dummy_cyclelen = dummy_n - 1; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1); } /** @@ -893,13 +894,13 @@ static inline void spi_ll_set_command(spi_dev_t *hw, uint16_t cmd, int cmdlen, b { if (lsbfirst) { // The output command start from bit0 to bit 15, kept as is. - hw->user2.usr_command_value = cmd; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, cmd); } else { /* Output command will be sent from bit 7 to 0 of command_value, and * then bit 15 to 8 of the same register field. Shift and swap to send * more straightly. */ - hw->user2.usr_command_value = HAL_SPI_SWAP_DATA_TX(cmd, cmdlen); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user2, usr_command_value, HAL_SPI_SWAP_DATA_TX(cmd, cmdlen)); } } @@ -1069,7 +1070,7 @@ static inline int spi_ll_slave_get_rx_byte_len(spi_dev_t* hw) static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t* hw) { - return hw->slave1.last_addr; + return HAL_FORCE_READ_U32_REG_FIELD(hw->slave1, last_addr); } /*------------------------------------------------------------------------------ diff --git a/components/hal/esp32s2/include/hal/spimem_flash_ll.h b/components/hal/esp32s2/include/hal/spimem_flash_ll.h index b04020eb51..7e526a916b 100644 --- a/components/hal/esp32s2/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32s2/include/hal/spimem_flash_ll.h @@ -28,8 +28,10 @@ #include #include "soc/spi_periph.h" +#include "soc/spi_mem_struct.h" #include "hal/spi_types.h" #include "hal/spi_flash_types.h" +#include "hal/hal_defs.h" #ifdef __cplusplus extern "C" { @@ -167,7 +169,7 @@ static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint3 */ static inline void spimem_flash_ll_suspend_cmd_setup(spi_mem_dev_t *dev, uint32_t sus_cmd) { - dev->flash_sus_ctrl.flash_pes_command = sus_cmd; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, flash_pes_command, sus_cmd); } /** @@ -179,7 +181,7 @@ static inline void spimem_flash_ll_suspend_cmd_setup(spi_mem_dev_t *dev, uint32_ */ static inline void spimem_flash_ll_resume_cmd_setup(spi_mem_dev_t *dev, uint32_t res_cmd) { - dev->flash_sus_ctrl.flash_per_command = res_cmd; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, flash_per_command, res_cmd); } /** @@ -226,7 +228,7 @@ static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, bool */ static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool auto_waiti) { - dev->flash_waiti_ctrl.waiti_cmd = 0x05; // Set the command to send, to fetch flash status reg value. + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_waiti_ctrl, waiti_cmd, 0x05); // Set the command to send, to fetch flash status reg value. dev->flash_waiti_ctrl.waiti_en = auto_waiti; // enable auto wait-idle function. } @@ -516,7 +518,7 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n) { dev->user.usr_dummy = dummy_n ? 1 : 0; - dev->user1.usr_dummy_cyclelen = dummy_n - 1; + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1); } /** diff --git a/components/hal/esp32s2/include/hal/timer_ll.h b/components/hal/esp32s2/include/hal/timer_ll.h index 3e8bc1930f..1849064381 100644 --- a/components/hal/esp32s2/include/hal/timer_ll.h +++ b/components/hal/esp32s2/include/hal/timer_ll.h @@ -24,6 +24,7 @@ extern "C" { #include #include "hal/timer_types.h" #include "soc/timer_periph.h" +#include "soc/timer_group_struct.h" _Static_assert(TIMER_INTR_T0 == TIMG_T0_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t"); _Static_assert(TIMER_INTR_T1 == TIMG_T1_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t"); diff --git a/components/hal/esp32s2/include/hal/touch_sensor_ll.h b/components/hal/esp32s2/include/hal/touch_sensor_ll.h index 2fa8227153..7fbbd34da0 100644 --- a/components/hal/esp32s2/include/hal/touch_sensor_ll.h +++ b/components/hal/esp32s2/include/hal/touch_sensor_ll.h @@ -25,8 +25,12 @@ #include #include #include "soc/touch_sensor_periph.h" +#include "soc/rtc_cntl_struct.h" +#include "soc/rtc_io_struct.h" +#include "soc/sens_struct.h" #include "soc/soc_caps.h" #include "hal/touch_sensor_types.h" +#include "hal/hal_defs.h" #ifdef __cplusplus extern "C" { @@ -47,9 +51,9 @@ extern "C" { static inline void touch_ll_set_meas_times(uint16_t meas_time) { //The times of charge and discharge in each measure process of touch channels. - RTCCNTL.touch_ctrl1.touch_meas_num = meas_time; + HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_ctrl1, touch_meas_num, meas_time); //the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD - RTCCNTL.touch_ctrl2.touch_xpd_wait = SOC_TOUCH_PAD_MEASURE_WAIT_MAX; //wait volt stable + HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_ctrl2, touch_xpd_wait, SOC_TOUCH_PAD_MEASURE_WAIT_MAX); //wait volt stable } /** @@ -59,7 +63,7 @@ static inline void touch_ll_set_meas_times(uint16_t meas_time) */ static inline void touch_ll_get_measure_times(uint16_t *meas_time) { - *meas_time = RTCCNTL.touch_ctrl1.touch_meas_num; + *meas_time = HAL_FORCE_READ_U32_REG_FIELD(RTCCNTL.touch_ctrl1, touch_meas_num); } /** @@ -73,7 +77,7 @@ static inline void touch_ll_get_measure_times(uint16_t *meas_time) static inline void touch_ll_set_sleep_time(uint16_t sleep_time) { // touch sensor sleep cycle Time = sleep_cycle / RTC_SLOW_CLK(90k) - RTCCNTL.touch_ctrl1.touch_sleep_cycles = sleep_time; + HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_ctrl1, touch_sleep_cycles, sleep_time); } /** @@ -83,7 +87,7 @@ static inline void touch_ll_set_sleep_time(uint16_t sleep_time) */ static inline void touch_ll_get_sleep_time(uint16_t *sleep_time) { - *sleep_time = RTCCNTL.touch_ctrl1.touch_sleep_cycles; + *sleep_time = HAL_FORCE_READ_U32_REG_FIELD(RTCCNTL.touch_ctrl1, touch_sleep_cycles); } /** @@ -990,7 +994,7 @@ static inline void touch_ll_proximity_get_channel_num(touch_pad_t prox_pad[]) */ static inline void touch_ll_proximity_set_meas_times(uint32_t times) { - RTCCNTL.touch_approach.touch_approach_meas_time = times; + HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_approach, touch_approach_meas_time, times); } /** @@ -1000,7 +1004,7 @@ static inline void touch_ll_proximity_set_meas_times(uint32_t times) */ static inline void touch_ll_proximity_get_meas_times(uint32_t *times) { - *times = RTCCNTL.touch_approach.touch_approach_meas_time; + *times = HAL_FORCE_READ_U32_REG_FIELD(RTCCNTL.touch_approach, touch_approach_meas_time); } /** @@ -1011,11 +1015,11 @@ static inline void touch_ll_proximity_get_meas_times(uint32_t *times) static inline void touch_ll_proximity_read_meas_cnt(touch_pad_t touch_num, uint32_t *cnt) { if (SENS.sar_touch_conf.touch_approach_pad0 == touch_num) { - *cnt = SENS.sar_touch_appr_status.touch_approach_pad0_cnt; + *cnt = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_approach_pad0_cnt); } else if (SENS.sar_touch_conf.touch_approach_pad1 == touch_num) { - *cnt = SENS.sar_touch_appr_status.touch_approach_pad1_cnt; + *cnt = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_approach_pad1_cnt); } else if (SENS.sar_touch_conf.touch_approach_pad2 == touch_num) { - *cnt = SENS.sar_touch_appr_status.touch_approach_pad2_cnt; + *cnt = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_approach_pad2_cnt); } } @@ -1163,7 +1167,7 @@ static inline void touch_ll_sleep_read_debounce(uint32_t *debounce) */ static inline void touch_ll_sleep_read_proximity_cnt(uint32_t *approach_cnt) { - *approach_cnt = SENS.sar_touch_appr_status.touch_slp_approach_cnt; + *approach_cnt = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_slp_approach_cnt); } /** diff --git a/components/hal/esp32s2/include/hal/twai_ll.h b/components/hal/esp32s2/include/hal/twai_ll.h index 8f8325d1d4..0dd352757c 100644 --- a/components/hal/esp32s2/include/hal/twai_ll.h +++ b/components/hal/esp32s2/include/hal/twai_ll.h @@ -30,6 +30,8 @@ extern "C" { #include #include "hal/twai_types.h" #include "soc/twai_periph.h" +#include "soc/twai_struct.h" +#include "hal/hal_defs.h" /* ------------------------- Defines and Typedefs --------------------------- */ @@ -398,7 +400,7 @@ static inline void twai_ll_clear_err_code_cap(twai_dev_t *hw) */ static inline void twai_ll_set_err_warn_lim(twai_dev_t *hw, uint32_t ewl) { - hw->error_warning_limit_reg.ewl = ewl; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->error_warning_limit_reg, ewl, ewl); } /** @@ -438,7 +440,7 @@ static inline uint32_t twai_ll_get_rec(twai_dev_t *hw) */ static inline void twai_ll_set_rec(twai_dev_t *hw, uint32_t rec) { - hw->rx_error_counter_reg.rxerr = rec; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_error_counter_reg, rxerr, rec); } /* ------------------------ TX Error Count Register ------------------------- */ @@ -466,7 +468,7 @@ static inline uint32_t twai_ll_get_tec(twai_dev_t *hw) */ static inline void twai_ll_set_tec(twai_dev_t *hw, uint32_t tec) { - hw->tx_error_counter_reg.txerr = tec; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_error_counter_reg, txerr, tec); } /* ---------------------- Acceptance Filter Registers ----------------------- */ @@ -651,14 +653,14 @@ static inline void twai_ll_set_clkout(twai_dev_t *hw, uint32_t divider) { if (divider >= 2 && divider <= 490) { hw->clock_divider_reg.co = 0; - hw->clock_divider_reg.cd = (divider / 2) - 1; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, (divider / 2) - 1); } else if (divider == 1) { //Setting the divider reg to max value (255) means a divider of 1 hw->clock_divider_reg.co = 0; - hw->clock_divider_reg.cd = 255; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 255); } else { hw->clock_divider_reg.co = 1; - hw->clock_divider_reg.cd = 0; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 0); } } diff --git a/components/hal/esp32s2/include/hal/uart_ll.h b/components/hal/esp32s2/include/hal/uart_ll.h index 6ece3e4084..4b9bc776a0 100644 --- a/components/hal/esp32s2/include/hal/uart_ll.h +++ b/components/hal/esp32s2/include/hal/uart_ll.h @@ -19,6 +19,8 @@ #pragma once #include "hal/uart_types.h" #include "soc/uart_periph.h" +#include "soc/uart_struct.h" +#include "hal/hal_defs.h" #include "esp_attr.h" #ifdef __cplusplus @@ -403,7 +405,7 @@ FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num) { if(break_num > 0) { - hw->idle_conf.tx_brk_num = break_num; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->idle_conf, tx_brk_num, break_num); hw->conf0.txd_brk = 1; } else { hw->conf0.txd_brk = 0; @@ -470,8 +472,8 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl hw->flow_conf.sw_flow_con_en = 1; hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd; hw->swfc_conf0.xoff_threshold = flow_ctrl->xoff_thrd; - hw->swfc_conf1.xon_char = flow_ctrl->xon_char; - hw->swfc_conf0.xoff_char = flow_ctrl->xoff_char; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_char, flow_ctrl->xon_char); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0, xoff_char, flow_ctrl->xoff_char); } else { hw->flow_conf.sw_flow_con_en = 0; hw->flow_conf.xonoff_del = 0; @@ -493,11 +495,11 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl */ FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char) { - hw->at_cmd_char.data = cmd_char->cmd_char; - hw->at_cmd_char.char_num = cmd_char->char_num; - hw->at_cmd_postcnt.post_idle_num = cmd_char->post_idle; - hw->at_cmd_precnt.pre_idle_num = cmd_char->pre_idle; - hw->at_cmd_gaptout.rx_gap_tout = cmd_char->gap_tout; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt, post_idle_num, cmd_char->post_idle); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt, pre_idle_num, cmd_char->pre_idle); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout, rx_gap_tout, cmd_char->gap_tout); } /** @@ -679,8 +681,8 @@ FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) */ FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num) { - *cmd_char = hw->at_cmd_char.data; - *char_num = hw->at_cmd_char.char_num; + *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, data); + *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, char_num); } /** diff --git a/components/hal/esp32s2/include/hal/usb_ll.h b/components/hal/esp32s2/include/hal/usb_ll.h index 5496d7a6d1..ffd648923d 100644 --- a/components/hal/esp32s2/include/hal/usb_ll.h +++ b/components/hal/esp32s2/include/hal/usb_ll.h @@ -17,6 +17,7 @@ #include "soc/system_reg.h" #include "soc/gpio_sig_map.h" #include "soc/usb_periph.h" +#include "soc/usb_wrap_struct.h" static inline void usb_ll_int_phy_enable(void) { diff --git a/components/hal/esp32s2/include/hal/usbh_ll.h b/components/hal/esp32s2/include/hal/usbh_ll.h index aa26cb6fba..bcb1b19cd4 100644 --- a/components/hal/esp32s2/include/hal/usbh_ll.h +++ b/components/hal/esp32s2/include/hal/usbh_ll.h @@ -23,6 +23,7 @@ extern "C" { #include "soc/usbh_struct.h" #include "soc/usb_wrap_struct.h" #include "hal/usb_types.h" +#include "hal/hal_defs.h" /* ----------------------------------------------------------------------------- ------------------------------- Global Registers ------------------------------- @@ -311,7 +312,7 @@ static inline void usb_ll_dis_intrs(usbh_dev_t *hw, uint32_t intr_mask) static inline void usb_ll_set_rx_fifo_size(usbh_dev_t *hw, uint32_t size) { //Set size in words - hw->grxfsiz_reg.rxfdep = size; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->grxfsiz_reg, rxfdep, size); } // -------------------------- GNPTXFSIZ Register ------------------------------- @@ -430,7 +431,7 @@ static inline void usbh_ll_hfir_set_defaults(usbh_dev_t *hw) static inline uint32_t usbh_ll_get_frm_time_rem(usbh_dev_t *hw) { - return hw->hfnum_reg.frrem; + return HAL_FORCE_READ_U32_REG_FIELD(hw->hfnum_reg, frrem); } static inline uint32_t usbh_ll_get_frm_num(usbh_dev_t *hw) @@ -442,7 +443,7 @@ static inline uint32_t usbh_ll_get_frm_num(usbh_dev_t *hw) static inline uint32_t usbh_ll_get_p_tx_queue_top(usbh_dev_t *hw) { - return hw->hptxsts_reg.ptxqtop; + return HAL_FORCE_READ_U32_REG_FIELD(hw->hptxsts_reg, ptxqtop); } static inline uint32_t usbh_ll_get_p_tx_queue_space_avail(usbh_dev_t *hw) @@ -452,14 +453,14 @@ static inline uint32_t usbh_ll_get_p_tx_queue_space_avail(usbh_dev_t *hw) static inline uint32_t usbh_ll_get_p_tx_fifo_space_avail(usbh_dev_t *hw) { - return hw->hptxsts_reg.ptxfspcavail; + return HAL_FORCE_READ_U32_REG_FIELD(hw->hptxsts_reg, ptxfspcavail); } // ----------------------------- HAINT Register -------------------------------- static inline uint32_t usbh_ll_get_chan_intrs_msk(usbh_dev_t *hw) { - return hw->haint_reg.haint; + return HAL_FORCE_READ_U32_REG_FIELD(hw->haint_reg, haint); } // --------------------------- HAINTMSK Register ------------------------------- diff --git a/components/hal/include/hal/hal_defs.h b/components/hal/include/hal/hal_defs.h index f209ac09c9..30ee882a9a 100644 --- a/components/hal/include/hal/hal_defs.h +++ b/components/hal/include/hal/hal_defs.h @@ -28,3 +28,44 @@ #define HAL_LOGV(...) ESP_LOGV(__VA_ARGS__) #define STATIC_HAL_REG_CHECK(TAG, ENUM, VAL) _Static_assert((ENUM) == (VAL), #TAG" "#ENUM" definition no longer matches register value") + +/** @cond */ //Doxy command to hide preprocessor definitions from docs */ + +/** + * @brief Macro to force a 32-bit read, modify, then write on a peripheral register + * + * Due to a GCC bug, the compiler may still try to optimize read/writes to peripheral register fields by using 8/16 bit + * access, even if they are marked volatile (i.e., -fstrict-volatile-bitfields has no effect). + * + * For ESP chips, the peripheral bus only allows 32-bit read/writes. The following macro works around the compiler issue + * by forcing a 32-bit read/modify/write. + * + * @note This macro should only be called on register fields of xxx_struct.h type headers, as it depends on the presence + * of a 'val' field of the register union. + * @note Current implementation reads into a uint32_t instead of copy base_reg direclty to temp_reg. The reason being + * that C++ does not create a copy constructor for volatile structs. + */ +#define HAL_FORCE_MODIFY_U32_REG_FIELD(base_reg, reg_field, field_val) \ +{ \ + uint32_t temp_val = base_reg.val; \ + typeof(base_reg) temp_reg; \ + temp_reg.val = temp_val; \ + temp_reg.reg_field = (field_val); \ + (base_reg).val = temp_reg.val; \ +} + +/** + * @brief Macro to force a 32-bit read on a peripheral register + * + * @note This macro should only be called on register fields of xxx_struct.h type headers. See description above for + * more details. + * @note Current implementation reads into a uint32_t. See description above for more details. + */ +#define HAL_FORCE_READ_U32_REG_FIELD(base_reg, reg_field) ({ \ + uint32_t temp_val = base_reg.val; \ + typeof(base_reg) temp_reg; \ + temp_reg.val = temp_val; \ + temp_reg.reg_field; \ +}) + +/** @endcond */ diff --git a/components/soc/esp32/include/soc/emac_dma_struct.h b/components/soc/esp32/include/soc/emac_dma_struct.h index 35d1361281..1f9a9832e1 100644 --- a/components/soc/esp32/include/soc/emac_dma_struct.h +++ b/components/soc/esp32/include/soc/emac_dma_struct.h @@ -20,7 +20,7 @@ extern "C" #include -typedef volatile struct { +typedef volatile struct emac_dma_dev_s { union { struct { uint32_t sw_rst : 1; /*When this bit is set the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the ETH_MAC clock domains. Before reprogramming any register of the ETH_MAC you should read a zero (0) value in this bit.*/ diff --git a/components/soc/esp32/include/soc/emac_ext_struct.h b/components/soc/esp32/include/soc/emac_ext_struct.h index 9b65c8d91c..5d2e1fecf5 100644 --- a/components/soc/esp32/include/soc/emac_ext_struct.h +++ b/components/soc/esp32/include/soc/emac_ext_struct.h @@ -19,7 +19,7 @@ extern "C" { #include -typedef volatile struct { +typedef volatile struct emac_ext_dev_s { union { struct { uint32_t div_num : 4; diff --git a/components/soc/esp32/include/soc/emac_mac_struct.h b/components/soc/esp32/include/soc/emac_mac_struct.h index b7f5b80ff5..a798b00f99 100644 --- a/components/soc/esp32/include/soc/emac_mac_struct.h +++ b/components/soc/esp32/include/soc/emac_mac_struct.h @@ -19,7 +19,7 @@ extern "C" { #include -typedef volatile struct { +typedef volatile struct emac_mac_dev_s { union { struct { uint32_t pltf : 2; /*These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.2'b00: 7 bytes of preamble. 2'b01: 5 bytes of preamble. 2'b10: 3 bytes of preamble.*/ diff --git a/components/soc/esp32/include/soc/i2c_struct.h b/components/soc/esp32/include/soc/i2c_struct.h index 3b17aeb463..3904248b6b 100644 --- a/components/soc/esp32/include/soc/i2c_struct.h +++ b/components/soc/esp32/include/soc/i2c_struct.h @@ -104,8 +104,8 @@ typedef volatile struct i2c_dev_s { } fifo_conf; union { struct { - uint8_t data; /*The register represent the byte data read from rx_fifo when use apb fifo access*/ - uint8_t reserved[3]; + uint32_t data: 8; /*The register represent the byte data read from rx_fifo when use apb fifo access*/ + uint32_t reserved8: 24; }; uint32_t val; } fifo_data; diff --git a/components/soc/esp32/include/soc/pcnt_struct.h b/components/soc/esp32/include/soc/pcnt_struct.h index caeb02ac23..ecb79f3f4f 100644 --- a/components/soc/esp32/include/soc/pcnt_struct.h +++ b/components/soc/esp32/include/soc/pcnt_struct.h @@ -21,7 +21,7 @@ extern "C" { #endif typedef volatile struct pcnt_dev_s { - struct{ + struct { union { struct { uint32_t filter_thres: 10; /*This register is used to filter pulse whose width is smaller than this value for unit0.*/ diff --git a/components/soc/esp32/include/soc/rmt_struct.h b/components/soc/esp32/include/soc/rmt_struct.h index 9736a28a77..fd1815a498 100644 --- a/components/soc/esp32/include/soc/rmt_struct.h +++ b/components/soc/esp32/include/soc/rmt_struct.h @@ -24,7 +24,7 @@ typedef volatile struct rmt_dev_s { uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access. Note that in some circumstances, data read from the FIFO may get lost. As RMT memory area accesses using the RMTMEM method do not have this issue and provide all the functionality that the FIFO register has, it is encouraged to use that instead.*/ - struct{ + struct { union { struct { uint32_t div_cnt: 8; /*This register is used to configure the frequency divider's factor in channel0-7.*/ @@ -250,9 +250,7 @@ typedef struct rmt_item32_s { //Allow access to RMT memory using RMTMEM.chan[0].data32[8] typedef volatile struct rmt_mem_s { struct { - union { - rmt_item32_t data32[64]; - }; + rmt_item32_t data32[64]; } chan[8]; } rmt_mem_t; extern rmt_mem_t RMTMEM; diff --git a/components/soc/esp32/include/soc/sdmmc_struct.h b/components/soc/esp32/include/soc/sdmmc_struct.h index 8a3bd8fcf6..90c6e3a9ff 100644 --- a/components/soc/esp32/include/soc/sdmmc_struct.h +++ b/components/soc/esp32/include/soc/sdmmc_struct.h @@ -23,18 +23,22 @@ extern "C" { #endif typedef struct sdmmc_desc_s { - uint32_t reserved1: 1; - uint32_t disable_int_on_completion: 1; - uint32_t last_descriptor: 1; - uint32_t first_descriptor: 1; - uint32_t second_address_chained: 1; - uint32_t end_of_ring: 1; - uint32_t reserved2: 24; - uint32_t card_error_summary: 1; - uint32_t owned_by_idmac: 1; - uint32_t buffer1_size: 13; - uint32_t buffer2_size: 13; - uint32_t reserved3: 6; + struct { + uint32_t reserved1: 1; + uint32_t disable_int_on_completion: 1; + uint32_t last_descriptor: 1; + uint32_t first_descriptor: 1; + uint32_t second_address_chained: 1; + uint32_t end_of_ring: 1; + uint32_t reserved2: 24; + uint32_t card_error_summary: 1; + uint32_t owned_by_idmac: 1; + }; + struct { + uint32_t buffer1_size: 13; + uint32_t buffer2_size: 13; + uint32_t reserved3: 6; + }; void* buffer1_ptr; union { void* buffer2_ptr; @@ -146,8 +150,10 @@ typedef volatile struct sdmmc_dev_s { uint32_t val; } ctype; - uint32_t blksiz: 16; ///< block size, default 0x200 - uint32_t : 16; + struct { + uint32_t blksiz: 16; ///< block size, default 0x200 + uint32_t reserved16: 16; + }; uint32_t bytcnt; ///< number of bytes to be transferred @@ -326,6 +332,7 @@ typedef volatile struct sdmmc_dev_s { uint32_t ces: 1; ///< card error summary uint32_t reserved2: 2; uint32_t nis: 1; ///< normal interrupt summary + uint32_t ais: 1; ///< abnormal interrupt summary uint32_t fbe_code: 3; ///< code of fatal bus error uint32_t fsm: 4; ///< DMAC FSM state uint32_t reserved3: 15; @@ -362,6 +369,7 @@ typedef volatile struct sdmmc_dev_s { uint32_t write_thr_en : 1; ///< equivalent of read_thr_en for writes uint32_t reserved1 : 13; uint32_t card_threshold : 12; ///< threshold value for reads/writes, in bytes + uint32_t reserved28: 4; }; uint32_t val; } cardthrctl; @@ -378,6 +386,7 @@ typedef volatile struct sdmmc_dev_s { uint32_t div_factor_p: 4; ///< controls clock period; it will be (div_factor_p + 1) / 160MHz uint32_t div_factor_h: 4; ///< controls length of high pulse; it will be (div_factor_h + 1) / 160MHz uint32_t div_factor_m: 4; ///< should be equal to div_factor_p + uint32_t reserved21: 11; }; uint32_t val; } clock; diff --git a/components/soc/esp32/include/soc/timer_group_struct.h b/components/soc/esp32/include/soc/timer_group_struct.h index 4ea1abe75d..ec43f6d7a3 100644 --- a/components/soc/esp32/include/soc/timer_group_struct.h +++ b/components/soc/esp32/include/soc/timer_group_struct.h @@ -21,7 +21,7 @@ extern "C" { #endif typedef volatile struct timg_dev_s { - struct{ + struct { union { struct { uint32_t reserved0: 10; diff --git a/components/soc/esp32/include/soc/twai_struct.h b/components/soc/esp32/include/soc/twai_struct.h index e9454e1cc5..a6844eb068 100644 --- a/components/soc/esp32/include/soc/twai_struct.h +++ b/components/soc/esp32/include/soc/twai_struct.h @@ -178,7 +178,7 @@ typedef volatile struct twai_dev_s { }; uint32_t val; } tx_rx_buffer[13]; - }; /* Address 16-28 TX/RX Buffer and Acc Filter*/; + }; /* Address 16-28 TX/RX Buffer and Acc Filter*/ //Misc Registers union { diff --git a/components/soc/esp32/include/soc/uart_struct.h b/components/soc/esp32/include/soc/uart_struct.h index 7dc9b5144c..0eb59a5603 100644 --- a/components/soc/esp32/include/soc/uart_struct.h +++ b/components/soc/esp32/include/soc/uart_struct.h @@ -23,8 +23,7 @@ extern "C" { typedef volatile struct uart_dev_s { union { struct { - uint8_t rw_byte; /*This register stores one byte data read by rx fifo.*/ - uint8_t reserved[3]; + uint32_t rw_byte; /*This register stores one byte data read by rx fifo.*/ }; uint32_t val; } fifo; diff --git a/components/soc/esp32/include/soc/uhci_struct.h b/components/soc/esp32/include/soc/uhci_struct.h index 3f42536c31..764268b35a 100644 --- a/components/soc/esp32/include/soc/uhci_struct.h +++ b/components/soc/esp32/include/soc/uhci_struct.h @@ -277,7 +277,7 @@ typedef volatile struct uhci_dev_s { }; uint32_t val; } quick_sent; - struct{ + struct { uint32_t w_data[2]; /*This register stores the content of short packet's dword*/ } q_data[7]; union { diff --git a/components/soc/esp32c3/include/soc/apb_ctrl_struct.h b/components/soc/esp32c3/include/soc/apb_ctrl_struct.h index 9b832df8dd..dd20d37894 100644 --- a/components/soc/esp32c3/include/soc/apb_ctrl_struct.h +++ b/components/soc/esp32c3/include/soc/apb_ctrl_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct apb_ctrl_dev_s { union { struct { uint32_t pre_div: 10; diff --git a/components/soc/esp32c3/include/soc/apb_saradc_struct.h b/components/soc/esp32c3/include/soc/apb_saradc_struct.h index c3ea73f150..c75e582f7d 100644 --- a/components/soc/esp32c3/include/soc/apb_saradc_struct.h +++ b/components/soc/esp32c3/include/soc/apb_saradc_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct apb_saradc_dev_s { union { struct { uint32_t start_force: 1; diff --git a/components/soc/esp32c3/include/soc/efuse_struct.h b/components/soc/esp32c3/include/soc/efuse_struct.h index 1c51e71475..eed9c2544f 100644 --- a/components/soc/esp32c3/include/soc/efuse_struct.h +++ b/components/soc/esp32c3/include/soc/efuse_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct efuse_dev_s { uint32_t pgm_data0; /*Register 0 that stores data to be programmed.*/ union { struct { diff --git a/components/soc/esp32c3/include/soc/gdma_struct.h b/components/soc/esp32c3/include/soc/gdma_struct.h index 446ff4c112..dde520f5ed 100644 --- a/components/soc/esp32c3/include/soc/gdma_struct.h +++ b/components/soc/esp32c3/include/soc/gdma_struct.h @@ -19,7 +19,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct gdma_dev_s { struct { union { struct { diff --git a/components/soc/esp32c3/include/soc/gpio_sd_struct.h b/components/soc/esp32c3/include/soc/gpio_sd_struct.h index cc73cebd03..45e21d58e1 100644 --- a/components/soc/esp32c3/include/soc/gpio_sd_struct.h +++ b/components/soc/esp32c3/include/soc/gpio_sd_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct gpio_sd_dev_s { union { struct { uint32_t duty: 8; diff --git a/components/soc/esp32c3/include/soc/gpio_struct.h b/components/soc/esp32c3/include/soc/gpio_struct.h index f260adbd2a..45f5e55412 100644 --- a/components/soc/esp32c3/include/soc/gpio_struct.h +++ b/components/soc/esp32c3/include/soc/gpio_struct.h @@ -18,7 +18,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct gpio_dev_s { uint32_t bt_select; /**/ union { struct { diff --git a/components/soc/esp32c3/include/soc/i2c_struct.h b/components/soc/esp32c3/include/soc/i2c_struct.h index 22c6c47041..ccd5fdb5b0 100644 --- a/components/soc/esp32c3/include/soc/i2c_struct.h +++ b/components/soc/esp32c3/include/soc/i2c_struct.h @@ -20,7 +20,7 @@ extern "C" { #endif #include "soc.h" -typedef volatile struct { +typedef volatile struct i2c_dev_s { union { struct { uint32_t period : 9; diff --git a/components/soc/esp32c3/include/soc/i2s_struct.h b/components/soc/esp32c3/include/soc/i2s_struct.h index 2f9c862b85..44334a8789 100644 --- a/components/soc/esp32c3/include/soc/i2s_struct.h +++ b/components/soc/esp32c3/include/soc/i2s_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct i2s_dev_s { uint32_t reserved_0; uint32_t reserved_4; uint32_t reserved_8; diff --git a/components/soc/esp32c3/include/soc/ledc_struct.h b/components/soc/esp32c3/include/soc/ledc_struct.h index 9e5a2a96c1..0eb8c18268 100644 --- a/components/soc/esp32c3/include/soc/ledc_struct.h +++ b/components/soc/esp32c3/include/soc/ledc_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct ledc_dev_s { struct { struct { union { diff --git a/components/soc/esp32c3/include/soc/rmt_struct.h b/components/soc/esp32c3/include/soc/rmt_struct.h index 7fc1890b12..b9b7533b3d 100644 --- a/components/soc/esp32c3/include/soc/rmt_struct.h +++ b/components/soc/esp32c3/include/soc/rmt_struct.h @@ -20,7 +20,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct rmt_dev_s { uint32_t data_ch[4]; /**/ union { struct { @@ -291,11 +291,9 @@ typedef struct { } rmt_item32_t; //Allow access to RMT memory using RMTMEM.chan[0].data32[8] -typedef volatile struct { +typedef volatile struct rmt_mem_s { struct { - union { - rmt_item32_t data32[48]; - }; + rmt_item32_t data32[48]; } chan[4]; } rmt_mem_t; diff --git a/components/soc/esp32c3/include/soc/rtc_cntl_struct.h b/components/soc/esp32c3/include/soc/rtc_cntl_struct.h index 358ebaded7..9478048648 100644 --- a/components/soc/esp32c3/include/soc/rtc_cntl_struct.h +++ b/components/soc/esp32c3/include/soc/rtc_cntl_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct rtc_cntl_dev_s { union { struct { uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ diff --git a/components/soc/esp32c3/include/soc/rtc_i2c_struct.h b/components/soc/esp32c3/include/soc/rtc_i2c_struct.h index 5141eebcd6..9f97a70cad 100644 --- a/components/soc/esp32c3/include/soc/rtc_i2c_struct.h +++ b/components/soc/esp32c3/include/soc/rtc_i2c_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct rtc_i2c_dev_s { union { struct { uint32_t period: 20; /*time period that scl = 0*/ diff --git a/components/soc/esp32c3/include/soc/sensitive_struct.h b/components/soc/esp32c3/include/soc/sensitive_struct.h index a24ccf6402..a48263b0bc 100644 --- a/components/soc/esp32c3/include/soc/sensitive_struct.h +++ b/components/soc/esp32c3/include/soc/sensitive_struct.h @@ -20,7 +20,7 @@ extern "C" { #endif #include "soc.h" -typedef volatile struct { +typedef volatile struct sensitive_dev_s { union { struct { uint32_t reg_rom_table_lock : 1; /*rom_table_lock*/ @@ -960,10 +960,9 @@ typedef volatile struct { struct { uint32_t reg_clk_en : 1; /*clk_en*/ uint32_t reserved1 : 31; - uint32_t reservedNone : None; /*SENSITIVE_CLOCK_GATE_REG_REG*/ }; uint32_t val; - } clock_gate; + } clock_gate; /*SENSITIVE_CLOCK_GATE_REG_REG*/ uint32_t reserved_174; uint32_t reserved_178; uint32_t reserved_17c; diff --git a/components/soc/esp32c3/include/soc/spi_mem_struct.h b/components/soc/esp32c3/include/soc/spi_mem_struct.h index e0f62b0d15..cde08c0207 100644 --- a/components/soc/esp32c3/include/soc/spi_mem_struct.h +++ b/components/soc/esp32c3/include/soc/spi_mem_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct spi_mem_dev_s { union { struct { uint32_t mst_st: 4; /*The current status of SPI1 master FSM.*/ diff --git a/components/soc/esp32c3/include/soc/spi_struct.h b/components/soc/esp32c3/include/soc/spi_struct.h index 24844d58ba..1823621492 100644 --- a/components/soc/esp32c3/include/soc/spi_struct.h +++ b/components/soc/esp32c3/include/soc/spi_struct.h @@ -20,7 +20,7 @@ extern "C" { #endif #include "soc.h" -typedef volatile struct { +typedef volatile struct spi_dev_s { union { struct { uint32_t conf_bitlen : 18; /*Define the APB cycles of SPI_CONF state. Can be configured in CONF state.*/ diff --git a/components/soc/esp32c3/include/soc/syscon_struct.h b/components/soc/esp32c3/include/soc/syscon_struct.h index 2a9485aa87..4be6b7f791 100644 --- a/components/soc/esp32c3/include/soc/syscon_struct.h +++ b/components/soc/esp32c3/include/soc/syscon_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct syscon_dev_s { union { struct { uint32_t apb_ctrl_pre_div_cnt: 10; diff --git a/components/soc/esp32c3/include/soc/system_struct.h b/components/soc/esp32c3/include/soc/system_struct.h index f07fab0aff..5e04cec828 100644 --- a/components/soc/esp32c3/include/soc/system_struct.h +++ b/components/soc/esp32c3/include/soc/system_struct.h @@ -20,7 +20,7 @@ extern "C" { #endif #include "soc.h" -typedef volatile struct { +typedef volatile struct system_dev_s { union { struct { uint32_t reserved0 : 6; /*reserved*/ diff --git a/components/soc/esp32c3/include/soc/systimer_struct.h b/components/soc/esp32c3/include/soc/systimer_struct.h index b029eca80b..9aaa5562c9 100644 --- a/components/soc/esp32c3/include/soc/systimer_struct.h +++ b/components/soc/esp32c3/include/soc/systimer_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct sys_timer_dev_s { union { struct { uint32_t systimer_clk_fo: 1; /*systimer clock force on*/ diff --git a/components/soc/esp32c3/include/soc/timer_group_struct.h b/components/soc/esp32c3/include/soc/timer_group_struct.h index e69f1fe777..a7ffb985a1 100644 --- a/components/soc/esp32c3/include/soc/timer_group_struct.h +++ b/components/soc/esp32c3/include/soc/timer_group_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct timg_dev_s { struct { union { struct { diff --git a/components/soc/esp32c3/include/soc/twai_struct.h b/components/soc/esp32c3/include/soc/twai_struct.h index 64cb80e5ed..8f73c0c55a 100644 --- a/components/soc/esp32c3/include/soc/twai_struct.h +++ b/components/soc/esp32c3/include/soc/twai_struct.h @@ -179,7 +179,7 @@ typedef volatile struct twai_dev_s { }; uint32_t val; } tx_rx_buffer[13]; - }; /* Address 16-28 TX/RX Buffer and Acc Filter*/; + }; /* Address 16-28 TX/RX Buffer and Acc Filter*/ //Misc Registers union { diff --git a/components/soc/esp32c3/include/soc/uart_struct.h b/components/soc/esp32c3/include/soc/uart_struct.h index ad9ca42ff7..82f8ef6686 100644 --- a/components/soc/esp32c3/include/soc/uart_struct.h +++ b/components/soc/esp32c3/include/soc/uart_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct uart_dev_s { union { struct { uint32_t rw_byte; /*a*/ diff --git a/components/soc/esp32c3/include/soc/uhci_struct.h b/components/soc/esp32c3/include/soc/uhci_struct.h index a89c4d0126..164f1a1334 100644 --- a/components/soc/esp32c3/include/soc/uhci_struct.h +++ b/components/soc/esp32c3/include/soc/uhci_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct uhci_dev_s { union { struct { uint32_t tx_rst: 1; /*Write 1 then write 0 to this bit to reset decode state machine.*/ diff --git a/components/soc/esp32s2/include/soc/apb_ctrl_struct.h b/components/soc/esp32s2/include/soc/apb_ctrl_struct.h index d05c2c9a00..dbf2e4e3ef 100644 --- a/components/soc/esp32s2/include/soc/apb_ctrl_struct.h +++ b/components/soc/esp32s2/include/soc/apb_ctrl_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct apb_ctrl_dev_s { union { struct { uint32_t pre_div: 10; diff --git a/components/soc/esp32s2/include/soc/apb_saradc_struct.h b/components/soc/esp32s2/include/soc/apb_saradc_struct.h index e9811dab60..505596f994 100644 --- a/components/soc/esp32s2/include/soc/apb_saradc_struct.h +++ b/components/soc/esp32s2/include/soc/apb_saradc_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct apb_saradc_dev_s { union { struct { uint32_t start_force: 1; diff --git a/components/soc/esp32s2/include/soc/cp_dma_struct.h b/components/soc/esp32s2/include/soc/cp_dma_struct.h index 208c82939c..15fb42e451 100644 --- a/components/soc/esp32s2/include/soc/cp_dma_struct.h +++ b/components/soc/esp32s2/include/soc/cp_dma_struct.h @@ -69,6 +69,7 @@ typedef union { * This is the interrupt raw bit. Triggered when crc calculation is done. */ uint32_t dma_crc_done_int_raw: 1; + uint32_t reserved9: 23; }; uint32_t val; } cp_dma_int_raw_reg_t; @@ -123,6 +124,7 @@ typedef union { * cp_crc_done_int_ena is set to 1. */ uint32_t dma_crc_done_int_st: 1; + uint32_t reserved9: 23; }; uint32_t val; } cp_dma_int_st_reg_t; @@ -168,6 +170,7 @@ typedef union { * This is the interrupt enable bit for cp_crc_done_int interrupt. */ uint32_t dma_crc_done_int_ena: 1; + uint32_t reserved9: 23; }; uint32_t val; } cp_dma_int_ena_reg_t; @@ -213,6 +216,7 @@ typedef union { * Set this bit to clear cp_crc_done_int interrupt. */ uint32_t dma_crc_done_int_clr: 1; + uint32_t reserved9: 23; }; uint32_t val; } cp_dma_int_clr_reg_t; @@ -491,6 +495,7 @@ typedef union { * Copy DMA FIFO empty signal. */ uint32_t dma_fifo_empty: 1; + uint32_t reserved24: 8; }; uint32_t val; } cp_dma_in_st_reg_t; @@ -516,6 +521,7 @@ typedef union { * Copy DMA FIFO full signal. */ uint32_t dma_fifo_full: 1; + uint32_t reserved24: 8; }; uint32_t val; } cp_dma_out_st_reg_t; diff --git a/components/soc/esp32s2/include/soc/dedic_gpio_struct.h b/components/soc/esp32s2/include/soc/dedic_gpio_struct.h index 3ccd588b97..04aae779ad 100644 --- a/components/soc/esp32s2/include/soc/dedic_gpio_struct.h +++ b/components/soc/esp32s2/include/soc/dedic_gpio_struct.h @@ -31,6 +31,7 @@ typedef union { * gpio. */ uint32_t gpio_out_drt_vlaue: 8; + uint32_t reserved8: 24; }; uint32_t val; } dedic_gpio_out_drt_reg_t; @@ -49,6 +50,7 @@ typedef union { * channel's output would be masked. */ uint32_t gpio_out_msk: 8; + uint32_t reserved16: 16; }; uint32_t val; } dedic_gpio_out_msk_reg_t; @@ -98,6 +100,7 @@ typedef union { * clear output value; 3: inverse output value. */ uint32_t gpio_out_idv_ch7: 2; + uint32_t reserved16: 16; }; uint32_t val; } dedic_gpio_out_idv_reg_t; @@ -147,6 +150,7 @@ typedef union { * select CPU instructors. */ uint32_t gpio_out_cpu_sel7: 1; + uint32_t reserved8: 24; }; uint32_t val; } dedic_gpio_out_cpu_reg_t; @@ -196,6 +200,7 @@ typedef union { * 3: three clock delay. */ uint32_t gpio_in_dly_ch7: 2; + uint32_t reserved16: 16; }; uint32_t val; } dedic_gpio_in_dly_reg_t; @@ -285,6 +290,7 @@ typedef union { * 6/7: falling and raising edge trigger. */ uint32_t gpio_intr_mode_ch7: 3; + uint32_t reserved24: 8; }; uint32_t val; } dedic_gpio_intr_rcgn_reg_t; @@ -301,6 +307,7 @@ typedef union { * DEDIC_GPIO_OUT_IDV_REG. */ uint32_t gpio_out_status: 8; + uint32_t reserved8: 24; }; uint32_t val; } dedic_gpio_out_scan_reg_t; @@ -314,6 +321,7 @@ typedef union { * gpio in value after configured by DEDIC_GPIO_IN_DLY_REG. */ uint32_t gpio_in_status: 8; + uint32_t reserved8: 24; }; uint32_t val; } dedic_gpio_in_scan_reg_t; @@ -365,6 +373,7 @@ typedef union { * change configured by DEDIC_GPIO_INTR_RCGN_REG. */ uint32_t gpio7_int_raw: 1; + uint32_t reserved8: 24; }; uint32_t val; } dedic_gpio_intr_raw_reg_t; @@ -406,6 +415,7 @@ typedef union { * This enable bit for reg_gpio7_int_st register. */ uint32_t gpio7_int_ena: 1; + uint32_t reserved8: 24; }; uint32_t val; } dedic_gpio_intr_rls_reg_t; @@ -447,6 +457,7 @@ typedef union { * This is the status bit for reg_gpio7_int_raw when reg_gpio7_int_ena is set to 1. */ uint32_t gpio7_int_st: 1; + uint32_t reserved8: 24; }; uint32_t val; } dedic_gpio_intr_st_reg_t; @@ -488,6 +499,7 @@ typedef union { * Set this bit to clear the reg_gpio7_int_raw interrupt. */ uint32_t gpio7_int_clr: 1; + uint32_t reserved8: 24; }; uint32_t val; } dedic_gpio_intr_clr_reg_t; diff --git a/components/soc/esp32s2/include/soc/efuse_struct.h b/components/soc/esp32s2/include/soc/efuse_struct.h index a9679c267c..1ba78a4147 100644 --- a/components/soc/esp32s2/include/soc/efuse_struct.h +++ b/components/soc/esp32s2/include/soc/efuse_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct efuse_dev_s { uint32_t pgm_data0; /**/ union { struct { diff --git a/components/soc/esp32s2/include/soc/gpio_sd_struct.h b/components/soc/esp32s2/include/soc/gpio_sd_struct.h index 6c28df52a8..71131ae881 100644 --- a/components/soc/esp32s2/include/soc/gpio_sd_struct.h +++ b/components/soc/esp32s2/include/soc/gpio_sd_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct gpio_sd_dev_s { union { struct { uint32_t duty: 8; diff --git a/components/soc/esp32s2/include/soc/gpio_struct.h b/components/soc/esp32s2/include/soc/gpio_struct.h index 70e82ee1fe..0dc1efdfda 100644 --- a/components/soc/esp32s2/include/soc/gpio_struct.h +++ b/components/soc/esp32s2/include/soc/gpio_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct gpio_dev_s { uint32_t bt_select; /**/ uint32_t out; /**/ uint32_t out_w1ts; /**/ diff --git a/components/soc/esp32s2/include/soc/i2c_struct.h b/components/soc/esp32s2/include/soc/i2c_struct.h index e54038aaea..150384992b 100644 --- a/components/soc/esp32s2/include/soc/i2c_struct.h +++ b/components/soc/esp32s2/include/soc/i2c_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct i2c_dev_s { union { struct { uint32_t period: 14; diff --git a/components/soc/esp32s2/include/soc/i2s_struct.h b/components/soc/esp32s2/include/soc/i2s_struct.h index 789f2c21c2..99220407e7 100644 --- a/components/soc/esp32s2/include/soc/i2s_struct.h +++ b/components/soc/esp32s2/include/soc/i2s_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct i2s_dev_s { uint32_t reserved_0; uint32_t reserved_4; union { diff --git a/components/soc/esp32s2/include/soc/ledc_struct.h b/components/soc/esp32s2/include/soc/ledc_struct.h index 4fe5af2cbf..3af81f8e3a 100644 --- a/components/soc/esp32s2/include/soc/ledc_struct.h +++ b/components/soc/esp32s2/include/soc/ledc_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct ledc_dev_s { struct { struct { union { diff --git a/components/soc/esp32s2/include/soc/pcnt_struct.h b/components/soc/esp32s2/include/soc/pcnt_struct.h index b0c811f9cb..80a1225f53 100644 --- a/components/soc/esp32s2/include/soc/pcnt_struct.h +++ b/components/soc/esp32s2/include/soc/pcnt_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct pcnt_dev_s { struct { union { struct { diff --git a/components/soc/esp32s2/include/soc/rmt_struct.h b/components/soc/esp32s2/include/soc/rmt_struct.h index e33fb3aff0..5e43004093 100644 --- a/components/soc/esp32s2/include/soc/rmt_struct.h +++ b/components/soc/esp32s2/include/soc/rmt_struct.h @@ -20,7 +20,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct rmt_dev_s { uint32_t data_ch[4]; /* Data FIFO, Can only be accessed by PeriBus2 */ struct { union { @@ -299,23 +299,10 @@ typedef struct { }; } rmt_item32_t; -typedef struct { - union { - struct { - uint16_t duration :15; - uint16_t level :1; - }; - uint16_t val; - }; -} rmt_item16_t; - //Allow access to RMT memory using RMTMEM.chan[0].data32[8] -typedef volatile struct { +typedef volatile struct rmt_mem_s { struct { - union { - rmt_item32_t data32[64]; - rmt_item16_t data16[128]; - }; + rmt_item32_t data32[64]; } chan[4]; } rmt_mem_t; extern rmt_mem_t RMTMEM; diff --git a/components/soc/esp32s2/include/soc/rtc_cntl_struct.h b/components/soc/esp32s2/include/soc/rtc_cntl_struct.h index 4a901a3231..695d18c616 100644 --- a/components/soc/esp32s2/include/soc/rtc_cntl_struct.h +++ b/components/soc/esp32s2/include/soc/rtc_cntl_struct.h @@ -19,7 +19,7 @@ extern "C" { #include -typedef volatile struct { +typedef volatile struct rtc_cntl_dev_s { union { struct { uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ diff --git a/components/soc/esp32s2/include/soc/rtc_i2c_struct.h b/components/soc/esp32s2/include/soc/rtc_i2c_struct.h index 2b9e6532d6..8f46d82fa3 100644 --- a/components/soc/esp32s2/include/soc/rtc_i2c_struct.h +++ b/components/soc/esp32s2/include/soc/rtc_i2c_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct rtc_i2c_dev_s { union { struct { uint32_t period: 20; /*time period that scl = 0*/ diff --git a/components/soc/esp32s2/include/soc/rtc_io_struct.h b/components/soc/esp32s2/include/soc/rtc_io_struct.h index c38c9fd4ab..6d4c883ed0 100644 --- a/components/soc/esp32s2/include/soc/rtc_io_struct.h +++ b/components/soc/esp32s2/include/soc/rtc_io_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct rtc_io_dev_s { union { struct { uint32_t reserved0: 10; diff --git a/components/soc/esp32s2/include/soc/sdmmc_struct.h b/components/soc/esp32s2/include/soc/sdmmc_struct.h deleted file mode 100644 index 7e3c6912eb..0000000000 --- a/components/soc/esp32s2/include/soc/sdmmc_struct.h +++ /dev/null @@ -1,377 +0,0 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_SDMMC_STRUCT_H_ -#define _SOC_SDMMC_STRUCT_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - uint32_t reserved1: 1; - uint32_t disable_int_on_completion: 1; - uint32_t last_descriptor: 1; - uint32_t first_descriptor: 1; - uint32_t second_address_chained: 1; - uint32_t end_of_ring: 1; - uint32_t reserved2: 24; - uint32_t card_error_summary: 1; - uint32_t owned_by_idmac: 1; - uint32_t buffer1_size: 13; - uint32_t buffer2_size: 13; - uint32_t reserved3: 6; - void* buffer1_ptr; - union { - void* buffer2_ptr; - void* next_desc_ptr; - }; -} sdmmc_desc_t; - -#define SDMMC_DMA_MAX_BUF_LEN 4096 - -_Static_assert(sizeof(sdmmc_desc_t) == 16, "invalid size of sdmmc_desc_t structure"); - - -typedef struct { - uint32_t cmd_index: 6; ///< Command index - uint32_t response_expect: 1; ///< set if response is expected - uint32_t response_long: 1; ///< 0: short response expected, 1: long response expected - uint32_t check_response_crc: 1; ///< set if controller should check response CRC - uint32_t data_expected: 1; ///< 0: no data expected, 1: data expected - uint32_t rw: 1; ///< 0: read from card, 1: write to card (don't care if no data expected) - uint32_t stream_mode: 1; ///< 0: block transfer, 1: stream transfer (don't care if no data expected) - uint32_t send_auto_stop: 1; ///< set to send stop at the end of the transfer - uint32_t wait_complete: 1; ///< 0: send command at once, 1: wait for previous command to complete - uint32_t stop_abort_cmd: 1; ///< set if this is a stop or abort command intended to stop current transfer - uint32_t send_init: 1; ///< set to send init sequence (80 clocks of 1) - uint32_t card_num: 5; ///< card number - uint32_t update_clk_reg: 1; ///< 0: normal command, 1: don't send command, just update clock registers - uint32_t read_ceata: 1; ///< set if performing read from CE-ATA device - uint32_t ccs_expected: 1; ///< set if CCS is expected from CE-ATA device - uint32_t enable_boot: 1; ///< set for mandatory boot mode - uint32_t expect_boot_ack: 1; ///< when set along with enable_boot, controller expects boot ack pattern - uint32_t disable_boot: 1; ///< set to terminate boot operation (don't set along with enable_boot) - uint32_t boot_mode: 1; ///< 0: mandatory boot operation, 1: alternate boot operation - uint32_t volt_switch: 1; ///< set to enable voltage switching (for CMD11 only) - uint32_t use_hold_reg: 1; ///< clear to bypass HOLD register - uint32_t reserved: 1; - uint32_t start_command: 1; ///< Start command; once command is sent to the card, bit is cleared. -} sdmmc_hw_cmd_t; ///< command format used in cmd register; this structure is defined to make it easier to build command values - -_Static_assert(sizeof(sdmmc_hw_cmd_t) == 4, "invalid size of sdmmc_cmd_t structure"); - - -typedef volatile struct { - union { - struct { - uint32_t controller_reset: 1; - uint32_t fifo_reset: 1; - uint32_t dma_reset: 1; - uint32_t reserved1: 1; - uint32_t int_enable: 1; - uint32_t dma_enable: 1; - uint32_t read_wait: 1; - uint32_t send_irq_response: 1; - uint32_t abort_read_data: 1; - uint32_t send_ccsd: 1; - uint32_t send_auto_stop_ccsd: 1; - uint32_t ceata_device_interrupt_status: 1; - uint32_t reserved2: 4; - uint32_t card_voltage_a: 4; - uint32_t card_voltage_b: 4; - uint32_t enable_od_pullup: 1; - uint32_t use_internal_dma: 1; - uint32_t reserved3: 6; - }; - uint32_t val; - } ctrl; - - uint32_t pwren; ///< 1: enable power to card, 0: disable power to card - - union { - struct { - uint32_t div0: 8; ///< 0: bypass, 1-255: divide clock by (2*div0). - uint32_t div1: 8; ///< 0: bypass, 1-255: divide clock by (2*div0). - uint32_t div2: 8; ///< 0: bypass, 1-255: divide clock by (2*div0). - uint32_t div3: 8; ///< 0: bypass, 1-255: divide clock by (2*div0). - }; - uint32_t val; - } clkdiv; - - union { - struct { - uint32_t card0: 2; ///< 0-3: select clock divider for card 0 among div0-div3 - uint32_t card1: 2; ///< 0-3: select clock divider for card 1 among div0-div3 - uint32_t reserved: 28; - }; - uint32_t val; - } clksrc; - - union { - struct { - uint32_t cclk_enable: 16; ///< 1: enable clock to card, 0: disable clock - uint32_t cclk_low_power: 16; ///< 1: enable clock gating when card is idle, 0: disable clock gating - }; - uint32_t val; - } clkena; - - union { - struct { - uint32_t response: 8; ///< response timeout, in card output clock cycles - uint32_t data: 24; ///< data read timeout, in card output clock cycles - }; - uint32_t val; - } tmout; - - union { - struct { - uint32_t card_width: 16; ///< one bit for each card: 0: 1-bit mode, 1: 4-bit mode - uint32_t card_width_8: 16; ///< one bit for each card: 0: not 8-bit mode (corresponding card_width bit is used), 1: 8-bit mode (card_width bit is ignored) - }; - uint32_t val; - } ctype; - - uint32_t blksiz: 16; ///< block size, default 0x200 - uint32_t : 16; - - uint32_t bytcnt; ///< number of bytes to be transferred - - union { - struct { - uint32_t cd: 1; ///< Card detect interrupt enable - uint32_t re: 1; ///< Response error interrupt enable - uint32_t cmd_done: 1; ///< Command done interrupt enable - uint32_t dto: 1; ///< Data transfer over interrupt enable - uint32_t txdr: 1; ///< Transmit FIFO data request interrupt enable - uint32_t rxdr: 1; ///< Receive FIFO data request interrupt enable - uint32_t rcrc: 1; ///< Response CRC error interrupt enable - uint32_t dcrc: 1; ///< Data CRC error interrupt enable - uint32_t rto: 1; ///< Response timeout interrupt enable - uint32_t drto: 1; ///< Data read timeout interrupt enable - uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt enable - uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt enable - uint32_t hle: 1; ///< Hardware locked write error interrupt enable - uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt enable - uint32_t acd: 1; ///< Auto command done interrupt enable - uint32_t ebe: 1; ///< End bit error / write no CRC interrupt enable - uint32_t sdio: 16; ///< SDIO interrupt enable - }; - uint32_t val; - } intmask; - - uint32_t cmdarg; ///< Command argument to be passed to card - - sdmmc_hw_cmd_t cmd; - - uint32_t resp[4]; ///< Response from card - - union { - struct { - uint32_t cd: 1; ///< Card detect interrupt masked status - uint32_t re: 1; ///< Response error interrupt masked status - uint32_t cmd_done: 1; ///< Command done interrupt masked status - uint32_t dto: 1; ///< Data transfer over interrupt masked status - uint32_t txdr: 1; ///< Transmit FIFO data request interrupt masked status - uint32_t rxdr: 1; ///< Receive FIFO data request interrupt masked status - uint32_t rcrc: 1; ///< Response CRC error interrupt masked status - uint32_t dcrc: 1; ///< Data CRC error interrupt masked status - uint32_t rto: 1; ///< Response timeout interrupt masked status - uint32_t drto: 1; ///< Data read timeout interrupt masked status - uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt masked status - uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt masked status - uint32_t hle: 1; ///< Hardware locked write error interrupt masked status - uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt masked status - uint32_t acd: 1; ///< Auto command done interrupt masked status - uint32_t ebe: 1; ///< End bit error / write no CRC interrupt masked status - uint32_t sdio: 16; ///< SDIO interrupt masked status - }; - uint32_t val; - } mintsts; - - union { - struct { - uint32_t cd: 1; ///< Card detect raw interrupt status - uint32_t re: 1; ///< Response error raw interrupt status - uint32_t cmd_done: 1; ///< Command done raw interrupt status - uint32_t dto: 1; ///< Data transfer over raw interrupt status - uint32_t txdr: 1; ///< Transmit FIFO data request raw interrupt status - uint32_t rxdr: 1; ///< Receive FIFO data request raw interrupt status - uint32_t rcrc: 1; ///< Response CRC error raw interrupt status - uint32_t dcrc: 1; ///< Data CRC error raw interrupt status - uint32_t rto: 1; ///< Response timeout raw interrupt status - uint32_t drto: 1; ///< Data read timeout raw interrupt status - uint32_t hto: 1; ///< Data starvation-by-host timeout raw interrupt status - uint32_t frun: 1; ///< FIFO underrun/overrun error raw interrupt status - uint32_t hle: 1; ///< Hardware locked write error raw interrupt status - uint32_t sbi_bci: 1; ///< Start bit error / busy clear raw interrupt status - uint32_t acd: 1; ///< Auto command done raw interrupt status - uint32_t ebe: 1; ///< End bit error / write no CRC raw interrupt status - uint32_t sdio: 16; ///< SDIO raw interrupt status - }; - uint32_t val; - } rintsts; ///< interrupts can be cleared by writing this register - - union { - struct { - uint32_t fifo_rx_watermark: 1; ///< FIFO reached receive watermark level - uint32_t fifo_tx_watermark: 1; ///< FIFO reached transmit watermark level - uint32_t fifo_empty: 1; ///< FIFO is empty - uint32_t fifo_full: 1; ///< FIFO is full - uint32_t cmd_fsm_state: 4; ///< command FSM state - uint32_t data3_status: 1; ///< this bit reads 1 if card is present - uint32_t data_busy: 1; ///< this bit reads 1 if card is busy - uint32_t data_fsm_busy: 1; ///< this bit reads 1 if transmit/receive FSM is busy - uint32_t response_index: 6; ///< index of the previous response - uint32_t fifo_count: 13; ///< number of filled locations in the FIFO - uint32_t dma_ack: 1; ///< DMA acknowledge signal - uint32_t dma_req: 1; ///< DMA request signal - }; - uint32_t val; - } status; - - union { - struct { - uint32_t tx_watermark: 12; ///< FIFO TX watermark level - uint32_t reserved1: 4; - uint32_t rx_watermark: 12; ///< FIFO RX watermark level - uint32_t dw_dma_mts: 3; - uint32_t reserved2: 1; - }; - uint32_t val; - } fifoth; - - union { - struct { - uint32_t cards: 2; ///< bit N reads 0 if card N is present - uint32_t reserved: 30; - }; - uint32_t val; - } cdetect; - - union { - struct { - uint32_t cards: 2; ///< bit N reads 1 if card N is write protected - uint32_t reserved: 30; - }; - uint32_t val; - } wrtprt; - - uint32_t gpio; ///< unused - uint32_t tcbcnt; ///< transferred (to card) byte count - uint32_t tbbcnt; ///< transferred from host to FIFO byte count - - union { - struct { - uint32_t debounce_count: 24; ///< number of host cycles used by debounce filter, typical time should be 5-25ms - uint32_t reserved: 8; - }; - } debnce; - - uint32_t usrid; ///< user ID - uint32_t verid; ///< IP block version - uint32_t hcon; ///< compile-time IP configuration - uint32_t uhs; ///< TBD - - union { - struct { - uint32_t cards: 2; ///< bit N resets card N, active low - uint32_t reserved: 30; - }; - } rst_n; - - uint32_t reserved_7c; - - union { - struct { - uint32_t sw_reset: 1; ///< set to reset DMA controller - uint32_t fb: 1; ///< set if AHB master performs fixed burst transfers - uint32_t dsl: 5; ///< descriptor skip length: number of words to skip between two unchained descriptors - uint32_t enable: 1; ///< set to enable IDMAC - uint32_t pbl: 3; ///< programmable burst length - uint32_t reserved: 21; - }; - uint32_t val; - } bmod; - - uint32_t pldmnd; ///< set any bit to resume IDMAC FSM from suspended state - sdmmc_desc_t* dbaddr; ///< descriptor list base - - union { - struct { - uint32_t ti: 1; ///< transmit interrupt status - uint32_t ri: 1; ///< receive interrupt status - uint32_t fbe: 1; ///< fatal bus error - uint32_t reserved1: 1; - uint32_t du: 1; ///< descriptor unavailable - uint32_t ces: 1; ///< card error summary - uint32_t reserved2: 2; - uint32_t nis: 1; ///< normal interrupt summary - uint32_t fbe_code: 3; ///< code of fatal bus error - uint32_t fsm: 4; ///< DMAC FSM state - uint32_t reserved3: 15; - }; - uint32_t val; - } idsts; - - union { - struct { - uint32_t ti: 1; ///< transmit interrupt enable - uint32_t ri: 1; ///< receive interrupt enable - uint32_t fbe: 1; ///< fatal bus error interrupt enable - uint32_t reserved1: 1; - uint32_t du: 1; ///< descriptor unavailable interrupt enable - uint32_t ces: 1; ///< card error interrupt enable - uint32_t reserved2: 2; - uint32_t ni: 1; ///< normal interrupt interrupt enable - uint32_t ai: 1; ///< abnormal interrupt enable - uint32_t reserved3: 22; - }; - uint32_t val; - } idinten; - - uint32_t dscaddr; ///< current host descriptor address - uint32_t dscaddrl; ///< unused - uint32_t dscaddru; ///< unused - uint32_t bufaddrl; ///< unused - uint32_t bufaddru; ///< unused - uint32_t reserved_a8[22]; - uint32_t cardthrctl; - uint32_t back_end_power; - uint32_t uhs_reg_ext; - uint32_t emmc_ddr_reg; - uint32_t enable_shift; - uint32_t reserved_114[443]; - union { - struct { - uint32_t phase_dout: 3; ///< phase of data output clock (0x0: 0, 0x1: 90, 0x4: 180, 0x6: 270) - uint32_t phase_din: 3; ///< phase of data input clock - uint32_t phase_core: 3; ///< phase of the clock to SDMMC peripheral - uint32_t div_factor_p: 4; ///< controls clock period; it will be (div_factor_p + 1) / 160MHz - uint32_t div_factor_h: 4; ///< controls length of high pulse; it will be (div_factor_h + 1) / 160MHz - uint32_t div_factor_m: 4; ///< should be equal to div_factor_p - }; - uint32_t val; - } clock; -} sdmmc_dev_t; -extern sdmmc_dev_t SDMMC; - -_Static_assert(sizeof(sdmmc_dev_t) == 0x804, "invalid size of sdmmc_dev_t structure"); - -#ifdef __cplusplus -} -#endif - -#endif //_SOC_SDMMC_STRUCT_H_ diff --git a/components/soc/esp32s2/include/soc/sens_struct.h b/components/soc/esp32s2/include/soc/sens_struct.h index 5f56714ee6..5a029dd9fe 100644 --- a/components/soc/esp32s2/include/soc/sens_struct.h +++ b/components/soc/esp32s2/include/soc/sens_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct sens_dev_s { union { struct { uint32_t sar1_clk_div: 8; /*clock divider*/ diff --git a/components/soc/esp32s2/include/soc/syscon_struct.h b/components/soc/esp32s2/include/soc/syscon_struct.h index d40e2dff50..f50baa2f9c 100644 --- a/components/soc/esp32s2/include/soc/syscon_struct.h +++ b/components/soc/esp32s2/include/soc/syscon_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct syscon_dev_s { union { struct { uint32_t pre_div: 10; diff --git a/components/soc/esp32s2/include/soc/timer_group_struct.h b/components/soc/esp32s2/include/soc/timer_group_struct.h index 55d6befeae..e9fb04747b 100644 --- a/components/soc/esp32s2/include/soc/timer_group_struct.h +++ b/components/soc/esp32s2/include/soc/timer_group_struct.h @@ -20,7 +20,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct timg_dev_s { struct { union { struct { diff --git a/components/soc/esp32s2/include/soc/twai_struct.h b/components/soc/esp32s2/include/soc/twai_struct.h index 5cba4d409a..61e2238f4b 100644 --- a/components/soc/esp32s2/include/soc/twai_struct.h +++ b/components/soc/esp32s2/include/soc/twai_struct.h @@ -178,7 +178,7 @@ typedef volatile struct twai_dev_s { }; uint32_t val; } tx_rx_buffer[13]; - }; /* Address 16-28 TX/RX Buffer and Acc Filter*/; + }; /* Address 16-28 TX/RX Buffer and Acc Filter*/ //Misc Registers union { diff --git a/components/soc/esp32s2/include/soc/uart_struct.h b/components/soc/esp32s2/include/soc/uart_struct.h index a470b6b968..5eb977825b 100644 --- a/components/soc/esp32s2/include/soc/uart_struct.h +++ b/components/soc/esp32s2/include/soc/uart_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct uart_dev_s { union { struct { uint32_t rw_byte;/*note: rw_byte is a uint8_t field, however, ESP32-S2 do not support 8 bits read/write*/ diff --git a/components/soc/esp32s2/include/soc/uhci_struct.h b/components/soc/esp32s2/include/soc/uhci_struct.h index aadc2a6303..63cc074161 100644 --- a/components/soc/esp32s2/include/soc/uhci_struct.h +++ b/components/soc/esp32s2/include/soc/uhci_struct.h @@ -17,7 +17,7 @@ extern "C" { #endif -typedef volatile struct { +typedef volatile struct uhci_dev_s { union { struct { uint32_t in_rst: 1; diff --git a/components/soc/esp32s2/include/soc/usb_wrap_struct.h b/components/soc/esp32s2/include/soc/usb_wrap_struct.h index 147afc3228..c196743ec0 100644 --- a/components/soc/esp32s2/include/soc/usb_wrap_struct.h +++ b/components/soc/esp32s2/include/soc/usb_wrap_struct.h @@ -153,6 +153,7 @@ typedef union { * USB D- rx value in test. */ uint32_t test_rx_dm:1; + uint32_t reserved:25; }; uint32_t val; } usb_wrap_test_conf_reg_t; diff --git a/components/soc/esp32s2/include/soc/usbh_struct.h b/components/soc/esp32s2/include/soc/usbh_struct.h index ace84d7fa9..182a6034d1 100644 --- a/components/soc/esp32s2/include/soc/usbh_struct.h +++ b/components/soc/esp32s2/include/soc/usbh_struct.h @@ -830,7 +830,7 @@ typedef union { uint32_t bbleerr: 1; uint32_t nakintrpt: 1; uint32_t nyetintrpt: 1; - uint32_t reserved16: 16; + uint32_t reserved15: 17; }; uint32_t val; } usb_diepint_reg_t;