diff --git a/components/bootloader_support/src/bootloader_clock_init.c b/components/bootloader_support/src/bootloader_clock_init.c
index 0e8f66b323..1f0dd50857 100644
--- a/components/bootloader_support/src/bootloader_clock_init.c
+++ b/components/bootloader_support/src/bootloader_clock_init.c
@@ -31,7 +31,7 @@ __attribute__((weak)) void bootloader_clock_configure(void)
     // This is not needed on power on reset, when ROM bootloader is running at
     // 40 MHz. But in case of TG WDT reset, CPU may still be running at >80 MHZ,
     // and will be done with the bootloader much earlier than UART FIFO is empty.
-    esp_rom_uart_tx_wait_idle(0);
+    esp_rom_output_tx_wait_idle(0);
 
     /* Set CPU to a higher certain frequency. Keep other clocks unmodified. */
     int cpu_freq_mhz = CPU_CLK_FREQ_MHZ_BTLD;
diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c
index 85512b3607..da047055a9 100644
--- a/components/bootloader_support/src/bootloader_console.c
+++ b/components/bootloader_support/src/bootloader_console.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -44,7 +44,7 @@ void bootloader_console_init(void)
     esp_rom_install_uart_printf();
 
     // Wait for UART FIFO to be empty.
-    esp_rom_uart_tx_wait_idle(0);
+    esp_rom_output_tx_wait_idle(0);
 
 #if CONFIG_ESP_CONSOLE_UART_CUSTOM
     // Some constants to make the following code less upper-case
@@ -52,7 +52,7 @@ void bootloader_console_init(void)
     const int uart_rx_gpio = CONFIG_ESP_CONSOLE_UART_RX_GPIO;
 
     // Switch to the new UART (this just changes UART number used for esp_rom_printf in ROM code).
-    esp_rom_uart_set_as_console(uart_num);
+    esp_rom_output_set_as_console(uart_num);
 
     // If console is attached to UART1 or if non-default pins are used,
     // need to reconfigure pins using GPIO matrix
@@ -102,8 +102,8 @@ void bootloader_console_init(void)
     rom_usb_cdc_set_descriptor_patch();
 #endif
 
-    esp_rom_uart_usb_acm_init(s_usb_cdc_buf, sizeof(s_usb_cdc_buf));
-    esp_rom_uart_set_as_console(ESP_ROM_USB_OTG_NUM);
+    esp_rom_output_usb_acm_init(s_usb_cdc_buf, sizeof(s_usb_cdc_buf));
+    esp_rom_output_set_as_console(ESP_ROM_USB_OTG_NUM);
     esp_rom_install_channel_putc(1, bootloader_console_write_char_usb);
 #if SOC_USB_SERIAL_JTAG_SUPPORTED
     usb_fsls_phy_ll_usb_wrap_pad_enable(&USB_WRAP, true);
@@ -115,6 +115,6 @@ void bootloader_console_init(void)
 #ifdef CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
 void bootloader_console_init(void)
 {
-    esp_rom_uart_switch_buffer(ESP_ROM_USB_SERIAL_DEVICE_NUM);
+    esp_rom_output_switch_buffer(ESP_ROM_USB_SERIAL_DEVICE_NUM);
 }
 #endif //CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
diff --git a/components/bootloader_support/src/bootloader_console_loader.c b/components/bootloader_support/src/bootloader_console_loader.c
index 647e6973f4..5235bb32a9 100644
--- a/components/bootloader_support/src/bootloader_console_loader.c
+++ b/components/bootloader_support/src/bootloader_console_loader.c
@@ -67,7 +67,7 @@ void bootloader_console_deinit(void)
 {
 #ifdef CONFIG_ESP_CONSOLE_UART
     /* Ensure any buffered log output is displayed */
-    esp_rom_uart_flush_tx(CONFIG_ESP_CONSOLE_UART_NUM);
+    esp_rom_output_flush_tx(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
 #endif // CONFIG_ESP_CONSOLE_UART
 
 #ifdef CONFIG_ESP_CONSOLE_USB_CDC
diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c
index bb1dc1ab6b..aa30037fca 100644
--- a/components/bootloader_support/src/bootloader_utility.c
+++ b/components/bootloader_support/src/bootloader_utility.c
@@ -708,7 +708,7 @@ static void load_image(const esp_image_metadata_t *image_data)
            so issue a system reset to ensure flash encryption
            cache resets properly */
         ESP_LOGI(TAG, "Resetting with flash encryption enabled...");
-        esp_rom_uart_tx_wait_idle(0);
+        esp_rom_output_tx_wait_idle(0);
         bootloader_reset();
     }
 #endif
diff --git a/components/driver/test_apps/touch_sensor_v2/main/touch_scope.c b/components/driver/test_apps/touch_sensor_v2/main/touch_scope.c
index 94e30a131e..dc4ddb299e 100644
--- a/components/driver/test_apps/touch_sensor_v2/main/touch_scope.c
+++ b/components/driver/test_apps/touch_sensor_v2/main/touch_scope.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -120,9 +120,9 @@ int test_tp_print_to_scope(float *data, unsigned char channel_num)
         return 0;
     } else {
 #if ROM_UART_DRIVER_ENABLE
-        esp_rom_uart_tx_wait_idle(uart_num);   // Default print uart mumber is 0.
+        esp_rom_output_tx_wait_idle(uart_num);   // Default print uart mumber is 0.
         for(int i=0; i<out_len; i++) {
-            esp_rom_uart_tx_one_char(out_data[i]);
+            esp_rom_output_tx_one_char(out_data[i]);
         }
         return out_len;
 #else
@@ -154,9 +154,9 @@ int test_tp_print_to_scope(float *data, unsigned char channel_num)
 esp_err_t test_tp_scope_debug_init(uint8_t uart_num, int tx_io_num, int rx_io_num, int baud_rate)
 {
 #if ROM_UART_DRIVER_ENABLE
-    esp_rom_uart_tx_wait_idle(0);   // Default print uart mumber is 0.
+    esp_rom_output_tx_wait_idle(0);   // Default print uart mumber is 0.
     if(uart_num != 0) {
-        esp_rom_uart_set_as_console(uart_num);
+        esp_rom_output_set_as_console(uart_num);
     }
 #else
     if(uart_used == uart_num) {
diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
index 59a54bfd2d..33161a80c2 100644
--- a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
+++ b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
@@ -668,10 +668,10 @@ static void prompt_to_continue(const char *str)
     char sign[5] = {0};
     while (strlen(sign) == 0) {
         /* Flush anything already in the RX buffer */
-        while (esp_rom_uart_rx_one_char((uint8_t *) sign) == 0) {
+        while (esp_rom_output_rx_one_char((uint8_t *) sign) == 0) {
         }
         /* Read line */
-        esp_rom_uart_rx_string((uint8_t *) sign, sizeof(sign) - 1);
+        esp_rom_output_rx_string((uint8_t *) sign, sizeof(sign) - 1);
     }
 }
 
diff --git a/components/esp_driver_uart/src/uart_vfs.c b/components/esp_driver_uart/src/uart_vfs.c
index a2ec035e27..146e96cf84 100644
--- a/components/esp_driver_uart/src/uart_vfs.c
+++ b/components/esp_driver_uart/src/uart_vfs.c
@@ -357,7 +357,7 @@ static int uart_fsync(int fd)
 {
     assert(fd >= 0 && fd < 3);
     _lock_acquire_recursive(&s_ctx[fd]->write_lock);
-    esp_rom_uart_tx_wait_idle((uint8_t) fd);
+    esp_rom_output_tx_wait_idle((uint8_t) fd);
     _lock_release_recursive(&s_ctx[fd]->write_lock);
     return 0;
 }
diff --git a/components/esp_driver_uart/test_apps/uart_vfs/main/test_vfs_uart.c b/components/esp_driver_uart/test_apps/uart_vfs/main/test_vfs_uart.c
index 561d20cf52..8c45624f77 100644
--- a/components/esp_driver_uart/test_apps/uart_vfs/main/test_vfs_uart.c
+++ b/components/esp_driver_uart/test_apps/uart_vfs/main/test_vfs_uart.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -25,11 +25,11 @@
 
 static void fwrite_str_loopback(const char* str, size_t size)
 {
-    esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+    esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
     uart_ll_set_loop_back(&UART0, 1);
     fwrite(str, 1, size, stdout);
     fflush(stdout);
-    esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+    esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
     vTaskDelay(2 / portTICK_PERIOD_MS);
     uart_ll_set_loop_back(&UART0, 0);
 }
@@ -42,7 +42,7 @@ static void flush_stdin_stdout(void)
         ;
     }
     fflush(stdout);
-    esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+    esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
 }
 
 TEST_CASE("can read from stdin", "[vfs_uart]")
diff --git a/components/esp_hw_support/port/esp32/rtc_clk_init.c b/components/esp_hw_support/port/esp32/rtc_clk_init.c
index aef313626e..ba03120191 100644
--- a/components/esp_hw_support/port/esp32/rtc_clk_init.c
+++ b/components/esp_hw_support/port/esp32/rtc_clk_init.c
@@ -97,7 +97,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
                     configured_xtal_freq, est_xtal_freq);
         }
     }
-    esp_rom_uart_tx_wait_idle(0);
+    esp_rom_output_tx_wait_idle(0);
     rtc_clk_xtal_freq_update(xtal_freq);
     rtc_clk_apb_freq_update(xtal_freq * MHZ);
 
diff --git a/components/esp_hw_support/port/esp32c2/rtc_clk_init.c b/components/esp_hw_support/port/esp32c2/rtc_clk_init.c
index 8b5a185a93..c1217733d4 100644
--- a/components/esp_hw_support/port/esp32c2/rtc_clk_init.c
+++ b/components/esp_hw_support/port/esp32c2/rtc_clk_init.c
@@ -48,7 +48,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
     regi2c_ctrl_ll_i2c_bbpll_enable(); // TODO: This should be moved to bbpll_set_config
 
     rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
-    esp_rom_uart_tx_wait_idle(0);
+    esp_rom_output_tx_wait_idle(0);
     rtc_clk_xtal_freq_update(xtal_freq);
     rtc_clk_apb_freq_update(xtal_freq * MHZ);
 
diff --git a/components/esp_hw_support/port/esp32c3/rtc_clk_init.c b/components/esp_hw_support/port/esp32c3/rtc_clk_init.c
index 5b28bd787d..6c7f693419 100644
--- a/components/esp_hw_support/port/esp32c3/rtc_clk_init.c
+++ b/components/esp_hw_support/port/esp32c3/rtc_clk_init.c
@@ -48,7 +48,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
     regi2c_ctrl_ll_i2c_bbpll_enable(); // TODO: This should be moved to bbpll_set_config
 
     rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
-    esp_rom_uart_tx_wait_idle(0);
+    esp_rom_output_tx_wait_idle(0);
     rtc_clk_xtal_freq_update(xtal_freq);
     rtc_clk_apb_freq_update(xtal_freq * MHZ);
 
diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk_init.c b/components/esp_hw_support/port/esp32c5/rtc_clk_init.c
index 95cb7a2d0a..2ffd652db1 100644
--- a/components/esp_hw_support/port/esp32c5/rtc_clk_init.c
+++ b/components/esp_hw_support/port/esp32c5/rtc_clk_init.c
@@ -82,7 +82,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
     clk_ll_rc_fast_tick_conf();
 
     rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
-    esp_rom_uart_tx_wait_idle(0);
+    esp_rom_output_tx_wait_idle(0);
     rtc_clk_xtal_freq_update(xtal_freq);
 
     /* Set CPU frequency */
diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk_init.c b/components/esp_hw_support/port/esp32c6/rtc_clk_init.c
index 2884550feb..03e3362297 100644
--- a/components/esp_hw_support/port/esp32c6/rtc_clk_init.c
+++ b/components/esp_hw_support/port/esp32c6/rtc_clk_init.c
@@ -82,7 +82,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
     clk_ll_rc_fast_tick_conf();
 
     rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
-    esp_rom_uart_tx_wait_idle(0);
+    esp_rom_output_tx_wait_idle(0);
     rtc_clk_xtal_freq_update(xtal_freq);
 
     // On ESP32C6, MSPI source clock's default HS divider leads to 120MHz, which is unusable before calibration
diff --git a/components/esp_hw_support/port/esp32h2/rtc_clk_init.c b/components/esp_hw_support/port/esp32h2/rtc_clk_init.c
index 8ce3a854a0..4f64d2dfb6 100644
--- a/components/esp_hw_support/port/esp32h2/rtc_clk_init.c
+++ b/components/esp_hw_support/port/esp32h2/rtc_clk_init.c
@@ -50,7 +50,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
     clk_ll_rc_fast_tick_conf();
 
     rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
-    esp_rom_uart_tx_wait_idle(0);
+    esp_rom_output_tx_wait_idle(0);
     rtc_clk_xtal_freq_update(xtal_freq);
 
     /* Set CPU frequency */
diff --git a/components/esp_hw_support/port/esp32p4/rtc_clk_init.c b/components/esp_hw_support/port/esp32p4/rtc_clk_init.c
index 6d6ff99631..2d1b5614c7 100644
--- a/components/esp_hw_support/port/esp32p4/rtc_clk_init.c
+++ b/components/esp_hw_support/port/esp32p4/rtc_clk_init.c
@@ -67,7 +67,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
     CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_XPD);
 
     rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
-    esp_rom_uart_tx_wait_idle(0);
+    esp_rom_output_tx_wait_idle(0);
     rtc_clk_xtal_freq_update(xtal_freq);
 
     /* Set CPU frequency */
diff --git a/components/esp_hw_support/port/esp32s2/rtc_clk_init.c b/components/esp_hw_support/port/esp32s2/rtc_clk_init.c
index c6f82576ad..ec7c336679 100644
--- a/components/esp_hw_support/port/esp32s2/rtc_clk_init.c
+++ b/components/esp_hw_support/port/esp32s2/rtc_clk_init.c
@@ -48,7 +48,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
     regi2c_ctrl_ll_i2c_apll_enable(); // TODO: This should be moved to apll_set_config
 
     rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
-    esp_rom_uart_tx_wait_idle(0);
+    esp_rom_output_tx_wait_idle(0);
     rtc_clk_apb_freq_update(xtal_freq * MHZ);
 
     /* Set CPU frequency */
diff --git a/components/esp_hw_support/port/esp32s3/rtc_clk_init.c b/components/esp_hw_support/port/esp32s3/rtc_clk_init.c
index 6c3323261c..2b6802ac99 100644
--- a/components/esp_hw_support/port/esp32s3/rtc_clk_init.c
+++ b/components/esp_hw_support/port/esp32s3/rtc_clk_init.c
@@ -45,7 +45,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
     regi2c_ctrl_ll_i2c_bbpll_enable(); // TODO: This should be moved to bbpll_set_config
 
     rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
-    esp_rom_uart_tx_wait_idle(0);
+    esp_rom_output_tx_wait_idle(0);
     rtc_clk_xtal_freq_update(xtal_freq);
     rtc_clk_apb_freq_update(xtal_freq * MHZ);
 
diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c
index 4d6391d0ee..0b64db3247 100644
--- a/components/esp_hw_support/sleep_modes.c
+++ b/components/esp_hw_support/sleep_modes.c
@@ -439,10 +439,10 @@ static void IRAM_ATTR flush_uarts(void)
 {
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
 #ifdef CONFIG_IDF_TARGET_ESP32
-        esp_rom_uart_tx_wait_idle(i);
+        esp_rom_output_tx_wait_idle(i);
 #else
         if (uart_ll_is_enabled(i)) {
-            esp_rom_uart_tx_wait_idle(i);
+            esp_rom_output_tx_wait_idle(i);
         }
 #endif
     }
@@ -517,7 +517,7 @@ FORCE_INLINE_ATTR bool light_sleep_uart_prepare(uint32_t pd_flags, int64_t sleep
         } else {
             /* Only flush the uart_num configured to console, the transmission integrity of
                other uarts is guaranteed by the UART driver */
-            esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+            esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
         }
     } else {
         suspend_uarts();
diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c
index 755d75a94a..72f4e6da26 100644
--- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c
+++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c
@@ -140,7 +140,7 @@ void run_tasks_with_change_freq_cpu(int cpu_freq_mhz)
         bool res = rtc_clk_cpu_freq_mhz_to_config(cpu_freq_mhz, &new_config);
         assert(res && "invalid frequency value");
 
-        esp_rom_uart_tx_wait_idle(uart_num);
+        esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
         rtc_clk_cpu_freq_set_config(&new_config);
         uart_ll_set_sclk(UART_LL_GET_HW(uart_num), UART_SCLK_DEFAULT);
 
@@ -156,7 +156,7 @@ void run_tasks_with_change_freq_cpu(int cpu_freq_mhz)
     run_tasks("accessDPORT", accessDPORT, "accessAPB", accessAPB, 10000);
 
     // return old freq.
-    esp_rom_uart_tx_wait_idle(uart_num);
+    esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
     rtc_clk_cpu_freq_set_config(&old_config);
     uart_ll_set_sclk(UART_LL_GET_HW(uart_num), UART_SCLK_DEFAULT);
 
diff --git a/components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c b/components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c
index ff8fe0b099..7254b6328f 100644
--- a/components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c
+++ b/components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c
@@ -153,7 +153,7 @@ TEST_CASE("Output 8M XTAL clock to GPIO25", "[ignore]")
 
 static void test_clock_switching(void (*switch_func)(const rtc_cpu_freq_config_t* config))
 {
-    esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+    esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
 
     const int test_duration_sec = 10;
     ref_clock_init();
diff --git a/components/esp_rom/esp32/Kconfig.soc_caps.in b/components/esp_rom/esp32/Kconfig.soc_caps.in
index 1e2fb931a3..5f63da9c19 100644
--- a/components/esp_rom/esp32/Kconfig.soc_caps.in
+++ b/components/esp_rom/esp32/Kconfig.soc_caps.in
@@ -34,3 +34,11 @@ config ESP_ROM_HAS_NEWLIB_NANO_FORMAT
 config ESP_ROM_HAS_SW_FLOAT
     bool
     default y
+
+config ESP_ROM_USB_OTG_NUM
+    int
+    default -1
+
+config ESP_ROM_USB_SERIAL_DEVICE_NUM
+    int
+    default -1
diff --git a/components/esp_rom/esp32/esp_rom_caps.h b/components/esp_rom/esp32/esp_rom_caps.h
index f072c6cc8f..9067600037 100644
--- a/components/esp_rom/esp32/esp_rom_caps.h
+++ b/components/esp_rom/esp32/esp_rom_caps.h
@@ -14,3 +14,5 @@
 #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND    (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing
 #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT  (1) // ROM has the newlib nano version of formatting functions
 #define ESP_ROM_HAS_SW_FLOAT            (1) // ROM has libgcc software floating point emulation functions
+#define ESP_ROM_USB_OTG_NUM                 (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.
+#define ESP_ROM_USB_SERIAL_DEVICE_NUM       (-1) // No USB_SERIAL_JTAG in the ROM, set -1 for Kconfig usage.
diff --git a/components/esp_rom/esp32/ld/esp32.rom.api.ld b/components/esp_rom/esp32/ld/esp32.rom.api.ld
index 75b1681e78..f09cc10453 100644
--- a/components/esp_rom/esp32/ld/esp32.rom.api.ld
+++ b/components/esp_rom/esp32/ld/esp32.rom.api.ld
@@ -28,6 +28,15 @@ PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
 PROVIDE ( esp_rom_uart_putc           = ets_write_char_uart );
 PROVIDE ( esp_rom_uart_switch_buffer  = uart_buff_switch );
 
+PROVIDE ( esp_rom_output_flush_tx       = uart_tx_flush );
+PROVIDE ( esp_rom_output_tx_one_char    = uart_tx_one_char );
+PROVIDE ( esp_rom_output_tx_wait_idle   = uart_tx_wait_idle );
+PROVIDE ( esp_rom_output_rx_one_char    = uart_rx_one_char );
+PROVIDE ( esp_rom_output_rx_string      = UartRxString );
+PROVIDE ( esp_rom_output_set_as_console = uart_tx_switch );
+PROVIDE ( esp_rom_output_putc           = ets_write_char_uart );
+PROVIDE ( esp_rom_output_switch_buffer  = uart_buff_switch );
+
 /* wpa_supplicant re-implements the MD5 functions: MD5Init, MD5Update, MD5Final */
 /* so here we directly assign the symbols with the ROM API address */
 PROVIDE ( esp_rom_md5_init   = 0x4005da7c );
diff --git a/components/esp_rom/esp32c2/Kconfig.soc_caps.in b/components/esp_rom/esp32c2/Kconfig.soc_caps.in
index 18d2f1fa74..e5bc96a913 100644
--- a/components/esp_rom/esp32c2/Kconfig.soc_caps.in
+++ b/components/esp_rom/esp32c2/Kconfig.soc_caps.in
@@ -66,3 +66,11 @@ config ESP_ROM_HAS_MBEDTLS_CRYPTO_LIB
 config ESP_ROM_HAS_SW_FLOAT
     bool
     default y
+
+config ESP_ROM_USB_OTG_NUM
+    int
+    default -1
+
+config ESP_ROM_USB_SERIAL_DEVICE_NUM
+    int
+    default -1
diff --git a/components/esp_rom/esp32c2/esp_rom_caps.h b/components/esp_rom/esp32c2/esp_rom_caps.h
index 8478361c90..fd73fa92b0 100644
--- a/components/esp_rom/esp32c2/esp_rom_caps.h
+++ b/components/esp_rom/esp32c2/esp_rom_caps.h
@@ -22,3 +22,5 @@
 #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT      (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init
 #define ESP_ROM_HAS_MBEDTLS_CRYPTO_LIB      (1) // ROM has the mbedtls crypto algorithm lib
 #define ESP_ROM_HAS_SW_FLOAT                (1) // ROM has libgcc software floating point emulation functions
+#define ESP_ROM_USB_OTG_NUM                 (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.
+#define ESP_ROM_USB_SERIAL_DEVICE_NUM       (-1) // No USB_SERIAL_JTAG in the ROM, set -1 for Kconfig usage.
diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld
index 04d9bcb388..f8a46d0e4c 100644
--- a/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld
+++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -30,6 +30,14 @@ PROVIDE ( esp_rom_uart_rx_string      = UartRxString );
 PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
 PROVIDE ( esp_rom_uart_putc           = ets_write_char_uart );
 
+PROVIDE ( esp_rom_output_flush_tx       = uart_tx_flush );
+PROVIDE ( esp_rom_output_tx_one_char    = uart_tx_one_char );
+PROVIDE ( esp_rom_output_tx_wait_idle   = uart_tx_wait_idle );
+PROVIDE ( esp_rom_output_rx_one_char    = uart_rx_one_char );
+PROVIDE ( esp_rom_output_rx_string      = UartRxString );
+PROVIDE ( esp_rom_output_set_as_console = uart_tx_switch );
+PROVIDE ( esp_rom_output_putc           = ets_write_char_uart );
+
 PROVIDE ( esp_rom_mbedtls_md5_starts_ret = mbedtls_md5_starts_ret );
 PROVIDE ( esp_rom_mbedtls_md5_update_ret = mbedtls_md5_update_ret );
 PROVIDE ( esp_rom_mbedtls_md5_finish_ret = mbedtls_md5_finish_ret );
diff --git a/components/esp_rom/esp32c3/Kconfig.soc_caps.in b/components/esp_rom/esp32c3/Kconfig.soc_caps.in
index ba3797fccf..8e8bade7f5 100644
--- a/components/esp_rom/esp32c3/Kconfig.soc_caps.in
+++ b/components/esp_rom/esp32c3/Kconfig.soc_caps.in
@@ -70,3 +70,7 @@ config ESP_ROM_RAM_APP_NEEDS_MMU_INIT
 config ESP_ROM_HAS_SW_FLOAT
     bool
     default y
+
+config ESP_ROM_USB_OTG_NUM
+    int
+    default -1
diff --git a/components/esp_rom/esp32c3/esp_rom_caps.h b/components/esp_rom/esp32c3/esp_rom_caps.h
index 0bf8742c40..5d39ab532d 100644
--- a/components/esp_rom/esp32c3/esp_rom_caps.h
+++ b/components/esp_rom/esp32c3/esp_rom_caps.h
@@ -23,3 +23,4 @@
 #define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE    (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap
 #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT      (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init
 #define ESP_ROM_HAS_SW_FLOAT                (1) // ROM has libgcc software floating point emulation functions
+#define ESP_ROM_USB_OTG_NUM                 (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.
diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld
index 4c4a4628d1..c7cf3573b8 100644
--- a/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld
+++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld
@@ -26,6 +26,12 @@ PROVIDE ( esp_rom_uart_tx_wait_idle   = uart_tx_wait_idle );
 PROVIDE ( esp_rom_uart_rx_one_char    = uart_rx_one_char );
 PROVIDE ( esp_rom_uart_rx_string      = UartRxString );
 
+PROVIDE ( esp_rom_output_flush_tx       = uart_tx_flush );
+PROVIDE ( esp_rom_output_tx_one_char    = uart_tx_one_char );
+PROVIDE ( esp_rom_output_tx_wait_idle   = uart_tx_wait_idle );
+PROVIDE ( esp_rom_output_rx_one_char    = uart_rx_one_char );
+PROVIDE ( esp_rom_output_rx_string      = UartRxString );
+
 PROVIDE ( esp_rom_md5_init   = MD5Init );
 PROVIDE ( esp_rom_md5_update = MD5Update );
 PROVIDE ( esp_rom_md5_final  = MD5Final );
diff --git a/components/esp_rom/esp32c5/Kconfig.soc_caps.in b/components/esp_rom/esp32c5/Kconfig.soc_caps.in
index 28b6cdcde3..fce9a24ae3 100644
--- a/components/esp_rom/esp32c5/Kconfig.soc_caps.in
+++ b/components/esp_rom/esp32c5/Kconfig.soc_caps.in
@@ -74,3 +74,7 @@ config ESP_ROM_WDT_INIT_PATCH
 config ESP_ROM_RAM_APP_NEEDS_MMU_INIT
     bool
     default y
+
+config ESP_ROM_USB_OTG_NUM
+    int
+    default -1
diff --git a/components/esp_rom/esp32c5/esp_rom_caps.h b/components/esp_rom/esp32c5/esp_rom_caps.h
index 4374a3641a..924a30c23a 100644
--- a/components/esp_rom/esp32c5/esp_rom_caps.h
+++ b/components/esp_rom/esp32c5/esp_rom_caps.h
@@ -24,3 +24,4 @@
 #define ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT    (1) // ROM has the newlib normal/full version of formatting functions (as opposed to the nano versions)
 #define ESP_ROM_WDT_INIT_PATCH              (1) // ROM version does not configure the clock
 #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT      (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init
+#define ESP_ROM_USB_OTG_NUM                 (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.
diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.api.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.api.ld
index cf8c34778e..421134e7c2 100644
--- a/components/esp_rom/esp32c5/ld/esp32c5.rom.api.ld
+++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.api.ld
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -31,6 +31,14 @@ PROVIDE ( esp_rom_uart_rx_string      = UartRxString );
 PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
 PROVIDE ( esp_rom_uart_putc           = ets_write_char_uart );
 
+PROVIDE ( esp_rom_output_flush_tx       = uart_tx_flush );
+PROVIDE ( esp_rom_output_tx_one_char    = uart_tx_one_char );
+PROVIDE ( esp_rom_output_tx_wait_idle   = uart_tx_wait_idle );
+PROVIDE ( esp_rom_output_rx_one_char    = uart_rx_one_char );
+PROVIDE ( esp_rom_output_rx_string      = UartRxString );
+PROVIDE ( esp_rom_output_set_as_console = uart_tx_switch );
+PROVIDE ( esp_rom_output_putc           = ets_write_char_uart );
+
 PROVIDE ( esp_rom_md5_init   = MD5Init );
 PROVIDE ( esp_rom_md5_update = MD5Update );
 PROVIDE ( esp_rom_md5_final  = MD5Final );
diff --git a/components/esp_rom/esp32c6/Kconfig.soc_caps.in b/components/esp_rom/esp32c6/Kconfig.soc_caps.in
index 53c794d20e..1999ddc331 100644
--- a/components/esp_rom/esp32c6/Kconfig.soc_caps.in
+++ b/components/esp_rom/esp32c6/Kconfig.soc_caps.in
@@ -86,3 +86,7 @@ config ESP_ROM_RAM_APP_NEEDS_MMU_INIT
 config ESP_ROM_HAS_SW_FLOAT
     bool
     default y
+
+config ESP_ROM_USB_OTG_NUM
+    int
+    default -1
diff --git a/components/esp_rom/esp32c6/esp_rom_caps.h b/components/esp_rom/esp32c6/esp_rom_caps.h
index adf8d09a88..ba530c862f 100644
--- a/components/esp_rom/esp32c6/esp_rom_caps.h
+++ b/components/esp_rom/esp32c6/esp_rom_caps.h
@@ -27,3 +27,4 @@
 #define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE    (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap
 #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT      (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init
 #define ESP_ROM_HAS_SW_FLOAT                (1) // ROM has libgcc software floating point emulation functions
+#define ESP_ROM_USB_OTG_NUM                 (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.
diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld
index cf8c34778e..421134e7c2 100644
--- a/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld
+++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -31,6 +31,14 @@ PROVIDE ( esp_rom_uart_rx_string      = UartRxString );
 PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
 PROVIDE ( esp_rom_uart_putc           = ets_write_char_uart );
 
+PROVIDE ( esp_rom_output_flush_tx       = uart_tx_flush );
+PROVIDE ( esp_rom_output_tx_one_char    = uart_tx_one_char );
+PROVIDE ( esp_rom_output_tx_wait_idle   = uart_tx_wait_idle );
+PROVIDE ( esp_rom_output_rx_one_char    = uart_rx_one_char );
+PROVIDE ( esp_rom_output_rx_string      = UartRxString );
+PROVIDE ( esp_rom_output_set_as_console = uart_tx_switch );
+PROVIDE ( esp_rom_output_putc           = ets_write_char_uart );
+
 PROVIDE ( esp_rom_md5_init   = MD5Init );
 PROVIDE ( esp_rom_md5_update = MD5Update );
 PROVIDE ( esp_rom_md5_final  = MD5Final );
diff --git a/components/esp_rom/esp32h2/Kconfig.soc_caps.in b/components/esp_rom/esp32h2/Kconfig.soc_caps.in
index be23a754fb..78c0c45b63 100644
--- a/components/esp_rom/esp32h2/Kconfig.soc_caps.in
+++ b/components/esp_rom/esp32h2/Kconfig.soc_caps.in
@@ -74,3 +74,7 @@ config ESP_ROM_RAM_APP_NEEDS_MMU_INIT
 config ESP_ROM_HAS_SW_FLOAT
     bool
     default y
+
+config ESP_ROM_USB_OTG_NUM
+    int
+    default -1
diff --git a/components/esp_rom/esp32h2/esp_rom_caps.h b/components/esp_rom/esp32h2/esp_rom_caps.h
index d61be8f260..5923dfbc4a 100644
--- a/components/esp_rom/esp32h2/esp_rom_caps.h
+++ b/components/esp_rom/esp32h2/esp_rom_caps.h
@@ -24,3 +24,4 @@
 #define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE    (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap
 #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT      (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init
 #define ESP_ROM_HAS_SW_FLOAT                (1) // ROM has libgcc software floating point emulation functions
+#define ESP_ROM_USB_OTG_NUM                 (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.
diff --git a/components/esp_rom/esp32h2/ld/esp32h2.rom.api.ld b/components/esp_rom/esp32h2/ld/esp32h2.rom.api.ld
index 773b57b5f2..41727f6a5e 100644
--- a/components/esp_rom/esp32h2/ld/esp32h2.rom.api.ld
+++ b/components/esp_rom/esp32h2/ld/esp32h2.rom.api.ld
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -31,6 +31,14 @@ PROVIDE ( esp_rom_uart_rx_string      = UartRxString );
 PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
 PROVIDE ( esp_rom_uart_putc           = ets_write_char_uart );
 
+PROVIDE ( esp_rom_output_flush_tx       = uart_tx_flush );
+PROVIDE ( esp_rom_output_tx_one_char    = uart_tx_one_char );
+PROVIDE ( esp_rom_output_tx_wait_idle   = uart_tx_wait_idle );
+PROVIDE ( esp_rom_output_rx_one_char    = uart_rx_one_char );
+PROVIDE ( esp_rom_output_rx_string      = UartRxString );
+PROVIDE ( esp_rom_output_set_as_console = uart_tx_switch );
+PROVIDE ( esp_rom_output_putc           = ets_write_char_uart );
+
 PROVIDE ( esp_rom_md5_init   = MD5Init );
 PROVIDE ( esp_rom_md5_update = MD5Update );
 PROVIDE ( esp_rom_md5_final  = MD5Final );
diff --git a/components/esp_rom/esp32p4/Kconfig.soc_caps.in b/components/esp_rom/esp32p4/Kconfig.soc_caps.in
index 75978111d7..78c3af265d 100644
--- a/components/esp_rom/esp32p4/Kconfig.soc_caps.in
+++ b/components/esp_rom/esp32p4/Kconfig.soc_caps.in
@@ -17,7 +17,11 @@ config ESP_ROM_UART_CLK_IS_XTAL
 
 config ESP_ROM_USB_SERIAL_DEVICE_NUM
     int
-    default 3
+    default 6
+
+config ESP_ROM_USB_OTG_NUM
+    int
+    default 5
 
 config ESP_ROM_HAS_RETARGETABLE_LOCKING
     bool
diff --git a/components/esp_rom/esp32p4/esp_rom_caps.h b/components/esp_rom/esp32p4/esp_rom_caps.h
index 60ffece0d5..acc4ff8e38 100644
--- a/components/esp_rom/esp32p4/esp_rom_caps.h
+++ b/components/esp_rom/esp32p4/esp_rom_caps.h
@@ -9,7 +9,8 @@
 #define ESP_ROM_HAS_CRC_LE                  (1) // ROM CRC library supports Little Endian
 #define ESP_ROM_HAS_CRC_BE                  (1) // ROM CRC library supports Big Endian
 #define ESP_ROM_UART_CLK_IS_XTAL            (1) // UART clock source is selected to XTAL in ROM
-#define ESP_ROM_USB_SERIAL_DEVICE_NUM       (3) // UART uses USB_SERIAL_JTAG port in ROM.
+#define ESP_ROM_USB_SERIAL_DEVICE_NUM       (6) // The serial port ID (UART, USB, ...) of USB_OTG CDC in the ROM.
+#define ESP_ROM_USB_OTG_NUM                 (5) // The serial port ID (UART, USB, ...) of USB_SERIAL_JTAG in the ROM.
 #define ESP_ROM_HAS_RETARGETABLE_LOCKING    (1) // ROM was built with retargetable locking
 #define ESP_ROM_GET_CLK_FREQ                (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
 #define ESP_ROM_HAS_RVFPLIB                 (1) // ROM has the rvfplib
diff --git a/components/esp_rom/esp32p4/ld/esp32p4.rom.api.ld b/components/esp_rom/esp32p4/ld/esp32p4.rom.api.ld
index cc4a2f969f..1c006e38b5 100644
--- a/components/esp_rom/esp32p4/ld/esp32p4.rom.api.ld
+++ b/components/esp_rom/esp32p4/ld/esp32p4.rom.api.ld
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -31,6 +31,14 @@ PROVIDE ( esp_rom_uart_rx_string      = UartRxString );
 PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
 PROVIDE ( esp_rom_uart_putc           = ets_write_char_uart );
 
+PROVIDE ( esp_rom_output_flush_tx       = uart_tx_flush );
+PROVIDE ( esp_rom_output_tx_one_char    = uart_tx_one_char );
+PROVIDE ( esp_rom_output_tx_wait_idle   = uart_tx_wait_idle );
+PROVIDE ( esp_rom_output_rx_one_char    = uart_rx_one_char );
+PROVIDE ( esp_rom_output_rx_string      = UartRxString );
+PROVIDE ( esp_rom_output_set_as_console = uart_tx_switch );
+PROVIDE ( esp_rom_output_putc           = ets_write_char_uart );
+
 PROVIDE ( esp_rom_md5_init   = MD5Init );
 PROVIDE ( esp_rom_md5_update = MD5Update );
 PROVIDE ( esp_rom_md5_final  = MD5Final );
diff --git a/components/esp_rom/esp32s2/Kconfig.soc_caps.in b/components/esp_rom/esp32s2/Kconfig.soc_caps.in
index c8dc1b24b9..077d3f780d 100644
--- a/components/esp_rom/esp32s2/Kconfig.soc_caps.in
+++ b/components/esp_rom/esp32s2/Kconfig.soc_caps.in
@@ -38,3 +38,7 @@ config ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG
 config ESP_ROM_HAS_SW_FLOAT
     bool
     default y
+
+config ESP_ROM_USB_SERIAL_DEVICE_NUM
+    int
+    default -1
diff --git a/components/esp_rom/esp32s2/esp_rom_caps.h b/components/esp_rom/esp32s2/esp_rom_caps.h
index b80ede21ce..0409926678 100644
--- a/components/esp_rom/esp32s2/esp_rom_caps.h
+++ b/components/esp_rom/esp32s2/esp_rom_caps.h
@@ -15,3 +15,4 @@
 #define ESP_ROM_USB_OTG_NUM                 (3) // The serial port ID (UART, USB, ...) of USB_OTG CDC in the ROM.
 #define ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG   (1) // ROM api Cache_Count_Flash_Pages will return unexpected value
 #define ESP_ROM_HAS_SW_FLOAT            (1) // ROM has libgcc software floating point emulation functions
+#define ESP_ROM_USB_SERIAL_DEVICE_NUM       (-1) // No USB_SERIAL_JTAG in the ROM, set -1 for Kconfig usage.
diff --git a/components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld b/components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld
index 98bda8396f..a67e67e834 100644
--- a/components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld
+++ b/components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld
@@ -29,6 +29,16 @@ PROVIDE ( esp_rom_uart_usb_acm_init   = Uart_Init_USB );
 PROVIDE ( esp_rom_uart_putc           = ets_write_char_uart );
 PROVIDE ( esp_rom_uart_switch_buffer  = uart_buff_switch );
 
+PROVIDE ( esp_rom_output_flush_tx       = uart_tx_flush );
+PROVIDE ( esp_rom_output_tx_one_char    = uart_tx_one_char );
+PROVIDE ( esp_rom_output_tx_wait_idle   = uart_tx_wait_idle );
+PROVIDE ( esp_rom_output_rx_one_char    = uart_rx_one_char );
+PROVIDE ( esp_rom_output_rx_string      = UartRxString );
+PROVIDE ( esp_rom_output_set_as_console = uart_tx_switch );
+PROVIDE ( esp_rom_output_usb_acm_init   = Uart_Init_USB );
+PROVIDE ( esp_rom_output_putc           = ets_write_char_uart );
+PROVIDE ( esp_rom_output_switch_buffer  = uart_buff_switch );
+
 /* wpa_supplicant re-implements the MD5 functions: MD5Init, MD5Update, MD5Final */
 /* so here we directly assign the symbols with the ROM API address */
 PROVIDE ( esp_rom_md5_init   = 0x4000526c );
diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld
index 2c63ea2647..8d2f2500ff 100644
--- a/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld
+++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld
@@ -29,6 +29,15 @@ PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
 PROVIDE ( esp_rom_uart_usb_acm_init   = Uart_Init_USB );
 PROVIDE ( esp_rom_uart_putc           = ets_write_char_uart );
 
+PROVIDE ( esp_rom_output_flush_tx       = uart_tx_flush );
+PROVIDE ( esp_rom_output_tx_one_char    = uart_tx_one_char );
+PROVIDE ( esp_rom_output_tx_wait_idle   = uart_tx_wait_idle );
+PROVIDE ( esp_rom_output_rx_one_char    = uart_rx_one_char );
+PROVIDE ( esp_rom_output_rx_string      = UartRxString );
+PROVIDE ( esp_rom_output_set_as_console = uart_tx_switch );
+PROVIDE ( esp_rom_output_usb_acm_init   = Uart_Init_USB );
+PROVIDE ( esp_rom_output_putc           = ets_write_char_uart );
+
 PROVIDE ( esp_rom_md5_init   = MD5Init );
 PROVIDE ( esp_rom_md5_update = MD5Update );
 PROVIDE ( esp_rom_md5_final  = MD5Final );
diff --git a/components/esp_rom/include/esp_rom_sys.h b/components/esp_rom/include/esp_rom_sys.h
index 953243ab20..c2eaabb98e 100644
--- a/components/esp_rom/include/esp_rom_sys.h
+++ b/components/esp_rom/include/esp_rom_sys.h
@@ -58,7 +58,7 @@ void esp_rom_delay_us(uint32_t us);
 void esp_rom_install_channel_putc(int channel, void (*putc)(char c));
 
 /**
- * @brief Install UART1 as the default console channel, equivalent to `esp_rom_install_channel_putc(1, esp_rom_uart_putc)`
+ * @brief Install UART1 as the default console channel, equivalent to `esp_rom_install_channel_putc(1, esp_rom_output_putc)`
  */
 void esp_rom_install_uart_printf(void);
 
diff --git a/components/esp_rom/include/esp_rom_uart.h b/components/esp_rom/include/esp_rom_uart.h
index c9350f5554..c09b7c5ac2 100644
--- a/components/esp_rom/include/esp_rom_uart.h
+++ b/components/esp_rom/include/esp_rom_uart.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -24,27 +24,31 @@ typedef enum {
 /**
  * @brief Wait for UART TX FIFO is empty and all data has been sent out.
  *
- * @param uart_no UART port number
+ * @param serial_num The serial number defined in ROM, including UART_x, USB_OTG, USB_SERIAL_JTAG..
  */
-void esp_rom_uart_tx_wait_idle(uint8_t uart_no);
+void esp_rom_output_tx_wait_idle(uint8_t serial_num);
+
+void esp_rom_uart_tx_wait_idle(uint8_t serial_num) __attribute__((deprecated("Please use esp_rom_output_tx_wait_idle instead")));
 
 /**
  * @brief Set clock source and baud rate for UART.
  *
- * @param uart_no UART port number
+ * @param serial_num UART port number
  * @param clock_hz Source clock (in Hz)
  * @param baud_rate Baud rate to set
  *
  * @note Only for HP UART
  */
-#define esp_rom_uart_set_clock_baudrate(uart_no, clock_hz, baud_rate) uart_ll_set_baudrate(UART_LL_GET_HW(uart_no), baud_rate, clock_hz)
+#define esp_rom_uart_set_clock_baudrate(serial_num, clock_hz, baud_rate) uart_ll_set_baudrate(UART_LL_GET_HW(serial_num), baud_rate, clock_hz)
 
 /**
  * @brief Wait until UART TX FIFO is empty (i.e. flush TX FIFO)
  *
- * @param uart_no UART port number
+ * @param serial_num UART port number
  */
-void esp_rom_uart_flush_tx(uint8_t uart_no);
+void esp_rom_output_flush_tx(uint8_t serial_num);
+
+void esp_rom_uart_flush_tx(uint8_t serial_num) __attribute__((deprecated("Please use esp_rom_output_flush_tx instead")));
 
 /**
  * @brief Transmit one character to the console channel.
@@ -54,7 +58,9 @@ void esp_rom_uart_flush_tx(uint8_t uart_no);
  *      - 0 on success
  *      - 1 on failure
  */
-int esp_rom_uart_tx_one_char(uint8_t c);
+int esp_rom_output_tx_one_char(uint8_t c);
+
+int esp_rom_uart_tx_one_char(uint8_t c) __attribute__((deprecated("Please use esp_rom_output_tx_one_char instead")));
 
 /**
  * @brief Transmit one character to the console channel.
@@ -62,7 +68,9 @@ int esp_rom_uart_tx_one_char(uint8_t c);
  *
  * @param c Character to send
  */
-void esp_rom_uart_putc(char c);
+void esp_rom_output_putc(char c);
+
+void esp_rom_uart_putc(char c) __attribute__((deprecated("Please use esp_rom_output_putc instead")));
 
 /**
  * @brief Get one character from the console channel.
@@ -72,7 +80,9 @@ void esp_rom_uart_putc(char c);
  *      - 0 on success
  *      - 1 on failure or no data available
  */
-int esp_rom_uart_rx_one_char(uint8_t *c);
+int esp_rom_output_rx_one_char(uint8_t *c);
+
+int esp_rom_uart_rx_one_char(uint8_t *c) __attribute__((deprecated("Please use esp_rom_output_rx_one_char instead")));
 
 /**
  * @brief Get one line of string from console channel (line ending won't be stored in the buffer).
@@ -81,7 +91,9 @@ int esp_rom_uart_rx_one_char(uint8_t *c);
  * @param max_len Maximum length of the buffer (including the NULL delimiter)
  * @return always return 0 when on success or wait in a loop for rx data
  */
-int esp_rom_uart_rx_string(uint8_t *str, uint8_t max_len);
+int esp_rom_output_rx_string(uint8_t *str, uint8_t max_len);
+
+int esp_rom_uart_rx_string(uint8_t *str, uint8_t max_len) __attribute__((deprecated("Please use esp_rom_output_rx_string instead")));
 
 /**
  * @brief Set the UART port used by ets_printf.
@@ -89,9 +101,11 @@ int esp_rom_uart_rx_string(uint8_t *str, uint8_t max_len);
  * @note USB-CDC port is also treated as "UART" port in the ROM code.
  *       Use ESP_ROM_USB_SERIAL_DEVICE_NUM or ESP_ROM_USB_OTG_NUM to identify USB_SERIAL_JTAG and USB_OTG, respectively.
  *
- * @param uart_no UART port number
+ * @param serial_num UART port number
  */
-void esp_rom_uart_set_as_console(uint8_t uart_no);
+void esp_rom_output_set_as_console(uint8_t serial_num);
+
+void esp_rom_uart_set_as_console(uint8_t serial_num) __attribute__((deprecated("Please use esp_rom_output_set_as_console instead")));
 
 /**
  * @brief Switch the UART port that will use a buffer for TX and RX.
@@ -99,9 +113,11 @@ void esp_rom_uart_set_as_console(uint8_t uart_no);
  * @note USB-CDC port is also treated as "UART" port in the ROM code.
  *       Use ESP_ROM_USB_SERIAL_DEVICE_NUM or ESP_ROM_USB_OTG_NUM to identify USB_SERIAL_JTAG and USB_OTG, respectively.
  *
- * @param uart_no UART port number
+ * @param serial_num UART port number
  */
-void esp_rom_uart_switch_buffer(uint8_t uart_no);
+void esp_rom_output_switch_buffer(uint8_t serial_num);
+
+void esp_rom_uart_switch_buffer(uint8_t serial_num) __attribute__((deprecated("Please use esp_rom_output_switch_buffer instead")));
 
 /**
  * @brief Initialize the USB ACM UART
@@ -110,7 +126,9 @@ void esp_rom_uart_switch_buffer(uint8_t uart_no);
  * @param cdc_acm_work_mem Pointer to the work memroy used for CDC-ACM
  * @param cdc_acm_work_mem_len Length of work memory
  */
-void esp_rom_uart_usb_acm_init(void *cdc_acm_work_mem, int cdc_acm_work_mem_len);
+void esp_rom_output_usb_acm_init(void *cdc_acm_work_mem, int cdc_acm_work_mem_len);
+
+void esp_rom_uart_usb_acm_init(uint8_t serial_num) __attribute__((deprecated("Please use esp_rom_output_usb_acm_init instead")));
 
 #ifdef __cplusplus
 }
diff --git a/components/esp_rom/linux/Kconfig.soc_caps.in b/components/esp_rom/linux/Kconfig.soc_caps.in
new file mode 100644
index 0000000000..d29fdef99a
--- /dev/null
+++ b/components/esp_rom/linux/Kconfig.soc_caps.in
@@ -0,0 +1,12 @@
+#####################################################
+# This file is auto-generated from SoC caps
+# using gen_soc_caps_kconfig.py, do not edit manually
+#####################################################
+
+config ESP_ROM_USB_OTG_NUM
+    int
+    default -1
+
+config ESP_ROM_USB_SERIAL_DEVICE_NUM
+    int
+    default -1
diff --git a/components/esp_rom/linux/esp_rom_caps.h b/components/esp_rom/linux/esp_rom_caps.h
new file mode 100644
index 0000000000..f51f1cda1f
--- /dev/null
+++ b/components/esp_rom/linux/esp_rom_caps.h
@@ -0,0 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define ESP_ROM_USB_OTG_NUM                 (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.
+#define ESP_ROM_USB_SERIAL_DEVICE_NUM       (-1) // No USB_SERIAL_JTAG in the ROM, set -1 for Kconfig usage.
diff --git a/components/esp_rom/patches/esp_rom_uart.c b/components/esp_rom/patches/esp_rom_uart.c
index 7e868b4b88..0740c9022e 100644
--- a/components/esp_rom/patches/esp_rom_uart.c
+++ b/components/esp_rom/patches/esp_rom_uart.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,7 +17,7 @@
 /**
  * The function defined in ROM code has a bug, so we re-implement it here.
  */
-IRAM_ATTR void esp_rom_uart_tx_wait_idle(uint8_t uart_no)
+IRAM_ATTR void esp_rom_output_tx_wait_idle(uint8_t uart_no)
 {
     while (!uart_ll_is_tx_idle(UART_LL_GET_HW(uart_no))) {};
 }
@@ -31,7 +31,7 @@ IRAM_ATTR void esp_rom_uart_tx_wait_idle(uint8_t uart_no)
  * function in the ROM interface, so here use the uart_tx_switch direct
  * address instead.
  */
-IRAM_ATTR void esp_rom_uart_set_as_console(uint8_t uart_no)
+IRAM_ATTR void esp_rom_output_set_as_console(uint8_t uart_no)
 {
     typedef void (*rom_func_t)(uint8_t);
     rom_func_t uart_tx_switch = NULL;
@@ -46,7 +46,7 @@ IRAM_ATTR void esp_rom_uart_set_as_console(uint8_t uart_no)
 #endif
 
 #if !ESP_ROM_HAS_UART_BUF_SWITCH
-IRAM_ATTR void esp_rom_uart_switch_buffer(uint8_t uart_no)
+IRAM_ATTR void esp_rom_output_switch_buffer(uint8_t uart_no)
 {
     UartDevice *uart = GetUartDevice();
     uart->buff_uart_no = uart_no;
diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig
index 7f3b2d1acc..a8763770ec 100644
--- a/components/esp_system/Kconfig
+++ b/components/esp_system/Kconfig
@@ -301,6 +301,17 @@ menu "ESP System Settings"
         default 1 if ESP_CONSOLE_UART_CUSTOM_NUM_1
         default -1 if !ESP_CONSOLE_UART
 
+    config ESP_CONSOLE_ROM_SERIAL_PORT_NUM
+        # This config is used for the correct serial number used in ROM uart function.
+        int
+        default 0 if ESP_CONSOLE_UART_DEFAULT
+        default 0 if ESP_CONSOLE_UART_CUSTOM_NUM_0
+        default 1 if ESP_CONSOLE_UART_CUSTOM_NUM_1
+        # Can be extended if we have more uarts.
+        default ESP_ROM_USB_SERIAL_DEVICE_NUM if ESP_CONSOLE_USB_SERIAL_JTAG
+        default ESP_ROM_USB_OTG_NUM if ESP_CONSOLE_USB_CDC
+        default -1 if ESP_CONSOLE_NONE
+
     config ESP_CONSOLE_UART_TX_GPIO
         int "UART TX on GPIO#"
         depends on ESP_CONSOLE_UART_CUSTOM
diff --git a/components/esp_system/fpga_overrides_clk.c b/components/esp_system/fpga_overrides_clk.c
index 72c7aa5ff2..51b9bae8fb 100644
--- a/components/esp_system/fpga_overrides_clk.c
+++ b/components/esp_system/fpga_overrides_clk.c
@@ -42,7 +42,7 @@ static void s_warn(void)
 void bootloader_clock_configure(void)
 {
     s_warn();
-    esp_rom_uart_tx_wait_idle(0);
+    esp_rom_output_tx_wait_idle(0);
 
     uint32_t xtal_freq_mhz = 40;
 #ifdef CONFIG_IDF_TARGET_ESP32S2
diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c
index 7e013976ba..7c5ee01583 100644
--- a/components/esp_system/port/cpu_start.c
+++ b/components/esp_system/port/cpu_start.c
@@ -220,7 +220,7 @@ void IRAM_ATTR call_start_cpu1(void)
     esp_rom_install_channel_putc(2, NULL);
 #else // CONFIG_ESP_CONSOLE_NONE
     esp_rom_install_uart_printf();
-    esp_rom_uart_set_as_console(CONFIG_ESP_CONSOLE_UART_NUM);
+    esp_rom_output_set_as_console(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
 #endif
 
 #if CONFIG_IDF_TARGET_ESP32
@@ -684,11 +684,11 @@ void IRAM_ATTR call_start_cpu0(void)
 #if ESP_ROM_UART_CLK_IS_XTAL
     clock_hz = esp_clk_xtal_freq(); // From esp32-s3 on, UART clock source is selected to XTAL in ROM
 #endif
-    esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+    esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
 
     // In a single thread mode, the freertos is not started yet. So don't have to use a critical section.
     int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); // To avoid build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV
-    esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
+    esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
 #endif
 #endif
 
diff --git a/components/esp_system/port/esp_system_chip.c b/components/esp_system/port/esp_system_chip.c
index d211df4122..6d535dcbe6 100644
--- a/components/esp_system/port/esp_system_chip.c
+++ b/components/esp_system/port/esp_system_chip.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -30,9 +30,8 @@ void IRAM_ATTR esp_restart_noos_dig(void)
     xt_ints_off(0xFFFFFFFF);
 #endif
 
-    // make sure all the panic handler output is sent from UART FIFO
-    if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
-        esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+    if (CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM != -1) {
+        esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
     }
 
 #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
diff --git a/components/esp_system/port/soc/esp32/clk.c b/components/esp_system/port/soc/esp32/clk.c
index 3cda5c5bae..d38eadb60b 100644
--- a/components/esp_system/port/soc/esp32/clk.c
+++ b/components/esp_system/port/soc/esp32/clk.c
@@ -175,8 +175,8 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
 
     // Wait for UART TX to finish, otherwise some UART output will be lost
     // when switching APB frequency
-    if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
-        esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+    if (CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM >= 0) {
+        esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
     }
 
     if (res) {
diff --git a/components/esp_system/port/soc/esp32/system_internal.c b/components/esp_system/port/soc/esp32/system_internal.c
index 47a0b1ace2..6a051a56e2 100644
--- a/components/esp_system/port/soc/esp32/system_internal.c
+++ b/components/esp_system/port/soc/esp32/system_internal.c
@@ -33,7 +33,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
     // Flush any data left in UART FIFOs before reset the UART peripheral
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
         if (uart_ll_is_enabled(i)) {
-            esp_rom_uart_tx_wait_idle(i);
+            esp_rom_output_tx_wait_idle(i);
         }
     }
 
diff --git a/components/esp_system/port/soc/esp32c2/clk.c b/components/esp_system/port/soc/esp32c2/clk.c
index ebeda2a9b8..37290f40a3 100644
--- a/components/esp_system/port/soc/esp32c2/clk.c
+++ b/components/esp_system/port/soc/esp32c2/clk.c
@@ -117,7 +117,7 @@ static const char *TAG = "clk";
 
     // Wait for UART TX to finish, otherwise some UART output will be lost
     // when switching APB frequency
-    esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+    esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
 
     if (res)  {
         rtc_clk_cpu_freq_set_config(&new_config);
diff --git a/components/esp_system/port/soc/esp32c2/system_internal.c b/components/esp_system/port/soc/esp32c2/system_internal.c
index da9094272a..1bf0b847cd 100644
--- a/components/esp_system/port/soc/esp32c2/system_internal.c
+++ b/components/esp_system/port/soc/esp32c2/system_internal.c
@@ -32,7 +32,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
     // Flush any data left in UART FIFOs before reset the UART peripheral
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
         if (uart_ll_is_enabled(i)) {
-            esp_rom_uart_tx_wait_idle(i);
+            esp_rom_output_tx_wait_idle(i);
         }
     }
 
diff --git a/components/esp_system/port/soc/esp32c3/clk.c b/components/esp_system/port/soc/esp32c3/clk.c
index 5dd4710eb9..361c728df3 100644
--- a/components/esp_system/port/soc/esp32c3/clk.c
+++ b/components/esp_system/port/soc/esp32c3/clk.c
@@ -122,7 +122,7 @@ static const char *TAG = "clk";
 
     // Wait for UART TX to finish, otherwise some UART output will be lost
     // when switching APB frequency
-    esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+    esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
 
     if (res)  {
         rtc_clk_cpu_freq_set_config(&new_config);
diff --git a/components/esp_system/port/soc/esp32c3/system_internal.c b/components/esp_system/port/soc/esp32c3/system_internal.c
index 5113bc2b72..f93a470c89 100644
--- a/components/esp_system/port/soc/esp32c3/system_internal.c
+++ b/components/esp_system/port/soc/esp32c3/system_internal.c
@@ -33,7 +33,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
     // Flush any data left in UART FIFOs before reset the UART peripheral
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
         if (uart_ll_is_enabled(i)) {
-            esp_rom_uart_tx_wait_idle(i);
+            esp_rom_output_tx_wait_idle(i);
         }
     }
 
diff --git a/components/esp_system/port/soc/esp32c5/clk.c b/components/esp_system/port/soc/esp32c5/clk.c
index 37b8c59d04..ec67c37346 100644
--- a/components/esp_system/port/soc/esp32c5/clk.c
+++ b/components/esp_system/port/soc/esp32c5/clk.c
@@ -98,7 +98,7 @@ static const char *TAG = "clk";
 
     // Wait for UART TX to finish, otherwise some UART output will be lost
     // when switching APB frequency
-    esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+    esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
 
     if (res)  {
         rtc_clk_cpu_freq_set_config(&new_config);
diff --git a/components/esp_system/port/soc/esp32c5/system_internal.c b/components/esp_system/port/soc/esp32c5/system_internal.c
index ea56bfead8..892a70dfbc 100644
--- a/components/esp_system/port/soc/esp32c5/system_internal.c
+++ b/components/esp_system/port/soc/esp32c5/system_internal.c
@@ -32,8 +32,8 @@
 void IRAM_ATTR esp_system_reset_modules_on_exit(void)
 {
     // Flush any data left in UART FIFOs before reset the UART peripheral
-    esp_rom_uart_tx_wait_idle(0);
-    esp_rom_uart_tx_wait_idle(1);
+    esp_rom_output_tx_wait_idle(0);
+    esp_rom_output_tx_wait_idle(1);
 
     modem_syscon_ll_reset_all(&MODEM_SYSCON);
     modem_lpcon_ll_reset_all(&MODEM_LPCON);
diff --git a/components/esp_system/port/soc/esp32c6/clk.c b/components/esp_system/port/soc/esp32c6/clk.c
index e16b697114..9143bacd68 100644
--- a/components/esp_system/port/soc/esp32c6/clk.c
+++ b/components/esp_system/port/soc/esp32c6/clk.c
@@ -99,7 +99,7 @@ static const char *TAG = "clk";
 
     // Wait for UART TX to finish, otherwise some UART output will be lost
     // when switching APB frequency
-    esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+    esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
 
     if (res)  {
         rtc_clk_cpu_freq_set_config(&new_config);
diff --git a/components/esp_system/port/soc/esp32c6/system_internal.c b/components/esp_system/port/soc/esp32c6/system_internal.c
index 2829b4de67..20ef9f373f 100644
--- a/components/esp_system/port/soc/esp32c6/system_internal.c
+++ b/components/esp_system/port/soc/esp32c6/system_internal.c
@@ -33,7 +33,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
     // Flush any data left in UART FIFOs before reset the UART peripheral
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
         if (uart_ll_is_enabled(i)) {
-            esp_rom_uart_tx_wait_idle(i);
+            esp_rom_output_tx_wait_idle(i);
         }
     }
 
diff --git a/components/esp_system/port/soc/esp32h2/clk.c b/components/esp_system/port/soc/esp32h2/clk.c
index 5546b1cd8d..2c8b5c6af1 100644
--- a/components/esp_system/port/soc/esp32h2/clk.c
+++ b/components/esp_system/port/soc/esp32h2/clk.c
@@ -98,7 +98,7 @@ static const char *TAG = "clk";
 
     // Wait for UART TX to finish, otherwise some UART output will be lost
     // when switching APB frequency
-    esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+    esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
 
     if (res)  {
         rtc_clk_cpu_freq_set_config(&new_config);
diff --git a/components/esp_system/port/soc/esp32h2/system_internal.c b/components/esp_system/port/soc/esp32h2/system_internal.c
index 93cbb12d55..9763d434b8 100644
--- a/components/esp_system/port/soc/esp32h2/system_internal.c
+++ b/components/esp_system/port/soc/esp32h2/system_internal.c
@@ -34,7 +34,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
     // Flush any data left in UART FIFOs before reset the UART peripheral
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
         if (uart_ll_is_enabled(i)) {
-            esp_rom_uart_tx_wait_idle(i);
+            esp_rom_output_tx_wait_idle(i);
         }
     }
 
diff --git a/components/esp_system/port/soc/esp32p4/clk.c b/components/esp_system/port/soc/esp32p4/clk.c
index 6f90f7c51c..d6c971e47d 100644
--- a/components/esp_system/port/soc/esp32p4/clk.c
+++ b/components/esp_system/port/soc/esp32p4/clk.c
@@ -93,7 +93,7 @@ static const char *TAG = "clk";
 
     // Wait for UART TX to finish, otherwise some UART output will be lost
     // when switching APB frequency
-    esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+    esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
 
     if (res)  {
         rtc_clk_cpu_freq_set_config(&new_config);
diff --git a/components/esp_system/port/soc/esp32p4/system_internal.c b/components/esp_system/port/soc/esp32p4/system_internal.c
index 8aaa97ce47..4e4ad39334 100644
--- a/components/esp_system/port/soc/esp32p4/system_internal.c
+++ b/components/esp_system/port/soc/esp32p4/system_internal.c
@@ -33,7 +33,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
     // Flush any data left in UART FIFOs
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
         if (uart_ll_is_enabled(i)) {
-            esp_rom_uart_tx_wait_idle(i);
+            esp_rom_output_tx_wait_idle(i);
         }
     }
 
diff --git a/components/esp_system/port/soc/esp32s2/clk.c b/components/esp_system/port/soc/esp32s2/clk.c
index 4c1fac6681..c962262d41 100644
--- a/components/esp_system/port/soc/esp32s2/clk.c
+++ b/components/esp_system/port/soc/esp32s2/clk.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -69,8 +69,8 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
         /* Ocode calibration will switch to XTAL frequency, need to wait for UART FIFO
          * to be empty, to avoid garbled output.
          */
-        if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
-            esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+        if (CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM >= 0) {
+            esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
         }
     }
     rtc_init(cfg);
@@ -123,8 +123,8 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
 
     // Wait for UART TX to finish, otherwise some UART output will be lost
     // when switching APB frequency
-    if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
-        esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+    if (CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM >= 0) {
+        esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
     }
 
     if (res) {
diff --git a/components/esp_system/port/soc/esp32s2/system_internal.c b/components/esp_system/port/soc/esp32s2/system_internal.c
index b790f36b65..1c3f3ed482 100644
--- a/components/esp_system/port/soc/esp32s2/system_internal.c
+++ b/components/esp_system/port/soc/esp32s2/system_internal.c
@@ -35,7 +35,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
     // Flush any data left in UART FIFOs before reset the UART peripheral
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
         if (uart_ll_is_enabled(i)) {
-            esp_rom_uart_tx_wait_idle(i);
+            esp_rom_output_tx_wait_idle(i);
         }
     }
 
diff --git a/components/esp_system/port/soc/esp32s3/clk.c b/components/esp_system/port/soc/esp32s3/clk.c
index 4c51e7fd9e..ba42cf0b9a 100644
--- a/components/esp_system/port/soc/esp32s3/clk.c
+++ b/components/esp_system/port/soc/esp32s3/clk.c
@@ -115,8 +115,8 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
 
     // Wait for UART TX to finish, otherwise some UART output will be lost
     // when switching APB frequency
-    if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
-        esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+    if (CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM >= 0) {
+        esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
     }
 
     if (res) {
diff --git a/components/esp_system/port/soc/esp32s3/system_internal.c b/components/esp_system/port/soc/esp32s3/system_internal.c
index aa6de2ece6..409dd35bf6 100644
--- a/components/esp_system/port/soc/esp32s3/system_internal.c
+++ b/components/esp_system/port/soc/esp32s3/system_internal.c
@@ -35,7 +35,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
     // Flush any data left in UART FIFOs before reset the UART peripheral
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
         if (uart_ll_is_enabled(i)) {
-            esp_rom_uart_tx_wait_idle(i);
+            esp_rom_output_tx_wait_idle(i);
         }
     }
 
diff --git a/components/esp_system/port/usb_console.c b/components/esp_system/port/usb_console.c
index fe8bf81587..d6d70b14ae 100644
--- a/components/esp_system/port/usb_console.c
+++ b/components/esp_system/port/usb_console.c
@@ -298,7 +298,7 @@ esp_err_t esp_usb_console_init(void)
 
 #ifdef CONFIG_ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
     /* Install esp_rom_printf handler */
-    esp_rom_uart_set_as_console(ESP_ROM_USB_OTG_NUM);
+    esp_rom_output_set_as_console(ESP_ROM_USB_OTG_NUM);
     esp_rom_install_channel_putc(1, &esp_usb_console_write_char);
 #endif // CONFIG_ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
 
diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_backtrace.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_backtrace.c
index 7724bc990a..f629b93739 100644
--- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_backtrace.c
+++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_backtrace.c
@@ -107,7 +107,7 @@ TEST_CASE_MULTIPLE_STAGES("Test backtrace from interrupt watchdog timeout", "[re
 
 static void write_char_crash(char c)
 {
-    esp_rom_uart_putc(c);
+    esp_rom_output_putc(c);
     hal_memset((void *)0x00000001, 0, 1);
 }
 
diff --git a/components/newlib/syscalls.c b/components/newlib/syscalls.c
index e5e1f24a0b..a573229923 100644
--- a/components/newlib/syscalls.c
+++ b/components/newlib/syscalls.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -32,7 +32,7 @@ ssize_t _write_r_console(struct _reent *r, int fd, const void * data, size_t siz
     const char* cdata = (const char*) data;
     if (fd == STDOUT_FILENO || fd == STDERR_FILENO) {
         for (size_t i = 0; i < size; ++i) {
-            esp_rom_uart_tx_one_char(cdata[i]);
+            esp_rom_output_tx_one_char(cdata[i]);
         }
         return size;
     }
@@ -46,7 +46,7 @@ ssize_t _read_r_console(struct _reent *r, int fd, void * data, size_t size)
     if (fd == STDIN_FILENO) {
         size_t received;
         for (received = 0; received < size; ++received) {
-            int status = esp_rom_uart_rx_one_char((uint8_t*) &cdata[received]);
+            int status = esp_rom_output_rx_one_char((uint8_t*) &cdata[received]);
             if (status != 0) {
                 break;
             }
@@ -76,13 +76,7 @@ static ssize_t _fstat_r_console(struct _reent *r, int fd, struct stat * st)
 static int _fsync_console(int fd)
 {
     if (fd == STDOUT_FILENO || fd == STDERR_FILENO) {
-#ifdef CONFIG_ESP_CONSOLE_UART
-        esp_rom_uart_flush_tx(CONFIG_ESP_CONSOLE_UART_NUM);
-#elif defined(CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG)
-        esp_rom_uart_flush_tx(CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM);
-#elif defined(CONFIG_ESP_CONSOLE_USB_CDC)
-        esp_rom_uart_flush_tx(CONFIG_ESP_ROM_USB_OTG_NUM);
-#endif
+        esp_rom_output_flush_tx(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
         return 0;
     }
     errno = EBADF;
diff --git a/components/unity/unity_port_esp32.c b/components/unity/unity_port_esp32.c
index 09c3a6ae96..2be18855d0 100644
--- a/components/unity/unity_port_esp32.c
+++ b/components/unity/unity_port_esp32.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,17 +16,17 @@ static uint32_t s_test_start, s_test_stop;
 void unity_putc(int c)
 {
     if (c == '\n') {
-        esp_rom_uart_tx_one_char('\r');
-        esp_rom_uart_tx_one_char('\n');
+        esp_rom_output_tx_one_char('\r');
+        esp_rom_output_tx_one_char('\n');
     } else if (c == '\r') {
     } else {
-        esp_rom_uart_tx_one_char(c);
+        esp_rom_output_tx_one_char(c);
     }
 }
 
 void unity_flush(void)
 {
-    esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+    esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM);
 }
 
 #define iscontrol(c) ((c) <= '\x1f' || (c) == '\x7f')
@@ -37,7 +37,7 @@ static void esp_unity_readline(char* dst, size_t len)
     size_t write_index = 0;
     for (;;) {
         char c = 0;
-        bool got_char = esp_rom_uart_rx_one_char((uint8_t*)&c) == 0;
+        bool got_char = esp_rom_output_rx_one_char((uint8_t*)&c) == 0;
         if (!got_char) {
           continue;
         }
@@ -50,9 +50,9 @@ static void esp_unity_readline(char* dst, size_t len)
             if (write_index > 0) {
                 /* Delete previously entered character */
                 write_index--;
-                esp_rom_uart_tx_one_char('\b');
-                esp_rom_uart_tx_one_char(' ');
-                esp_rom_uart_tx_one_char('\b');
+                esp_rom_output_tx_one_char('\b');
+                esp_rom_output_tx_one_char(' ');
+                esp_rom_output_tx_one_char('\b');
             }
         } else if (len > 0 && write_index < len - 1 && !iscontrol(c)) {
             /* Write a max of len - 1 characters to allow for null terminator */
@@ -83,7 +83,7 @@ void unity_gets(char *dst, size_t len)
     }
     /* Flush anything already in the RX buffer */
     uint8_t ignore;
-    while (esp_rom_uart_rx_one_char(&ignore) == 0) { }
+    while (esp_rom_output_rx_one_char(&ignore) == 0) { }
     /* Read input */
     esp_unity_readline(dst, len);
 }
diff --git a/tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py b/tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py
index a2ebffab39..3ba6608652 100755
--- a/tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py
+++ b/tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py
@@ -1,12 +1,10 @@
 #!/usr/bin/env python
 #
-# SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Apache-2.0
-
 """
 Generate Kconfig.soc_caps.in with defines from soc_caps.h
 """
-
 import argparse
 import inspect
 import io
@@ -18,8 +16,19 @@ from pathlib import Path
 from string import Template
 
 import pyparsing
-from pyparsing import (CaselessLiteral, Char, Combine, Group, Literal, OneOrMore,  # pylint: disable=unused-import
-                       Optional, ParserElement, QuotedString, Word, alphas, hexnums, nums)
+from pyparsing import alphas
+from pyparsing import CaselessLiteral
+from pyparsing import Char
+from pyparsing import Combine
+from pyparsing import Group
+from pyparsing import hexnums
+from pyparsing import Literal
+from pyparsing import nums
+from pyparsing import OneOrMore
+from pyparsing import Optional
+from pyparsing import ParserElement
+from pyparsing import QuotedString
+from pyparsing import Word
 
 pyparsing.usePackrat = True
 
@@ -107,7 +116,7 @@ def parse_define(define_line):  # type: (str) -> typing.Any[typing.Type[ParserEl
 
     # Define value, either a hex, int or a string
     hex_value = Combine(Literal('0x') + Word(hexnums) + Optional(literal_suffix).suppress())('hex_value')
-    int_value = Word(nums)('int_value') + ~Char('.') + Optional(literal_suffix)('literal_suffix')
+    int_value = Combine(Optional('-') + Word(nums))('int_value') + ~Char('.') + Optional(literal_suffix)('literal_suffix')
     str_value = QuotedString('"')('str_value')
 
     # Remove optional parenthesis around values