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component/bt : new coexist lib
change boot loader.ld , the 0x40098000 may set other instructions
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@ -15,7 +15,7 @@ MEMORY
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of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
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are connected to the data port of the CPU and eg allow bytewise access. */
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dport0_seg (RW) : org = 0x3FF00000, len = 0x10 /* IO */
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iram_seg (RWX) : org = 0x40098000, len = 0x1000
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iram_seg (RWX) : org = 0x4009A000, len = 0x1000
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iram_pool_1_seg (RWX) : org = 0x40078000, len = 0x8000 /* IRAM POOL1, used for APP CPU cache. We can abuse it in bootloader because APP CPU is still held in reset, until we enable APP CPU cache */
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dram_seg (RW) : org = 0x3FFC0000, len = 0x20000 /* Shared RAM, minus rom bss/data/stack.*/
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}
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@ -1 +1 @@
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Subproject commit 079b86ab34b57a6d62beb3f171af99399d45eb09
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Subproject commit 0c3df46cb357b795ff217e68f7a8fb56d68c537f
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@ -1 +1 @@
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Subproject commit ae7d66f7edb4f30372c9a620ac07e4559f55a85a
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Subproject commit 0ee9babfd9a9c95ff0395d442153df894df550f2
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@ -113,7 +113,6 @@ void app_main()
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{
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esp_err_t ret;
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phy_set_wifi_mode_only(0);
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nvs_flash_init();
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system_init();
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initialise_wifi();
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