alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

gpio: Fix IO hold function related problems

Browse Source 
1. Fix deep sleep wakeup IOs can not be unhold issue
2. Correct hold related APIs' description
3. Fix gpio_force_hold_all API

docs: Add GPIO wakeup source to sleep_modes doc for ESP32C3 and C2
This commit is contained in:
Song Ruo Jing 2022-10-27 15:09:34 +08:00
parent b3b3947207
commit 27f9ee66d5
27 changed files with 285 additions and 231 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
components/driver/gpio/gpio.c
View File

@ -707,10 +707,10 @@ void gpio_deep_sleep_hold_dis(void)
#if SOC_GPIO_SUPPORT_FORCE_HOLD
esp_err_t gpio_force_hold_all()
esp_err_t IRAM_ATTR gpio_force_hold_all()
{
#if SOC_RTCIO_HOLD_SUPPORTED
rtc_gpio_force_hold_all();
rtc_gpio_force_hold_en_all();
#endif
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
gpio_hal_force_hold_all();
@ -718,14 +718,14 @@ esp_err_t gpio_force_hold_all()
return ESP_OK;
}
esp_err_t gpio_force_unhold_all()
esp_err_t IRAM_ATTR gpio_force_unhold_all()
{
#if SOC_RTCIO_HOLD_SUPPORTED
rtc_gpio_force_hold_dis_all();
#endif
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
gpio_hal_force_unhold_all();
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
#if SOC_RTCIO_HOLD_SUPPORTED
rtc_gpio_force_hold_dis_all();
#endif
return ESP_OK;
}
#endif

42
components/driver/include/driver/gpio.h
View File

@ -361,16 +361,21 @@ esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t *stren
/**
* @brief Enable gpio pad hold function.
*
* When the pin is set to hold, the state is latched at that moment and will not change no matter how the internal
* signals change or how the IO MUX/GPIO configuration is modified (including input enable, output enable,
* output value, function, and drive strength values). It can be used to retain the pin state through a
* core reset and system reset triggered by watchdog time-out or Deep-sleep events.
*
* The gpio pad hold function works in both input and output modes, but must be output-capable gpios.
* If pad hold enabled:
* in output mode: the output level of the pad will be force locked and can not be changed.
* in input mode: the input value read will not change, regardless the changes of input signal.
* in input mode: input read value can still reflect the changes of the input signal.
*
* The state of digital gpio cannot be held during Deep-sleep, and it will resume the hold function
* The state of the digital gpio cannot be held during Deep-sleep, and it will resume to hold at its default pin state
* when the chip wakes up from Deep-sleep. If the digital gpio also needs to be held during Deep-sleep,
* `gpio_deep_sleep_hold_en` should also be called.
*
* Power down or call gpio_hold_dis will disable this function.
* Power down or call `gpio_hold_dis` will disable this function.
*
* @param gpio_num GPIO number, only support output-capable GPIOs
*
@ -400,19 +405,21 @@ esp_err_t gpio_hold_en(gpio_num_t gpio_num);
esp_err_t gpio_hold_dis(gpio_num_t gpio_num);
/**
* @brief Enable all digital gpio pad hold function during Deep-sleep.
* @brief Enable all digital gpio pads hold function during Deep-sleep.
*
* When the chip is in Deep-sleep mode, all digital gpio will hold the state before sleep, and when the chip is woken up,
* the status of digital gpio will not be held. Note that the pad hold feature only works when the chip is in Deep-sleep mode,
* when not in sleep mode, the digital gpio state can be changed even you have called this function.
* Enabling this feature makes all digital gpio pads be at the holding state during Deep-sleep. The state of each pad
* holds is its active configuration (not pad's sleep configuration!).
*
* Power down or call gpio_hold_dis will disable this function, otherwise, the digital gpio hold feature works as long as the chip enter Deep-sleep.
* Note that this pad hold feature only works when the chip is in Deep-sleep mode. When the chip is in active mode,
* the digital gpio state can be changed freely even you have called this function.
*
* After this API is being called, the digital gpio Deep-sleep hold feature will work during every sleep process. You
* should call `gpio_deep_sleep_hold_dis` to disable this feature.
*/
void gpio_deep_sleep_hold_en(void);
/**
* @brief Disable all digital gpio pad hold function during Deep-sleep.
*
* @brief Disable all digital gpio pads hold function during Deep-sleep.
*/
void gpio_deep_sleep_hold_dis(void);
@ -434,14 +441,21 @@ void gpio_iomux_out(uint8_t gpio_num, int func, bool oen_inv);
#if SOC_GPIO_SUPPORT_FORCE_HOLD
/**
* @brief Force hold digital and rtc gpio pad.
* @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
* @brief Force hold all digital and rtc gpio pads.
*
* GPIO force hold, no matter the chip in active mode or sleep modes.
*
* This function will immediately cause all pads to latch the current values of input enable, output enable,
* output value, function, and drive strength values.
*
* @warning This function will hold flash and UART pins as well. Therefore, this function, and all code run afterwards
* (till calling `gpio_force_unhold_all` to disable this feature), MUST be placed in internal RAM as holding the flash
* pins will halt SPI flash operation, and holding the UART pins will halt any UART logging.
* */
esp_err_t gpio_force_hold_all(void);
/**
* @brief Force unhold digital and rtc gpio pad.
* @note GPIO force unhold, whether the chip in sleep mode or wakeup mode.
* @brief Force unhold all digital and rtc gpio pads.
* */
esp_err_t gpio_force_unhold_all(void);
#endif

2
components/driver/include/driver/rtc_io.h
View File

@ -258,7 +258,7 @@ esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num);
* Force hold signal is enabled before going into deep sleep for pins which
* are used for EXT1 wakeup.
*/
esp_err_t rtc_gpio_force_hold_all(void);
esp_err_t rtc_gpio_force_hold_en_all(void);
/**
* @brief Disable force hold signal for all RTC IOs

7
components/esp_hw_support/include/esp_private/sleep_gpio.h
View File

@ -15,7 +15,7 @@ extern "C" {
/**
* @file sleep_gpio.h
*
* This file contains declarations of GPIO related functions in light sleep mode.
* This file contains declarations of GPIO related functions in sleep modes.
*/
#if CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL
@ -41,6 +41,11 @@ void gpio_sleep_mode_config_unapply(void);
#endif // CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL
/**
* @brief Call once in startup to disable the wakeup IO pins and release their holding state after waking up from Deep-sleep
*/
void esp_deep_sleep_wakeup_io_reset(void);
#ifdef __cplusplus
}
#endif

14
components/esp_hw_support/include/esp_sleep.h
View File

@ -239,25 +239,25 @@ esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t mask, esp_sleep_ext1_wakeup_mode
* This function enables an IO pin to wake up the chip from deep sleep.
*
* @note This function does not modify pin configuration. The pins are
* configured in esp_deep_sleep_start/esp_light_sleep_start,
* immediately before entering sleep mode.
* configured inside esp_deep_sleep_start, immediately before entering sleep mode.
*
* @note You don't need to care to pull-up or pull-down before using this
* function, because this will be done in esp_deep_sleep_start/esp_light_sleep_start
* based on param mask you give. BTW, when you use low level to wake up the
* chip, we strongly recommand you to add external registors (pull-up).
* function, because this will be set internally in esp_deep_sleep_start
* based on the wakeup mode. BTW, when you use low level to wake up the
* chip, we strongly recommend you to add external resistors (pull-up).
*
* @param gpio_pin_mask Bit mask of GPIO numbers which will cause wakeup. Only GPIOs
* which are have RTC functionality can be used in this bit map.
* which have RTC functionality (pads that powered by VDD3P3_RTC) can be used in this bit map.
* @param mode Select logic function used to determine wakeup condition:
* - ESP_GPIO_WAKEUP_GPIO_LOW: wake up when the gpio turn to low.
* - ESP_GPIO_WAKEUP_GPIO_HIGH: wake up when the gpio turn to high.
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_ARG if gpio num is more than 5 or mode is invalid,
* - ESP_ERR_INVALID_ARG if the mask contains any invalid deep sleep wakeup pin or wakeup mode is invalid
*/
esp_err_t esp_deep_sleep_enable_gpio_wakeup(uint64_t gpio_pin_mask, esp_deepsleep_gpio_wake_up_mode_t mode);
#endif
/**
* @brief Enable wakeup from light sleep using GPIOs
*

36
components/esp_hw_support/sleep_gpio.c
View File

@ -19,6 +19,8 @@
#include "driver/gpio.h"
#include "hal/gpio_hal.h"
#include "hal/rtc_io_hal.h"
#include "hal/rtc_hal.h"
#include "esp_private/gpio.h"
#include "esp_private/sleep_gpio.h"
#include "esp_private/spi_flash_os.h"
@ -133,3 +135,37 @@ IRAM_ATTR void esp_sleep_isolate_digital_gpio(void)
}
}
#endif
void esp_deep_sleep_wakeup_io_reset(void)
{
#if SOC_PM_SUPPORT_EXT_WAKEUP
uint32_t rtc_io_mask = rtc_hal_ext1_get_wakeup_pins();
// Disable ext1 wakeup before releasing hold, such that wakeup status can reflect the correct wakeup pin
rtc_hal_ext1_clear_wakeup_pins();
for (int gpio_num = 0; gpio_num < SOC_GPIO_PIN_COUNT && rtc_io_mask != 0; ++gpio_num) {
int rtcio_num = rtc_io_num_map[gpio_num];
if ((rtc_io_mask & BIT(rtcio_num)) == 0) {
continue;
}
rtcio_hal_hold_disable(rtcio_num);
rtc_io_mask &= ~BIT(rtcio_num);
}
#endif
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
uint32_t dl_io_mask = SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK;
gpio_hal_context_t gpio_hal = {
.dev = GPIO_HAL_GET_HW(GPIO_PORT_0)
};
while (dl_io_mask) {
int gpio_num = __builtin_ffs(dl_io_mask) - 1;
bool wakeup_io_enabled = gpio_hal_deepsleep_wakeup_is_enabled(&gpio_hal, gpio_num);
if (wakeup_io_enabled) {
// Disable the wakeup before releasing hold, such that wakeup status can reflect the correct wakeup pin
gpio_hal_deepsleep_wakeup_disable(&gpio_hal, gpio_num);
gpio_hal_hold_dis(&gpio_hal, gpio_num);
}
dl_io_mask &= ~BIT(gpio_num);
}
#endif
}

20
components/esp_hw_support/sleep_modes.c
View File

@ -207,7 +207,7 @@ static void timer_wakeup_prepare(void);
static void touch_wakeup_prepare(void);
#endif
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
static void esp_deep_sleep_wakeup_prepare(void);
static void gpio_deep_sleep_wakeup_prepare(void);
#endif
#if SOC_RTC_FAST_MEM_SUPPORTED
@ -431,8 +431,8 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
#endif
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
if (s_config.wakeup_triggers & RTC_GPIO_TRIG_EN) {
esp_deep_sleep_wakeup_prepare();
if (deep_sleep && (s_config.wakeup_triggers & RTC_GPIO_TRIG_EN)) {
gpio_deep_sleep_wakeup_prepare();
}
#endif
@ -1101,7 +1101,7 @@ static void ext1_wakeup_prepare(void)
}
// Clear state from previous wakeup
rtc_hal_ext1_clear_wakeup_pins();
rtc_hal_ext1_clear_wakeup_status();
// Set RTC IO pins and mode (any high, all low) to be used for wakeup
rtc_hal_ext1_set_wakeup_pins(s_config.ext1_rtc_gpio_mask, s_config.ext1_trigger_mode);
}
@ -1111,7 +1111,7 @@ uint64_t esp_sleep_get_ext1_wakeup_status(void)
if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_EXT1) {
return 0;
}
uint32_t status = rtc_hal_ext1_get_wakeup_pins();
uint32_t status = rtc_hal_ext1_get_wakeup_status();
// Translate bit map of RTC IO numbers into the bit map of GPIO numbers
uint64_t gpio_mask = 0;
for (int gpio = 0; gpio < GPIO_PIN_COUNT; ++gpio) {
@ -1136,10 +1136,10 @@ uint64_t esp_sleep_get_gpio_wakeup_status(void)
return 0;
}
return rtc_hal_gpio_get_wakeup_pins();
return rtc_hal_gpio_get_wakeup_status();
}
static void esp_deep_sleep_wakeup_prepare(void)
static void gpio_deep_sleep_wakeup_prepare(void)
{
for (gpio_num_t gpio_idx = GPIO_NUM_0; gpio_idx < GPIO_NUM_MAX; gpio_idx++) {
if (((1ULL << gpio_idx) & s_config.gpio_wakeup_mask) == 0) {
@ -1152,9 +1152,10 @@ static void esp_deep_sleep_wakeup_prepare(void)
ESP_ERROR_CHECK(gpio_pullup_en(gpio_idx));
ESP_ERROR_CHECK(gpio_pulldown_dis(gpio_idx));
}
rtc_hal_gpio_set_wakeup_pins();
ESP_ERROR_CHECK(gpio_hold_en(gpio_idx));
}
// Clear state from previous wakeup
rtc_hal_gpio_clear_wakeup_status();
}
esp_err_t esp_deep_sleep_enable_gpio_wakeup(uint64_t gpio_pin_mask, esp_deepsleep_gpio_wake_up_mode_t mode)
@ -1170,7 +1171,7 @@ esp_err_t esp_deep_sleep_enable_gpio_wakeup(uint64_t gpio_pin_mask, esp_deepslee
continue;
}
if (!esp_sleep_is_valid_wakeup_gpio(gpio_idx)) {
ESP_LOGE(TAG, "invalid mask, please ensure gpio number is no more than 5");
ESP_LOGE(TAG, "gpio %d is an invalid deep sleep wakeup IO", gpio_idx);
return ESP_ERR_INVALID_ARG;
}
err = gpio_deep_sleep_wakeup_enable(gpio_idx, intr_type);
@ -1183,7 +1184,6 @@ esp_err_t esp_deep_sleep_enable_gpio_wakeup(uint64_t gpio_pin_mask, esp_deepslee
}
}
s_config.wakeup_triggers |= RTC_GPIO_TRIG_EN;
rtc_hal_gpio_clear_wakeup_pins();
return err;
}

12
components/esp_system/port/cpu_start.c
View File

@ -71,8 +71,7 @@
#include "esp_private/crosscore_int.h"
#include "esp_flash_encrypt.h"
#include "hal/rtc_io_hal.h"
#include "hal/gpio_hal.h"
#include "esp_private/sleep_gpio.h"
#include "hal/wdt_hal.h"
#include "soc/rtc.h"
#include "hal/efuse_ll.h"
@ -519,11 +518,10 @@ void IRAM_ATTR call_start_cpu0(void)
#endif
#endif
#if SOC_RTCIO_HOLD_SUPPORTED
rtcio_hal_unhold_all();
#else
gpio_hal_force_unhold_all();
#endif
// Need to unhold the IOs that were hold right before entering deep sleep, which are used as wakeup pins
if (rst_reas[0] == RESET_REASON_CORE_DEEP_SLEEP) {
esp_deep_sleep_wakeup_io_reset();
}
esp_cache_err_int_init();

14
components/hal/esp32/include/hal/rtc_cntl_ll.h
View File

@ -20,12 +20,12 @@ static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
}
static inline void rtc_cntl_ll_ext1_clear_wakeup_pins(void)
static inline void rtc_cntl_ll_ext1_clear_wakeup_status(void)
{
REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR);
}
static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void)
static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_status(void)
{
return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS);
}
@ -37,6 +37,16 @@ static inline void rtc_cntl_ll_ext1_set_wakeup_pins(uint32_t mask, int mode)
mode, RTC_CNTL_EXT_WAKEUP1_LV_S);
}
static inline void rtc_cntl_ll_ext1_clear_wakeup_pins(void)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL_M);
}
static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void)
{
return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL);
}
static inline void rtc_cntl_ll_ulp_wakeup_enable(void)
{
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN);

8
components/hal/esp32/include/hal/rtc_io_ll.h
View File

@ -209,7 +209,7 @@ static inline void rtcio_ll_pulldown_disable(int rtcio_num)
}
/**
* Enable force hold function for RTC IO pad.
* Enable force hold function on an RTC IO pad.
*
* Enabling HOLD function will cause the pad to lock current status, such as,
* input/output enable, input/output value, function, drive strength values.
@ -225,7 +225,7 @@ static inline void rtcio_ll_force_hold_enable(int rtcio_num)
}
/**
* Disable hold function on an RTC IO pad
* Disable hold function on an RTC IO pad.
*
* @note If disable the pad hold, the status of pad maybe changed in sleep mode.
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
@ -237,7 +237,7 @@ static inline void rtcio_ll_force_hold_disable(int rtcio_num)
}
/**
* Enable force hold function for RTC IO pad.
* Enable force hold function on all RTC IO pads.
*
* Enabling HOLD function will cause the pad to lock current status, such as,
* input/output enable, input/output value, function, drive strength values.
@ -252,7 +252,7 @@ static inline void rtcio_ll_force_hold_all(void)
}
/**
* Disable hold function on an RTC IO pad
* Disable hold function on all RTC IO pads.
*
* @note If disable the pad hold, the status of pad maybe changed in sleep mode.
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).

20
components/hal/esp32c2/include/hal/gpio_ll.h
View File

@ -453,7 +453,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
}
/**
* @brief Force hold digital and rtc gpio pad.
* @brief Force hold all digital(VDD3P3_CPU) and rtc(VDD3P3_RTC) gpio pads.
* @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
*/
static inline void gpio_ll_force_hold_all(void)
@ -464,15 +464,15 @@ static inline void gpio_ll_force_hold_all(void)
}
/**
* @brief Force unhold digital and rtc gpio pad.
* @brief Force unhold all digital(VDD3P3_CPU) and rtc(VDD3P3_RTC) gpio pads.
* @note GPIO force unhold, whether the chip in sleep mode or wakeup mode.
*/
static inline void gpio_ll_force_unhold_all(void)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M);
SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M);
}
/**
@ -619,6 +619,20 @@ static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, uint32_t gpi
CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3);
}
/**
* @brief Get the status of whether an IO is used for deep-sleep wake-up.
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number
* @return True if the pin is enabled to wake up from deep-sleep
*/
static inline bool gpio_ll_deepsleep_wakeup_is_enabled(gpio_dev_t *hw, uint32_t gpio_num)
{
HAL_ASSERT(gpio_num <= GPIO_NUM_5 && "gpio larger than 5 does not support deep sleep wake-up function");
return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num));
}
#ifdef __cplusplus
}
#endif

10
components/hal/esp32c2/include/hal/rtc_cntl_ll.h
View File

@ -24,19 +24,15 @@ static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
}
static inline uint32_t rtc_cntl_ll_gpio_get_wakeup_pins(void)
static inline uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void)
{
return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS);
}
static inline void rtc_cntl_ll_gpio_set_wakeup_pins(void)
{
REG_CLR_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR);
}
static inline void rtc_cntl_ll_gpio_clear_wakeup_pins(void)
static inline void rtc_cntl_ll_gpio_clear_wakeup_status(void)
{
REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR);
REG_CLR_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR);
}
static inline void rtc_cntl_ll_enable_cpu_retention(uint32_t addr)

20
components/hal/esp32c3/include/hal/gpio_ll.h
View File

@ -469,7 +469,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
}
/**
* @brief Force hold digital and rtc gpio pad.
* @brief Force hold all digital(VDD3P3_CPU) and rtc(VDD3P3_RTC) gpio pads.
* @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
*/
static inline void gpio_ll_force_hold_all(void)
@ -480,15 +480,15 @@ static inline void gpio_ll_force_hold_all(void)
}
/**
* @brief Force unhold digital and rtc gpio pad.
* @brief Force unhold all digital(VDD3P3_CPU) and rtc(VDD3P3_RTC) gpio pads.
* @note GPIO force unhold, whether the chip in sleep mode or wakeup mode.
*/
static inline void gpio_ll_force_unhold_all(void)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M);
SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M);
}
/**
@ -635,6 +635,20 @@ static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, uint32_t gpi
CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3);
}
/**
* @brief Get the status of whether an IO is used for deep-sleep wake-up.
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number
* @return True if the pin is enabled to wake up from deep-sleep
*/
static inline bool gpio_ll_deepsleep_wakeup_is_enabled(gpio_dev_t *hw, uint32_t gpio_num)
{
HAL_ASSERT(gpio_num <= GPIO_NUM_5 && "gpio larger than 5 does not support deep sleep wake-up function");
return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num));
}
#ifdef __cplusplus
}
#endif

28
components/hal/esp32c3/include/hal/rtc_cntl_ll.h
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
@ -32,19 +24,15 @@ static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
}
static inline uint32_t rtc_cntl_ll_gpio_get_wakeup_pins(void)
static inline uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void)
{
return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS);
}
static inline void rtc_cntl_ll_gpio_set_wakeup_pins(void)
{
REG_CLR_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR);
}
static inline void rtc_cntl_ll_gpio_clear_wakeup_pins(void)
static inline void rtc_cntl_ll_gpio_clear_wakeup_status(void)
{
REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR);
REG_CLR_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR);
}
static inline void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t addr)

28
components/hal/esp32h2/include/hal/rtc_cntl_ll.h
View File

@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
@ -32,19 +24,15 @@ static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
}
static inline uint32_t rtc_cntl_ll_gpio_get_wakeup_pins(void)
static inline uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void)
{
return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS);
}
static inline void rtc_cntl_ll_gpio_set_wakeup_pins(void)
{
REG_CLR_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR);
}
static inline void rtc_cntl_ll_gpio_clear_wakeup_pins(void)
static inline void rtc_cntl_ll_gpio_clear_wakeup_status(void)
{
REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR);
REG_CLR_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR);
}
static inline void rtc_cntl_ll_enable_cpu_retention(uint32_t addr)

23
components/hal/esp32h2/include/rev1/hal/gpio_ll.h
View File

@ -14,6 +14,8 @@
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/gpio_periph.h"
#include "soc/rtc_cntl_reg.h"
@ -21,7 +23,6 @@
#include "soc/usb_serial_jtag_reg.h"
#include "hal/gpio_types.h"
#include "hal/assert.h"
#include "stdlib.h"
#ifdef __cplusplus
extern "C" {
@ -439,7 +440,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
}
/**
* @brief Force hold digital and rtc gpio pad.
* @brief Force hold all digital(VDD3P3_CPU) and rtc(VDD3P3_RTC) gpio pads.
* @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
*/
static inline void gpio_ll_force_hold_all(void)
@ -450,15 +451,15 @@ static inline void gpio_ll_force_hold_all(void)
}
/**
* @brief Force unhold digital and rtc gpio pad.
* @brief Force unhold all digital(VDD3P3_CPU) and rtc(VDD3P3_RTC) gpio pads.
* @note GPIO force unhold, whether the chip in sleep mode or wakeup mode.
*/
static inline void gpio_ll_force_unhold_all(void)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M);
SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M);
}
/**
@ -605,6 +606,20 @@ static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, uint32_t gpi
CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3);
}
/**
* @brief Get the status of whether an IO is used for deep-sleep wake-up.
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number
* @return True if the pin is enabled to wake up from deep-sleep
*/
static inline bool gpio_ll_deepsleep_wakeup_is_enabled(gpio_dev_t *hw, uint32_t gpio_num)
{
HAL_ASSERT(gpio_num <= GPIO_NUM_5 && "gpio larger than 5 does not support deep sleep wake-up function");
return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num));
}
#ifdef __cplusplus
}
#endif

34
components/hal/esp32h2/include/rev2/hal/gpio_ll.h
View File

@ -14,6 +14,8 @@
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/gpio_periph.h"
#include "soc/rtc_cntl_reg.h"
@ -21,7 +23,6 @@
#include "soc/usb_serial_jtag_reg.h"
#include "hal/gpio_types.h"
#include "hal/assert.h"
#include "stdlib.h"
#ifdef __cplusplus
extern "C" {
@ -415,7 +416,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
}
/**
* @brief Force hold digital and rtc gpio pad.
* @brief Force hold all digital(VDD3P3_CPU) and rtc(VDD3P3_RTC) gpio pads.
* @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
*/
static inline void gpio_ll_force_hold_all(void)
@ -426,15 +427,15 @@ static inline void gpio_ll_force_hold_all(void)
}
/**
* @brief Force unhold digital and rtc gpio pad.
* @brief Force unhold all digital(VDD3P3_CPU) and rtc(VDD3P3_RTC) gpio pads.
* @note GPIO force unhold, whether the chip in sleep mode or wakeup mode.
*/
static inline void gpio_ll_force_unhold_all(void)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M);
SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD);
CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M);
}
/**
@ -561,10 +562,10 @@ static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, uint32_t gpio
REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN_CLK_GATE);
REG_SET_BIT(RTC_CNTL_EXT_WAKEUP_CONF_REG, RTC_CNTL_GPIO_WAKEUP_FILTER);
SET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num));
SET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - (gpio_num - 7)));
uint32_t reg = REG_READ(RTC_CNTL_GPIO_WAKEUP_REG);
reg &= (~(RTC_CNTL_GPIO_PIN0_INT_TYPE_V << (RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3)));
reg |= (intr_type << (RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3));
reg &= (~(RTC_CNTL_GPIO_PIN0_INT_TYPE_V << (RTC_CNTL_GPIO_PIN0_INT_TYPE_S - (gpio_num - 7) * 3)));
reg |= (intr_type << (RTC_CNTL_GPIO_PIN0_INT_TYPE_S - (gpio_num - 7) * 3));
REG_WRITE(RTC_CNTL_GPIO_WAKEUP_REG, reg);
}
@ -579,8 +580,23 @@ static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, uint32_t gpi
HAL_ASSERT((gpio_num >= GPIO_NUM_7 && gpio_num <= GPIO_NUM_12) &&
"only gpio7~12 support deep sleep wake-up function");
CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num));
CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3);
CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - (gpio_num - 7)));
CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN0_INT_TYPE_S - (gpio_num - 7) * 3);
}
/**
* @brief Get the status of whether an IO is used for deep-sleep wake-up.
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number
* @return True if the pin is enabled to wake up from deep-sleep
*/
static inline bool gpio_ll_deepsleep_wakeup_is_enabled(gpio_dev_t *hw, uint32_t gpio_num)
{
HAL_ASSERT((gpio_num >= GPIO_NUM_7 && gpio_num <= GPIO_NUM_12) &&
"only gpio7~12 support deep sleep wake-up function");
return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - (gpio_num - 7)));
}
#ifdef __cplusplus

14
components/hal/esp32s2/include/hal/rtc_cntl_ll.h
View File

@ -23,7 +23,12 @@ static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
}
static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void)
static inline void rtc_cntl_ll_ext1_clear_wakeup_status(void)
{
REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR);
}
static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_status(void)
{
return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS);
}
@ -37,7 +42,12 @@ static inline void rtc_cntl_ll_ext1_set_wakeup_pins(uint32_t mask, int mode)
static inline void rtc_cntl_ll_ext1_clear_wakeup_pins(void)
{
REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR);
CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL_M);
}
static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void)
{
return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL);
}
static inline void rtc_cntl_ll_ulp_int_clear(void)

26
components/hal/esp32s2/include/hal/rtc_io_ll.h
View File

@ -1,16 +1,8 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
@ -220,7 +212,7 @@ static inline void rtcio_ll_pulldown_disable(int rtcio_num)
}
/**
* Enable force hold function for RTC IO pad.
* Enable force hold function on an RTC IO pad.
*
* Enabling HOLD function will cause the pad to lock current status, such as,
* input/output enable, input/output value, function, drive strength values.
@ -235,7 +227,7 @@ static inline void rtcio_ll_force_hold_enable(int rtcio_num)
}
/**
* Disable hold function on an RTC IO pad
* Disable hold function on an RTC IO pad.
*
* @note If disable the pad hold, the status of pad maybe changed in sleep mode.
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
@ -246,7 +238,7 @@ static inline void rtcio_ll_force_hold_disable(int rtcio_num)
}
/**
* Enable force hold function for RTC IO pad.
* Enable force hold function on all RTC IO pads.
*
* Enabling HOLD function will cause the pad to lock current status, such as,
* input/output enable, input/output value, function, drive strength values.
@ -261,7 +253,7 @@ static inline void rtcio_ll_force_hold_all(void)
}
/**
* Disable hold function on an RTC IO pad
* Disable hold function on all RTC IO pads.
*
* @note If disable the pad hold, the status of pad maybe changed in sleep mode.
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).

14
components/hal/esp32s3/include/hal/rtc_cntl_ll.h
View File

@ -27,7 +27,12 @@ static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
}
static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void)
static inline void rtc_cntl_ll_ext1_clear_wakeup_status(void)
{
REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR);
}
static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_status(void)
{
return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS);
}
@ -41,7 +46,12 @@ static inline void rtc_cntl_ll_ext1_set_wakeup_pins(uint32_t mask, int mode)
static inline void rtc_cntl_ll_ext1_clear_wakeup_pins(void)
{
REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR);
CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL_M);
}
static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void)
{
return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL);
}
static inline void rtc_cntl_ll_set_tagmem_retention_link_addr(uint32_t link_addr)

8
components/hal/esp32s3/include/hal/rtc_io_ll.h
View File

@ -228,7 +228,7 @@ static inline void rtcio_ll_pulldown_disable(int rtcio_num)
}
/**
* Enable force hold function for RTC IO pad.
* Enable force hold function on an RTC IO pad.
*
* Enabling HOLD function will cause the pad to lock current status, such as,
* input/output enable, input/output value, function, drive strength values.
@ -243,7 +243,7 @@ static inline void rtcio_ll_force_hold_enable(int rtcio_num)
}
/**
* Disable hold function on an RTC IO pad
* Disable hold function on an RTC IO pad.
*
* @note If disable the pad hold, the status of pad maybe changed in sleep mode.
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
@ -254,7 +254,7 @@ static inline void rtcio_ll_force_hold_disable(int rtcio_num)
}
/**
* Enable force hold function for RTC IO pad.
* Enable force hold function on all RTC IO pads.
*
* Enabling HOLD function will cause the pad to lock current status, such as,
* input/output enable, input/output value, function, drive strength values.
@ -269,7 +269,7 @@ static inline void rtcio_ll_force_hold_all(void)
}
/**
* Disable hold function on an RTC IO pad
* Disable hold function on all RTC IO pads.
*
* @note If disable the pad hold, the status of pad maybe changed in sleep mode.
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).

13
components/hal/include/hal/gpio_hal.h
View File

@ -338,13 +338,13 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num);
#if SOC_GPIO_SUPPORT_FORCE_HOLD
/**
* @brief Force hold digital gpio pad.
* @brief Force hold all digital gpio pads (including those powered by VDD3P3_RTC power domain).
* @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
*/
#define gpio_hal_force_hold_all() gpio_ll_force_hold_all()
/**
* @brief Force unhold digital gpio pad.
* @brief Force unhold all digital gpio pads (including those powered by VDD3P3_RTC power domain).
* @note GPIO force unhold, whether the chip in sleep mode or wakeup mode.
*/
#define gpio_hal_force_unhold_all() gpio_ll_force_unhold_all()
@ -474,6 +474,15 @@ void gpio_hal_sleep_pupd_config_unapply(gpio_hal_context_t *hal, uint32_t gpio_n
*/
#define gpio_hal_is_valid_deepsleep_wakeup_gpio(gpio_num) (gpio_num <= GPIO_NUM_5)
/**
* @brief Get the status of whether an IO is used for deep-sleep wake-up.
*
* @param hal Context of the HAL layer
* @param gpio_num GPIO number
*
* @return True if the pin is enabled to wake up from deep-sleep
*/
#define gpio_hal_deepsleep_wakeup_is_enabled(hal, gpio_num) gpio_ll_deepsleep_wakeup_is_enabled((hal)->dev, gpio_num)
#endif //SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
/**

12
components/hal/include/hal/rtc_hal.h
View File

@ -41,21 +41,23 @@ typedef struct rtc_cntl_sleep_retent {
#if SOC_PM_SUPPORT_EXT_WAKEUP
#define rtc_hal_ext1_get_wakeup_pins() rtc_cntl_ll_ext1_get_wakeup_pins()
#define rtc_hal_ext1_get_wakeup_status() rtc_cntl_ll_ext1_get_wakeup_status()
#define rtc_hal_ext1_clear_wakeup_status() rtc_cntl_ll_ext1_clear_wakeup_status()
#define rtc_hal_ext1_set_wakeup_pins(mask, mode) rtc_cntl_ll_ext1_set_wakeup_pins(mask, mode)
#define rtc_hal_ext1_clear_wakeup_pins() rtc_cntl_ll_ext1_clear_wakeup_pins()
#define rtc_hal_ext1_get_wakeup_pins() rtc_cntl_ll_ext1_get_wakeup_pins()
#endif
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
#define rtc_hal_gpio_get_wakeup_pins() rtc_cntl_ll_gpio_get_wakeup_pins()
#define rtc_hal_gpio_get_wakeup_status() rtc_cntl_ll_gpio_get_wakeup_status()
#define rtc_hal_gpio_clear_wakeup_pins() rtc_cntl_ll_gpio_clear_wakeup_pins()
#define rtc_hal_gpio_set_wakeup_pins() rtc_cntl_ll_gpio_set_wakeup_pins()
#define rtc_hal_gpio_clear_wakeup_status() rtc_cntl_ll_gpio_clear_wakeup_status()
#endif

8
components/hal/include/hal/rtc_io_hal.h
View File

@ -167,7 +167,7 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
#if SOC_RTCIO_HOLD_SUPPORTED
/**
* Enable force hold function for RTC IO pad.
* Enable force hold function on an RTC IO pad.
*
* Enabling HOLD function will cause the pad to lock current status, such as,
* input/output enable, input/output value, function, drive strength values.
@ -179,7 +179,7 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
#define rtcio_hal_hold_enable(rtcio_num) rtcio_ll_force_hold_enable(rtcio_num)
/**
* Disable hold function on an RTC IO pad
* Disable hold function on an RTC IO pad.
*
* @note If disable the pad hold, the status of pad maybe changed in sleep mode.
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
@ -187,7 +187,7 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
#define rtcio_hal_hold_disable(rtcio_num) rtcio_ll_force_hold_disable(rtcio_num)
/**
* Enable force hold function for RTC IO pads.
* Enable force hold function on all RTC IO pads.
*
* Enabling HOLD function will cause the pad to lock current status, such as,
* input/output enable, input/output value, function, drive strength values.
@ -199,7 +199,7 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
#define rtcio_hal_hold_all() rtcio_ll_force_hold_all()
/**
* Disable hold function on an RTC IO pads.
* Disable hold function on all RTC IO pads.
*
* @note If disable the pad hold, the status of pad maybe changed in sleep mode.
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.

70
components/soc/esp32s3/include/soc/rtc_gpio_channel.h
View File

@ -1,70 +0,0 @@
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
//RTC GPIO channels
#define RTCIO_GPIO36_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 36
#define RTCIO_GPIO37_CHANNEL 1 //RTCIO_CHANNEL_1
#define RTCIO_CHANNEL_1_GPIO_NUM 37
#define RTCIO_GPIO38_CHANNEL 2 //RTCIO_CHANNEL_2
#define RTCIO_CHANNEL_2_GPIO_NUM 38
#define RTCIO_GPIO39_CHANNEL 3 //RTCIO_CHANNEL_3
#define RTCIO_CHANNEL_3_GPIO_NUM 39
#define RTCIO_GPIO34_CHANNEL 4 //RTCIO_CHANNEL_4
#define RTCIO_CHANNEL_4_GPIO_NUM 34
#define RTCIO_GPIO35_CHANNEL 5 //RTCIO_CHANNEL_5
#define RTCIO_CHANNEL_5_GPIO_NUM 35
#define RTCIO_GPIO25_CHANNEL 6 //RTCIO_CHANNEL_6
#define RTCIO_CHANNEL_6_GPIO_NUM 25
#define RTCIO_GPIO26_CHANNEL 7 //RTCIO_CHANNEL_7
#define RTCIO_CHANNEL_7_GPIO_NUM 26
#define RTCIO_GPIO33_CHANNEL 8 //RTCIO_CHANNEL_8
#define RTCIO_CHANNEL_8_GPIO_NUM 33
#define RTCIO_GPIO32_CHANNEL 9 //RTCIO_CHANNEL_9
#define RTCIO_CHANNEL_9_GPIO_NUM 32
#define RTCIO_GPIO4_CHANNEL 10 //RTCIO_CHANNEL_10
#define RTCIO_CHANNEL_10_GPIO_NUM 4
#define RTCIO_GPIO0_CHANNEL 11 //RTCIO_CHANNEL_11
#define RTCIO_CHANNEL_11_GPIO_NUM 0
#define RTCIO_GPIO2_CHANNEL 12 //RTCIO_CHANNEL_12
#define RTCIO_CHANNEL_12_GPIO_NUM 2
#define RTCIO_GPIO15_CHANNEL 13 //RTCIO_CHANNEL_13
#define RTCIO_CHANNEL_13_GPIO_NUM 15
#define RTCIO_GPIO13_CHANNEL 14 //RTCIO_CHANNEL_14
#define RTCIO_CHANNEL_14_GPIO_NUM 13
#define RTCIO_GPIO12_CHANNEL 15 //RTCIO_CHANNEL_15
#define RTCIO_CHANNEL_15_GPIO_NUM 12
#define RTCIO_GPIO14_CHANNEL 16 //RTCIO_CHANNEL_16
#define RTCIO_CHANNEL_16_GPIO_NUM 14
#define RTCIO_GPIO27_CHANNEL 17 //RTCIO_CHANNEL_17
#define RTCIO_CHANNEL_17_GPIO_NUM 27

17
docs/en/api-reference/system/sleep_modes.rst
View File

@ -99,10 +99,13 @@ RTC peripherals or RTC memories don't need to be powered on during sleep in this
This wakeup source is implemented by the RTC controller. As such, RTC peripherals and RTC memories can be powered down in this mode. However, if RTC peripherals are powered down, internal pullup and pulldown resistors will be disabled. To use internal pullup or pulldown resistors, request the RTC peripherals power domain to be kept on during sleep, and configure pullup/pulldown resistors using ``rtc_gpio_`` functions before entering sleep::
esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
gpio_pullup_dis(gpio_num);
gpio_pulldown_en(gpio_num);
rtc_gpio_pullup_dis(gpio_num);
rtc_gpio_pulldown_en(gpio_num);
.. warning:: After waking up from sleep, IO pad(s) used for wakeup will be configured as RTC IO. Before using these pads as digital GPIOs, reconfigure them using :cpp:func:`rtc_gpio_deinit` function.
.. warning::
- To use the EXT1 wakeup, the IO pad(s) are configured as RTC IO. Thus if these pads want to be used as digital GPIOs after waking up from sleep, :cpp:func:`rtc_gpio_deinit` needs to be called first.
- If the RTC peripherals are configured to be powered down (which is by default), the wakeup IOs will be set to holding state before entering sleep. Therefore, after waking up from Light-sleep, please call `rtc_gpio_hold_dis` to disable the hold function to perform any pin re-configuration. For Deep-sleep wakeup, this is already being handled at the application startup stage.
:cpp:func:`esp_sleep_enable_ext1_wakeup` function can be used to enable this wakeup source.
@ -141,6 +144,14 @@ RTC peripherals or RTC memories don't need to be powered on during sleep in this
esp_sleep_pd_config(ESP_PD_DOMAIN_VDDSDIO, ESP_PD_OPTION_ON);
.. only:: not SOC_RTCIO_WAKE_SUPPORTED
GPIO Wakeup
^^^^^^^^^^^
Any IO can be used as the external input to wakeup the chip from Light-sleep. Each pin can be individually configured to trigger wakeup on high or low level using :cpp:func:`gpio_wakeup_enable` function. Then :cpp:func:`esp_sleep_enable_gpio_wakeup` function should be called to enable this wakeup source.
Additionally, IOs that are powered by the VDD3P3_RTC power domain can be used to wakeup the chip from Deep-sleep. The wakeup pin and wakeup trigger level can be configured by calling :cpp:func:`esp_deep_sleep_enable_gpio_wakeup`. The function will enable the Deep-sleep wakeup for the selected pin.
UART Wakeup (Light-sleep Only)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

4
tools/ci/check_copyright_ignore.txt
View File

@ -714,7 +714,6 @@ components/hal/esp32c3/include/hal/ds_ll.h
components/hal/esp32c3/include/hal/hmac_hal.h
components/hal/esp32c3/include/hal/hmac_ll.h
components/hal/esp32c3/include/hal/mpu_ll.h
components/hal/esp32c3/include/hal/rtc_cntl_ll.h
components/hal/esp32c3/include/hal/sha_ll.h
components/hal/esp32c3/include/hal/spi_flash_encrypted_ll.h
components/hal/esp32c3/include/hal/uhci_ll.h
@ -726,7 +725,6 @@ components/hal/esp32h2/include/hal/ds_ll.h
components/hal/esp32h2/include/hal/hmac_hal.h
components/hal/esp32h2/include/hal/hmac_ll.h
components/hal/esp32h2/include/hal/mpu_ll.h
components/hal/esp32h2/include/hal/rtc_cntl_ll.h
components/hal/esp32h2/include/hal/sha_ll.h
components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h
components/hal/esp32h2/include/hal/uhci_ll.h
@ -737,7 +735,6 @@ components/hal/esp32s2/include/hal/crypto_dma_ll.h
components/hal/esp32s2/include/hal/dac_hal.h
components/hal/esp32s2/include/hal/dedic_gpio_ll.h
components/hal/esp32s2/include/hal/mpu_ll.h
components/hal/esp32s2/include/hal/rtc_io_ll.h
components/hal/esp32s2/include/hal/sha_ll.h
components/hal/esp32s2/include/hal/spi_flash_encrypted_ll.h
components/hal/esp32s2/include/hal/trace_ll.h
@ -1161,7 +1158,6 @@ components/soc/esp32s3/include/soc/nrx_reg.h
components/soc/esp32s3/include/soc/peri_backup_reg.h
components/soc/esp32s3/include/soc/peri_backup_struct.h
components/soc/esp32s3/include/soc/reset_reasons.h
components/soc/esp32s3/include/soc/rtc_gpio_channel.h
components/soc/esp32s3/include/soc/rtc_i2c_reg.h
components/soc/esp32s3/include/soc/rtc_i2c_struct.h
components/soc/esp32s3/include/soc/rtc_io_channel.h