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fix(mbedtls/ecdsa): Fix dependant peripheral's enable and reset

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This commit is contained in:
harshal.patil 2024-03-28 19:33:23 +05:30
parent 84b6940ce4
commit 272633bde1
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GPG Key ID: 5B5EC97C35B9A2E5
6 changed files with 54 additions and 13 deletions
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23
components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c
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@ -17,6 +17,8 @@
#include "hal/ecdsa_hal.h"
#include "hal/ecdsa_ll.h"
#include "hal/ecdsa_types.h"
#include "hal/mpi_ll.h"
#include "soc/soc_caps.h"
#include "memory_checks.h"
#include "unity_fixture.h"
@ -26,21 +28,32 @@
static void ecdsa_enable_and_reset(void)
{
esp_crypto_ecdsa_lock_acquire();
ECDSA_RCC_ATOMIC() {
ecdsa_ll_enable_bus_clock(true);
ecdsa_ll_reset_register();
}
ECC_RCC_ATOMIC() {
ecc_ll_enable_bus_clock(true);
ecc_ll_reset_register();
}
ECDSA_RCC_ATOMIC() {
ecdsa_ll_enable_bus_clock(true);
ecdsa_ll_reset_register();
#ifdef SOC_ECDSA_USES_MPI
MPI_RCC_ATOMIC() {
mpi_ll_enable_bus_clock(true);
mpi_ll_reset_register();
}
#endif
}
static void ecdsa_disable(void)
{
#ifdef SOC_ECDSA_USES_MPI
MPI_RCC_ATOMIC() {
mpi_ll_enable_bus_clock(false);
}
#endif
ECC_RCC_ATOMIC() {
ecc_ll_enable_bus_clock(false);
}
@ -48,8 +61,6 @@ static void ecdsa_disable(void)
ECDSA_RCC_ATOMIC() {
ecdsa_ll_enable_bus_clock(false);
}
esp_crypto_ecdsa_lock_release();
}
static void ecc_be_to_le(const uint8_t* be_point, uint8_t *le_point, uint8_t len)

28
components/mbedtls/port/ecdsa/ecdsa_alt.c
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@ -7,6 +7,7 @@
#include "hal/ecc_ll.h"
#include "hal/ecdsa_ll.h"
#include "hal/ecdsa_hal.h"
#include "hal/mpi_ll.h"
#include "esp_crypto_lock.h"
#include "esp_efuse.h"
#include "esp_private/esp_crypto_lock_internal.h"
@ -15,6 +16,7 @@
#include "mbedtls/asn1write.h"
#include "mbedtls/platform_util.h"
#include "ecdsa/ecdsa_alt.h"
#include "soc/soc_caps.h"
#define ECDSA_KEY_MAGIC (short) 0xECD5A
#define ECDSA_SHA_LEN 32
@ -26,26 +28,42 @@ static void esp_ecdsa_acquire_hardware(void)
{
esp_crypto_ecdsa_lock_acquire();
ECDSA_RCC_ATOMIC() {
ecdsa_ll_enable_bus_clock(true);
ecdsa_ll_reset_register();
}
ECC_RCC_ATOMIC() {
ecc_ll_enable_bus_clock(true);
ecc_ll_reset_register();
}
ECDSA_RCC_ATOMIC() {
ecdsa_ll_enable_bus_clock(true);
ecdsa_ll_reset_register();
#ifdef SOC_ECDSA_USES_MPI
/* We need to reset the MPI peripheral because ECDSA peripheral
* of some targets use the MPI peripheral as well.
*/
MPI_RCC_ATOMIC() {
mpi_ll_enable_bus_clock(true);
mpi_ll_reset_register();
}
#endif /* SOC_ECDSA_USES_MPI */
}
static void esp_ecdsa_release_hardware(void)
{
ECDSA_RCC_ATOMIC() {
ecdsa_ll_enable_bus_clock(false);
}
ECC_RCC_ATOMIC() {
ecc_ll_enable_bus_clock(false);
}
ECDSA_RCC_ATOMIC() {
ecdsa_ll_enable_bus_clock(false);
#ifdef SOC_ECDSA_USES_MPI
MPI_RCC_ATOMIC() {
mpi_ll_enable_bus_clock(false);
}
#endif /* SOC_ECDSA_USES_MPI */
esp_crypto_ecdsa_lock_release();
}

4
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
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@ -1187,6 +1187,10 @@ config SOC_CRYPTO_DPA_PROTECTION_SUPPORTED
bool
default y
config SOC_ECDSA_USES_MPI
bool
default y
config SOC_UART_NUM
int
default 2

7
components/soc/esp32h2/include/soc/soc_caps.h
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@ -212,7 +212,7 @@
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
// The Clock Out singnal is route to the pin by GPIO matrix
// The Clock Out signal is route to the pin by GPIO matrix
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
#define SOC_CLOCKOUT_HAS_SOURCE_GATE (1)
@ -467,6 +467,9 @@
/*------------------------ Anti DPA (Security) CAPS --------------------------*/
#define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1
/*------------------------- ECDSA CAPS -------------------------*/
#define SOC_ECDSA_USES_MPI (1)
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-H2 has 2 UARTs
#define SOC_UART_NUM (2)
@ -496,7 +499,7 @@
/*-------------------------- Power Management CAPS ----------------------------*/
#define SOC_PM_SUPPORT_BT_WAKEUP (1)
#define SOC_PM_SUPPORT_EXT1_WAKEUP (1)
#define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!<Supports one bit per pin to configue the EXT1 trigger level */
#define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
#define SOC_PM_SUPPORT_CPU_PD (1)
#define SOC_PM_SUPPORT_MODEM_PD (1) /*!<modem includes BLE and 15.4 */
#define SOC_PM_SUPPORT_XTAL32K_PD (1)

4
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
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@ -1055,6 +1055,10 @@ config SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE
bool
default y
config SOC_ECDSA_USES_MPI
bool
default y
config SOC_SDM_GROUPS
int
default 1

1
components/soc/esp32p4/include/soc/soc_caps.h
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@ -435,6 +435,7 @@
/*--------------------------- ECDSA CAPS ---------------------------------------*/
#define SOC_ECDSA_SUPPORT_EXPORT_PUBKEY (1)
#define SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE (1)
#define SOC_ECDSA_USES_MPI (1)
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1U