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efuse: Adds major and minor versions and others

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This commit is contained in:
KonstantinKondrashov 2022-05-26 03:16:15 +08:00
parent 56efeb2c76
commit 26960f1734
86 changed files with 1534 additions and 466 deletions
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3
components/bootloader/subproject/main/ld/esp32/bootloader.ld
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@ -44,7 +44,7 @@ SECTIONS
*libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
*libesp_common.a:fpga_overrides.*(.literal.bootloader_fill_random .text.bootloader_fill_random)
*libbootloader_support.a:bootloader_efuse_esp32.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
@ -60,6 +60,7 @@ SECTIONS
*libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
*libspi_flash.a:*.*(.literal .text .literal.* .text.*)
*libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
*libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
*libefuse.a:*.*(.literal .text .literal.* .text.*)

3
components/bootloader/subproject/main/ld/esp32c3/bootloader.ld
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@ -57,7 +57,7 @@ SECTIONS
*libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
*libbootloader_support.a:bootloader_efuse_esp32c3.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
@ -73,6 +73,7 @@ SECTIONS
*libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
*libspi_flash.a:*.*(.literal .text .literal.* .text.*)
*libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
*libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)

3
components/bootloader/subproject/main/ld/esp32h2/bootloader.ld
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@ -57,7 +57,7 @@ SECTIONS
*libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
*libbootloader_support.a:bootloader_efuse_esp32h2.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
@ -71,6 +71,7 @@ SECTIONS
*libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
*libspi_flash.a:*.*(.literal .text .literal.* .text.*)
*libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
*libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)

3
components/bootloader/subproject/main/ld/esp32s2/bootloader.ld
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@ -31,7 +31,7 @@ SECTIONS
*libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
*libesp_common.a:fpga_overrides.*(.literal.bootloader_fill_random .text.bootloader_fill_random)
*libbootloader_support.a:bootloader_efuse_esp32s2.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
@ -47,6 +47,7 @@ SECTIONS
*libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
*libspi_flash.a:*.*(.literal .text .literal.* .text.*)
*libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
*libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)

3
components/bootloader/subproject/main/ld/esp32s3/bootloader.ld
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@ -66,7 +66,7 @@ SECTIONS
*libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
*libesp_common.a:fpga_overrides.*(.literal.bootloader_fill_random .text.bootloader_fill_random)
*libbootloader_support.a:bootloader_efuse_esp32s3.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
@ -82,6 +82,7 @@ SECTIONS
*libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
*libspi_flash.a:*.*(.literal .text .literal.* .text.*)
*libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
*libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)

2
components/bootloader_support/CMakeLists.txt
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@ -13,7 +13,7 @@ set(srcs
"src/flash_partitions.c"
"src/flash_qio_mode.c"
"src/bootloader_flash_config_${IDF_TARGET}.c"
"src/bootloader_efuse_${IDF_TARGET}.c"
"src/bootloader_efuse.c"
)
if(BOOTLOADER_BUILD)

7
components/bootloader_support/include/bootloader_common.h
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@ -187,13 +187,6 @@ int bootloader_common_select_otadata(const esp_ota_select_entry_t *two_otadata,
*/
esp_err_t bootloader_common_get_partition_description(const esp_partition_pos_t *partition, esp_app_desc_t *app_desc);
/**
* @brief Get chip revision
*
* @return Chip revision number
*/
uint8_t bootloader_common_get_chip_revision(void);
/**
* @brief Get chip package
*

4
components/bootloader_support/src/bootloader_clock_init.c
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@ -11,6 +11,7 @@
#if CONFIG_IDF_TARGET_ESP32
#include "soc/dport_reg.h"
#endif
#include "hal/efuse_hal.h"
#include "esp_rom_sys.h"
#include "esp_rom_uart.h"
@ -32,8 +33,7 @@ __attribute__((weak)) void bootloader_clock_configure(void)
* document). For rev. 0, switch to 240 instead if it has been enabled
* previously.
*/
uint32_t chip_ver_reg = REG_READ(EFUSE_BLK0_RDATA3_REG);
if ((chip_ver_reg & EFUSE_RD_CHIP_VER_REV1_M) == 0 &&
if (efuse_hal_get_major_chip_version() == 0 &&
DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL) == DPORT_CPUPERIOD_SEL_240) {
cpu_freq_mhz = 240;
}

9
components/bootloader_support/src/bootloader_common_loader.c
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@ -22,6 +22,7 @@
#include "soc/gpio_periph.h"
#include "soc/rtc.h"
#include "soc/efuse_reg.h"
#include "hal/efuse_hal.h"
#include "soc/soc_memory_types.h"
#include "hal/gpio_ll.h"
#include "esp_image_format.h"
@ -69,7 +70,13 @@ esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hd
}
#ifndef CONFIG_IDF_ENV_FPGA
uint8_t revision = bootloader_common_get_chip_revision();
#if defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32H2)
uint8_t revision = efuse_hal_get_major_chip_version();
// min_chip_rev keeps the MAJOR wafer version for these chips
#else
uint8_t revision = efuse_hal_get_minor_chip_version();
// min_chip_rev keeps the MINOR wafer version for these chips
#endif
if (revision < img_hdr->min_chip_rev) {
/* To fix this error, please update mininum supported chip revision from configuration,
* located in TARGET (e.g. ESP32) specific options under "Component config" menu */

37
components/bootloader_support/src/bootloader_efuse.c Normal file
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@ -0,0 +1,37 @@
/*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include "sdkconfig.h"
#include "bootloader_common.h"
#include "hal/efuse_ll.h"
#include "hal/efuse_hal.h"
#include "esp_attr.h"
IRAM_ATTR uint32_t bootloader_common_get_chip_ver_pkg(void)
{
return efuse_ll_get_chip_ver_pkg();
}
int bootloader_clock_get_rated_freq_mhz(void)
{
#ifdef CONFIG_IDF_TARGET_ESP32
return efuse_hal_get_rated_freq_mhz();
#elif CONFIG_IDF_TARGET_ESP32C3
return 160;
#elif CONFIG_IDF_TARGET_ESP32H2
return 96;
#elif CONFIG_IDF_TARGET_ESP32S2
return 240;
#elif CONFIG_IDF_TARGET_ESP32S3
return 240;
#endif
}

61
components/bootloader_support/src/bootloader_efuse_esp32.c
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@ -1,61 +0,0 @@
/*
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "bootloader_common.h"
#include "bootloader_clock.h"
#include "soc/efuse_reg.h"
#include "soc/syscon_reg.h"
#include "esp_attr.h"
IRAM_ATTR uint8_t bootloader_common_get_chip_revision(void)
{
uint8_t eco_bit0, eco_bit1, eco_bit2;
eco_bit0 = (REG_READ(EFUSE_BLK0_RDATA3_REG) & 0xF000) >> 15;
eco_bit1 = (REG_READ(EFUSE_BLK0_RDATA5_REG) & 0x100000) >> 20;
eco_bit2 = (REG_READ(SYSCON_DATE_REG) & 0x80000000) >> 31;
uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0;
uint8_t chip_ver = 0;
switch (combine_value) {
case 0:
chip_ver = 0;
break;
case 1:
chip_ver = 1;
break;
case 3:
chip_ver = 2;
break;
#if CONFIG_IDF_ENV_FPGA
case 4: /* Empty efuses, but SYSCON_DATE_REG bit is set */
chip_ver = 3;
break;
#endif
case 7:
chip_ver = 3;
break;
default:
chip_ver = 0;
break;
}
return chip_ver;
}
IRAM_ATTR uint32_t bootloader_common_get_chip_ver_pkg(void)
{
uint32_t pkg_version = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
uint32_t pkg_version_4bit = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG_4BIT);
return (pkg_version_4bit << 3) | pkg_version;
}
int bootloader_clock_get_rated_freq_mhz()
{
//Check if ESP32 is rated for a CPU frequency of 160MHz only
if (REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED) &&
REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW)) {
return 160;
}
return 240;
}

21
components/bootloader_support/src/bootloader_efuse_esp32c3.c
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@ -1,21 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include "soc/efuse_reg.h"
#include "esp_attr.h"
IRAM_ATTR uint8_t bootloader_common_get_chip_revision(void)
{
// should return the same value as esp_efuse_get_chip_ver()
return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_WAFER_VERSION);
}
IRAM_ATTR uint32_t bootloader_common_get_chip_ver_pkg(void)
{
// should return the same value as esp_efuse_get_pkg_ver()
return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION);
}

21
components/bootloader_support/src/bootloader_efuse_esp32h2.c
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@ -1,21 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include "soc/efuse_reg.h"
#include "esp_attr.h"
IRAM_ATTR uint8_t bootloader_common_get_chip_revision(void)
{
// should return the same value as esp_efuse_get_chip_ver()
return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_WAFER_VERSION);
}
IRAM_ATTR uint32_t bootloader_common_get_chip_ver_pkg(void)
{
// should return the same value as esp_efuse_get_pkg_ver()
return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION);
}

23
components/bootloader_support/src/bootloader_efuse_esp32s2.c
View File

@ -1,23 +0,0 @@
/*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "bootloader_clock.h"
#include "bootloader_common.h"
#include "soc/efuse_reg.h"
#include "esp_attr.h"
IRAM_ATTR uint8_t bootloader_common_get_chip_revision(void)
{
// should return the same value as esp_efuse_get_chip_ver()
return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_WAFER_VERSION);
}
IRAM_ATTR uint32_t bootloader_common_get_chip_ver_pkg(void)
{
// should return the same value as esp_efuse_get_pkg_ver()
return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_4_REG, EFUSE_PKG_VERSION);
}

21
components/bootloader_support/src/bootloader_efuse_esp32s3.c
View File

@ -1,21 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include "esp_attr.h"
IRAM_ATTR uint8_t bootloader_common_get_chip_revision(void)
{
// should return the same value as esp_efuse_get_chip_ver()
/* No other revisions for ESP32-S3 */
return 0;
}
IRAM_ATTR uint32_t bootloader_common_get_chip_ver_pkg(void)
{
// should return the same value as esp_efuse_get_pkg_ver()
return 0;
}

3
components/bootloader_support/src/bootloader_flash_config_esp32.c
View File

@ -17,6 +17,7 @@
#include "soc/spi_reg.h"
#include "soc/soc_caps.h"
#include "soc/soc_pins.h"
#include "hal/efuse_hal.h"
#include "hal/gpio_hal.h"
#include "flash_qio_mode.h"
#include "bootloader_common.h"
@ -176,7 +177,7 @@ int bootloader_flash_get_wp_pin(void)
return ESP32_D2WD_WP_GPIO;
case EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4:
/* Same package IDs are used for ESP32-PICO-V3 and ESP32-PICO-D4, silicon version differentiates */
chip_ver = bootloader_common_get_chip_revision();
chip_ver = efuse_hal_get_major_chip_version();
return (chip_ver < 3) ? ESP32_D2WD_WP_GPIO : ESP32_PICO_V3_GPIO;
case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302:
return ESP32_PICO_V3_GPIO;

8
components/bootloader_support/src/bootloader_init.c
View File

@ -18,6 +18,7 @@
#include "soc/cpu.h"
#include "soc/rtc.h"
#include "hal/wdt_hal.h"
#include "hal/efuse_hal.h"
static const char *TAG = "boot";
@ -40,9 +41,10 @@ esp_err_t bootloader_read_bootloader_header(void)
esp_err_t bootloader_check_bootloader_validity(void)
{
/* read chip revision from efuse */
uint8_t revision = bootloader_common_get_chip_revision();
ESP_LOGI(TAG, "chip revision: %d", revision);
unsigned revision = efuse_hal_chip_revision();
unsigned major = revision / 100;
unsigned minor = revision % 100;
ESP_LOGI(TAG, "chip revision: v%d.%d", major, minor);
/* compare with the one set in bootloader image header */
if (bootloader_common_check_chip_validity(&bootloader_image_hdr, ESP_IMAGE_BOOTLOADER) != ESP_OK) {
return ESP_FAIL;

5
components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
View File

@ -38,6 +38,7 @@
#include "bootloader_flash_priv.h"
#include "bootloader_soc.h"
#include "esp_efuse.h"
#include "hal/efuse_hal.h"
static const char *TAG = "boot.esp32c3";
@ -258,7 +259,7 @@ static inline void bootloader_hardware_init(void)
{
// This check is always included in the bootloader so it can
// print the minimum revision error message later in the boot
if (bootloader_common_get_chip_revision() < 3) {
if (efuse_hal_get_minor_chip_version() < 3) {
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 1);
REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 12);
}
@ -271,7 +272,7 @@ static inline void bootloader_ana_reset_config(void)
For ECO2: fix brownout reset bug, support swt & brownout reset;
For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
*/
uint8_t chip_version = bootloader_common_get_chip_revision();
uint8_t chip_version = efuse_hal_get_minor_chip_version();
switch (chip_version) {
case 0:
case 1:

32
components/efuse/esp32/esp_efuse_fields.c
View File

@ -13,6 +13,7 @@
#include "esp_err.h"
#include "esp_log.h"
#include "soc/efuse_periph.h"
#include "hal/efuse_hal.h"
#include "bootloader_random.h"
#include "sys/param.h"
#include "soc/syscon_reg.h"
@ -21,35 +22,6 @@ const static char *TAG = "efuse";
// Contains functions that provide access to efuse fields which are often used in IDF.
// Returns chip version from efuse
uint8_t esp_efuse_get_chip_ver(void)
{
uint8_t eco_bit0, eco_bit1, eco_bit2;
esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV1, &eco_bit0, 1);
esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV2, &eco_bit1, 1);
eco_bit2 = (REG_READ(SYSCON_DATE_REG) & 0x80000000) >> 31;
uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0;
uint8_t chip_ver = 0;
switch (combine_value) {
case 0:
chip_ver = 0;
break;
case 1:
chip_ver = 1;
break;
case 3:
chip_ver = 2;
break;
case 7:
chip_ver = 3;
break;
default:
chip_ver = 0;
break;
}
return chip_ver;
}
// Returns chip package from efuse
uint32_t esp_efuse_get_pkg_ver(void)
{
@ -71,7 +43,7 @@ esp_err_t esp_efuse_disable_rom_download_mode(void)
{
#ifndef CONFIG_ESP32_REV_MIN_3
/* Check if we support this revision at all */
if(esp_efuse_get_chip_ver() < 3) {
if (efuse_hal_get_major_chip_version() < 3) {
return ESP_ERR_NOT_SUPPORTED;
}
#endif

13
components/efuse/esp32/esp_efuse_table.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -9,7 +9,7 @@
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table f552d73ac112985991efa6734a60c8d9
// md5_digest_table 6256f9b7c6783e0b651bf52b5b162aa8
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -160,6 +160,10 @@ static const esp_efuse_desc_t CHIP_VER_REV2[] = {
{EFUSE_BLK0, 180, 1}, // EFUSE_RD_CHIP_VER_REV2,
};
static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
{EFUSE_BLK0, 184, 2}, // WAFER_VERSION_MINOR,
};
static const esp_efuse_desc_t XPD_SDIO_REG[] = {
{EFUSE_BLK0, 142, 1}, // EFUSE_RD_XPD_SDIO_REG,
};
@ -366,6 +370,11 @@ const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV2[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = {
&WAFER_VERSION_MINOR[0], // WAFER_VERSION_MINOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_REG[] = {
&XPD_SDIO_REG[0], // EFUSE_RD_XPD_SDIO_REG
NULL

1
components/efuse/esp32/esp_efuse_table.csv
View File

@ -71,6 +71,7 @@ CHIP_CPU_FREQ_LOW, EFUSE_BLK0, 108, 1, EFUSE_RD_CHIP_CPU_FREQ_LOW
CHIP_CPU_FREQ_RATED, EFUSE_BLK0, 109, 1, EFUSE_RD_CHIP_CPU_FREQ_RATED
CHIP_VER_REV1, EFUSE_BLK0, 111, 1, EFUSE_RD_CHIP_VER_REV1
CHIP_VER_REV2, EFUSE_BLK0, 180, 1, EFUSE_RD_CHIP_VER_REV2
WAFER_VERSION_MINOR, EFUSE_BLK0, 184, 2, WAFER_VERSION_MINOR
XPD_SDIO_REG, EFUSE_BLK0, 142, 1, EFUSE_RD_XPD_SDIO_REG
SDIO_TIEH, EFUSE_BLK0, 143, 1, EFUSE_RD_SDIO_TIEH
SDIO_FORCE, EFUSE_BLK0, 144, 1, EFUSE_RD_SDIO_FORCE

Can't render this file because it contains an unexpected character in line 7 and column 87.

5
components/efuse/esp32/include/esp_efuse_table.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -9,7 +9,7 @@ extern "C" {
#endif
// md5_digest_table f552d73ac112985991efa6734a60c8d9
// md5_digest_table 6256f9b7c6783e0b651bf52b5b162aa8
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -48,6 +48,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_LOW[];
extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_RATED[];
extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV1[];
extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_REG[];
extern const esp_efuse_desc_t* ESP_EFUSE_SDIO_TIEH[];
extern const esp_efuse_desc_t* ESP_EFUSE_SDIO_FORCE[];

8
components/efuse/esp32c3/esp_efuse_fields.c
View File

@ -21,14 +21,6 @@ static __attribute__((unused)) const char *TAG = "efuse";
// Contains functions that provide access to efuse fields which are often used in IDF.
// Returns chip version from efuse
uint8_t esp_efuse_get_chip_ver(void)
{
uint32_t chip_ver = 0;
esp_efuse_read_field_blob(ESP_EFUSE_WAFER_VERSION, &chip_ver, ESP_EFUSE_WAFER_VERSION[0]->bit_count);
return chip_ver;
}
// Returns chip package from efuse
uint32_t esp_efuse_get_pkg_ver(void)
{

2
components/efuse/esp32c3/esp_efuse_rtc_calib.c
View File

@ -11,7 +11,7 @@
int esp_efuse_rtc_calib_get_ver(void)
{
uint32_t result = 0;
esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &result, 3);
esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &result, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count); // IDF-5366
return result;
}

55
components/efuse/esp32c3/esp_efuse_table.c
View File

@ -9,7 +9,7 @@
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table 6614a99de35023cf9ba3849a2b80e9e7
// md5_digest_table d006c80095638b5dbdc8649bf7e04dce
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -315,6 +315,14 @@ static const esp_efuse_desc_t ERR_RST_ENABLE[] = {
{EFUSE_BLK0, 159, 1}, // Use BLOCK0 to check error record registers,
};
static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK0, 160, 1}, // Disables check of wafer version major,
};
static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = {
{EFUSE_BLK0, 161, 1}, // Disables check of blk version major,
};
static const esp_efuse_desc_t MAC_FACTORY[] = {
{EFUSE_BLK1, 40, 8}, // Factory MAC addr [0],
{EFUSE_BLK1, 32, 8}, // Factory MAC addr [1],
@ -368,24 +376,29 @@ static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = {
{EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7,
};
static const esp_efuse_desc_t WAFER_VERSION[] = {
{EFUSE_BLK1, 114, 3}, // WAFER version,
static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
{EFUSE_BLK1, 114, 3}, // WAFER_VERSION_MINOR least significant bits,
{EFUSE_BLK1, 183, 1}, // WAFER_VERSION_MINOR most significant bit,
};
static const esp_efuse_desc_t PKG_VERSION[] = {
{EFUSE_BLK1, 117, 3}, // Package version 0:ESP32C3,
};
static const esp_efuse_desc_t BLOCK1_VERSION[] = {
{EFUSE_BLK1, 120, 3}, // BLOCK1 efuse version,
static const esp_efuse_desc_t BLK_VERSION_MINOR[] = {
{EFUSE_BLK1, 120, 3}, // BLK_VERSION_MINOR,
};
static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK1, 184, 2}, // WAFER_VERSION_MAJOR,
};
static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
{EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID,
};
static const esp_efuse_desc_t BLOCK2_VERSION[] = {
{EFUSE_BLK2, 128, 3}, // Version of BLOCK2,
static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = {
{EFUSE_BLK2, 128, 2}, // BLK_VERSION_MAJOR of BLOCK2,
};
static const esp_efuse_desc_t TEMP_CALIB[] = {
@ -867,6 +880,16 @@ const esp_efuse_desc_t* ESP_EFUSE_ERR_RST_ENABLE[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = {
&DISABLE_WAFER_VERSION_MAJOR[0], // Disables check of wafer version major
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = {
&DISABLE_BLK_VERSION_MAJOR[0], // Disables check of blk version major
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
&MAC_FACTORY[0], // Factory MAC addr [0]
&MAC_FACTORY[1], // Factory MAC addr [1]
@ -932,8 +955,9 @@ const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = {
&WAFER_VERSION[0], // WAFER version
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = {
&WAFER_VERSION_MINOR[0], // WAFER_VERSION_MINOR least significant bits
&WAFER_VERSION_MINOR[1], // WAFER_VERSION_MINOR most significant bit
NULL
};
@ -942,8 +966,13 @@ const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = {
&BLOCK1_VERSION[0], // BLOCK1 efuse version
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = {
&BLK_VERSION_MINOR[0], // BLK_VERSION_MINOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = {
&WAFER_VERSION_MAJOR[0], // WAFER_VERSION_MAJOR
NULL
};
@ -952,8 +981,8 @@ const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = {
&BLOCK2_VERSION[0], // Version of BLOCK2
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = {
&BLK_VERSION_MAJOR[0], // BLK_VERSION_MAJOR of BLOCK2
NULL
};

22
components/efuse/esp32c3/esp_efuse_table.csv
View File

@ -98,10 +98,13 @@
ERR_RST_ENABLE, EFUSE_BLK0, 159, 1, Use BLOCK0 to check error record registers, 0 - without check.
# EFUSE_RD_REPEAT_DATA4_REG #
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major
# MAC_SPI_SYS BLOCK#
#######################
# RD_MAC_SPI_SYS_0 - RD_MAC_SPI_SYS_2
MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0]
, EFUSE_BLK1, 32, 8, Factory MAC addr [1]
, EFUSE_BLK1, 24, 8, Factory MAC addr [2]
@ -117,20 +120,33 @@
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5
# RD_MAC_SPI_SYS_3
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version
WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, WAFER_VERSION_MINOR least significant bits
, EFUSE_BLK1, 183, 1, WAFER_VERSION_MINOR most significant bit
# WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5
PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32C3
BLOCK1_VERSION, EFUSE_BLK1, 120, 3, BLOCK1 efuse version
BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, BLK_VERSION_MINOR
# RD_MAC_SPI_SYS_5
# WAFER_VERSION_MINOR most significant bit
WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, WAFER_VERSION_MAJOR
# SYS_DATA_PART1 BLOCK# - System configuration
#######################
# RD_SYS_PART1_DATA0 - rd_sys_part1_data3
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
BLOCK2_VERSION, EFUSE_BLK2, 128, 3, Version of BLOCK2
# RD_SYS_PART1_DATA4
BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, BLK_VERSION_MAJOR of BLOCK2
TEMP_CALIB, EFUSE_BLK2, 131, 9, Temperature calibration data
OCODE, EFUSE_BLK2, 140, 8, ADC OCode
ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, ADC1 init code at atten0
ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 158, 10, ADC1 init code at atten1
# RD_SYS_PART1_DATA5
ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 168, 10, ADC1 init code at atten2
ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 178, 10, ADC1 init code at atten3
ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 188, 10, ADC1 calibration voltage at atten0

Can't render this file because it contains an unexpected character in line 7 and column 87.

11
components/efuse/esp32c3/include/esp_efuse_table.h
View File

@ -9,7 +9,7 @@ extern "C" {
#endif
// md5_digest_table 6614a99de35023cf9ba3849a2b80e9e7
// md5_digest_table d006c80095638b5dbdc8649bf7e04dce
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -91,6 +91,8 @@ extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_ERR_RST_ENABLE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];
@ -103,11 +105,12 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[];

8
components/efuse/esp32h2/esp_efuse_fields.c
View File

@ -21,14 +21,6 @@ static __attribute__((unused)) const char *TAG = "efuse";
// Contains functions that provide access to efuse fields which are often used in IDF.
// Returns chip version from efuse
uint8_t esp_efuse_get_chip_ver(void)
{
uint32_t chip_ver = 0;
esp_efuse_read_field_blob(ESP_EFUSE_WAFER_VERSION, &chip_ver, ESP_EFUSE_WAFER_VERSION[0]->bit_count);
return chip_ver;
}
// Returns chip package from efuse
uint32_t esp_efuse_get_pkg_ver(void)
{

9
components/efuse/esp32s2/esp_efuse_fields.c
View File

@ -20,15 +20,6 @@ static __attribute__((unused)) const char *TAG = "efuse";
// Contains functions that provide access to efuse fields which are often used in IDF.
// Returns chip version from efuse
uint8_t esp_efuse_get_chip_ver(void)
{
// should return the same value as bootloader_common_get_chip_revision()
uint32_t chip_ver = 0;
esp_efuse_read_field_blob(ESP_EFUSE_WAFER_VERSION, &chip_ver, ESP_EFUSE_WAFER_VERSION[0]->bit_count);
return chip_ver;
}
// Returns chip package from efuse
uint32_t esp_efuse_get_pkg_ver(void)
{

2
components/efuse/esp32s2/esp_efuse_rtc_table.c
View File

@ -90,7 +90,7 @@ static const efuse_map_info_t adc_efuse_raw_map[] = {
int esp_efuse_rtc_table_read_calib_version(void)
{
uint32_t result = 0;
esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &result, 32);
esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MINOR, &result, 3);
return result;
}

57
components/efuse/esp32s2/esp_efuse_table.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -9,7 +9,7 @@
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table 614c862c2cfa8ccda3a79183ce767255
// md5_digest_table 3ac9188bf7eb0a27f3f636085a260743
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -331,6 +331,14 @@ static const esp_efuse_desc_t SECURE_VERSION[] = {
{EFUSE_BLK0, 139, 16}, // Secure version for anti-rollback,
};
static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK0, 160, 1}, // Disables check of wafer version major,
};
static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = {
{EFUSE_BLK0, 161, 1}, // Disables check of blk version major,
};
static const esp_efuse_desc_t MAC_FACTORY[] = {
{EFUSE_BLK1, 40, 8}, // Factory MAC addr [0],
{EFUSE_BLK1, 32, 8}, // Factory MAC addr [1],
@ -384,16 +392,21 @@ static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = {
{EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7,
};
static const esp_efuse_desc_t WAFER_VERSION[] = {
{EFUSE_BLK1, 114, 3}, // WAFER version 0:A,
static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK1, 114, 2}, // WAFER_VERSION_MAJOR,
};
static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
{EFUSE_BLK1, 132, 3}, // WAFER_VERSION_MINOR least significant bits,
{EFUSE_BLK1, 116, 1}, // WAFER_VERSION_MINOR most significant bit,
};
static const esp_efuse_desc_t FLASH_VERSION[] = {
{EFUSE_BLK1, 117, 4}, // Flash_version,
};
static const esp_efuse_desc_t BLOCK1_VERSION[] = {
{EFUSE_BLK1, 121, 3}, // BLOCK1 efuse version,
static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = {
{EFUSE_BLK1, 121, 2}, // BLK_VERSION_MAJOR,
};
static const esp_efuse_desc_t PSRAM_VERSION[] = {
@ -408,8 +421,8 @@ static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
{EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID,
};
static const esp_efuse_desc_t BLOCK2_VERSION[] = {
{EFUSE_BLK2, 132, 3}, // Version of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2,
static const esp_efuse_desc_t BLK_VERSION_MINOR[] = {
{EFUSE_BLK2, 132, 3}, // BLK_VERSION_MINOR of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2,
};
static const esp_efuse_desc_t USER_DATA[] = {
@ -847,6 +860,16 @@ const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = {
&DISABLE_WAFER_VERSION_MAJOR[0], // Disables check of wafer version major
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = {
&DISABLE_BLK_VERSION_MAJOR[0], // Disables check of blk version major
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
&MAC_FACTORY[0], // Factory MAC addr [0]
&MAC_FACTORY[1], // Factory MAC addr [1]
@ -912,8 +935,14 @@ const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = {
&WAFER_VERSION[0], // WAFER version 0:A
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = {
&WAFER_VERSION_MAJOR[0], // WAFER_VERSION_MAJOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = {
&WAFER_VERSION_MINOR[0], // WAFER_VERSION_MINOR least significant bits
&WAFER_VERSION_MINOR[1], // WAFER_VERSION_MINOR most significant bit
NULL
};
@ -922,8 +951,8 @@ const esp_efuse_desc_t* ESP_EFUSE_FLASH_VERSION[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = {
&BLOCK1_VERSION[0], // BLOCK1 efuse version
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = {
&BLK_VERSION_MAJOR[0], // BLK_VERSION_MAJOR
NULL
};
@ -942,8 +971,8 @@ const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = {
&BLOCK2_VERSION[0], // Version of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = {
&BLK_VERSION_MINOR[0], // BLK_VERSION_MINOR of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2
NULL
};

21
components/efuse/esp32s2/esp_efuse_table.csv
View File

@ -102,10 +102,13 @@
SECURE_VERSION, EFUSE_BLK0, 139, 16, Secure version for anti-rollback
# EFUSE_RD_REPEAT_DATA4_REG #
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major
# MAC_SPI_8M_SYS BLOCK#
#######################
# RD_MAC_SPI_8M_0 - RD_MAC_SPI_8M_2
MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0]
, EFUSE_BLK1, 32, 8, Factory MAC addr [1]
, EFUSE_BLK1, 24, 8, Factory MAC addr [2]
@ -120,20 +123,30 @@
SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2)
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4
# RD_MAC_SPI_8M_3
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version 0:A
WAFER_VERSION_MAJOR, EFUSE_BLK1, 114, 2, WAFER_VERSION_MAJOR
WAFER_VERSION_MINOR, EFUSE_BLK1, 132, 3, WAFER_VERSION_MINOR least significant bits
, EFUSE_BLK1, 116, 1, WAFER_VERSION_MINOR most significant bit
# WAFER_VERSION_MINOR least significant bits is from RD_MAC_SPI_8M_4
FLASH_VERSION, EFUSE_BLK1, 117, 4, Flash_version
BLOCK1_VERSION, EFUSE_BLK1, 121, 3, BLOCK1 efuse version
BLK_VERSION_MAJOR, EFUSE_BLK1, 121, 2, BLK_VERSION_MAJOR
PSRAM_VERSION, EFUSE_BLK1, 124, 4, PSRAM version
# RD_MAC_SPI_8M_4
PKG_VERSION, EFUSE_BLK1, 128, 4, Package version
# SYS_DATA_PART0, EFUSE_BLK1, 132, 60, System configuration (Reserve)
# WAFER_VERSION_MINOR least significant bits
# SYS_DATA_PART1 BLOCK# - System configuration
#######################
# RD_SYS_DATA0 - RD_SYS_DATA3
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
BLOCK2_VERSION, EFUSE_BLK2, 132, 3, Version of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2
# RD_SYS_DATA4
BLK_VERSION_MINOR, EFUSE_BLK2, 132, 3, BLK_VERSION_MINOR of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2
################
USER_DATA, EFUSE_BLK3, 0, 256, User data

Can't render this file because it contains an unexpected character in line 7 and column 87.

13
components/efuse/esp32s2/include/esp_efuse_table.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -9,7 +9,7 @@ extern "C" {
#endif
// md5_digest_table 614c862c2cfa8ccda3a79183ce767255
// md5_digest_table 3ac9188bf7eb0a27f3f636085a260743
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -95,6 +95,8 @@ extern const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[];
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];
@ -107,13 +109,14 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];

9
components/efuse/esp32s3/esp_efuse_fields.c
View File

@ -20,15 +20,6 @@ static __attribute__((unused)) const char *TAG = "efuse";
// Contains functions that provide access to efuse fields which are often used in IDF.
// Returns chip version from efuse
uint8_t esp_efuse_get_chip_ver(void)
{
// should return the same value as bootloader_common_get_chip_revision()
uint32_t chip_ver = 0;
// TODO: ESP32S2 does not have this field
return chip_ver;
}
// Returns chip package from efuse
uint32_t esp_efuse_get_pkg_ver(void)
{

2
components/efuse/esp32s3/esp_efuse_rtc_calib.c
View File

@ -20,7 +20,7 @@
int esp_efuse_rtc_calib_get_ver(void)
{
uint32_t blk_ver_major = 0;
ESP_ERROR_CHECK(esp_efuse_read_field_blob(ESP_EFUSE_BLK_VER_MAJOR, &blk_ver_major, ESP_EFUSE_BLK_VER_MAJOR[0]->bit_count));
ESP_ERROR_CHECK(esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &blk_ver_major, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count)); // IDF-5366
uint32_t cali_version_v1 = (blk_ver_major == 1) ? 1 : 0;
if (!cali_version_v1) {

53
components/efuse/esp32s3/esp_efuse_table.c
View File

@ -9,7 +9,7 @@
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table 5d853dcd3eb114e78147566245552b2d
// md5_digest_table 87c5ae68b74dbafb114e14f6febff9e2
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -355,6 +355,14 @@ static const esp_efuse_desc_t DIS_USB_OTG_DOWNLOAD_MODE[] = {
{EFUSE_BLK0, 159, 1}, // Set this bit to disable download through USB-OTG,
};
static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK0, 160, 1}, // Disables check of wafer version major,
};
static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = {
{EFUSE_BLK0, 161, 1}, // Disables check of blk version major,
};
static const esp_efuse_desc_t MAC_FACTORY[] = {
{EFUSE_BLK1, 40, 8}, // Factory MAC addr [0],
{EFUSE_BLK1, 32, 8}, // Factory MAC addr [1],
@ -408,18 +416,23 @@ static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = {
{EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7,
};
static const esp_efuse_desc_t WAFER_VERSION[] = {
{EFUSE_BLK1, 114, 3}, // WAFER version 0:A,
static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
{EFUSE_BLK1, 114, 3}, // WAFER_VERSION_MINOR least significant bits,
{EFUSE_BLK1, 183, 1}, // WAFER_VERSION_MINOR most significant bit,
};
static const esp_efuse_desc_t PKG_VERSION[] = {
{EFUSE_BLK1, 117, 3}, // Package version,
};
static const esp_efuse_desc_t BLK_VER_MINOR[] = {
static const esp_efuse_desc_t BLK_VERSION_MINOR[] = {
{EFUSE_BLK1, 120, 3}, // BLK_VERSION_MINOR,
};
static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK1, 184, 2}, // WAFER_VERSION_MAJOR,
};
static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN3[] = {
{EFUSE_BLK1, 186, 6}, // ADC2 calibration voltage at atten3,
};
@ -428,8 +441,8 @@ static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
{EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID,
};
static const esp_efuse_desc_t BLK_VER_MAJOR[] = {
{EFUSE_BLK2, 128, 2}, // BLK_VERSION_MAJOR,
static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = {
{EFUSE_BLK2, 128, 2}, // BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware,
};
static const esp_efuse_desc_t TEMP_CALIB[] = {
@ -985,6 +998,16 @@ const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = {
&DISABLE_WAFER_VERSION_MAJOR[0], // Disables check of wafer version major
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = {
&DISABLE_BLK_VERSION_MAJOR[0], // Disables check of blk version major
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
&MAC_FACTORY[0], // Factory MAC addr [0]
&MAC_FACTORY[1], // Factory MAC addr [1]
@ -1050,8 +1073,9 @@ const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = {
&WAFER_VERSION[0], // WAFER version 0:A
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = {
&WAFER_VERSION_MINOR[0], // WAFER_VERSION_MINOR least significant bits
&WAFER_VERSION_MINOR[1], // WAFER_VERSION_MINOR most significant bit
NULL
};
@ -1060,8 +1084,13 @@ const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_BLK_VER_MINOR[] = {
&BLK_VER_MINOR[0], // BLK_VERSION_MINOR
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = {
&BLK_VERSION_MINOR[0], // BLK_VERSION_MINOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = {
&WAFER_VERSION_MAJOR[0], // WAFER_VERSION_MAJOR
NULL
};
@ -1075,8 +1104,8 @@ const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_BLK_VER_MAJOR[] = {
&BLK_VER_MAJOR[0], // BLK_VERSION_MAJOR
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = {
&BLK_VERSION_MAJOR[0], // BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware
NULL
};

22
components/efuse/esp32s3/esp_efuse_table.csv
View File

@ -107,6 +107,8 @@
DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 159, 1, Set this bit to disable download through USB-OTG
# EFUSE_RD_REPEAT_DATA4_REG #
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major
# MAC_SPI_8M_SYS BLOCK#
@ -125,22 +127,36 @@
SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2)
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4
# RD_MAC_SPI_SYS_3
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version 0:A
WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, WAFER_VERSION_MINOR least significant bits
, EFUSE_BLK1, 183, 1, WAFER_VERSION_MINOR most significant bit
# WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5
PKG_VERSION, EFUSE_BLK1, 117, 3, Package version
BLK_VER_MINOR, EFUSE_BLK1, 120, 3, BLK_VERSION_MINOR, won't influence users
BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, BLK_VERSION_MINOR
# RD_MAC_SPI_SYS_5
# WAFER_VERSION_MINOR most significant bit
WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, WAFER_VERSION_MAJOR
ADC2_CAL_VOL_ATTEN3, EFUSE_BLK1, 186, 6, ADC2 calibration voltage at atten3
# SYS_DATA_PART1 BLOCK# - System configuration
#######################
# RD_SYS_PART1_DATA0
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
BLK_VER_MAJOR, EFUSE_BLK2, 128, 2, BLK_VERSION_MAJOR, change of this bit means users need to update firmware
# RD_SYS_PART1_DATA4
BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware
TEMP_CALIB, EFUSE_BLK2, 132, 9, Temperature calibration data
OCODE, EFUSE_BLK2, 141, 8, ADC OCode
ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 149, 8, ADC1 init code at atten0
ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 157, 6, ADC1 init code at atten1
# RD_SYS_PART1_DATA5
ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 163, 6, ADC1 init code at atten2
ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 169, 6, ADC1 init code at atten3
ADC2_INIT_CODE_ATTEN0, EFUSE_BLK2, 175, 8, ADC2 init code at atten0

Can't render this file because it contains an unexpected character in line 8 and column 53.

11
components/efuse/esp32s3/include/esp_efuse_table.h
View File

@ -9,7 +9,7 @@ extern "C" {
#endif
// md5_digest_table 5d853dcd3eb114e78147566245552b2d
// md5_digest_table 87c5ae68b74dbafb114e14f6febff9e2
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -101,6 +101,8 @@ extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[];
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];
@ -113,12 +115,13 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VER_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VER_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[];

7
components/efuse/include/esp_efuse.h
View File

@ -276,13 +276,6 @@ esp_err_t esp_efuse_read_block(esp_efuse_block_t blk, void* dst_key, size_t offs
*/
esp_err_t esp_efuse_write_block(esp_efuse_block_t blk, const void* src_key, size_t offset_in_bits, size_t size_bits);
/**
* @brief Returns chip version from efuse
*
* @return chip version
*/
uint8_t esp_efuse_get_chip_ver(void);
/**
* @brief Returns chip package from efuse
*

6
components/efuse/test/test_efuse.c
View File

@ -950,12 +950,6 @@ TEST_CASE("Test chip_ver_pkg APIs return the same value", "[efuse]")
TEST_ASSERT_EQUAL_INT(esp_efuse_get_pkg_ver(), bootloader_common_get_chip_ver_pkg());
}
TEST_CASE("Test chip_revision APIs return the same value", "[efuse]")
{
esp_efuse_utility_update_virt_blocks();
TEST_ASSERT_EQUAL_INT(esp_efuse_get_chip_ver(), bootloader_common_get_chip_revision());
}
#ifndef CONFIG_IDF_TARGET_ESP32
#if CONFIG_IDF_ENV_FPGA || CONFIG_EFUSE_VIRTUAL
TEST_CASE("Test writing order is BLK_MAX->BLK0", "[efuse]")

1
components/esp_hw_support/include/esp_chip_info.h
View File

@ -41,6 +41,7 @@ typedef enum {
typedef struct {
esp_chip_model_t model; //!< chip model, one of esp_chip_model_t
uint32_t features; //!< bit mask of CHIP_FEATURE_x feature flags
uint16_t full_revision; //!< chip revision number (in format MXX; where M - wafer major version, XX - wafer minor version)
uint8_t cores; //!< number of CPU cores
uint8_t revision; //!< chip revision number
} esp_chip_info_t;

12
components/esp_hw_support/port/esp32/chip_info.c
View File

@ -9,22 +9,24 @@
#include "soc/soc.h"
#include "soc/efuse_reg.h"
#include "esp_efuse.h"
#include "hal/efuse_hal.h"
#include "hal/efuse_ll.h"
void esp_chip_info(esp_chip_info_t* out_info)
{
uint32_t efuse_rd3 = REG_READ(EFUSE_BLK0_RDATA3_REG);
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32;
out_info->revision = esp_efuse_get_chip_ver();
out_info->revision = efuse_hal_get_major_chip_version();
out_info->full_revision = efuse_hal_chip_revision();
if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_APP_CPU_M) == 0) {
if (efuse_ll_get_disable_app_cpu() == 0) {
out_info->cores = 2;
} else {
out_info->cores = 1;
}
out_info->features = CHIP_FEATURE_WIFI_BGN;
if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0) {
if (efuse_ll_get_disable_bt() == 0) {
out_info->features |= CHIP_FEATURE_BT | CHIP_FEATURE_BLE;
}
uint32_t package = esp_efuse_get_pkg_ver();
@ -42,6 +44,6 @@ void esp_chip_info(esp_chip_info_t* out_info)
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
inline bool soc_has_cache_lock_bug(void)
{
return (esp_efuse_get_chip_ver() == 3);
return (efuse_hal_get_major_chip_version() == 3);
}
#endif

13
components/esp_hw_support/port/esp32/rtc_clk.c
View File

@ -16,6 +16,8 @@
#include "soc/rtc_periph.h"
#include "soc/sens_periph.h"
#include "soc/dport_reg.h"
#include "hal/efuse_ll.h"
#include "hal/efuse_hal.h"
#include "soc/efuse_periph.h"
#include "soc/syscon_reg.h"
#include "soc/gpio_struct.h"
@ -122,7 +124,7 @@ static void rtc_clk_32k_enable_common(int dac, int dres, int dbias)
REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DBIAS_XTAL_32K, dbias);
#ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
uint8_t chip_ver = esp_efuse_get_chip_ver();
uint8_t chip_ver = efuse_hal_get_major_chip_version();
// version0 and version1 need provide additional current to external XTAL.
if(chip_ver == 0 || chip_ver == 1) {
/* TOUCH sensor can provide additional current to external XTAL.
@ -138,7 +140,7 @@ static void rtc_clk_32k_enable_common(int dac, int dres, int dbias)
SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
}
#elif defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_V2
uint8_t chip_ver = esp_efuse_get_chip_ver();
uint8_t chip_ver = efuse_hal_get_major_chip_version();
if(chip_ver == 0 || chip_ver == 1) {
/* TOUCH sensor can provide additional current to external XTAL.
In some case, X32N and X32P PAD don't have enough drive capability to start XTAL */
@ -172,13 +174,13 @@ void rtc_clk_32k_enable(bool enable)
CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
#ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
uint8_t chip_ver = esp_efuse_get_chip_ver();
uint8_t chip_ver = efuse_hal_get_major_chip_version();
if(chip_ver == 0 || chip_ver == 1) {
/* Power down TOUCH */
CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
}
#elif defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_V2
uint8_t chip_ver = esp_efuse_get_chip_ver();
uint8_t chip_ver = efuse_hal_get_major_chip_version();
if(chip_ver == 0 || chip_ver == 1) {
/* Power down TOUCH */
CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_XPD_BIAS_M);
@ -281,8 +283,7 @@ void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm
if (enable) {
uint8_t sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV1;
uint32_t is_rev0 = (GET_PERI_REG_BITS2(EFUSE_BLK0_RDATA3_REG, 1, 15) == 0);
if (is_rev0) {
if (efuse_hal_get_major_chip_version() == 0) {
sdm0 = 0;
sdm1 = 0;
sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV0;

3
components/esp_hw_support/port/esp32/rtc_init.c
View File

@ -11,6 +11,7 @@
#include "soc/rtc_periph.h"
#include "soc/dport_reg.h"
#include "soc/efuse_periph.h"
#include "hal/efuse_ll.h"
#include "soc/gpio_periph.h"
@ -118,7 +119,7 @@ rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
result.tieh = (efuse_reg & EFUSE_RD_SDIO_TIEH_M) >> EFUSE_RD_SDIO_TIEH_S;
//DREFH/M/L eFuse are used for EFUSE_ADC_VREF instead. Therefore tuning
//will only be available on older chips that don't have EFUSE_ADC_VREF
if(REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG ,EFUSE_RD_BLK3_PART_RESERVE) == 0){
if(!efuse_ll_get_blk3_part_reserve()){
//BLK3_PART_RESERVE indicates the presence of EFUSE_ADC_VREF
// in this case, DREFH/M/L are also set from EFUSE
result.drefh = (efuse_reg & EFUSE_RD_SDIO_DREFH_M) >> EFUSE_RD_SDIO_DREFH_S;

3
components/esp_hw_support/port/esp32/spiram_psram.c
View File

@ -25,6 +25,7 @@
#include "soc/efuse_periph.h"
#include "soc/soc_caps.h"
#include "driver/gpio.h"
#include "hal/efuse_hal.h"
#include "hal/gpio_hal.h"
#include "driver/spi_common_internal.h"
#include "driver/periph_ctrl.h"
@ -831,7 +832,7 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
}
psram_io.psram_clk_io = D2WD_PSRAM_CLK_IO;
psram_io.psram_cs_io = D2WD_PSRAM_CS_IO;
} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 && esp_efuse_get_chip_ver() >= 3) {
} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 && efuse_hal_get_major_chip_version() >= 3) {
ESP_EARLY_LOGE(TAG, "This chip is ESP32-PICO-V3. It does not support PSRAM (disable it in Kconfig)");
abort();
} else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)) {

4
components/esp_hw_support/port/esp32c3/chip_info.c
View File

@ -6,13 +6,13 @@
#include <string.h>
#include "esp_chip_info.h"
#include "esp_efuse.h"
#include "hal/efuse_hal.h"
void esp_chip_info(esp_chip_info_t *out_info)
{
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32C3;
out_info->revision = esp_efuse_get_chip_ver();
out_info->full_revision = efuse_hal_chip_revision();
out_info->cores = 1;
out_info->features = CHIP_FEATURE_WIFI_BGN | CHIP_FEATURE_BLE;
}

5
components/esp_hw_support/port/esp32c3/rtc_init.c
View File

@ -14,6 +14,7 @@
#include "soc/spi_mem_reg.h"
#include "soc/extmem_reg.h"
#include "soc/system_reg.h"
#include "hal/efuse_hal.h"
#include "regi2c_ctrl.h"
#include "soc_log.h"
#include "esp_efuse.h"
@ -50,7 +51,7 @@ void rtc_init(rtc_config_t cfg)
if (cfg.cali_ocode) {
uint32_t rtc_calib_version = 0;
esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 3);
esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &rtc_calib_version, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count); // IDF-5366
if (err != ESP_OK) {
rtc_calib_version = 0;
SOC_LOGW(TAG, "efuse read fail, set default rtc_calib_version: %d\n", rtc_calib_version);
@ -316,7 +317,7 @@ static void set_rtc_dig_dbias()
3. a reasonable rtc_dbias can be calculated by a certion formula.
*/
uint32_t rtc_dbias = 28, dig_dbias = 28;
uint8_t chip_version = esp_efuse_get_chip_ver();
uint8_t chip_version = efuse_hal_get_minor_chip_version();
if (chip_version >= 3) {
dig_dbias = get_dig_dbias_by_efuse(chip_version);
if (dig_dbias != 0) {

3
components/esp_hw_support/port/esp32c3/rtc_sleep.c
View File

@ -22,6 +22,7 @@
#include "esp32c3/rom/rtc.h"
#include "regi2c_ctrl.h"
#include "esp_efuse.h"
#include "hal/efuse_hal.h"
/**
* Configure whether certain peripherals are powered down in deep sleep
@ -77,7 +78,7 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_
if (sleep_flags & RTC_SLEEP_PD_DIG) {
unsigned atten_deep_sleep = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT;
#if CONFIG_ESP32C3_REV_MIN < 3
if (esp_efuse_get_chip_ver() < 3) {
if (efuse_hal_get_minor_chip_version() < 3) {
atten_deep_sleep = 0; /* workaround for deep sleep issue in high temp on ECO2 and below */
}
#endif

4
components/esp_hw_support/port/esp32h2/chip_info.c
View File

@ -6,13 +6,13 @@
#include <string.h>
#include "esp_chip_info.h"
#include "esp_efuse.h"
#include "hal/efuse_hal.h"
void esp_chip_info(esp_chip_info_t *out_info)
{
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32H2;
out_info->revision = esp_efuse_get_chip_ver();
out_info->full_revision = efuse_hal_chip_revision();
out_info->cores = 1;
out_info->features = CHIP_FEATURE_IEEE802154 | CHIP_FEATURE_BLE;
}

6
components/esp_hw_support/port/esp32s2/chip_info.c
View File

@ -6,15 +6,17 @@
#include <string.h>
#include "esp_chip_info.h"
#include "esp_efuse.h"
#include "hal/efuse_ll.h"
#include "hal/efuse_hal.h"
void esp_chip_info(esp_chip_info_t *out_info)
{
uint32_t pkg_ver = esp_efuse_get_pkg_ver();
uint32_t pkg_ver = efuse_ll_get_chip_ver_pkg();
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32S2;
out_info->full_revision = efuse_hal_chip_revision();
out_info->cores = 1;
out_info->features = CHIP_FEATURE_WIFI_BGN;

2
components/esp_hw_support/port/esp32s2/rtc_init.c
View File

@ -152,7 +152,7 @@ void rtc_init(rtc_config_t cfg)
#if !CONFIG_IDF_ENV_FPGA
if (cfg.cali_ocode) {
uint32_t rtc_calib_version = 0;
esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 32);
esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MINOR, &rtc_calib_version, ESP_EFUSE_BLK_VERSION_MINOR[0]->bit_count); // IDF-5366
if (rtc_calib_version == 2) {
set_ocode_by_efuse(rtc_calib_version);
} else {

2
components/esp_hw_support/port/esp32s3/chip_info.c
View File

@ -6,11 +6,13 @@
#include <string.h>
#include "esp_chip_info.h"
#include "hal/efuse_hal.h"
void esp_chip_info(esp_chip_info_t *out_info)
{
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32S3;
out_info->full_revision = efuse_hal_chip_revision();
out_info->cores = 2;
out_info->features = CHIP_FEATURE_WIFI_BGN | CHIP_FEATURE_BLE;
}

6
components/esp_hw_support/port/esp32s3/rtc_init.c
View File

@ -79,7 +79,7 @@ void rtc_init(rtc_config_t cfg)
if (cfg.cali_ocode) {
uint32_t blk_ver_major = 0;
esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VER_MAJOR, &blk_ver_major, ESP_EFUSE_BLK_VER_MAJOR[0]->bit_count);
esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &blk_ver_major, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count); // IDF-5366
if (err != ESP_OK) {
blk_ver_major = 0;
SOC_LOGW(TAG, "efuse read fail, set default blk_ver_major: %d\n", blk_ver_major);
@ -405,8 +405,8 @@ static void rtc_set_stored_dbias(void)
4. save these values for reuse
*/
uint32_t blk_minor = 0, blk_major = 0;
esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VER_MINOR, &blk_minor, ESP_EFUSE_BLK_VER_MINOR[0]->bit_count);
esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VER_MAJOR, &blk_major, ESP_EFUSE_BLK_VER_MAJOR[0]->bit_count);
esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MINOR, &blk_minor, ESP_EFUSE_BLK_VERSION_MINOR[0]->bit_count);
esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &blk_major, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count);
if ((err0 != ESP_OK) | (err1 != ESP_OK)) {
blk_minor = 0;
blk_major = 0;

3
components/esp_phy/src/phy_init.c
View File

@ -34,6 +34,7 @@
#if CONFIG_IDF_TARGET_ESP32
#include "soc/dport_reg.h"
#endif
#include "hal/efuse_hal.h"
#if CONFIG_IDF_TARGET_ESP32
extern wifi_mac_time_update_cb_t s_wifi_mac_time_update_cb;
@ -666,7 +667,7 @@ void esp_phy_load_cal_and_init(void)
ESP_LOGI(TAG, "phy_version %s", phy_version);
#if CONFIG_IDF_TARGET_ESP32S2
phy_eco_version_sel(esp_efuse_get_chip_ver());
phy_eco_version_sel(efuse_hal_get_major_chip_version());
#endif
esp_phy_calibration_data_t* cal_data =
(esp_phy_calibration_data_t*) calloc(sizeof(esp_phy_calibration_data_t), 1);

4
components/esp_rom/patches/esp_rom_uart.c
View File

@ -15,7 +15,7 @@
#include <stdint.h>
#include <stdlib.h>
#include "esp_attr.h"
#include "esp_efuse.h"
#include "hal/efuse_hal.h"
#include "sdkconfig.h"
#include "hal/uart_ll.h"
@ -48,7 +48,7 @@ IRAM_ATTR void esp_rom_uart_set_as_console(uint8_t uart_no)
typedef void (*rom_func_t)(uint8_t);
rom_func_t uart_tx_switch = NULL;
if (esp_efuse_get_chip_ver() < 3) {
if (efuse_hal_chip_revision() < 3) {
uart_tx_switch = (rom_func_t)0x4004b8ca;
} else {
uart_tx_switch = (rom_func_t)0x4004c166;

4
components/hal/CMakeLists.txt
View File

@ -2,7 +2,9 @@ idf_build_get_property(target IDF_TARGET)
set(srcs "wdt_hal_iram.c"
"mpu_hal.c"
"cpu_hal.c")
"cpu_hal.c"
"efuse_hal.c"
"${target}/efuse_hal.c")
set(includes "${target}/include" "include" "platform_port/include")

18
components/hal/efuse_hal.c Normal file
View File

@ -0,0 +1,18 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include <sys/param.h>
#include "soc/soc_caps.h"
#include "hal/efuse_ll.h"
#include "hal/assert.h"
#include "hal/efuse_hal.h"
uint32_t efuse_hal_chip_revision(void)
{
return efuse_hal_get_major_chip_version() * 100 + efuse_hal_get_minor_chip_version();
}

59
components/hal/esp32/efuse_hal.c Normal file
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@ -0,0 +1,59 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include <sys/param.h>
#include "soc/soc_caps.h"
#include "hal/efuse_ll.h"
#include "hal/assert.h"
#include "hal/efuse_hal.h"
#include "soc/syscon_reg.h"
uint32_t efuse_hal_get_major_chip_version(void)
{
uint8_t eco_bit0 = efuse_ll_get_chip_ver_rev1();
uint8_t eco_bit1 = efuse_ll_get_chip_ver_rev2();
uint8_t eco_bit2 = (REG_READ(SYSCON_DATE_REG) & 0x80000000) >> 31;
uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0;
uint32_t chip_ver = 0;
switch (combine_value) {
case 0:
chip_ver = 0;
break;
case 1:
chip_ver = 1;
break;
case 3:
chip_ver = 2;
break;
#if CONFIG_IDF_ENV_FPGA
case 4: /* Empty efuses, but SYSCON_DATE_REG bit is set */
chip_ver = 3;
break;
#endif // CONFIG_IDF_ENV_FPGA
case 7:
chip_ver = 3;
break;
default:
chip_ver = 0;
break;
}
return chip_ver;
}
uint32_t efuse_hal_get_minor_chip_version(void)
{
return efuse_ll_get_chip_wafer_version_minor();
}
uint32_t efuse_hal_get_rated_freq_mhz(void)
{
//Check if ESP32 is rated for a CPU frequency of 160MHz only
if (efuse_ll_get_chip_cpu_freq_rated() && efuse_ll_get_chip_cpu_freq_low()) {
return 160;
}
return 240;
}

26
components/hal/esp32/include/hal/efuse_hal.h Normal file
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@ -0,0 +1,26 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "soc/soc_caps.h"
#include "hal/efuse_ll.h"
#include_next "hal/efuse_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief get rated frequency in MHz
*/
uint32_t efuse_hal_get_rated_freq_mhz(void);
#ifdef __cplusplus
}
#endif

213
components/hal/esp32/include/hal/efuse_ll.h Normal file
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@ -0,0 +1,213 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
// Always inline these functions even no gcc optimization is applied.
/******************* eFuse fields *************************/
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void)
{
return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_FLASH_CRYPT_CNT);
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void)
{
return REG_READ(EFUSE_BLK0_RDATA1_REG);
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void)
{
return REG_GET_FIELD(EFUSE_BLK0_RDATA2_REG, EFUSE_RD_WIFI_MAC_CRC_HIGH) & 0x0000FFFF;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v1_en(void)
{
return REG_GET_BIT(EFUSE_BLK0_RDATA6_REG, EFUSE_RD_ABS_DONE_0);
}
__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void)
{
return REG_GET_BIT(EFUSE_BLK0_RDATA6_REG, EFUSE_RD_ABS_DONE_1);
}
__attribute__((always_inline)) static inline bool efuse_ll_get_sdio_force(void)
{
return REG_GET_BIT(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_SDIO_FORCE);
}
__attribute__((always_inline)) static inline bool efuse_ll_get_xpd_sdio(void)
{
return REG_GET_BIT(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_XPD_SDIO_REG);
}
__attribute__((always_inline)) static inline bool efuse_ll_get_sdio_tieh(void)
{
return REG_GET_BIT(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_SDIO_TIEH);
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefh(void)
{
return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_SDIO_DREFH);
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefm(void)
{
return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_SDIO_DREFM);
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefl(void)
{
return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_SDIO_DREFL);
}
__attribute__((always_inline)) static inline bool efuse_ll_get_blk3_part_reserve(void)
{
return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_BLK3_PART_RESERVE);
}
__attribute__((always_inline)) static inline bool efuse_ll_get_chip_cpu_freq_rated(void)
{
return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED);
}
__attribute__((always_inline)) static inline bool efuse_ll_get_chip_cpu_freq_low(void)
{
return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW);
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
{
uint32_t pkg_version = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
uint32_t pkg_version_4bit = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG_4BIT);
return (pkg_version_4bit << 3) | pkg_version;
}
// use efuse_hal_get_major_chip_version() to get full major chip version
__attribute__((always_inline)) static inline bool efuse_ll_get_chip_ver_rev1(void)
{
return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_REV1);
}
// use efuse_hal_get_major_chip_version() to get full major chip version
__attribute__((always_inline)) static inline bool efuse_ll_get_chip_ver_rev2(void)
{
return REG_GET_BIT(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_CHIP_VER_REV2);
}
// use efuse_hal_get_minor_chip_version() to get minor chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
{
return REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_WAFER_VERSION_MINOR);
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
{
return false;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_coding_scheme(void)
{
return REG_GET_FIELD(EFUSE_BLK0_RDATA6_REG, EFUSE_CODING_SCHEME);
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_app_cpu(void)
{
return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_APP_CPU);
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_bt(void)
{
return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_BT);
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_vol_level_hp_inv(void)
{
return REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_VOL_LEVEL_HP_INV);
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc_vref(void)
{
return REG_GET_FIELD(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_ADC_VREF);
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc1_tp_low(void)
{
return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC1_TP_LOW);
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc2_tp_low(void)
{
return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC2_TP_LOW);
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc1_tp_high(void)
{
return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC1_TP_HIGH);
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc2_tp_high(void)
{
return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC2_TP_HIGH);
}
/******************* eFuse control functions *************************/
__attribute__((always_inline)) static inline bool efuse_ll_get_cmd(void)
{
return REG_READ(EFUSE_CMD_REG);
}
__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
{
REG_WRITE(EFUSE_CMD_REG, EFUSE_READ_CMD);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(void)
{
REG_WRITE(EFUSE_CMD_REG, EFUSE_PGM_CMD);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
{
REG_WRITE(EFUSE_CONF_REG, EFUSE_READ_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
{
REG_WRITE(EFUSE_CONF_REG, EFUSE_WRITE_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint32_t value)
{
REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, value);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_sel0(uint32_t value)
{
REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL0, value);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_sel1(uint32_t value)
{
REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL1, value);
}
/******************* eFuse control functions *************************/
#ifdef __cplusplus
}
#endif

22
components/hal/esp32c3/efuse_hal.c Normal file
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@ -0,0 +1,22 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include <sys/param.h>
#include "soc/soc_caps.h"
#include "hal/assert.h"
#include "hal/efuse_hal.h"
#include "hal/efuse_ll.h"
uint32_t efuse_hal_get_major_chip_version(void)
{
return efuse_ll_get_chip_wafer_version_major();
}
uint32_t efuse_hal_get_minor_chip_version(void)
{
return efuse_ll_get_chip_wafer_version_minor();
}

132
components/hal/esp32c3/include/hal/efuse_ll.h Normal file
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@ -0,0 +1,132 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#include "esp32c3/rom/efuse.h"
#ifdef __cplusplus
extern "C" {
#endif
// Always inline these functions even no gcc optimization is applied.
/******************* eFuse fields *************************/
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void)
{
return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void)
{
return EFUSE.rd_repeat_data1.wdt_delay_sel;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void)
{
return EFUSE.rd_mac_spi_sys_0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void)
{
return EFUSE.rd_mac_spi_sys_1.mac_1;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void)
{
return EFUSE.rd_repeat_data2.secure_boot_en;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_err_rst_enable(void)
{
return EFUSE.rd_repeat_data3.err_rst_enable;
}
// use efuse_hal_get_major_chip_version() to get major chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
{
return EFUSE.rd_mac_spi_sys_5.wafer_version_major;
}
// use efuse_hal_get_minor_chip_version() to get minor chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
{
return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_low;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
{
return EFUSE.rd_repeat_data4.disable_wafer_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
{
return EFUSE.rd_sys_part1_data4.blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
{
return EFUSE.rd_mac_spi_sys_3.blk_version_minor;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
{
return EFUSE.rd_repeat_data4.disable_blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
{
return EFUSE.rd_mac_spi_sys_3.pkg_version;
}
/******************* eFuse control functions *************************/
__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void)
{
return EFUSE.cmd.read_cmd;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void)
{
return EFUSE.cmd.pgm_cmd;
}
__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
{
EFUSE.cmd.read_cmd = 1;
}
__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
{
HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
{
EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
{
EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
{
EFUSE.wr_tim_conf2.pwr_off_num = value;
}
/******************* eFuse control functions *************************/
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include <sys/param.h>
#include "soc/soc_caps.h"
#include "hal/assert.h"
#include "hal/efuse_hal.h"
#include "hal/efuse_ll.h"
uint32_t efuse_hal_get_major_chip_version(void)
{
return efuse_ll_get_chip_wafer_version_major();
}
uint32_t efuse_hal_get_minor_chip_version(void)
{
return efuse_ll_get_chip_wafer_version_minor();
}

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/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#include "esp32h2/rom/efuse.h"
#ifdef __cplusplus
extern "C" {
#endif
// Always inline these functions even no gcc optimization is applied.
/******************* eFuse fields *************************/
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void)
{
return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void)
{
return EFUSE.rd_repeat_data1.wdt_delay_sel;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void)
{
return EFUSE.rd_mac_spi_sys_0.mac_0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void)
{
return EFUSE.rd_mac_spi_sys_1.mac_1;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void)
{
return EFUSE.rd_repeat_data2.secure_boot_en;
}
// use efuse_hal_get_major_chip_version() to get major chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
{
return EFUSE.rd_mac_spi_sys_3.wafer_version;
}
// use efuse_hal_get_minor_chip_version() to get minor chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
{
return 0;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
{
return 0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
{
return 0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
{
return 0;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
{
return 0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
{
return EFUSE.rd_mac_spi_sys_3.pkg_version;
}
/******************* eFuse control functions *************************/
__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void)
{
return EFUSE.cmd.read_cmd;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void)
{
return EFUSE.cmd.pgm_cmd;
}
__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
{
EFUSE.cmd.read_cmd = 1;
}
__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
{
HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
{
EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
{
EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
{
EFUSE.wr_tim_conf2.pwr_off_num = value;
}
/******************* eFuse control functions *************************/
#ifdef __cplusplus
}
#endif

22
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/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include <sys/param.h>
#include "soc/soc_caps.h"
#include "hal/assert.h"
#include "hal/efuse_hal.h"
#include "hal/efuse_ll.h"
uint32_t efuse_hal_get_major_chip_version(void)
{
return efuse_ll_get_chip_wafer_version_major();
}
uint32_t efuse_hal_get_minor_chip_version(void)
{
return efuse_ll_get_chip_wafer_version_minor();
}

152
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@ -0,0 +1,152 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#include "esp32s2/rom/efuse.h"
#ifdef __cplusplus
extern "C" {
#endif
// Always inline these functions even no gcc optimization is applied.
/******************* eFuse fields *************************/
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void)
{
return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void)
{
return EFUSE.rd_repeat_data1.wdt_delay_sel;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void)
{
return EFUSE.rd_mac_spi_8m_0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void)
{
return EFUSE.rd_mac_spi_8m_1.mac_1;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void)
{
return EFUSE.rd_repeat_data2.secure_boot_en;
}
// use efuse_hal_get_major_chip_version() to get major chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
{
return EFUSE.rd_mac_spi_8m_3.wafer_version_major;
}
// use efuse_hal_get_minor_chip_version() to get minor chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
{
return (EFUSE.rd_mac_spi_8m_3.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_8m_4.wafer_version_minor_low;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
{
return EFUSE.rd_repeat_data4.disable_wafer_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
{
return EFUSE.rd_mac_spi_8m_3.blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
{
return EFUSE.rd_sys_data4.blk_version_minor;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
{
return EFUSE.rd_repeat_data4.disable_blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
{
return EFUSE.rd_mac_spi_8m_4.pkg_version;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_sdio_force(void)
{
return EFUSE.rd_repeat_data1.sdio_force;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_sdio_tieh(void)
{
return EFUSE.rd_repeat_data1.sdio_tieh;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_sdio_xpd(void)
{
return EFUSE.rd_repeat_data1.sdio_xpd;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefl(void)
{
return EFUSE.rd_repeat_data1.sdio_drefl;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefm(void)
{
return EFUSE.rd_repeat_data1.sdio_drefm;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefh(void)
{
return EFUSE.rd_repeat_data0.sdio_drefh;
}
/******************* eFuse control functions *************************/
__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void)
{
return EFUSE.cmd.read_cmd;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void)
{
return EFUSE.cmd.pgm_cmd;
}
__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
{
EFUSE.cmd.read_cmd = 1;
}
__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
{
HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
{
EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
{
EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
}
/******************* eFuse control functions *************************/
#ifdef __cplusplus
}
#endif

22
components/hal/esp32s3/efuse_hal.c Normal file
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@ -0,0 +1,22 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include <sys/param.h>
#include "soc/soc_caps.h"
#include "hal/assert.h"
#include "hal/efuse_hal.h"
#include "hal/efuse_ll.h"
uint32_t efuse_hal_get_major_chip_version(void)
{
return efuse_ll_get_chip_wafer_version_major();
}
uint32_t efuse_hal_get_minor_chip_version(void)
{
return efuse_ll_get_chip_wafer_version_minor();
}

132
components/hal/esp32s3/include/hal/efuse_ll.h Normal file
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@ -0,0 +1,132 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#include "esp32s3/rom/efuse.h"
#ifdef __cplusplus
extern "C" {
#endif
// Always inline these functions even no gcc optimization is applied.
/******************* eFuse fields *************************/
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void)
{
return EFUSE.rd_repeat_data1.reg_spi_boot_crypt_cnt;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void)
{
return EFUSE.rd_repeat_data1.reg_wdt_delay_sel;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_type(void)
{
return EFUSE.rd_repeat_data3.reg_flash_type;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void)
{
return EFUSE.rd_mac_spi_sys_0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void)
{
return EFUSE.rd_mac_spi_sys_1.reg_mac_1;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void)
{
return EFUSE.rd_repeat_data2.reg_secure_boot_en;
}
// use efuse_hal_get_major_chip_version() to get major chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
{
return EFUSE.rd_mac_spi_sys_5.wafer_version_major;
}
// use efuse_hal_get_minor_chip_version() to get minor chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
{
return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_low;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
{
return EFUSE.rd_repeat_data4.disable_wafer_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
{
return EFUSE.rd_sys_part1_data4.blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
{
return EFUSE.rd_mac_spi_sys_3.blk_version_minor;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
{
return EFUSE.rd_repeat_data4.disable_blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
{
return 0;
}
/******************* eFuse control functions *************************/
__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void)
{
return EFUSE.cmd.read_cmd;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void)
{
return EFUSE.cmd.pgm_cmd;
}
__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
{
EFUSE.cmd.read_cmd = 1;
}
__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
{
HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
{
EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
{
EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
{
EFUSE.wr_tim_conf2.pwr_off_num = value;
}
/******************* eFuse control functions *************************/
#ifdef __cplusplus
}
#endif

36
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@ -0,0 +1,36 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Returns chip version
*
* @return Chip version in format: Major * 100 + Minor
*/
uint32_t efuse_hal_chip_revision(void);
/**
* @brief Returns major chip version
*/
uint32_t efuse_hal_get_major_chip_version(void);
/**
* @brief Returns minor chip version
*/
uint32_t efuse_hal_get_minor_chip_version(void);
#ifdef __cplusplus
}
#endif

29
components/soc/esp32/include/soc/efuse_reg.h
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@ -200,15 +200,12 @@
#define EFUSE_RD_FLASH_CRYPT_CONFIG_M ((EFUSE_RD_FLASH_CRYPT_CONFIG_V)<<(EFUSE_RD_FLASH_CRYPT_CONFIG_S))
#define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0xF
#define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28
/* EFUSE_RD_DIG_VOL_L6: RO; bitpos:[27:24]; */
/*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (RO)
BIT[27] is the sign bit, 0: + , 1: -
BIT[26:24] is the difference value, unit: 0.017V
volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017 */
#define EFUSE_RD_DIG_VOL_L6 0x0F
#define EFUSE_RD_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S))
#define EFUSE_RD_DIG_VOL_L6_V 0x0F
#define EFUSE_RD_DIG_VOL_L6_S 24
/* EFUSE_RD_WAFER_VERSION_MINOR: RO; bitpos:[25:24]; */
/*descritpion: Wafer version minor*/
#define EFUSE_RD_WAFER_VERSION_MINOR 0x00000003
#define EFUSE_RD_WAFER_VERSION_MINOR_M ((EFUSE_RD_WAFER_VERSION_MINOR_V)<<(EFUSE_RD_WAFER_VERSION_MINOR_S))
#define EFUSE_RD_WAFER_VERSION_MINOR_V 0x03
#define EFUSE_RD_WAFER_VERSION_MINOR_S 24
/* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] */
/*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz.
0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)*/
@ -216,12 +213,11 @@
#define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S))
#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03
#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22
/* EFUSE_RD_INST_CONFIG : RO ;bitpos:[27:20] ;default: 8'b0 ; */
/* Deprecated */
#define EFUSE_RD_INST_CONFIG 0x000000FF /** Deprecated **/
#define EFUSE_RD_INST_CONFIG_M ((EFUSE_RD_INST_CONFIG_V)<<(EFUSE_RD_INST_CONFIG_S)) /** Deprecated **/
#define EFUSE_RD_INST_CONFIG_V 0xFF /** Deprecated **/
#define EFUSE_RD_INST_CONFIG_S 20 /** Deprecated **/
/* EFUSE_RD_CHIP_VER_REV2 : RO ;bitpos:[20] ;default: 8'b0 ; */
#define EFUSE_RD_CHIP_VER_REV2 (BIT(20))
#define EFUSE_RD_CHIP_VER_REV2_M ((EFUSE_RD_CHIP_VER_REV2_V)<<(EFUSE_RD_CHIP_VER_REV2_S))
#define EFUSE_RD_CHIP_VER_REV2_V 0x1
#define EFUSE_RD_CHIP_VER_REV2_S 20
/* EFUSE_RD_SPI_PAD_CONFIG_CS0 : RO ;bitpos:[19:15] ;default: 5'b0 ; */
/*description: read for SPI_pad_config_cs0*/
#define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001F
@ -1054,6 +1050,9 @@
#define EFUSE_CLK_SEL0_V 0xFF
#define EFUSE_CLK_SEL0_S 0
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x0fc)
/* EFUSE_FORCE_NO_WR_RD_DIS : R/W ;bitpos:[16] ;default: 1'h1 ; */
/*description: */

7
components/soc/esp32/include/soc/efuse_struct.h Normal file
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@ -0,0 +1,7 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once

3
components/soc/esp32c3/include/soc/efuse_reg.h
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@ -1807,6 +1807,9 @@ extern "C" {
#define EFUSE_MEM_FORCE_PD_V 0x1
#define EFUSE_MEM_FORCE_PD_S 0
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1CC)
/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command.*/

27
components/soc/esp32c3/include/soc/efuse_struct.h
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@ -172,7 +172,9 @@ typedef volatile struct efuse_dev_s {
} rd_repeat_data3;
union {
struct {
uint32_t rpt4_reserved4:24; /*Reserved.*/
uint32_t disable_wafer_version_major: 1;
uint32_t disable_blk_version_major: 1;
uint32_t rpt4_reserved4:22; /*Reserved.*/
uint32_t reserved24: 8; /*Reserved.*/
};
uint32_t val;
@ -189,17 +191,34 @@ typedef volatile struct efuse_dev_s {
union {
struct {
uint32_t spi_pad_conf_2: 18; /*Stores the second part of SPI_PAD_CONF.*/
uint32_t sys_data_part0_0:14; /*Stores the fist 14 bits of the zeroth part of system data.*/
uint32_t wafer_version_minor_low: 3;
uint32_t pkg_version: 3;
uint32_t blk_version_minor:3;
uint32_t sys_data_part0_0: 5;
};
uint32_t val;
} rd_mac_spi_sys_3;
uint32_t rd_mac_spi_sys_4; /*BLOCK1 data register $n.*/
uint32_t rd_mac_spi_sys_5; /*BLOCK1 data register $n.*/
union {
struct {
uint32_t reserved1: 23;
uint32_t wafer_version_minor_high: 1;
uint32_t wafer_version_major: 2;
uint32_t reserved2: 6;
};
uint32_t val;
} rd_mac_spi_sys_5; /*BLOCK1 data register $n.*/
uint32_t rd_sys_part1_data0; /*Register $n of BLOCK2 (system).*/
uint32_t rd_sys_part1_data1; /*Register $n of BLOCK2 (system).*/
uint32_t rd_sys_part1_data2; /*Register $n of BLOCK2 (system).*/
uint32_t rd_sys_part1_data3; /*Register $n of BLOCK2 (system).*/
uint32_t rd_sys_part1_data4; /*Register $n of BLOCK2 (system).*/
union {
struct {
uint32_t blk_version_major : 2;
uint32_t reserved1: 30;
};
uint32_t val;
} rd_sys_part1_data4; /*Register $n of BLOCK2 (system).*/
uint32_t rd_sys_part1_data5; /*Register $n of BLOCK2 (system).*/
uint32_t rd_sys_part1_data6; /*Register $n of BLOCK2 (system).*/
uint32_t rd_sys_part1_data7; /*Register $n of BLOCK2 (system).*/

1
components/soc/esp32c3/ld/esp32c3.peripherals.ld
View File

@ -6,6 +6,7 @@ PROVIDE ( GPIO = 0x60004000 );
PROVIDE ( SIGMADELTA = 0x60004f00 );
PROVIDE ( RTCCNTL = 0x60008000 );
PROVIDE ( RTCIO = 0x60008400 );
PROVIDE ( EFUSE = 0x60008800 );
PROVIDE ( HINF = 0x6000B000 );
PROVIDE ( I2S0 = 0x6002d000 );
PROVIDE ( I2C0 = 0x60013000 );

3
components/soc/esp32h2/include/soc/efuse_reg.h
View File

@ -1850,6 +1850,9 @@ extern "C" {
#define EFUSE_MEM_FORCE_PD_V 0x1
#define EFUSE_MEM_FORCE_PD_S 0
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1CC)
/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command.*/

11
components/soc/esp32h2/include/soc/efuse_struct.h
View File

@ -173,7 +173,12 @@ typedef volatile struct efuse_dev_s {
};
uint32_t val;
} rd_repeat_data4;
uint32_t rd_mac_spi_sys_0; /*BLOCK1 data register $n.*/
union {
struct {
uint32_t mac_0;
};
uint32_t val;
} rd_mac_spi_sys_0; /*BLOCK1 data register $n.*/
union {
struct {
uint32_t mac_1: 16; /*Stores the high 16 bits of MAC address.*/
@ -185,7 +190,9 @@ typedef volatile struct efuse_dev_s {
union {
struct {
uint32_t spi_pad_conf_2: 18; /*Stores the second part of SPI_PAD_CONF.*/
uint32_t sys_data_part0_0:14; /*Stores the fist 14 bits of the zeroth part of system data.*/
uint32_t wafer_version: 3;
uint32_t pkg_version: 3;
uint32_t sys_data_part0_0: 8; /*Stores the fist 14 bits of the zeroth part of system data.*/
};
uint32_t val;
} rd_mac_spi_sys_3;

1
components/soc/esp32h2/ld/esp32h2.peripherals.ld
View File

@ -17,6 +17,7 @@ PROVIDE ( RMTMEM = 0x60016400 );
PROVIDE ( PCNT = 0x60017000 );
PROVIDE ( SLC = 0x60018000 );
PROVIDE ( LEDC = 0x60019000 );
PROVIDE ( EFUSE = 0x6001A000 );
PROVIDE ( TIMERG0 = 0x6001F000 );
PROVIDE ( TIMERG1 = 0x60020000 );
PROVIDE ( SYSTIMER = 0x60023000 );

3
components/soc/esp32s2/include/soc/efuse_reg.h
View File

@ -2072,6 +2072,9 @@ extern "C" {
#define EFUSE_MEM_FORCE_PD_V 0x1
#define EFUSE_MEM_FORCE_PD_S 0
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: 0x5A5A: Operate programming command*/

34
components/soc/esp32s2/include/soc/efuse_struct.h
View File

@ -186,7 +186,9 @@ typedef volatile struct efuse_dev_s {
} rd_repeat_data3;
union {
struct {
uint32_t chip_version:24;
uint32_t disable_wafer_version_major: 1;
uint32_t disable_blk_version_major: 1;
uint32_t rpt4_reserved4:22;
uint32_t reserved24: 8;
};
uint32_t val;
@ -206,14 +208,38 @@ typedef volatile struct efuse_dev_s {
};
uint32_t val;
} rd_mac_spi_8m_2;
uint32_t rd_mac_spi_8m_3; /**/
uint32_t rd_mac_spi_8m_4; /**/
union {
struct {
uint32_t spi_pad_conf_2: 18;
uint32_t wafer_version_major: 2;
uint32_t wafer_version_minor_high: 1; // most significant bit
uint32_t reserve1: 4;
uint32_t blk_version_major: 2;
uint32_t reserve2: 5;
};
uint32_t val;
} rd_mac_spi_8m_3;
union {
struct {
uint32_t pkg_version: 4;
uint32_t wafer_version_minor_low: 3; // least significant bits
uint32_t reserve: 25;
};
uint32_t val;
} rd_mac_spi_8m_4;
uint32_t rd_mac_spi_8m_5; /**/
uint32_t rd_sys_data0; /**/
uint32_t rd_sys_data1; /**/
uint32_t rd_sys_data2; /**/
uint32_t rd_sys_data3; /**/
uint32_t rd_sys_data4; /**/
union {
struct {
uint32_t reserved1: 4;
uint32_t blk_version_minor : 3;
uint32_t reserved2: 25;
};
uint32_t val;
} rd_sys_data4; /**/
uint32_t rd_sys_data5; /**/
uint32_t rd_sys_data6; /**/
uint32_t rd_sys_data7; /**/

1
components/soc/esp32s2/ld/esp32s2.peripherals.ld
View File

@ -22,6 +22,7 @@ PROVIDE ( RMTMEM = 0x3f416400 );
PROVIDE ( PCNT = 0x3f417000 );
PROVIDE ( SLC = 0x3f418000 );
PROVIDE ( LEDC = 0x3f419000 );
PROVIDE ( EFUSE = 0x3f41A000 );
PROVIDE ( CP_DMA = 0x3f4c3000 );
PROVIDE ( TIMERG0 = 0x3f41F000 );
PROVIDE ( TIMERG1 = 0x3f420000 );

3
components/soc/esp32s3/include/soc/efuse_reg.h
View File

@ -1732,6 +1732,9 @@ ing user data failed and the number of error bytes is over 6..*/
#define EFUSE_MEM_FORCE_PD_V 0x1
#define EFUSE_MEM_FORCE_PD_S 0
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1CC)
/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command..*/

29
components/soc/esp32s3/include/soc/efuse_struct.h
View File

@ -120,7 +120,9 @@ typedef volatile struct efuse_dev_s {
} rd_repeat_data3;
union {
struct {
uint32_t reg_rpt4_reserved2 : 24; /*Reserved (used for four backups method).*/
uint32_t disable_wafer_version_major : 1;
uint32_t disable_blk_version_major : 1;
uint32_t reg_rpt4_reserved2 : 22; /*Reserved.*/
uint32_t reserved24 : 8; /*Reserved.*/
};
uint32_t val;
@ -136,18 +138,35 @@ typedef volatile struct efuse_dev_s {
uint32_t rd_mac_spi_sys_2;
union {
struct {
uint32_t reg_spi_pad_conf_2 : 18; /*Stores the second part of SPI_PAD_CONF.*/
uint32_t reg_sys_data_part0_0 : 14; /*Stores the fist 14 bits of the zeroth part of system data.*/
uint32_t spi_pad_conf_2: 18; /*Stores the second part of SPI_PAD_CONF.*/
uint32_t wafer_version_minor_low: 3;
uint32_t pkg_version: 3;
uint32_t blk_version_minor:3;
uint32_t reg_sys_data_part0_0: 5;
};
uint32_t val;
} rd_mac_spi_sys_3;
uint32_t rd_mac_spi_sys_4;
uint32_t rd_mac_spi_sys_5;
union {
struct {
uint32_t reserved1: 23;
uint32_t wafer_version_minor_high: 1;
uint32_t wafer_version_major: 2;
uint32_t reserved2: 6;
};
uint32_t val;
} rd_mac_spi_sys_5;
uint32_t rd_sys_part1_data0;
uint32_t rd_sys_part1_data1;
uint32_t rd_sys_part1_data2;
uint32_t rd_sys_part1_data3;
uint32_t rd_sys_part1_data4;
union {
struct {
uint32_t blk_version_major : 2;
uint32_t reserved1: 30;
};
uint32_t val;
} rd_sys_part1_data4;
uint32_t rd_sys_part1_data5;
uint32_t rd_sys_part1_data6;
uint32_t rd_sys_part1_data7;

1
components/soc/esp32s3/ld/esp32s3.peripherals.ld
View File

@ -8,6 +8,7 @@ PROVIDE ( SPIMEM1 = 0x60002000 );
PROVIDE ( SPIMEM0 = 0x60003000 );
PROVIDE ( GPIO = 0x60004000 );
PROVIDE ( SIGMADELTA = 0x60004f00 );
PROVIDE ( EFUSE = 0x60007000 );
PROVIDE ( RTCCNTL = 0x60008000 );
PROVIDE ( RTCIO = 0x60008400 );
PROVIDE ( SENS = 0x60008800 );

1
components/soc/include/soc/efuse_periph.h
View File

@ -14,3 +14,4 @@
#pragma once
#include "soc/efuse_reg.h"
#include "soc/efuse_struct.h"

2
docs/en/api-reference/system/efuse.rst
View File

@ -244,7 +244,7 @@ Access to the fields is via a pointer to the description structure. API function
* :cpp:func:`esp_efuse_get_keypurpose_dis_write` - Returns a write protection of the key purpose field for an eFuse key block (for esp32 always true).
* :cpp:func:`esp_efuse_key_block_unused` - Returns true if the key block is unused, false otherwise.
For frequently used fields, special functions are made, like this :cpp:func:`esp_efuse_get_chip_ver`, :cpp:func:`esp_efuse_get_pkg_ver`.
For frequently used fields, special functions are made, like this :cpp:func:`esp_efuse_get_pkg_ver`.
.. only:: not esp32

2
examples/build_system/cmake/idf_as_lib/stubs/esp32/esp_system.h
View File

@ -7,8 +7,8 @@
typedef struct {
uint32_t features; //!< bit mask of CHIP_FEATURE_x feature flags
uint16_t revision; //!< chip revision number (in format MXX; where M - wafer major version, XX - wafer minor version)
uint8_t cores; //!< number of CPU cores
uint8_t revision; //!< chip revision number
} esp_chip_info_t;
void esp_restart(void);