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Merge branch 'feature/esp32c5beta3_light_sleep_support_stage_2' into 'master'

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feat(esp_hw_support): esp32c5 sleep support (Stage 3:  support system peripheral sleep retention)

Closes IDF-8640

See merge request espressif/esp-idf!29723
This commit is contained in:
Jiang Jiang Jian 2024-04-15 14:40:52 +08:00
commit 25d40a67bc
16 changed files with 837 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
components/driver/i2c/i2c.c
View File

@ -276,7 +276,7 @@ static void i2c_hw_enable(i2c_port_t i2c_num)
I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock));
}
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_I2C_SUPPORT_SLEEP_RETENTION
static esp_err_t i2c_sleep_retention_init(void *arg)
{
i2c_port_t i2c_num = *(i2c_port_t *)arg;
@ -424,7 +424,7 @@ esp_err_t i2c_driver_install(i2c_port_t i2c_num, i2c_mode_t mode, size_t slv_rx_
}
#endif // SOC_I2C_SUPPORT_SLAVE
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-9353
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_I2C_SUPPORT_SLEEP_RETENTION
sleep_retention_module_init_param_t init_param = {
.cbs = { .create = { .handle = i2c_sleep_retention_init, .arg = &i2c_num } }
};
@ -485,7 +485,7 @@ esp_err_t i2c_driver_delete(i2c_port_t i2c_num)
esp_intr_free(p_i2c->intr_handle);
p_i2c->intr_handle = NULL;
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-9353
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_I2C_SUPPORT_SLEEP_RETENTION
esp_err_t err = sleep_retention_module_free(I2C_SLEEP_RETENTION_MODULE(i2c_num));
if (err == ESP_OK) {
err = sleep_retention_module_deinit(I2C_SLEEP_RETENTION_MODULE(i2c_num));

6
components/esp_driver_i2c/i2c_common.c
View File

@ -47,7 +47,7 @@ typedef struct i2c_platform_t {
static i2c_platform_t s_i2c_platform = {}; // singleton platform
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_I2C_SUPPORT_SLEEP_RETENTION
static esp_err_t s_i2c_sleep_retention_init(void *arg)
{
i2c_bus_t *bus = (i2c_bus_t *)arg;
@ -77,7 +77,7 @@ static esp_err_t s_i2c_bus_handle_acquire(i2c_port_num_t port_num, i2c_bus_handl
bus->bus_mode = mode;
bus->is_lp_i2c = (bus->port_num < SOC_HP_I2C_NUM) ? false : true;
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-9353
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_I2C_SUPPORT_SLEEP_RETENTION
if (bus->is_lp_i2c == false) {
sleep_retention_module_init_param_t init_param = {
.cbs = { .create = { .handle = s_i2c_sleep_retention_init, .arg = (void *)bus } }
@ -175,7 +175,7 @@ esp_err_t i2c_release_bus_handle(i2c_bus_handle_t i2c_bus)
if (s_i2c_platform.count[port_num] == 0) {
do_deinitialize = true;
s_i2c_platform.buses[port_num] = NULL;
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-9353
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_I2C_SUPPORT_SLEEP_RETENTION
if (i2c_bus->is_lp_i2c == false) {
esp_err_t err = sleep_retention_module_free(I2C_SLEEP_RETENTION_MODULE(port_num));
if (err == ESP_OK) {

14
components/esp_hw_support/CMakeLists.txt
View File

@ -152,17 +152,17 @@ if(NOT BOOTLOADER_BUILD)
if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
list(REMOVE_ITEM srcs
"sleep_gpio.c" # TODO: [ESP32C5] IDF-8638, IDF-8640
"port/esp_clk_tree_common.c" # TODO: [ESP32C5] IDF-8638, IDF-8640
"sleep_gpio.c" # TODO: [ESP32C5] IDF-8638
"port/esp_clk_tree_common.c" # TODO: [ESP32C5] IDF-8638
)
endif()
if(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
list(REMOVE_ITEM srcs
"sleep_modes.c" # TODO: [ESP32C5] IDF-8638, IDF-8640
"sleep_modem.c" # TODO: [ESP32C5] IDF-8638, IDF-8640
"sleep_wake_stub.c" # TODO: [ESP32C5] IDF-8638, IDF-8640
"sleep_gpio.c" # TODO: [ESP32C5] IDF-8638, IDF-8640
"port/esp_clk_tree_common.c" # TODO: [ESP32C5] IDF-8638, IDF-8640
"sleep_modes.c" # TODO: [ESP32C5] IDF-8638
"sleep_modem.c" # TODO: [ESP32C5] IDF-8638
"sleep_wake_stub.c" # TODO: [ESP32C5] IDF-8638
"sleep_gpio.c" # TODO: [ESP32C5] IDF-8638
"port/esp_clk_tree_common.c" # TODO: [ESP32C5] IDF-8638
)
endif()
if(CONFIG_IDF_TARGET_ESP32C61) # TODO: [ESP32C61] IDF-9245, IDF-9247, IDF-9248

2
components/esp_hw_support/sleep_modes.c
View File

@ -146,7 +146,7 @@
#elif CONFIG_IDF_TARGET_ESP32C6
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (318)
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (56)
#elif CONFIG_IDF_TARGET_ESP32C5 // TODO: [ESP32C5] IDF-8638, IDF-8640
#elif CONFIG_IDF_TARGET_ESP32C5 // TODO: [ESP32C5] IDF-8638
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (318)
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (56)
#elif CONFIG_IDF_TARGET_ESP32H2

2
components/esp_wifi/esp32c5/esp_adapter.c
View File

@ -661,8 +661,6 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
#if SOC_PM_MODEM_RETENTION_BY_REGDMA
._regdma_link_set_write_wait_content = regdma_link_set_write_wait_content,
._sleep_retention_find_link_by_id = sleep_retention_find_link_by_id,
._sleep_retention_entries_create = (int (*)(const void *, int, int, int))sleep_retention_entries_create,
._sleep_retention_entries_destroy = sleep_retention_entries_destroy,
#endif
._coex_schm_process_restart = coex_schm_process_restart_wrapper,
._coex_schm_register_cb = coex_schm_register_cb_wrapper,

12
components/hal/esp32c5/include/hal/pau_ll.h
View File

@ -13,6 +13,7 @@
#include "soc/soc.h"
#include "soc/pau_reg.h"
#include "soc/pau_struct.h"
#include "soc/pcr_struct.h"
#include "hal/pau_types.h"
#include "hal/assert.h"
@ -20,6 +21,17 @@
extern "C" {
#endif
static inline void pau_ll_enable_bus_clock(bool enable)
{
if (enable) {
PCR.regdma_conf.regdma_clk_en = 1;
PCR.regdma_conf.regdma_rst_en = 0;
} else {
PCR.regdma_conf.regdma_clk_en = 0;
PCR.regdma_conf.regdma_rst_en = 1;
}
}
static inline uint32_t pau_ll_get_regdma_backup_flow_error(pau_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION

71
components/soc/esp32c5/beta3/gpio_periph.c
View File

@ -0,0 +1,71 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/gpio_periph.h"
const uint32_t GPIO_PIN_MUX_REG[] = {
IO_MUX_GPIO0_REG,
IO_MUX_GPIO1_REG,
IO_MUX_GPIO2_REG,
IO_MUX_GPIO3_REG,
IO_MUX_GPIO4_REG,
IO_MUX_GPIO5_REG,
IO_MUX_GPIO6_REG,
IO_MUX_GPIO7_REG,
IO_MUX_GPIO8_REG,
IO_MUX_GPIO9_REG,
IO_MUX_GPIO10_REG,
IO_MUX_GPIO11_REG,
IO_MUX_GPIO12_REG,
IO_MUX_GPIO13_REG,
IO_MUX_GPIO14_REG,
IO_MUX_GPIO15_REG,
IO_MUX_GPIO16_REG,
IO_MUX_GPIO17_REG,
IO_MUX_GPIO18_REG,
IO_MUX_GPIO19_REG,
IO_MUX_GPIO20_REG,
IO_MUX_GPIO21_REG,
IO_MUX_GPIO22_REG,
IO_MUX_GPIO23_REG,
IO_MUX_GPIO24_REG,
IO_MUX_GPIO25_REG,
IO_MUX_GPIO26_REG,
};
_Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG");
const uint32_t GPIO_HOLD_MASK[] = {
BIT(0), //GPIO0 // LP_AON_GPIO_HOLD0_REG
BIT(1), //GPIO1
BIT(2), //GPIO2
BIT(3), //GPIO3
BIT(4), //GPIO4
BIT(5), //GPIO5
BIT(6), //GPIO6
BIT(7), //GPIO7
BIT(8), //GPIO8
BIT(9), //GPIO9
BIT(10), //GPIO10
BIT(11), //GPIO11
BIT(12), //GPIO12
BIT(13), //GPIO13
BIT(14), //GPIO14
BIT(15), //GPIO15
BIT(16), //GPIO16
BIT(17), //GPIO17
BIT(18), //GPIO18
BIT(19), //GPIO19
BIT(20), //GPIO20
BIT(21), //GPIO21
BIT(22), //GPIO22
BIT(23), //GPIO23
BIT(24), //GPIO24
BIT(25), //GPIO25
BIT(26), //GPIO26
};
_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");

16
components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in
View File

@ -103,6 +103,10 @@ config SOC_PMU_SUPPORTED
bool
default y
config SOC_PAU_SUPPORTED
bool
default y
config SOC_LP_TIMER_SUPPORTED
bool
default y
@ -127,6 +131,10 @@ config SOC_SPI_FLASH_SUPPORTED
bool
default y
config SOC_LIGHT_SLEEP_SUPPORTED
bool
default y
config SOC_MODEM_CLOCK_SUPPORTED
bool
default y
@ -655,6 +663,10 @@ config SOC_PM_SUPPORT_VDDSDIO_PD
bool
default y
config SOC_PM_SUPPORT_TOP_PD
bool
default y
config SOC_PM_SUPPORT_HP_AON_PD
bool
default y
@ -675,6 +687,10 @@ config SOC_PM_CPU_RETENTION_BY_SW
bool
default y
config SOC_PM_MODEM_RETENTION_BY_REGDMA
bool
default y
config SOC_PM_PAU_LINK_NUM
int
default 4

350
components/soc/esp32c5/beta3/include/soc/hp_system_reg.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -48,6 +48,13 @@ extern "C" {
* HP memory usage configuration register
*/
#define HP_SYS_SRAM_USAGE_CONF_REG (DR_REG_HP_SYS_BASE + 0x4)
/** HP_SYS_CACHE_USAGE : HRO; bitpos: [0]; default: 0;
* reserved
*/
#define HP_SYS_CACHE_USAGE (BIT(0))
#define HP_SYS_CACHE_USAGE_M (HP_SYS_CACHE_USAGE_V << HP_SYS_CACHE_USAGE_S)
#define HP_SYS_CACHE_USAGE_V 0x00000001U
#define HP_SYS_CACHE_USAGE_S 0
/** HP_SYS_SRAM_USAGE : R/W; bitpos: [11:8]; default: 0;
* 0: cpu use hp-memory. 1:mac-dump accessing hp-memory.
*/
@ -191,6 +198,58 @@ extern "C" {
#define HP_SYS_HP_PERI_TIMEOUT_UID_V 0x0000007FU
#define HP_SYS_HP_PERI_TIMEOUT_UID_S 0
/** HP_SYS_MODEM_PERI_TIMEOUT_CONF_REG register
* MODEM_PERI_TIMEOUT configuration register
*/
#define HP_SYS_MODEM_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0x24)
/** HP_SYS_MODEM_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
#define HP_SYS_MODEM_PERI_TIMEOUT_THRES 0x0000FFFFU
#define HP_SYS_MODEM_PERI_TIMEOUT_THRES_M (HP_SYS_MODEM_PERI_TIMEOUT_THRES_V << HP_SYS_MODEM_PERI_TIMEOUT_THRES_S)
#define HP_SYS_MODEM_PERI_TIMEOUT_THRES_V 0x0000FFFFU
#define HP_SYS_MODEM_PERI_TIMEOUT_THRES_S 0
/** HP_SYS_MODEM_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
#define HP_SYS_MODEM_PERI_TIMEOUT_INT_CLEAR (BIT(16))
#define HP_SYS_MODEM_PERI_TIMEOUT_INT_CLEAR_M (HP_SYS_MODEM_PERI_TIMEOUT_INT_CLEAR_V << HP_SYS_MODEM_PERI_TIMEOUT_INT_CLEAR_S)
#define HP_SYS_MODEM_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
#define HP_SYS_MODEM_PERI_TIMEOUT_INT_CLEAR_S 16
/** HP_SYS_MODEM_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing modem registers
*/
#define HP_SYS_MODEM_PERI_TIMEOUT_PROTECT_EN (BIT(17))
#define HP_SYS_MODEM_PERI_TIMEOUT_PROTECT_EN_M (HP_SYS_MODEM_PERI_TIMEOUT_PROTECT_EN_V << HP_SYS_MODEM_PERI_TIMEOUT_PROTECT_EN_S)
#define HP_SYS_MODEM_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
#define HP_SYS_MODEM_PERI_TIMEOUT_PROTECT_EN_S 17
/** HP_SYS_MODEM_PERI_TIMEOUT_ADDR_REG register
* MODEM_PERI_TIMEOUT_ADDR register
*/
#define HP_SYS_MODEM_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYS_BASE + 0x28)
/** HP_SYS_MODEM_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
#define HP_SYS_MODEM_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
#define HP_SYS_MODEM_PERI_TIMEOUT_ADDR_M (HP_SYS_MODEM_PERI_TIMEOUT_ADDR_V << HP_SYS_MODEM_PERI_TIMEOUT_ADDR_S)
#define HP_SYS_MODEM_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
#define HP_SYS_MODEM_PERI_TIMEOUT_ADDR_S 0
/** HP_SYS_MODEM_PERI_TIMEOUT_UID_REG register
* MODEM_PERI_TIMEOUT_UID register
*/
#define HP_SYS_MODEM_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYS_BASE + 0x2c)
/** HP_SYS_MODEM_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
#define HP_SYS_MODEM_PERI_TIMEOUT_UID 0x0000007FU
#define HP_SYS_MODEM_PERI_TIMEOUT_UID_M (HP_SYS_MODEM_PERI_TIMEOUT_UID_V << HP_SYS_MODEM_PERI_TIMEOUT_UID_S)
#define HP_SYS_MODEM_PERI_TIMEOUT_UID_V 0x0000007FU
#define HP_SYS_MODEM_PERI_TIMEOUT_UID_S 0
/** HP_SYS_SDIO_CTRL_REG register
* SDIO Control configuration register
*/
@ -254,6 +313,228 @@ extern "C" {
#define HP_SYS_CORE_RUNSTALLED_V 0x00000001U
#define HP_SYS_CORE_RUNSTALLED_S 1
/** HP_SYS_MEM_TEST_CONF_REG register
* MEM_TEST configuration register
*/
#define HP_SYS_MEM_TEST_CONF_REG (DR_REG_HP_SYS_BASE + 0x44)
/** HP_SYS_HP_MEM_WPULSE : R/W; bitpos: [2:0]; default: 0;
* This field controls hp system memory WPULSE parameter.
*/
#define HP_SYS_HP_MEM_WPULSE 0x00000007U
#define HP_SYS_HP_MEM_WPULSE_M (HP_SYS_HP_MEM_WPULSE_V << HP_SYS_HP_MEM_WPULSE_S)
#define HP_SYS_HP_MEM_WPULSE_V 0x00000007U
#define HP_SYS_HP_MEM_WPULSE_S 0
/** HP_SYS_HP_MEM_WA : R/W; bitpos: [5:3]; default: 4;
* This field controls hp system memory WA parameter.
*/
#define HP_SYS_HP_MEM_WA 0x00000007U
#define HP_SYS_HP_MEM_WA_M (HP_SYS_HP_MEM_WA_V << HP_SYS_HP_MEM_WA_S)
#define HP_SYS_HP_MEM_WA_V 0x00000007U
#define HP_SYS_HP_MEM_WA_S 3
/** HP_SYS_HP_MEM_RA : R/W; bitpos: [7:6]; default: 0;
* This field controls hp system memory RA parameter.
*/
#define HP_SYS_HP_MEM_RA 0x00000003U
#define HP_SYS_HP_MEM_RA_M (HP_SYS_HP_MEM_RA_V << HP_SYS_HP_MEM_RA_S)
#define HP_SYS_HP_MEM_RA_V 0x00000003U
#define HP_SYS_HP_MEM_RA_S 6
/** HP_SYS_AUDIO_CODEC_SDADC_CNTL_REG register
* reserved
*/
#define HP_SYS_AUDIO_CODEC_SDADC_CNTL_REG (DR_REG_HP_SYS_BASE + 0x50)
/** HP_SYS_SDADC_PAD_EN_VNCP : R/W; bitpos: [0]; default: 0;
* reserved
*/
#define HP_SYS_SDADC_PAD_EN_VNCP (BIT(0))
#define HP_SYS_SDADC_PAD_EN_VNCP_M (HP_SYS_SDADC_PAD_EN_VNCP_V << HP_SYS_SDADC_PAD_EN_VNCP_S)
#define HP_SYS_SDADC_PAD_EN_VNCP_V 0x00000001U
#define HP_SYS_SDADC_PAD_EN_VNCP_S 0
/** HP_SYS_SDADC_PAD_FAST_CHG : R/W; bitpos: [1]; default: 0;
* reserved
*/
#define HP_SYS_SDADC_PAD_FAST_CHG (BIT(1))
#define HP_SYS_SDADC_PAD_FAST_CHG_M (HP_SYS_SDADC_PAD_FAST_CHG_V << HP_SYS_SDADC_PAD_FAST_CHG_S)
#define HP_SYS_SDADC_PAD_FAST_CHG_V 0x00000001U
#define HP_SYS_SDADC_PAD_FAST_CHG_S 1
/** HP_SYS_SDADC_PAD_EN_0V : R/W; bitpos: [2]; default: 0;
* reserved
*/
#define HP_SYS_SDADC_PAD_EN_0V (BIT(2))
#define HP_SYS_SDADC_PAD_EN_0V_M (HP_SYS_SDADC_PAD_EN_0V_V << HP_SYS_SDADC_PAD_EN_0V_S)
#define HP_SYS_SDADC_PAD_EN_0V_V 0x00000001U
#define HP_SYS_SDADC_PAD_EN_0V_S 2
/** HP_SYS_SDADC_EN_CHOPPER : R/W; bitpos: [3]; default: 1;
* reserved
*/
#define HP_SYS_SDADC_EN_CHOPPER (BIT(3))
#define HP_SYS_SDADC_EN_CHOPPER_M (HP_SYS_SDADC_EN_CHOPPER_V << HP_SYS_SDADC_EN_CHOPPER_S)
#define HP_SYS_SDADC_EN_CHOPPER_V 0x00000001U
#define HP_SYS_SDADC_EN_CHOPPER_S 3
/** HP_SYS_SDADC_EN_DEM : R/W; bitpos: [4]; default: 1;
* reserved
*/
#define HP_SYS_SDADC_EN_DEM (BIT(4))
#define HP_SYS_SDADC_EN_DEM_M (HP_SYS_SDADC_EN_DEM_V << HP_SYS_SDADC_EN_DEM_S)
#define HP_SYS_SDADC_EN_DEM_V 0x00000001U
#define HP_SYS_SDADC_EN_DEM_S 4
/** HP_SYS_SDADC_DREG_OA : R/W; bitpos: [7:5]; default: 3;
* reserved
*/
#define HP_SYS_SDADC_DREG_OA 0x00000007U
#define HP_SYS_SDADC_DREG_OA_M (HP_SYS_SDADC_DREG_OA_V << HP_SYS_SDADC_DREG_OA_S)
#define HP_SYS_SDADC_DREG_OA_V 0x00000007U
#define HP_SYS_SDADC_DREG_OA_S 5
/** HP_SYS_SDADC_DGAIN_INPUT : R/W; bitpos: [9:8]; default: 3;
* reserved
*/
#define HP_SYS_SDADC_DGAIN_INPUT 0x00000003U
#define HP_SYS_SDADC_DGAIN_INPUT_M (HP_SYS_SDADC_DGAIN_INPUT_V << HP_SYS_SDADC_DGAIN_INPUT_S)
#define HP_SYS_SDADC_DGAIN_INPUT_V 0x00000003U
#define HP_SYS_SDADC_DGAIN_INPUT_S 8
/** HP_SYS_SDADC_DCAP : R/W; bitpos: [14:10]; default: 12;
* reserved
*/
#define HP_SYS_SDADC_DCAP 0x0000001FU
#define HP_SYS_SDADC_DCAP_M (HP_SYS_SDADC_DCAP_V << HP_SYS_SDADC_DCAP_S)
#define HP_SYS_SDADC_DCAP_V 0x0000001FU
#define HP_SYS_SDADC_DCAP_S 10
/** HP_SYS_AUDIO_CODEC_DAC_L_CNTL_REG register
* reserved
*/
#define HP_SYS_AUDIO_CODEC_DAC_L_CNTL_REG (DR_REG_HP_SYS_BASE + 0x54)
/** HP_SYS_ENHANCE_L_AUDIO_DAC : R/W; bitpos: [0]; default: 0;
* reserved
*/
#define HP_SYS_ENHANCE_L_AUDIO_DAC (BIT(0))
#define HP_SYS_ENHANCE_L_AUDIO_DAC_M (HP_SYS_ENHANCE_L_AUDIO_DAC_V << HP_SYS_ENHANCE_L_AUDIO_DAC_S)
#define HP_SYS_ENHANCE_L_AUDIO_DAC_V 0x00000001U
#define HP_SYS_ENHANCE_L_AUDIO_DAC_S 0
/** HP_SYS_GAIN_L_AUDIO_DAC : R/W; bitpos: [5:1]; default: 19;
* reserved
*/
#define HP_SYS_GAIN_L_AUDIO_DAC 0x0000001FU
#define HP_SYS_GAIN_L_AUDIO_DAC_M (HP_SYS_GAIN_L_AUDIO_DAC_V << HP_SYS_GAIN_L_AUDIO_DAC_S)
#define HP_SYS_GAIN_L_AUDIO_DAC_V 0x0000001FU
#define HP_SYS_GAIN_L_AUDIO_DAC_S 1
/** HP_SYS_MUTE_L_AUDIO_DAC : R/W; bitpos: [6]; default: 0;
* reserved
*/
#define HP_SYS_MUTE_L_AUDIO_DAC (BIT(6))
#define HP_SYS_MUTE_L_AUDIO_DAC_M (HP_SYS_MUTE_L_AUDIO_DAC_V << HP_SYS_MUTE_L_AUDIO_DAC_S)
#define HP_SYS_MUTE_L_AUDIO_DAC_V 0x00000001U
#define HP_SYS_MUTE_L_AUDIO_DAC_S 6
/** HP_SYS_XPD_L_AUDIO_DAC : R/W; bitpos: [7]; default: 0;
* reserved
*/
#define HP_SYS_XPD_L_AUDIO_DAC (BIT(7))
#define HP_SYS_XPD_L_AUDIO_DAC_M (HP_SYS_XPD_L_AUDIO_DAC_V << HP_SYS_XPD_L_AUDIO_DAC_S)
#define HP_SYS_XPD_L_AUDIO_DAC_V 0x00000001U
#define HP_SYS_XPD_L_AUDIO_DAC_S 7
/** HP_SYS_AUDIO_CODEC_DAC_L_DIN_REG register
* reserved
*/
#define HP_SYS_AUDIO_CODEC_DAC_L_DIN_REG (DR_REG_HP_SYS_BASE + 0x58)
/** HP_SYS_DAC_DIN_L : R/W; bitpos: [21:0]; default: 0;
* reserved
*/
#define HP_SYS_DAC_DIN_L 0x003FFFFFU
#define HP_SYS_DAC_DIN_L_M (HP_SYS_DAC_DIN_L_V << HP_SYS_DAC_DIN_L_S)
#define HP_SYS_DAC_DIN_L_V 0x003FFFFFU
#define HP_SYS_DAC_DIN_L_S 0
/** HP_SYS_AUDIO_CODEC_DAC_R_CNTL_REG register
* reserved
*/
#define HP_SYS_AUDIO_CODEC_DAC_R_CNTL_REG (DR_REG_HP_SYS_BASE + 0x5c)
/** HP_SYS_ENHANCE_R_AUDIO_DAC : R/W; bitpos: [0]; default: 0;
* reserved
*/
#define HP_SYS_ENHANCE_R_AUDIO_DAC (BIT(0))
#define HP_SYS_ENHANCE_R_AUDIO_DAC_M (HP_SYS_ENHANCE_R_AUDIO_DAC_V << HP_SYS_ENHANCE_R_AUDIO_DAC_S)
#define HP_SYS_ENHANCE_R_AUDIO_DAC_V 0x00000001U
#define HP_SYS_ENHANCE_R_AUDIO_DAC_S 0
/** HP_SYS_GAIN_R_AUDIO_DAC : R/W; bitpos: [5:1]; default: 19;
* reserved
*/
#define HP_SYS_GAIN_R_AUDIO_DAC 0x0000001FU
#define HP_SYS_GAIN_R_AUDIO_DAC_M (HP_SYS_GAIN_R_AUDIO_DAC_V << HP_SYS_GAIN_R_AUDIO_DAC_S)
#define HP_SYS_GAIN_R_AUDIO_DAC_V 0x0000001FU
#define HP_SYS_GAIN_R_AUDIO_DAC_S 1
/** HP_SYS_MUTE_R_AUDIO_DAC : R/W; bitpos: [6]; default: 0;
* reserved
*/
#define HP_SYS_MUTE_R_AUDIO_DAC (BIT(6))
#define HP_SYS_MUTE_R_AUDIO_DAC_M (HP_SYS_MUTE_R_AUDIO_DAC_V << HP_SYS_MUTE_R_AUDIO_DAC_S)
#define HP_SYS_MUTE_R_AUDIO_DAC_V 0x00000001U
#define HP_SYS_MUTE_R_AUDIO_DAC_S 6
/** HP_SYS_XPD_R_AUDIO_DAC : R/W; bitpos: [7]; default: 0;
* reserved
*/
#define HP_SYS_XPD_R_AUDIO_DAC (BIT(7))
#define HP_SYS_XPD_R_AUDIO_DAC_M (HP_SYS_XPD_R_AUDIO_DAC_V << HP_SYS_XPD_R_AUDIO_DAC_S)
#define HP_SYS_XPD_R_AUDIO_DAC_V 0x00000001U
#define HP_SYS_XPD_R_AUDIO_DAC_S 7
/** HP_SYS_AUDIO_CODEC_DAC_R_DIN_REG register
* reserved
*/
#define HP_SYS_AUDIO_CODEC_DAC_R_DIN_REG (DR_REG_HP_SYS_BASE + 0x60)
/** HP_SYS_DAC_DIN_R : R/W; bitpos: [21:0]; default: 0;
* reserved
*/
#define HP_SYS_DAC_DIN_R 0x003FFFFFU
#define HP_SYS_DAC_DIN_R_M (HP_SYS_DAC_DIN_R_V << HP_SYS_DAC_DIN_R_S)
#define HP_SYS_DAC_DIN_R_V 0x003FFFFFU
#define HP_SYS_DAC_DIN_R_S 0
/** HP_SYS_AUDIO_CODEC_PLL_CNTL_REG register
* reserved
*/
#define HP_SYS_AUDIO_CODEC_PLL_CNTL_REG (DR_REG_HP_SYS_BASE + 0x64)
/** HP_SYS_CAL_STOP_PLLA : R/W; bitpos: [0]; default: 0;
* reserved
*/
#define HP_SYS_CAL_STOP_PLLA (BIT(0))
#define HP_SYS_CAL_STOP_PLLA_M (HP_SYS_CAL_STOP_PLLA_V << HP_SYS_CAL_STOP_PLLA_S)
#define HP_SYS_CAL_STOP_PLLA_V 0x00000001U
#define HP_SYS_CAL_STOP_PLLA_S 0
/** HP_SYS_CAL_END_PLLA : RO; bitpos: [1]; default: 0;
* reserved
*/
#define HP_SYS_CAL_END_PLLA (BIT(1))
#define HP_SYS_CAL_END_PLLA_M (HP_SYS_CAL_END_PLLA_V << HP_SYS_CAL_END_PLLA_S)
#define HP_SYS_CAL_END_PLLA_V 0x00000001U
#define HP_SYS_CAL_END_PLLA_S 1
/** HP_SYS_AUDIO_CODEC_DATA_MODE_CNTL_REG register
* reserved
*/
#define HP_SYS_AUDIO_CODEC_DATA_MODE_CNTL_REG (DR_REG_HP_SYS_BASE + 0x68)
/** HP_SYS_AUDIO_ADC_MODE : R/W; bitpos: [1:0]; default: 0;
* reserved
*/
#define HP_SYS_AUDIO_ADC_MODE 0x00000003U
#define HP_SYS_AUDIO_ADC_MODE_M (HP_SYS_AUDIO_ADC_MODE_V << HP_SYS_AUDIO_ADC_MODE_S)
#define HP_SYS_AUDIO_ADC_MODE_V 0x00000003U
#define HP_SYS_AUDIO_ADC_MODE_S 0
/** HP_SYS_AUDIO_DAC_DSM_MODE_R : R/W; bitpos: [3:2]; default: 0;
* reserved
*/
#define HP_SYS_AUDIO_DAC_DSM_MODE_R 0x00000003U
#define HP_SYS_AUDIO_DAC_DSM_MODE_R_M (HP_SYS_AUDIO_DAC_DSM_MODE_R_V << HP_SYS_AUDIO_DAC_DSM_MODE_R_S)
#define HP_SYS_AUDIO_DAC_DSM_MODE_R_V 0x00000003U
#define HP_SYS_AUDIO_DAC_DSM_MODE_R_S 2
/** HP_SYS_AUDIO_DAC_DSM_MODE_L : R/W; bitpos: [5:4]; default: 0;
* reserved
*/
#define HP_SYS_AUDIO_DAC_DSM_MODE_L 0x00000003U
#define HP_SYS_AUDIO_DAC_DSM_MODE_L_M (HP_SYS_AUDIO_DAC_DSM_MODE_L_V << HP_SYS_AUDIO_DAC_DSM_MODE_L_S)
#define HP_SYS_AUDIO_DAC_DSM_MODE_L_V 0x00000003U
#define HP_SYS_AUDIO_DAC_DSM_MODE_L_S 4
/** HP_SYS_SPROM_CTRL_REG register
* reserved
*/
@ -419,6 +700,73 @@ extern "C" {
#define HP_SYS_ADC_CK_DATA_OE_V 0x00000001U
#define HP_SYS_ADC_CK_DATA_OE_S 15
/** HP_SYS_RND_ECO_REG register
* redcy eco register.
*/
#define HP_SYS_RND_ECO_REG (DR_REG_HP_SYS_BASE + 0x3e0)
/** HP_SYS_REDCY_ENA : W/R; bitpos: [0]; default: 0;
* Only reserved for ECO.
*/
#define HP_SYS_REDCY_ENA (BIT(0))
#define HP_SYS_REDCY_ENA_M (HP_SYS_REDCY_ENA_V << HP_SYS_REDCY_ENA_S)
#define HP_SYS_REDCY_ENA_V 0x00000001U
#define HP_SYS_REDCY_ENA_S 0
/** HP_SYS_REDCY_RESULT : RO; bitpos: [1]; default: 0;
* Only reserved for ECO.
*/
#define HP_SYS_REDCY_RESULT (BIT(1))
#define HP_SYS_REDCY_RESULT_M (HP_SYS_REDCY_RESULT_V << HP_SYS_REDCY_RESULT_S)
#define HP_SYS_REDCY_RESULT_V 0x00000001U
#define HP_SYS_REDCY_RESULT_S 1
/** HP_SYS_RND_ECO_LOW_REG register
* redcy eco low register.
*/
#define HP_SYS_RND_ECO_LOW_REG (DR_REG_HP_SYS_BASE + 0x3e4)
/** HP_SYS_REDCY_LOW : W/R; bitpos: [31:0]; default: 0;
* Only reserved for ECO.
*/
#define HP_SYS_REDCY_LOW 0xFFFFFFFFU
#define HP_SYS_REDCY_LOW_M (HP_SYS_REDCY_LOW_V << HP_SYS_REDCY_LOW_S)
#define HP_SYS_REDCY_LOW_V 0xFFFFFFFFU
#define HP_SYS_REDCY_LOW_S 0
/** HP_SYS_RND_ECO_HIGH_REG register
* redcy eco high register.
*/
#define HP_SYS_RND_ECO_HIGH_REG (DR_REG_HP_SYS_BASE + 0x3e8)
/** HP_SYS_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295;
* Only reserved for ECO.
*/
#define HP_SYS_REDCY_HIGH 0xFFFFFFFFU
#define HP_SYS_REDCY_HIGH_M (HP_SYS_REDCY_HIGH_V << HP_SYS_REDCY_HIGH_S)
#define HP_SYS_REDCY_HIGH_V 0xFFFFFFFFU
#define HP_SYS_REDCY_HIGH_S 0
/** HP_SYS_DEBUG_REG register
* HP-SYSTEM debug register
*/
#define HP_SYS_DEBUG_REG (DR_REG_HP_SYS_BASE + 0x3f4)
/** HP_SYS_FPGA_DEBUG : R/W; bitpos: [0]; default: 1;
* Reserved
*/
#define HP_SYS_FPGA_DEBUG (BIT(0))
#define HP_SYS_FPGA_DEBUG_M (HP_SYS_FPGA_DEBUG_V << HP_SYS_FPGA_DEBUG_S)
#define HP_SYS_FPGA_DEBUG_V 0x00000001U
#define HP_SYS_FPGA_DEBUG_S 0
/** HP_SYS_CLOCK_GATE_REG register
* HP-SYSTEM clock gating configure register
*/
#define HP_SYS_CLOCK_GATE_REG (DR_REG_HP_SYS_BASE + 0x3f8)
/** HP_SYS_CLK_EN : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to force on clock gating.
*/
#define HP_SYS_CLK_EN (BIT(0))
#define HP_SYS_CLK_EN_M (HP_SYS_CLK_EN_V << HP_SYS_CLK_EN_S)
#define HP_SYS_CLK_EN_V 0x00000001U
#define HP_SYS_CLK_EN_S 0
/** HP_SYS_DATE_REG register
* Date register.
*/

346
components/soc/esp32c5/beta3/include/soc/hp_system_struct.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -42,7 +42,11 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0:8;
/** cache_usage : HRO; bitpos: [0]; default: 0;
* reserved
*/
uint32_t cache_usage:1;
uint32_t reserved_1:7;
/** sram_usage : R/W; bitpos: [11:8]; default: 0;
* 0: cpu use hp-memory. 1:mac-dump accessing hp-memory.
*/
@ -66,7 +70,7 @@ typedef union {
* 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
* the number, the stronger the ability to resist DPA attacks and the higher the
* security level, but it will increase the computational overhead of the hardware
* crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0.
* crypto-accelerators. Only available if HP_SYS_SEC_DPA_CFG_SEL is 0.
*/
uint32_t sec_dpa_level:2;
/** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;
@ -143,6 +147,190 @@ typedef union {
uint32_t val;
} hp_sys_core_debug_runstall_conf_reg_t;
/** Type of mem_test_conf register
* MEM_TEST configuration register
*/
typedef union {
struct {
/** hp_mem_wpulse : R/W; bitpos: [2:0]; default: 0;
* This field controls hp system memory WPULSE parameter.
*/
uint32_t hp_mem_wpulse:3;
/** hp_mem_wa : R/W; bitpos: [5:3]; default: 4;
* This field controls hp system memory WA parameter.
*/
uint32_t hp_mem_wa:3;
/** hp_mem_ra : R/W; bitpos: [7:6]; default: 0;
* This field controls hp system memory RA parameter.
*/
uint32_t hp_mem_ra:2;
uint32_t reserved_8:24;
};
uint32_t val;
} hp_sys_mem_test_conf_reg_t;
/** Type of audio_codec_sdadc_cntl register
* reserved
*/
typedef union {
struct {
/** sdadc_pad_en_vncp : R/W; bitpos: [0]; default: 0;
* reserved
*/
uint32_t sdadc_pad_en_vncp:1;
/** sdadc_pad_fast_chg : R/W; bitpos: [1]; default: 0;
* reserved
*/
uint32_t sdadc_pad_fast_chg:1;
/** sdadc_pad_en_0v : R/W; bitpos: [2]; default: 0;
* reserved
*/
uint32_t sdadc_pad_en_0v:1;
/** sdadc_en_chopper : R/W; bitpos: [3]; default: 1;
* reserved
*/
uint32_t sdadc_en_chopper:1;
/** sdadc_en_dem : R/W; bitpos: [4]; default: 1;
* reserved
*/
uint32_t sdadc_en_dem:1;
/** sdadc_dreg_oa : R/W; bitpos: [7:5]; default: 3;
* reserved
*/
uint32_t sdadc_dreg_oa:3;
/** sdadc_dgain_input : R/W; bitpos: [9:8]; default: 3;
* reserved
*/
uint32_t sdadc_dgain_input:2;
/** sdadc_dcap : R/W; bitpos: [14:10]; default: 12;
* reserved
*/
uint32_t sdadc_dcap:5;
uint32_t reserved_15:17;
};
uint32_t val;
} hp_sys_audio_codec_sdadc_cntl_reg_t;
/** Type of audio_codec_dac_l_cntl register
* reserved
*/
typedef union {
struct {
/** enhance_l_audio_dac : R/W; bitpos: [0]; default: 0;
* reserved
*/
uint32_t enhance_l_audio_dac:1;
/** gain_l_audio_dac : R/W; bitpos: [5:1]; default: 19;
* reserved
*/
uint32_t gain_l_audio_dac:5;
/** mute_l_audio_dac : R/W; bitpos: [6]; default: 0;
* reserved
*/
uint32_t mute_l_audio_dac:1;
/** xpd_l_audio_dac : R/W; bitpos: [7]; default: 0;
* reserved
*/
uint32_t xpd_l_audio_dac:1;
uint32_t reserved_8:24;
};
uint32_t val;
} hp_sys_audio_codec_dac_l_cntl_reg_t;
/** Type of audio_codec_dac_l_din register
* reserved
*/
typedef union {
struct {
/** dac_din_l : R/W; bitpos: [21:0]; default: 0;
* reserved
*/
uint32_t dac_din_l:22;
uint32_t reserved_22:10;
};
uint32_t val;
} hp_sys_audio_codec_dac_l_din_reg_t;
/** Type of audio_codec_dac_r_cntl register
* reserved
*/
typedef union {
struct {
/** enhance_r_audio_dac : R/W; bitpos: [0]; default: 0;
* reserved
*/
uint32_t enhance_r_audio_dac:1;
/** gain_r_audio_dac : R/W; bitpos: [5:1]; default: 19;
* reserved
*/
uint32_t gain_r_audio_dac:5;
/** mute_r_audio_dac : R/W; bitpos: [6]; default: 0;
* reserved
*/
uint32_t mute_r_audio_dac:1;
/** xpd_r_audio_dac : R/W; bitpos: [7]; default: 0;
* reserved
*/
uint32_t xpd_r_audio_dac:1;
uint32_t reserved_8:24;
};
uint32_t val;
} hp_sys_audio_codec_dac_r_cntl_reg_t;
/** Type of audio_codec_dac_r_din register
* reserved
*/
typedef union {
struct {
/** dac_din_r : R/W; bitpos: [21:0]; default: 0;
* reserved
*/
uint32_t dac_din_r:22;
uint32_t reserved_22:10;
};
uint32_t val;
} hp_sys_audio_codec_dac_r_din_reg_t;
/** Type of audio_codec_pll_cntl register
* reserved
*/
typedef union {
struct {
/** cal_stop_plla : R/W; bitpos: [0]; default: 0;
* reserved
*/
uint32_t cal_stop_plla:1;
/** cal_end_plla : RO; bitpos: [1]; default: 0;
* reserved
*/
uint32_t cal_end_plla:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_sys_audio_codec_pll_cntl_reg_t;
/** Type of audio_codec_data_mode_cntl register
* reserved
*/
typedef union {
struct {
/** audio_adc_mode : R/W; bitpos: [1:0]; default: 0;
* reserved
*/
uint32_t audio_adc_mode:2;
/** audio_dac_dsm_mode_r : R/W; bitpos: [3:2]; default: 0;
* reserved
*/
uint32_t audio_dac_dsm_mode_r:2;
/** audio_dac_dsm_mode_l : R/W; bitpos: [5:4]; default: 0;
* reserved
*/
uint32_t audio_dac_dsm_mode_l:2;
uint32_t reserved_6:26;
};
uint32_t val;
} hp_sys_audio_codec_data_mode_cntl_reg_t;
/** Type of sprom_ctrl register
* reserved
*/
@ -269,6 +457,20 @@ typedef union {
uint32_t val;
} hp_sys_audio_codex_ctrl0_reg_t;
/** Type of clock_gate register
* HP-SYSTEM clock gating configure register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Set this bit as 1 to force on clock gating.
*/
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_sys_clock_gate_reg_t;
/** Group: Timeout Register */
/** Type of cpu_peri_timeout_conf register
@ -374,6 +576,119 @@ typedef union {
uint32_t val;
} hp_sys_hp_peri_timeout_uid_reg_t;
/** Type of modem_peri_timeout_conf register
* MODEM_PERI_TIMEOUT configuration register
*/
typedef union {
struct {
/** modem_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
* Set the timeout threshold for bus access, corresponding to the number of clock
* cycles of the clock domain.
*/
uint32_t modem_peri_timeout_thres:16;
/** modem_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
* Set this bit as 1 to clear timeout interrupt
*/
uint32_t modem_peri_timeout_int_clear:1;
/** modem_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
* Set this bit as 1 to enable timeout protection for accessing modem registers
*/
uint32_t modem_peri_timeout_protect_en:1;
uint32_t reserved_18:14;
};
uint32_t val;
} hp_sys_modem_peri_timeout_conf_reg_t;
/** Type of modem_peri_timeout_addr register
* MODEM_PERI_TIMEOUT_ADDR register
*/
typedef union {
struct {
/** modem_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
* Record the address information of abnormal access
*/
uint32_t modem_peri_timeout_addr:32;
};
uint32_t val;
} hp_sys_modem_peri_timeout_addr_reg_t;
/** Type of modem_peri_timeout_uid register
* MODEM_PERI_TIMEOUT_UID register
*/
typedef union {
struct {
/** modem_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
* will be cleared after the interrupt is cleared.
*/
uint32_t modem_peri_timeout_uid:7;
uint32_t reserved_7:25;
};
uint32_t val;
} hp_sys_modem_peri_timeout_uid_reg_t;
/** Group: Redcy ECO Registers */
/** Type of rnd_eco register
* redcy eco register.
*/
typedef union {
struct {
/** redcy_ena : W/R; bitpos: [0]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_ena:1;
/** redcy_result : RO; bitpos: [1]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_result:1;
uint32_t reserved_2:30;
};
uint32_t val;
} hp_sys_rnd_eco_reg_t;
/** Type of rnd_eco_low register
* redcy eco low register.
*/
typedef union {
struct {
/** redcy_low : W/R; bitpos: [31:0]; default: 0;
* Only reserved for ECO.
*/
uint32_t redcy_low:32;
};
uint32_t val;
} hp_sys_rnd_eco_low_reg_t;
/** Type of rnd_eco_high register
* redcy eco high register.
*/
typedef union {
struct {
/** redcy_high : W/R; bitpos: [31:0]; default: 4294967295;
* Only reserved for ECO.
*/
uint32_t redcy_high:32;
};
uint32_t val;
} hp_sys_rnd_eco_high_reg_t;
/** Group: Debug Register */
/** Type of debug register
* HP-SYSTEM debug register
*/
typedef union {
struct {
/** fpga_debug : R/W; bitpos: [0]; default: 1;
* Reserved
*/
uint32_t fpga_debug:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hp_sys_debug_reg_t;
/** Group: Version Register */
/** Type of date register
@ -391,7 +706,7 @@ typedef union {
} hp_sys_date_reg_t;
typedef struct hp_sys_dev_t {
typedef struct {
volatile hp_sys_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control;
volatile hp_sys_sram_usage_conf_reg_t sram_usage_conf;
volatile hp_sys_sec_dpa_conf_reg_t sec_dpa_conf;
@ -401,19 +716,36 @@ typedef struct hp_sys_dev_t {
volatile hp_sys_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf;
volatile hp_sys_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr;
volatile hp_sys_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid;
uint32_t reserved_024[3];
volatile hp_sys_modem_peri_timeout_conf_reg_t modem_peri_timeout_conf;
volatile hp_sys_modem_peri_timeout_addr_reg_t modem_peri_timeout_addr;
volatile hp_sys_modem_peri_timeout_uid_reg_t modem_peri_timeout_uid;
volatile hp_sys_sdio_ctrl_reg_t sdio_ctrl;
uint32_t reserved_034;
volatile hp_sys_rom_table_lock_reg_t rom_table_lock;
volatile hp_sys_rom_table_reg_t rom_table;
volatile hp_sys_core_debug_runstall_conf_reg_t core_debug_runstall_conf;
uint32_t reserved_044[11];
volatile hp_sys_mem_test_conf_reg_t mem_test_conf;
uint32_t reserved_048[2];
volatile hp_sys_audio_codec_sdadc_cntl_reg_t audio_codec_sdadc_cntl;
volatile hp_sys_audio_codec_dac_l_cntl_reg_t audio_codec_dac_l_cntl;
volatile hp_sys_audio_codec_dac_l_din_reg_t audio_codec_dac_l_din;
volatile hp_sys_audio_codec_dac_r_cntl_reg_t audio_codec_dac_r_cntl;
volatile hp_sys_audio_codec_dac_r_din_reg_t audio_codec_dac_r_din;
volatile hp_sys_audio_codec_pll_cntl_reg_t audio_codec_pll_cntl;
volatile hp_sys_audio_codec_data_mode_cntl_reg_t audio_codec_data_mode_cntl;
uint32_t reserved_06c;
volatile hp_sys_sprom_ctrl_reg_t sprom_ctrl;
volatile hp_sys_spram_ctrl_reg_t spram_ctrl;
volatile hp_sys_sprf_ctrl_reg_t sprf_ctrl;
volatile hp_sys_sdprf_ctrl_reg_t sdprf_ctrl;
volatile hp_sys_audio_codex_ctrl0_reg_t audio_codex_ctrl0;
uint32_t reserved_084[222];
uint32_t reserved_084[215];
volatile hp_sys_rnd_eco_reg_t rnd_eco;
volatile hp_sys_rnd_eco_low_reg_t rnd_eco_low;
volatile hp_sys_rnd_eco_high_reg_t rnd_eco_high;
uint32_t reserved_3ec[2];
volatile hp_sys_debug_reg_t debug;
volatile hp_sys_clock_gate_reg_t clock_gate;
volatile hp_sys_date_reg_t date;
} hp_sys_dev_t;

2
components/soc/esp32c5/beta3/include/soc/reg_base.h
View File

@ -57,7 +57,7 @@
#define DR_REG_GPIO_BASE 0x60091000
#define DR_REG_MEM_MONITOR_BASE 0x60092000
#define DR_REG_PAU_BASE 0x60093000
#define DR_REG_HP_SYSTEM_BASE 0x60095000
#define DR_REG_HP_SYS_BASE 0x60095000
#define DR_REG_PCR_BASE 0x60096000
#define DR_REG_TEE_BASE 0x60098000
#define DR_REG_HP_APM_BASE 0x60099000

12
components/soc/esp32c5/beta3/include/soc/soc_caps.h
View File

@ -60,9 +60,9 @@
// #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32C5] IDF-8647
// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8614, IDF-8615
#define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667
// #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640
#define SOC_PAU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638
#define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8636
#define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640
#define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638
#define SOC_LP_PERIPHERALS_SUPPORTED 1
// #define SOC_LP_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8634
#define SOC_ULP_SUPPORTED 1
@ -76,7 +76,7 @@
// #define SOC_ECDSA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8618
// #define SOC_KEY_MANAGER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8621
// #define SOC_HUK_SUPPORTED 1 // TODO: [ESP32C5] IDF-8617
// #define SOC_LIGHT_SLEEP_SUPPORTED 1 // TODO: [ESP32C5] IDF-8640
#define SOC_LIGHT_SLEEP_SUPPORTED 1
// #define SOC_DEEP_SLEEP_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638
#define SOC_MODEM_CLOCK_SUPPORTED 1 // TODO: [ESP32C5] IDF-8845 need check, it is opened because pll has been used on beta3
#define SOC_BT_SUPPORTED 1
@ -254,6 +254,8 @@
#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1)
// #define SOC_I2C_SUPPORT_SLEEP_RETENTION (1) // TODO: IDF-9693
/*-------------------------- LP_I2C CAPS -------------------------------------*/
// ESP32-C5 has 1 LP_I2C
// #define SOC_LP_I2C_NUM (1U)
@ -519,7 +521,7 @@
#define SOC_PM_SUPPORT_RC32K_PD (1)
#define SOC_PM_SUPPORT_RC_FAST_PD (1)
#define SOC_PM_SUPPORT_VDDSDIO_PD (1)
// #define SOC_PM_SUPPORT_TOP_PD (1) // TODO: IDF-8643
#define SOC_PM_SUPPORT_TOP_PD (1)
#define SOC_PM_SUPPORT_HP_AON_PD (1)
// #define SOC_PM_SUPPORT_MAC_BB_PD (1)
#define SOC_PM_SUPPORT_RTC_PERIPH_PD (1)
@ -531,7 +533,7 @@
#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */
#define SOC_PM_CPU_RETENTION_BY_SW (1)
// #define SOC_PM_MODEM_RETENTION_BY_REGDMA (1)
#define SOC_PM_MODEM_RETENTION_BY_REGDMA (1)
// #define SOC_PM_RETENTION_HAS_CLOCK_BUG (1)
#define SOC_PM_PAU_LINK_NUM (4)

18
components/soc/esp32c5/beta3/include/soc/system_periph_retention.h
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@ -15,10 +15,10 @@ extern "C"
{
#endif
#if SOC_PAU_SUPPORTED // TODO: [ESP32C5] IDF-8640
#if SOC_PAU_SUPPORTED
/**
* @brief Provide access to interrupt matrix configuration registers retention
* context defination.
* context definition.
*
* This is an internal function of the sleep retention driver, and is not
* useful for external use.
@ -28,7 +28,7 @@ extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTIO
/**
* @brief Provide access to hp_system configuration registers retention
* context defination.
* context definition.
*
* This is an internal function of the sleep retention driver, and is not
* useful for external use.
@ -38,7 +38,7 @@ extern const regdma_entries_config_t hp_system_regs_retention[HP_SYSTEM_RETENTIO
/**
* @brief Provide access to TEE_APM configuration registers retention
* context defination.
* context definition.
*
* This is an internal function of the sleep retention driver, and is not
* useful for external use.
@ -50,7 +50,7 @@ extern const regdma_entries_config_t tee_apm_highpri_regs_retention[TEE_APM_HIGH
/**
* @brief Provide access to uart configuration registers retention
* context defination.
* context definition.
*
* This is an internal function of the sleep retention driver, and is not
* useful for external use.
@ -60,7 +60,7 @@ extern const regdma_entries_config_t uart_regs_retention[UART_RETENTION_LINK_LEN
/**
* @brief Provide access to timer group configuration registers retention
* context defination.
* context definition.
*
* This is an internal function of the sleep retention driver, and is not
* useful for external use.
@ -70,7 +70,7 @@ extern const regdma_entries_config_t tg_regs_retention[TIMG_RETENTION_LINK_LEN];
/**
* @brief Provide access to IOMUX configuration registers retention
* context defination.
* context definition.
*
* This is an internal function of the sleep retention driver, and is not
* useful for external use.
@ -80,7 +80,7 @@ extern const regdma_entries_config_t iomux_regs_retention[IOMUX_RETENTION_LINK_L
/**
* @brief Provide access to spimem configuration registers retention
* context defination.
* context definition.
*
* This is an internal function of the sleep retention driver, and is not
* useful for external use.
@ -90,7 +90,7 @@ extern const regdma_entries_config_t spimem_regs_retention[SPIMEM_RETENTION_LINK
/**
* @brief Provide access to systimer configuration registers retention
* context defination.
* context definition.
*
* This is an internal function of the sleep retention driver, and is not
* useful for external use.

27
components/soc/esp32c5/beta3/system_retention_periph.c
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@ -19,16 +19,16 @@
#include "soc/interrupt_matrix_reg.h"
/* Interrupt Matrix Registers Context */
#define N_REGS_INTR_MATRIX() (((INTMTX_CORE0_CLOCK_GATE_REG - DR_REG_INTERRUPT_MATRIX_BASE) / 4) + 1)
#define N_REGS_INTR_MATRIX() (((INTERRUPT_CORE0_CLOCK_GATE_REG - DR_REG_INTERRUPT_MATRIX_BASE) / 4) + 1)
const regdma_entries_config_t intr_matrix_regs_retention[] = {
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0), DR_REG_INTERRUPT_MATRIX_BASE, DR_REG_INTERRUPT_MATRIX_BASE, N_REGS_INTR_MATRIX(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* intr matrix */
};
_Static_assert(ARRAY_SIZE(intr_matrix_regs_retention) == INT_MTX_RETENTION_LINK_LEN, "Inconsistent INT_MTX retention link length definitions");
/* HP System Registers Context */
#define N_REGS_HP_SYSTEM() (((HP_SYSTEM_MEM_TEST_CONF_REG - DR_REG_HP_SYSTEM_BASE) / 4) + 1)
#define N_REGS_HP_SYSTEM() (((HP_SYS_MEM_TEST_CONF_REG - DR_REG_HP_SYS_BASE) / 4) + 1)
const regdma_entries_config_t hp_system_regs_retention[] = {
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_HPSYS_LINK(0), DR_REG_HP_SYSTEM_BASE, DR_REG_HP_SYSTEM_BASE, N_REGS_HP_SYSTEM(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* hp system */
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_HPSYS_LINK(0), DR_REG_HP_SYS_BASE, DR_REG_HP_SYS_BASE, N_REGS_HP_SYSTEM(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* hp system */
};
_Static_assert(ARRAY_SIZE(hp_system_regs_retention) == HP_SYSTEM_RETENTION_LINK_LEN, "Inconsistent HP_SYSTEM retention link length definitions");
@ -70,11 +70,10 @@ const regdma_entries_config_t tg_regs_retention[] = {
_Static_assert(ARRAY_SIZE(tg_regs_retention) == TIMG_RETENTION_LINK_LEN, "Inconsistent Timergroup retention link length definitions");
/* IO MUX Registers Context */
// TODO: [ESP32C5] IDF-8638, IDF-8640
#define N_REGS_IOMUX_0() (((PERIPHS_IO_MUX_SPID_U - REG_IO_MUX_BASE) / 4) + 1)
#define N_REGS_IOMUX_1() (((GPIO_FUNC34_OUT_SEL_CFG_REG - GPIO_FUNC0_OUT_SEL_CFG_REG) / 4) + 1)
#define N_REGS_IOMUX_0() (((IO_MUX_GPIO26_REG - REG_IO_MUX_BASE) / 4) + 1)
#define N_REGS_IOMUX_1() (((GPIO_FUNC30_OUT_SEL_CFG_REG - GPIO_FUNC0_OUT_SEL_CFG_REG) / 4) + 1)
#define N_REGS_IOMUX_2() (((GPIO_FUNC124_IN_SEL_CFG_REG - GPIO_STATUS_NEXT_REG) / 4) + 1)
#define N_REGS_IOMUX_3() (((GPIO_PIN34_REG - DR_REG_GPIO_BASE) / 4) + 1)
#define N_REGS_IOMUX_3() (((GPIO_PIN30_REG - DR_REG_GPIO_BASE) / 4) + 1)
const regdma_entries_config_t iomux_regs_retention[] = {
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x00), REG_IO_MUX_BASE, REG_IO_MUX_BASE, N_REGS_IOMUX_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* io_mux */
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x01), GPIO_FUNC0_OUT_SEL_CFG_REG, GPIO_FUNC0_OUT_SEL_CFG_REG, N_REGS_IOMUX_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
@ -83,25 +82,25 @@ const regdma_entries_config_t iomux_regs_retention[] = {
};
_Static_assert(ARRAY_SIZE(iomux_regs_retention) == IOMUX_RETENTION_LINK_LEN, "Inconsistent IOMUX retention link length definitions");
/* Mememory SPI Registers Context */
#define N_REGS_SPI1_MEM_0() (((SPI_MEM_SPI_SMEM_DDR_REG(1) - REG_SPI_MEM_BASE(1)) / 4) + 1)
#define N_REGS_SPI1_MEM_1() (((SPI_MEM_SPI_SMEM_AC_REG(1) - SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(1)) / 4) + 1)
/* Memory SPI Registers Context */
#define N_REGS_SPI1_MEM_0() (((SPI_SMEM_DDR_REG(1) - REG_SPI_MEM_BASE(1)) / 4) + 1)
#define N_REGS_SPI1_MEM_1() (((SPI_SMEM_AC_REG(1) - SPI_FMEM_PMS0_ATTR_REG(1)) / 4) + 1)
#define N_REGS_SPI1_MEM_2() (1)
#define N_REGS_SPI1_MEM_3() (((SPI_MEM_DATE_REG(1) - SPI_MEM_MMU_POWER_CTRL_REG(1)) / 4) + 1)
#define N_REGS_SPI0_MEM_0() (((SPI_MEM_SPI_SMEM_DDR_REG(0) - REG_SPI_MEM_BASE(0)) / 4) + 1)
#define N_REGS_SPI0_MEM_1() (((SPI_MEM_SPI_SMEM_AC_REG(0) - SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(0)) / 4) + 1)
#define N_REGS_SPI0_MEM_0() (((SPI_SMEM_DDR_REG(0) - REG_SPI_MEM_BASE(0)) / 4) + 1)
#define N_REGS_SPI0_MEM_1() (((SPI_SMEM_AC_REG(0) - SPI_FMEM_PMS0_ATTR_REG(0)) / 4) + 1)
#define N_REGS_SPI0_MEM_2() (1)
#define N_REGS_SPI0_MEM_3() (((SPI_MEM_DATE_REG(0) - SPI_MEM_MMU_POWER_CTRL_REG(0)) / 4) + 1)
const regdma_entries_config_t spimem_regs_retention[] = {
/* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x00), REG_SPI_MEM_BASE(1), REG_SPI_MEM_BASE(1), N_REGS_SPI1_MEM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* spi1_mem */
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x01), SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(1), SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(1), N_REGS_SPI1_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x01), SPI_FMEM_PMS0_ATTR_REG(1), SPI_FMEM_PMS0_ATTR_REG(1), N_REGS_SPI1_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x02), SPI_MEM_CLOCK_GATE_REG(1), SPI_MEM_CLOCK_GATE_REG(1), N_REGS_SPI1_MEM_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x03), SPI_MEM_MMU_POWER_CTRL_REG(1), SPI_MEM_MMU_POWER_CTRL_REG(1), N_REGS_SPI1_MEM_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
/* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x04), REG_SPI_MEM_BASE(0), REG_SPI_MEM_BASE(0), N_REGS_SPI0_MEM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* spi0_mem */
[5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x05), SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(0), SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(0), N_REGS_SPI0_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x05), SPI_FMEM_PMS0_ATTR_REG(0), SPI_FMEM_PMS0_ATTR_REG(0), N_REGS_SPI0_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x06), SPI_MEM_CLOCK_GATE_REG(0), SPI_MEM_CLOCK_GATE_REG(0), N_REGS_SPI0_MEM_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x07), SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_POWER_CTRL_REG(0), N_REGS_SPI0_MEM_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }
};

6
components/soc/esp32c5/mp/include/soc/soc_caps.h
View File

@ -57,9 +57,9 @@
// #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32C5] IDF-8647
// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8614
// #define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667
// #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640
// #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638
// #define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8636
// #define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640
// #define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638
// #define SOC_LP_PERIPHERALS_SUPPORTED 1 // TODO: [ESP32C5] IDF-8695, IDF-8723, IDF-8719
// #define SOC_LP_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8634
// #define SOC_ULP_LP_UART_SUPPORTED 1 // TODO: [ESP32C5] IDF-8633
@ -245,6 +245,8 @@
// #define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1)
// #define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1)
// #define SOC_I2C_SUPPORT_SLEEP_RETENTION (1) // TODO: IDF-9693
/*-------------------------- LP_I2C CAPS -------------------------------------*/
// ESP32-C5 has 1 LP_I2C
// #define SOC_LP_I2C_NUM (1U)

2
components/soc/esp32p4/include/soc/soc_caps.h
View File

@ -273,6 +273,8 @@
#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1)
#define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1)
// #define SOC_I2C_SUPPORT_SLEEP_RETENTION (1) // TODO: IDF-9353
/*-------------------------- LP_I2C CAPS -------------------------------------*/
// ESP32-P4 has 1 LP_I2C
#define SOC_LP_I2C_NUM (1U)