diff --git a/components/efuse/efuse_table_gen.py b/components/efuse/efuse_table_gen.py index 976b2d6a20..fc3b865ef3 100755 --- a/components/efuse/efuse_table_gen.py +++ b/components/efuse/efuse_table_gen.py @@ -4,11 +4,9 @@ # # Converts efuse table to header file efuse_table.h. # -# SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD # # SPDX-License-Identifier: Apache-2.0 -from __future__ import division, print_function - import argparse import hashlib import os @@ -371,7 +369,7 @@ class FuseDefinition(object): res.bit_count = res.parse_bit_count(fields[3]) if res.bit_count is None or res.bit_count == 0: raise InputError("Field bit_count can't be empty") - res.comment = fields[4] + res.comment = fields[4].rstrip('\\').rstrip() return res def parse_num(self, strval): @@ -498,7 +496,7 @@ def main(): parser = argparse.ArgumentParser(description='ESP32 eFuse Manager') parser.add_argument('--idf_target', '-t', help='Target chip type', choices=['esp32', 'esp32s2', 'esp32s3', 'esp32c3', - 'esp32c2', 'esp32c6', 'esp32h2', 'esp32p4'], default='esp32') + 'esp32c2', 'esp32c6', 'esp32h2', 'esp32p4', 'esp32c5', 'esp32c61'], default='esp32') parser.add_argument('--quiet', '-q', help="Don't print non-critical status messages to stderr", action='store_true') parser.add_argument('--debug', help='Create header file with debug info', default=False, action='store_false') parser.add_argument('--info', help='Print info about range of used bits', default=False, action='store_true') diff --git a/components/efuse/esp32c5/esp_efuse_fields.c b/components/efuse/esp32c5/esp_efuse_fields.c index 5e2007604a..853fbf5ae7 100644 --- a/components/efuse/esp32c5/esp_efuse_fields.c +++ b/components/efuse/esp32c5/esp_efuse_fields.c @@ -17,15 +17,15 @@ static __attribute__((unused)) const char *TAG = "efuse"; -// TODO: [ESP32C5] IDF-8674 - // Contains functions that provide access to efuse fields which are often used in IDF. // Returns chip package from efuse uint32_t esp_efuse_get_pkg_ver(void) { uint32_t pkg_ver = 0; +#ifdef EFUSE_PKG_VERSION esp_efuse_read_field_blob(ESP_EFUSE_PKG_VERSION, &pkg_ver, ESP_EFUSE_PKG_VERSION[0]->bit_count); +#endif return pkg_ver; } diff --git a/components/efuse/esp32c5/esp_efuse_table.c b/components/efuse/esp32c5/esp_efuse_table.c index ad13b03aba..e0ac143372 100644 --- a/components/efuse/esp32c5/esp_efuse_table.c +++ b/components/efuse/esp32c5/esp_efuse_table.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,9 +9,7 @@ #include #include "esp_efuse_table.h" -// TODO: [ESP32C5] IDF-8674 - -// md5_digest_table fd5a35cea89bfad954e834bc92bed385 +// md5_digest_table eb005412b657c9be0ce4bb699e5813c9 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -25,14 +23,6 @@ static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { {EFUSE_BLK0, 0, 1}, // [] wr_dis of RD_DIS, }; -static const esp_efuse_desc_t WR_DIS_CRYPT_DPA_ENABLE[] = { - {EFUSE_BLK0, 1, 1}, // [] wr_dis of CRYPT_DPA_ENABLE, -}; - -static const esp_efuse_desc_t WR_DIS_SWAP_UART_SDIO_EN[] = { - {EFUSE_BLK0, 2, 1}, // [] wr_dis of SWAP_UART_SDIO_EN, -}; - static const esp_efuse_desc_t WR_DIS_DIS_ICACHE[] = { {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_ICACHE, }; @@ -41,20 +31,12 @@ static const esp_efuse_desc_t WR_DIS_DIS_USB_JTAG[] = { {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_USB_JTAG, }; -static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_ICACHE[] = { - {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_ICACHE, -}; - -static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG[] = { - {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_USB_SERIAL_JTAG, -}; - static const esp_efuse_desc_t WR_DIS_DIS_FORCE_DOWNLOAD[] = { {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_FORCE_DOWNLOAD, }; static const esp_efuse_desc_t WR_DIS_DIS_TWAI[] = { - {EFUSE_BLK0, 2, 1}, // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI, + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_TWAI, }; static const esp_efuse_desc_t WR_DIS_JTAG_SEL_ENABLE[] = { @@ -114,7 +96,7 @@ static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5[] = { }; static const esp_efuse_desc_t WR_DIS_SEC_DPA_LEVEL[] = { - {EFUSE_BLK0, 14, 1}, // [WR_DIS.DPA_SEC_LEVEL] wr_dis of SEC_DPA_LEVEL, + {EFUSE_BLK0, 14, 1}, // [] wr_dis of SEC_DPA_LEVEL, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = { @@ -142,7 +124,7 @@ static const esp_efuse_desc_t WR_DIS_DIS_DIRECT_BOOT[] = { }; static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - {EFUSE_BLK0, 18, 1}, // [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT, + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT, }; static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { @@ -169,14 +151,6 @@ static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { {EFUSE_BLK0, 19, 1}, // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE, }; -static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK0, 19, 1}, // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR, -}; - -static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { - {EFUSE_BLK0, 19, 1}, // [] wr_dis of DISABLE_BLK_VERSION_MAJOR, -}; - static const esp_efuse_desc_t WR_DIS_BLK1[] = { {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLOCK1, }; @@ -189,112 +163,12 @@ static const esp_efuse_desc_t WR_DIS_MAC_EXT[] = { {EFUSE_BLK0, 20, 1}, // [] wr_dis of MAC_EXT, }; -static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR, -}; - -static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MAJOR, -}; - -static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of PKG_VERSION, -}; - -static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MINOR, -}; - -static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MAJOR, -}; - -static const esp_efuse_desc_t WR_DIS_FLASH_CAP[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_CAP, -}; - -static const esp_efuse_desc_t WR_DIS_FLASH_TEMP[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_TEMP, -}; - -static const esp_efuse_desc_t WR_DIS_FLASH_VENDOR[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_VENDOR, -}; - static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2, }; -static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID, -}; - -static const esp_efuse_desc_t WR_DIS_TEMP_CALIB[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of TEMP_CALIB, -}; - -static const esp_efuse_desc_t WR_DIS_OCODE[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of OCODE, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN1[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN1, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN2[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN2, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN3[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN3, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN0[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN0, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN1[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN1, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN2[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN2, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN3[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN3, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH0[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH0, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH1[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH1, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH2[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH2, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH3[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH3, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH4[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH4, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH5[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH5, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH6[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH6, +static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK_SYS_DATA1, }; static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = { @@ -377,64 +251,72 @@ static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = { {EFUSE_BLK0, 38, 1}, // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2, }; -static const esp_efuse_desc_t SWAP_UART_SDIO_EN[] = { - {EFUSE_BLK0, 39, 1}, // [] Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not swapped, -}; - static const esp_efuse_desc_t DIS_ICACHE[] = { - {EFUSE_BLK0, 40, 1}, // [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 40, 1}, // [] Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled, }; static const esp_efuse_desc_t DIS_USB_JTAG[] = { - {EFUSE_BLK0, 41, 1}, // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled, -}; - -static const esp_efuse_desc_t DIS_DOWNLOAD_ICACHE[] = { - {EFUSE_BLK0, 42, 1}, // [] Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0: enabled, -}; - -static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG[] = { - {EFUSE_BLK0, 43, 1}, // [] Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 41, 1}, // [] Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled, }; static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = { - {EFUSE_BLK0, 44, 1}, // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 44, 1}, // [] Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled, }; static const esp_efuse_desc_t SPI_DOWNLOAD_MSPI_DIS[] = { - {EFUSE_BLK0, 45, 1}, // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 45, 1}, // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled, }; static const esp_efuse_desc_t DIS_TWAI[] = { - {EFUSE_BLK0, 46, 1}, // [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 46, 1}, // [] Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0: enabled, }; static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = { - {EFUSE_BLK0, 47, 1}, // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled, + {EFUSE_BLK0, 47, 1}, // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled, }; static const esp_efuse_desc_t SOFT_DIS_JTAG[] = { - {EFUSE_BLK0, 48, 3}, // [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled, + {EFUSE_BLK0, 48, 3}, // [] Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even number: enabled, }; static const esp_efuse_desc_t DIS_PAD_JTAG[] = { - {EFUSE_BLK0, 51, 1}, // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled, + {EFUSE_BLK0, 51, 1}, // [] Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled, }; static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - {EFUSE_BLK0, 52, 1}, // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled, + {EFUSE_BLK0, 52, 1}, // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled, }; static const esp_efuse_desc_t USB_EXCHG_PINS[] = { - {EFUSE_BLK0, 57, 1}, // [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged, + {EFUSE_BLK0, 57, 1}, // [] Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged, }; static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = { - {EFUSE_BLK0, 58, 1}, // [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned, + {EFUSE_BLK0, 58, 1}, // [] Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned, +}; + +static const esp_efuse_desc_t KM_DISABLE_DEPLOY_MODE[] = { + {EFUSE_BLK0, 64, 4}, // [] Represents whether the deploy mode of key manager is disable or not. \\ 1: disabled \\ 0: enabled., +}; + +static const esp_efuse_desc_t KM_RND_SWITCH_CYCLE[] = { + {EFUSE_BLK0, 68, 2}, // [] Set the bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles, +}; + +static const esp_efuse_desc_t KM_DEPLOY_ONLY_ONCE[] = { + {EFUSE_BLK0, 70, 4}, // [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds, +}; + +static const esp_efuse_desc_t FORCE_USE_KEY_MANAGER_KEY[] = { + {EFUSE_BLK0, 74, 4}, // [] Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds, +}; + +static const esp_efuse_desc_t FORCE_DISABLE_SW_INIT_KEY[] = { + {EFUSE_BLK0, 78, 1}, // [] Set this bit to disable software written init key; and force use efuse_init_key, }; static const esp_efuse_desc_t WDT_DELAY_SEL[] = { - {EFUSE_BLK0, 80, 2}, // [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected, + {EFUSE_BLK0, 80, 2}, // [] Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16, }; static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { @@ -478,19 +360,19 @@ static const esp_efuse_desc_t KEY_PURPOSE_5[] = { }; static const esp_efuse_desc_t SEC_DPA_LEVEL[] = { - {EFUSE_BLK0, 112, 2}, // [DPA_SEC_LEVEL] Represents the spa secure level by configuring the clock random divide mode, -}; - -static const esp_efuse_desc_t CRYPT_DPA_ENABLE[] = { - {EFUSE_BLK0, 114, 1}, // [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled, + {EFUSE_BLK0, 112, 2}, // [] Represents the spa secure level by configuring the clock random divide mode, }; static const esp_efuse_desc_t SECURE_BOOT_EN[] = { - {EFUSE_BLK0, 116, 1}, // [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled, + {EFUSE_BLK0, 116, 1}, // [] Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled, }; static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - {EFUSE_BLK0, 117, 1}, // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled, + {EFUSE_BLK0, 117, 1}, // [] Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled, +}; + +static const esp_efuse_desc_t KM_XTS_KEY_LENGTH_256[] = { + {EFUSE_BLK0, 123, 1}, // [] Set this bitto configure flash encryption use xts-128 key. else use xts-256 key, }; static const esp_efuse_desc_t FLASH_TPUW[] = { @@ -498,23 +380,27 @@ static const esp_efuse_desc_t FLASH_TPUW[] = { }; static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 128, 1}, // [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 128, 1}, // [] Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled, }; static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = { - {EFUSE_BLK0, 129, 1}, // [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 129, 1}, // [] Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0: enabled, }; static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - {EFUSE_BLK0, 130, 1}, // [DIS_USB_PRINT] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 130, 1}, // [] Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: enabled, +}; + +static const esp_efuse_desc_t LOCK_KM_KEY[] = { + {EFUSE_BLK0, 131, 1}, // [] Represetns whether to lock the efuse xts key.\\ 1. Lock\\ 0: Unlock, }; static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 132, 1}, // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 132, 1}, // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable, }; static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { - {EFUSE_BLK0, 133, 1}, // [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled, + {EFUSE_BLK0, 133, 1}, // [] Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0: disabled, }; static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { @@ -522,23 +408,47 @@ static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { }; static const esp_efuse_desc_t FORCE_SEND_RESUME[] = { - {EFUSE_BLK0, 141, 1}, // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced, + {EFUSE_BLK0, 136, 1}, // [] Represents whether ROM code is forced to send a resume command during SPI boot.\\ 1: forced\\ 0:not forced, }; static const esp_efuse_desc_t SECURE_VERSION[] = { - {EFUSE_BLK0, 142, 16}, // [] Represents the version used by ESP-IDF anti-rollback feature, + {EFUSE_BLK0, 137, 16}, // [] Represents the version used by ESP-IDF anti-rollback feature, }; static const esp_efuse_desc_t SECURE_BOOT_DISABLE_FAST_WAKE[] = { - {EFUSE_BLK0, 158, 1}, // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 153, 1}, // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled.\\ 1: disabled\\ 0: enabled, }; -static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK0, 160, 1}, // [] Disables check of wafer version major, +static const esp_efuse_desc_t HYS_EN_PAD[] = { + {EFUSE_BLK0, 154, 1}, // [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled, }; -static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = { - {EFUSE_BLK0, 161, 1}, // [] Disables check of blk version major, +static const esp_efuse_desc_t XTS_DPA_PSEUDO_LEVEL[] = { + {EFUSE_BLK0, 155, 2}, // [] Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2: Moderate 1. Low\\ 0: Disabled, +}; + +static const esp_efuse_desc_t XTS_DPA_CLK_ENABLE[] = { + {EFUSE_BLK0, 157, 1}, // [] Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0: Disable., +}; + +static const esp_efuse_desc_t HUK_GEN_STATE[] = { + {EFUSE_BLK0, 160, 9}, // [] Set the bits to control validation of HUK generate mode.\\ Odd of 1 is invalid.\\ Even of 1 is valid., +}; + +static const esp_efuse_desc_t XTAL_48M_SEL[] = { + {EFUSE_BLK0, 169, 3}, // [] Represents whether XTAL frequency is 48MHz or not. If not; 40MHz XTAL will be used. If this field contains Odd number bit 1: Enable 48MHz XTAL\ Even number bit 1: Enable 40MHz XTAL, +}; + +static const esp_efuse_desc_t XTAL_48M_SEL_MODE[] = { + {EFUSE_BLK0, 172, 1}, // [] Specify the XTAL frequency selection is decided by eFuse or strapping-PAD-state. 1: eFuse\\ 0: strapping-PAD-state, +}; + +static const esp_efuse_desc_t ECDSA_DISABLE_P192[] = { + {EFUSE_BLK0, 173, 1}, // [] Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable, +}; + +static const esp_efuse_desc_t ECC_FORCE_CONST_TIME[] = { + {EFUSE_BLK0, 174, 1}, // [] Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable, }; static const esp_efuse_desc_t MAC[] = { @@ -551,112 +461,11 @@ static const esp_efuse_desc_t MAC[] = { }; static const esp_efuse_desc_t MAC_EXT[] = { - {EFUSE_BLK1, 56, 8}, // [] Stores the extended bits of MAC address, - {EFUSE_BLK1, 48, 8}, // [] Stores the extended bits of MAC address, + {EFUSE_BLK1, 48, 16}, // [] Represents the extended bits of MAC address, }; -static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { - {EFUSE_BLK1, 114, 4}, // [], -}; - -static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK1, 118, 2}, // [], -}; - -static const esp_efuse_desc_t PKG_VERSION[] = { - {EFUSE_BLK1, 120, 3}, // [] Package version, -}; - -static const esp_efuse_desc_t BLK_VERSION_MINOR[] = { - {EFUSE_BLK1, 123, 3}, // [] BLK_VERSION_MINOR of BLOCK2, -}; - -static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { - {EFUSE_BLK1, 126, 2}, // [] BLK_VERSION_MAJOR of BLOCK2, -}; - -static const esp_efuse_desc_t FLASH_CAP[] = { - {EFUSE_BLK1, 128, 3}, // [], -}; - -static const esp_efuse_desc_t FLASH_TEMP[] = { - {EFUSE_BLK1, 131, 2}, // [], -}; - -static const esp_efuse_desc_t FLASH_VENDOR[] = { - {EFUSE_BLK1, 133, 3}, // [], -}; - -static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { - {EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID, -}; - -static const esp_efuse_desc_t TEMP_CALIB[] = { - {EFUSE_BLK2, 128, 9}, // [] Temperature calibration data, -}; - -static const esp_efuse_desc_t OCODE[] = { - {EFUSE_BLK2, 137, 8}, // [] ADC OCode, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = { - {EFUSE_BLK2, 145, 10}, // [] ADC1 init code at atten0, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = { - {EFUSE_BLK2, 155, 10}, // [] ADC1 init code at atten1, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = { - {EFUSE_BLK2, 165, 10}, // [] ADC1 init code at atten2, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = { - {EFUSE_BLK2, 175, 10}, // [] ADC1 init code at atten3, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = { - {EFUSE_BLK2, 185, 10}, // [] ADC1 calibration voltage at atten0, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = { - {EFUSE_BLK2, 195, 10}, // [] ADC1 calibration voltage at atten1, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = { - {EFUSE_BLK2, 205, 10}, // [] ADC1 calibration voltage at atten2, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = { - {EFUSE_BLK2, 215, 10}, // [] ADC1 calibration voltage at atten3, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH0[] = { - {EFUSE_BLK2, 225, 4}, // [] ADC1 init code at atten0 ch0, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH1[] = { - {EFUSE_BLK2, 229, 4}, // [] ADC1 init code at atten0 ch1, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH2[] = { - {EFUSE_BLK2, 233, 4}, // [] ADC1 init code at atten0 ch2, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH3[] = { - {EFUSE_BLK2, 237, 4}, // [] ADC1 init code at atten0 ch3, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH4[] = { - {EFUSE_BLK2, 241, 4}, // [] ADC1 init code at atten0 ch4, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH5[] = { - {EFUSE_BLK2, 245, 4}, // [] ADC1 init code at atten0 ch5, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH6[] = { - {EFUSE_BLK2, 249, 4}, // [] ADC1 init code at atten0 ch6, +static const esp_efuse_desc_t BLOCK_SYS_DATA1[] = { + {EFUSE_BLK2, 0, 256}, // [] System data part 1 (reserved), }; static const esp_efuse_desc_t USER_DATA[] = { @@ -709,16 +518,6 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[] = { - &WR_DIS_CRYPT_DPA_ENABLE[0], // [] wr_dis of CRYPT_DPA_ENABLE - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SWAP_UART_SDIO_EN[] = { - &WR_DIS_SWAP_UART_SDIO_EN[0], // [] wr_dis of SWAP_UART_SDIO_EN - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[] = { &WR_DIS_DIS_ICACHE[0], // [] wr_dis of DIS_ICACHE NULL @@ -729,23 +528,13 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[] = { - &WR_DIS_DIS_DOWNLOAD_ICACHE[0], // [] wr_dis of DIS_DOWNLOAD_ICACHE - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG[] = { - &WR_DIS_DIS_USB_SERIAL_JTAG[0], // [] wr_dis of DIS_USB_SERIAL_JTAG - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[] = { &WR_DIS_DIS_FORCE_DOWNLOAD[0], // [] wr_dis of DIS_FORCE_DOWNLOAD NULL }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[] = { - &WR_DIS_DIS_TWAI[0], // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI + &WR_DIS_DIS_TWAI[0], // [] wr_dis of DIS_TWAI NULL }; @@ -820,7 +609,7 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[] = { }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[] = { - &WR_DIS_SEC_DPA_LEVEL[0], // [WR_DIS.DPA_SEC_LEVEL] wr_dis of SEC_DPA_LEVEL + &WR_DIS_SEC_DPA_LEVEL[0], // [] wr_dis of SEC_DPA_LEVEL NULL }; @@ -855,7 +644,7 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[] = { }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - &WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT + &WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT NULL }; @@ -889,16 +678,6 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { - &WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0], // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { - &WR_DIS_DISABLE_BLK_VERSION_MAJOR[0], // [] wr_dis of DISABLE_BLK_VERSION_MAJOR - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = { &WR_DIS_BLK1[0], // [] wr_dis of BLOCK1 NULL @@ -914,138 +693,13 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[] = { - &WR_DIS_WAFER_VERSION_MINOR[0], // [] wr_dis of WAFER_VERSION_MINOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[] = { - &WR_DIS_WAFER_VERSION_MAJOR[0], // [] wr_dis of WAFER_VERSION_MAJOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = { - &WR_DIS_PKG_VERSION[0], // [] wr_dis of PKG_VERSION - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = { - &WR_DIS_BLK_VERSION_MINOR[0], // [] wr_dis of BLK_VERSION_MINOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = { - &WR_DIS_BLK_VERSION_MAJOR[0], // [] wr_dis of BLK_VERSION_MAJOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[] = { - &WR_DIS_FLASH_CAP[0], // [] wr_dis of FLASH_CAP - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[] = { - &WR_DIS_FLASH_TEMP[0], // [] wr_dis of FLASH_TEMP - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[] = { - &WR_DIS_FLASH_VENDOR[0], // [] wr_dis of FLASH_VENDOR - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { &WR_DIS_SYS_DATA_PART1[0], // [] wr_dis of BLOCK2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = { - &WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[] = { - &WR_DIS_TEMP_CALIB[0], // [] wr_dis of TEMP_CALIB - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[] = { - &WR_DIS_OCODE[0], // [] wr_dis of OCODE - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN0[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN1[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN2[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN3[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[] = { - &WR_DIS_ADC1_CAL_VOL_ATTEN0[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[] = { - &WR_DIS_ADC1_CAL_VOL_ATTEN1[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[] = { - &WR_DIS_ADC1_CAL_VOL_ATTEN2[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[] = { - &WR_DIS_ADC1_CAL_VOL_ATTEN3[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH0[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH0[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH1[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH1[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH2[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH2[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH3[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH3[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH4[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH4[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH4 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH5[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH5[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH5 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH6[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH6[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH6 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA1[] = { + &WR_DIS_BLOCK_SYS_DATA1[0], // [] wr_dis of BLOCK_SYS_DATA1 NULL }; @@ -1149,78 +803,88 @@ const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SWAP_UART_SDIO_EN[] = { - &SWAP_UART_SDIO_EN[0], // [] Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not swapped - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { - &DIS_ICACHE[0], // [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled + &DIS_ICACHE[0], // [] Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = { - &DIS_USB_JTAG[0], // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = { - &DIS_DOWNLOAD_ICACHE[0], // [] Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0: enabled - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[] = { - &DIS_USB_SERIAL_JTAG[0], // [] Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled + &DIS_USB_JTAG[0], // [] Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = { - &DIS_FORCE_DOWNLOAD[0], // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled + &DIS_FORCE_DOWNLOAD[0], // [] Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[] = { - &SPI_DOWNLOAD_MSPI_DIS[0], // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled + &SPI_DOWNLOAD_MSPI_DIS[0], // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = { - &DIS_TWAI[0], // [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled + &DIS_TWAI[0], // [] Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = { - &JTAG_SEL_ENABLE[0], // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled + &JTAG_SEL_ENABLE[0], // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = { - &SOFT_DIS_JTAG[0], // [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled + &SOFT_DIS_JTAG[0], // [] Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even number: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = { - &DIS_PAD_JTAG[0], // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled + &DIS_PAD_JTAG[0], // [] Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled + &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = { - &USB_EXCHG_PINS[0], // [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged + &USB_EXCHG_PINS[0], // [] Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged NULL }; const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = { - &VDD_SPI_AS_GPIO[0], // [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned + &VDD_SPI_AS_GPIO[0], // [] Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[] = { + &KM_DISABLE_DEPLOY_MODE[0], // [] Represents whether the deploy mode of key manager is disable or not. \\ 1: disabled \\ 0: enabled. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[] = { + &KM_RND_SWITCH_CYCLE[0], // [] Set the bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[] = { + &KM_DEPLOY_ONLY_ONCE[0], // [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[] = { + &FORCE_USE_KEY_MANAGER_KEY[0], // [] Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[] = { + &FORCE_DISABLE_SW_INIT_KEY[0], // [] Set this bit to disable software written init key; and force use efuse_init_key NULL }; const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { - &WDT_DELAY_SEL[0], // [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected + &WDT_DELAY_SEL[0], // [] Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16 NULL }; @@ -1275,22 +939,22 @@ const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = { }; const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = { - &SEC_DPA_LEVEL[0], // [DPA_SEC_LEVEL] Represents the spa secure level by configuring the clock random divide mode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[] = { - &CRYPT_DPA_ENABLE[0], // [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled + &SEC_DPA_LEVEL[0], // [] Represents the spa secure level by configuring the clock random divide mode NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { - &SECURE_BOOT_EN[0], // [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled + &SECURE_BOOT_EN[0], // [] Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled + &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KM_XTS_KEY_LENGTH_256[] = { + &KM_XTS_KEY_LENGTH_256[0], // [] Set this bitto configure flash encryption use xts-128 key. else use xts-256 key NULL }; @@ -1300,27 +964,32 @@ const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = { }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { - &DIS_DOWNLOAD_MODE[0], // [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled + &DIS_DOWNLOAD_MODE[0], // [] Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = { - &DIS_DIRECT_BOOT[0], // [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled + &DIS_DIRECT_BOOT[0], // [] Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [DIS_USB_PRINT] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled + &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [] Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[] = { + &LOCK_KM_KEY[0], // [] Represetns whether to lock the efuse xts key.\\ 1. Lock\\ 0: Unlock NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled + &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable NULL }; const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { - &ENABLE_SECURITY_DOWNLOAD[0], // [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled + &ENABLE_SECURITY_DOWNLOAD[0], // [] Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0: disabled NULL }; @@ -1330,7 +999,7 @@ const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = { }; const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = { - &FORCE_SEND_RESUME[0], // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced + &FORCE_SEND_RESUME[0], // [] Represents whether ROM code is forced to send a resume command during SPI boot.\\ 1: forced\\ 0:not forced NULL }; @@ -1340,17 +1009,47 @@ const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[] = { - &SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled + &SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled.\\ 1: disabled\\ 0: enabled NULL }; -const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = { - &DISABLE_WAFER_VERSION_MAJOR[0], // [] Disables check of wafer version major +const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[] = { + &HYS_EN_PAD[0], // [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled NULL }; -const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = { - &DISABLE_BLK_VERSION_MAJOR[0], // [] Disables check of blk version major +const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[] = { + &XTS_DPA_PSEUDO_LEVEL[0], // [] Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2: Moderate 1. Low\\ 0: Disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[] = { + &XTS_DPA_CLK_ENABLE[0], // [] Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0: Disable. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_HUK_GEN_STATE[] = { + &HUK_GEN_STATE[0], // [] Set the bits to control validation of HUK generate mode.\\ Odd of 1 is invalid.\\ Even of 1 is valid. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_XTAL_48M_SEL[] = { + &XTAL_48M_SEL[0], // [] Represents whether XTAL frequency is 48MHz or not. If not; 40MHz XTAL will be used. If this field contains Odd number bit 1: Enable 48MHz XTAL\ Even number bit 1: Enable 40MHz XTAL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_XTAL_48M_SEL_MODE[] = { + &XTAL_48M_SEL_MODE[0], // [] Specify the XTAL frequency selection is decided by eFuse or strapping-PAD-state. 1: eFuse\\ 0: strapping-PAD-state + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ECDSA_DISABLE_P192[] = { + &ECDSA_DISABLE_P192[0], // [] Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[] = { + &ECC_FORCE_CONST_TIME[0], // [] Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable NULL }; @@ -1365,138 +1064,12 @@ const esp_efuse_desc_t* ESP_EFUSE_MAC[] = { }; const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = { - &MAC_EXT[0], // [] Stores the extended bits of MAC address - &MAC_EXT[1], // [] Stores the extended bits of MAC address + &MAC_EXT[0], // [] Represents the extended bits of MAC address NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { - &WAFER_VERSION_MINOR[0], // [] - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { - &WAFER_VERSION_MAJOR[0], // [] - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { - &PKG_VERSION[0], // [] Package version - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = { - &BLK_VERSION_MINOR[0], // [] BLK_VERSION_MINOR of BLOCK2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { - &BLK_VERSION_MAJOR[0], // [] BLK_VERSION_MAJOR of BLOCK2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = { - &FLASH_CAP[0], // [] - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[] = { - &FLASH_TEMP[0], // [] - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = { - &FLASH_VENDOR[0], // [] - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { - &OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = { - &TEMP_CALIB[0], // [] Temperature calibration data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { - &OCODE[0], // [] ADC OCode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = { - &ADC1_INIT_CODE_ATTEN0[0], // [] ADC1 init code at atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = { - &ADC1_INIT_CODE_ATTEN1[0], // [] ADC1 init code at atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = { - &ADC1_INIT_CODE_ATTEN2[0], // [] ADC1 init code at atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = { - &ADC1_INIT_CODE_ATTEN3[0], // [] ADC1 init code at atten3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = { - &ADC1_CAL_VOL_ATTEN0[0], // [] ADC1 calibration voltage at atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = { - &ADC1_CAL_VOL_ATTEN1[0], // [] ADC1 calibration voltage at atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = { - &ADC1_CAL_VOL_ATTEN2[0], // [] ADC1 calibration voltage at atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = { - &ADC1_CAL_VOL_ATTEN3[0], // [] ADC1 calibration voltage at atten3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH0[] = { - &ADC1_INIT_CODE_ATTEN0_CH0[0], // [] ADC1 init code at atten0 ch0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH1[] = { - &ADC1_INIT_CODE_ATTEN0_CH1[0], // [] ADC1 init code at atten0 ch1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH2[] = { - &ADC1_INIT_CODE_ATTEN0_CH2[0], // [] ADC1 init code at atten0 ch2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH3[] = { - &ADC1_INIT_CODE_ATTEN0_CH3[0], // [] ADC1 init code at atten0 ch3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH4[] = { - &ADC1_INIT_CODE_ATTEN0_CH4[0], // [] ADC1 init code at atten0 ch4 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH5[] = { - &ADC1_INIT_CODE_ATTEN0_CH5[0], // [] ADC1 init code at atten0 ch5 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH6[] = { - &ADC1_INIT_CODE_ATTEN0_CH6[0], // [] ADC1 init code at atten0 ch6 +const esp_efuse_desc_t* ESP_EFUSE_BLOCK_SYS_DATA1[] = { + &BLOCK_SYS_DATA1[0], // [] System data part 1 (reserved) NULL }; diff --git a/components/efuse/esp32c5/esp_efuse_table.csv b/components/efuse/esp32c5/esp_efuse_table.csv index 66a395c1ed..4dd7b43eab 100644 --- a/components/efuse/esp32c5/esp_efuse_table.csv +++ b/components/efuse/esp32c5/esp_efuse_table.csv @@ -4,23 +4,19 @@ # | EFUSE_BLK1 | | | # # | ...) | | | # ########################################################################## -# !!!!!!!!!!! # // TODO: [ESP32C5] IDF-8674 +# !!!!!!!!!!! # # After editing this file, run the command manually "idf.py efuse-common-table" # this will generate new source files, next rebuild all the sources. # !!!!!!!!!!! # -# This file was generated by regtools.py based on the efuses.yaml file with the version: 709e8ea096e8a03a10006d40d5451a49 +# This file was generated by regtools.py based on the efuses.yaml file with the version: 64acd55d57b7452dbb6838b7237c795b WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS -WR_DIS.CRYPT_DPA_ENABLE, EFUSE_BLK0, 1, 1, [] wr_dis of CRYPT_DPA_ENABLE -WR_DIS.SWAP_UART_SDIO_EN, EFUSE_BLK0, 2, 1, [] wr_dis of SWAP_UART_SDIO_EN WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG -WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE -WR_DIS.DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_SERIAL_JTAG WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD -WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI +WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_TWAI WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT @@ -35,52 +31,25 @@ WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.K WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 -WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [WR_DIS.DPA_SEC_LEVEL] wr_dis of SEC_DPA_LEVEL +WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of SEC_DPA_LEVEL WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 17, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DIRECT_BOOT -WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT +WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 19, 1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE -WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR -WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1 WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC WR_DIS.MAC_EXT, EFUSE_BLK0, 20, 1, [] wr_dis of MAC_EXT -WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR -WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR -WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION -WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR -WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR -WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP -WR_DIS.FLASH_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_TEMP -WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 -WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID -WR_DIS.TEMP_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIB -WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE -WR_DIS.ADC1_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0 -WR_DIS.ADC1_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN1 -WR_DIS.ADC1_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN2 -WR_DIS.ADC1_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN3 -WR_DIS.ADC1_CAL_VOL_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN0 -WR_DIS.ADC1_CAL_VOL_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN1 -WR_DIS.ADC1_CAL_VOL_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN2 -WR_DIS.ADC1_CAL_VOL_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN3 -WR_DIS.ADC1_INIT_CODE_ATTEN0_CH0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH0 -WR_DIS.ADC1_INIT_CODE_ATTEN0_CH1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH1 -WR_DIS.ADC1_INIT_CODE_ATTEN0_CH2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH2 -WR_DIS.ADC1_INIT_CODE_ATTEN0_CH3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH3 -WR_DIS.ADC1_INIT_CODE_ATTEN0_CH4, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH4 -WR_DIS.ADC1_INIT_CODE_ATTEN0_CH5, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH5 -WR_DIS.ADC1_INIT_CODE_ATTEN0_CH6, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH6 +WR_DIS.BLOCK_SYS_DATA1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK_SYS_DATA1 WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 @@ -101,21 +70,23 @@ RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.K RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 -SWAP_UART_SDIO_EN, EFUSE_BLK0, 39, 1, [] Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not swapped -DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled -DIS_USB_JTAG, EFUSE_BLK0, 41, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled -DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, [] Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0: enabled -DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 43, 1, [] Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled -DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled -SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 45, 1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled -DIS_TWAI, EFUSE_BLK0, 46, 1, [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled -JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled -SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled -DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled -DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled -USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged -VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned -WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected +DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ +DIS_USB_JTAG, EFUSE_BLK0, 41, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ +DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ +SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 45, 1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ +DIS_TWAI, EFUSE_BLK0, 46, 1, [] Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ +JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ +SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even number: enabled\\ +DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled\\ +DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled\\ +USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged\\ +VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, [] Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned\\ +KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 64, 4, [] Represents whether the deploy mode of key manager is disable or not. \\ 1: disabled \\ 0: enabled.\\ +KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 68, 2, [] Set the bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles +KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 70, 4, [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds +FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 74, 4, [] Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds +FORCE_DISABLE_SW_INIT_KEY, EFUSE_BLK0, 78, 1, [] Set this bit to disable software written init key; and force use efuse_init_key +WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16 \\ SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key @@ -126,56 +97,37 @@ KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PUR KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Represents the purpose of Key3 KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Represents the purpose of Key4 KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Represents the purpose of Key5 -SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, [DPA_SEC_LEVEL] Represents the spa secure level by configuring the clock random divide mode -CRYPT_DPA_ENABLE, EFUSE_BLK0, 114, 1, [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled -SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled -SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled +SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, [] Represents the spa secure level by configuring the clock random divide mode +SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ +SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled\\ +KM_XTS_KEY_LENGTH_256, EFUSE_BLK0, 123, 1, [] Set this bitto configure flash encryption use xts-128 key. else use xts-256 key FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value -DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled -DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled -DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [DIS_USB_PRINT] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled -DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled -ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled +DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ +DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [] Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ +DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [] Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ +LOCK_KM_KEY, EFUSE_BLK0, 131, 1, [] Represetns whether to lock the efuse xts key.\\ 1. Lock\\ 0: Unlock\\ +DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable\\ +ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"} -FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced -SECURE_VERSION, EFUSE_BLK0, 142, 16, [] Represents the version used by ESP-IDF anti-rollback feature -SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 158, 1, [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled -DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, [] Disables check of wafer version major -DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, [] Disables check of blk version major +FORCE_SEND_RESUME, EFUSE_BLK0, 136, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot.\\ 1: forced\\ 0:not forced\\ +SECURE_VERSION, EFUSE_BLK0, 137, 16, [] Represents the version used by ESP-IDF anti-rollback feature +SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 153, 1, [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled.\\ 1: disabled\\ 0: enabled\\ +HYS_EN_PAD, EFUSE_BLK0, 154, 1, [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled\\ +XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 155, 2, [] Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2: Moderate 1. Low\\ 0: Disabled\\ +XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 157, 1, [] Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0: Disable.\\ +HUK_GEN_STATE, EFUSE_BLK0, 160, 9, [] Set the bits to control validation of HUK generate mode.\\ Odd of 1 is invalid.\\ Even of 1 is valid.\\ +XTAL_48M_SEL, EFUSE_BLK0, 169, 3, [] Represents whether XTAL frequency is 48MHz or not. If not; 40MHz XTAL will be used. If this field contains Odd number bit 1: Enable 48MHz XTAL\ Even number bit 1: Enable 40MHz XTAL +XTAL_48M_SEL_MODE, EFUSE_BLK0, 172, 1, [] Specify the XTAL frequency selection is decided by eFuse or strapping-PAD-state. 1: eFuse\\ 0: strapping-PAD-state +ECDSA_DISABLE_P192, EFUSE_BLK0, 173, 1, [] Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable +ECC_FORCE_CONST_TIME, EFUSE_BLK0, 174, 1, [] Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address -MAC_EXT, EFUSE_BLK1, 56, 8, [] Stores the extended bits of MAC address -, EFUSE_BLK1, 48, 8, [] Stores the extended bits of MAC address -WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 4, [] -WAFER_VERSION_MAJOR, EFUSE_BLK1, 118, 2, [] -PKG_VERSION, EFUSE_BLK1, 120, 3, [] Package version -BLK_VERSION_MINOR, EFUSE_BLK1, 123, 3, [] BLK_VERSION_MINOR of BLOCK2 -BLK_VERSION_MAJOR, EFUSE_BLK1, 126, 2, [] BLK_VERSION_MAJOR of BLOCK2 -FLASH_CAP, EFUSE_BLK1, 128, 3, [] -FLASH_TEMP, EFUSE_BLK1, 131, 2, [] -FLASH_VENDOR, EFUSE_BLK1, 133, 3, [] -OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID -TEMP_CALIB, EFUSE_BLK2, 128, 9, [] Temperature calibration data -OCODE, EFUSE_BLK2, 137, 8, [] ADC OCode -ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 145, 10, [] ADC1 init code at atten0 -ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 155, 10, [] ADC1 init code at atten1 -ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 165, 10, [] ADC1 init code at atten2 -ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 175, 10, [] ADC1 init code at atten3 -ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 185, 10, [] ADC1 calibration voltage at atten0 -ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 195, 10, [] ADC1 calibration voltage at atten1 -ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 205, 10, [] ADC1 calibration voltage at atten2 -ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 215, 10, [] ADC1 calibration voltage at atten3 -ADC1_INIT_CODE_ATTEN0_CH0, EFUSE_BLK2, 225, 4, [] ADC1 init code at atten0 ch0 -ADC1_INIT_CODE_ATTEN0_CH1, EFUSE_BLK2, 229, 4, [] ADC1 init code at atten0 ch1 -ADC1_INIT_CODE_ATTEN0_CH2, EFUSE_BLK2, 233, 4, [] ADC1 init code at atten0 ch2 -ADC1_INIT_CODE_ATTEN0_CH3, EFUSE_BLK2, 237, 4, [] ADC1 init code at atten0 ch3 -ADC1_INIT_CODE_ATTEN0_CH4, EFUSE_BLK2, 241, 4, [] ADC1 init code at atten0 ch4 -ADC1_INIT_CODE_ATTEN0_CH5, EFUSE_BLK2, 245, 4, [] ADC1 init code at atten0 ch5 -ADC1_INIT_CODE_ATTEN0_CH6, EFUSE_BLK2, 249, 4, [] ADC1 init code at atten0 ch6 +MAC_EXT, EFUSE_BLK1, 48, 16, [] Represents the extended bits of MAC address +BLOCK_SYS_DATA1, EFUSE_BLK2, 0, 256, [] System data part 1 (reserved) USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data diff --git a/components/efuse/esp32c5/esp_efuse_utility.c b/components/efuse/esp32c5/esp_efuse_utility.c index 39712b77f1..1dc28a7aa0 100644 --- a/components/efuse/esp32c5/esp_efuse_utility.c +++ b/components/efuse/esp32c5/esp_efuse_utility.c @@ -12,9 +12,7 @@ #include "soc/efuse_periph.h" #include "hal/efuse_hal.h" -// static const char *TAG = "efuse"; - -// TODO: [ESP32C5] IDF-8674 +static const char *TAG = "efuse"; #ifdef CONFIG_EFUSE_VIRTUAL extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK]; @@ -22,17 +20,17 @@ extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK]; /*Range addresses to read blocks*/ const esp_efuse_range_addr_t range_read_addr_blocks[] = { - // {EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT - // {EFUSE_RD_MAC_SPI_SYS_0_REG, EFUSE_RD_MAC_SPI_SYS_5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M - // {EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA - // {EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA - // {EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0 - // {EFUSE_RD_KEY1_DATA0_REG, EFUSE_RD_KEY1_DATA7_REG}, // range address of EFUSE_BLK5 KEY1 - // {EFUSE_RD_KEY2_DATA0_REG, EFUSE_RD_KEY2_DATA7_REG}, // range address of EFUSE_BLK6 KEY2 - // {EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3 - // {EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4 - // {EFUSE_RD_KEY5_DATA0_REG, EFUSE_RD_KEY5_DATA7_REG}, // range address of EFUSE_BLK9 KEY5 - // {EFUSE_RD_SYS_PART2_DATA0_REG, EFUSE_RD_SYS_PART2_DATA7_REG} // range address of EFUSE_BLK10 KEY6 + {EFUSE_RD_WR_DIS0_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT + {EFUSE_RD_MAC_SYS0_REG, EFUSE_RD_MAC_SYS5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M + {EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA + {EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA + {EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0 + {EFUSE_RD_KEY1_DATA0_REG, EFUSE_RD_KEY1_DATA7_REG}, // range address of EFUSE_BLK5 KEY1 + {EFUSE_RD_KEY2_DATA0_REG, EFUSE_RD_KEY2_DATA7_REG}, // range address of EFUSE_BLK6 KEY2 + {EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3 + {EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4 + {EFUSE_RD_KEY5_DATA0_REG, EFUSE_RD_KEY5_DATA7_REG}, // range address of EFUSE_BLK9 KEY5 + {EFUSE_RD_SYS_PART2_DATA0_REG, EFUSE_RD_SYS_PART2_DATA7_REG} // range address of EFUSE_BLK10 KEY6 }; static uint32_t write_mass_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK] = { 0 }; @@ -58,9 +56,7 @@ static esp_err_t esp_efuse_set_timing(void) { // efuse clock is fixed. // An argument (0) is for compatibility and will be ignored. - // TODO: [ESP32C5] IDF-8674 - abort(); - // efuse_hal_set_timing(0); + efuse_hal_set_timing(0); return ESP_OK; } #endif // ifndef CONFIG_EFUSE_VIRTUAL @@ -68,10 +64,8 @@ static esp_err_t esp_efuse_set_timing(void) // Efuse read operation: copies data from physical efuses to efuse read registers. void esp_efuse_utility_clear_program_registers(void) { - // TODO: [ESP32C5] IDF-8674 - abort(); - // efuse_hal_read(); - // efuse_hal_clear_program_registers(); + efuse_hal_read(); + efuse_hal_clear_program_registers(); } esp_err_t esp_efuse_utility_check_errors(void) @@ -87,103 +81,103 @@ esp_err_t esp_efuse_utility_burn_chip(void) esp_err_t esp_efuse_utility_burn_chip_opt(bool ignore_coding_errors, bool verify_written_data) { - // TODO: [ESP32C5] IDF-8674 - abort(); esp_err_t error = ESP_OK; #ifdef CONFIG_EFUSE_VIRTUAL -// ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses"); -// for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) { -// int subblock = 0; -// for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { -// virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block); -// } -// } -// #ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH -// esp_efuse_utility_write_efuses_to_flash(); -// #endif + (void) ignore_coding_errors; + (void) verify_written_data; + ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses"); + for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) { + int subblock = 0; + for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { + virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block); + } + } +#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH + esp_efuse_utility_write_efuses_to_flash(); +#endif #else // CONFIG_EFUSE_VIRTUAL if (esp_efuse_set_timing() != ESP_OK) { -// ESP_LOGE(TAG, "Efuse fields are not burnt"); + ESP_LOGE(TAG, "Efuse fields are not burnt"); } else { -// // Permanently update values written to the efuse write registers -// // It is necessary to process blocks in the order from MAX-> EFUSE_BLK0, because EFUSE_BLK0 has protection bits for other blocks. -// for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) { -// bool need_burn_block = false; -// for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { -// if (REG_READ(addr_wr_block) != 0) { -// need_burn_block = true; -// break; -// } -// } -// if (!need_burn_block) { -// continue; -// } -// if (error) { -// // It is done for a use case: BLOCK2 (Flash encryption key) could have an error (incorrect written data) -// // in this case we can not burn any data into BLOCK0 because it might set read/write protections of BLOCK2. -// ESP_LOGE(TAG, "BLOCK%d can not be burned because a previous block got an error, skipped.", num_block); -// continue; -// } -// efuse_hal_clear_program_registers(); -// if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { -// uint8_t block_rs[12]; -// efuse_hal_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs); -// hal_memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs)); -// } -// unsigned r_data_len = (range_read_addr_blocks[num_block].end - range_read_addr_blocks[num_block].start) + sizeof(uint32_t); -// unsigned data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t); -// memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len); + // Permanently update values written to the efuse write registers + // It is necessary to process blocks in the order from MAX-> EFUSE_BLK0, because EFUSE_BLK0 has protection bits for other blocks. + for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) { + bool need_burn_block = false; + for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { + if (REG_READ(addr_wr_block) != 0) { + need_burn_block = true; + break; + } + } + if (!need_burn_block) { + continue; + } + if (error) { + // It is done for a use case: BLOCK2 (Flash encryption key) could have an error (incorrect written data) + // in this case we can not burn any data into BLOCK0 because it might set read/write protections of BLOCK2. + ESP_LOGE(TAG, "BLOCK%d can not be burned because a previous block got an error, skipped.", num_block); + continue; + } + efuse_hal_clear_program_registers(); + if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { + uint8_t block_rs[12]; + efuse_hal_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs); + hal_memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs)); + } + unsigned r_data_len = (range_read_addr_blocks[num_block].end - range_read_addr_blocks[num_block].start) + sizeof(uint32_t); + unsigned data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t); + memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len); -// uint32_t backup_write_data[8 + 3]; // 8 words are data and 3 words are RS coding data -// hal_memcpy(backup_write_data, (void *)EFUSE_PGM_DATA0_REG, sizeof(backup_write_data)); -// int repeat_burn_op = 1; -// bool correct_written_data; -// bool coding_error_before = efuse_hal_is_coding_error_in_block(num_block); -// if (coding_error_before) { -// ESP_LOGW(TAG, "BLOCK%d already has a coding error", num_block); -// } -// bool coding_error_occurred; + uint32_t backup_write_data[8 + 3]; // 8 words are data and 3 words are RS coding data + hal_memcpy(backup_write_data, (void *)EFUSE_PGM_DATA0_REG, sizeof(backup_write_data)); + int repeat_burn_op = 1; + bool correct_written_data; + bool coding_error_before = !ignore_coding_errors && efuse_hal_is_coding_error_in_block(num_block); + if (coding_error_before) { + ESP_LOGW(TAG, "BLOCK%d already has a coding error", num_block); + } + bool coding_error_occurred; -// do { -// ESP_LOGI(TAG, "BURN BLOCK%d", num_block); -// efuse_hal_program(num_block); // BURN a block + do { + ESP_LOGI(TAG, "BURN BLOCK%d", num_block); + efuse_hal_program(num_block); // BURN a block -// bool coding_error_after; -// for (unsigned i = 0; i < 5; i++) { -// efuse_hal_read(); -// coding_error_after = efuse_hal_is_coding_error_in_block(num_block); -// if (coding_error_after == true) { -// break; -// } -// } -// coding_error_occurred = (coding_error_before != coding_error_after) && coding_error_before == false; -// if (coding_error_occurred) { -// ESP_LOGW(TAG, "BLOCK%d got a coding error", num_block); -// } + bool coding_error_after; + for (unsigned i = 0; i < 5; i++) { + efuse_hal_read(); + coding_error_after = efuse_hal_is_coding_error_in_block(num_block); + if (coding_error_after == true) { + break; + } + } + coding_error_occurred = !ignore_coding_errors && (coding_error_before != coding_error_after) && !coding_error_before; + if (coding_error_occurred) { + ESP_LOGW(TAG, "BLOCK%d got a coding error", num_block); + } -// correct_written_data = esp_efuse_utility_is_correct_written_data(num_block, r_data_len); -// if (!correct_written_data || coding_error_occurred) { -// ESP_LOGW(TAG, "BLOCK%d: next retry to fix an error [%d/3]...", num_block, repeat_burn_op); -// hal_memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)backup_write_data, sizeof(backup_write_data)); -// } + correct_written_data = (verify_written_data) ? esp_efuse_utility_is_correct_written_data(num_block, r_data_len) : true; + if (!correct_written_data || coding_error_occurred) { + ESP_LOGW(TAG, "BLOCK%d: next retry to fix an error [%d/3]...", num_block, repeat_burn_op); + hal_memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)backup_write_data, sizeof(backup_write_data)); + } -// } while ((!correct_written_data || coding_error_occurred) && repeat_burn_op++ < 3); + } while ((!correct_written_data || coding_error_occurred) && repeat_burn_op++ < 3); -// if (coding_error_occurred) { -// ESP_LOGW(TAG, "Coding error was not fixed"); -// if (num_block == 0) { -// ESP_LOGE(TAG, "BLOCK0 got a coding error, which might be critical for security"); -// error = ESP_FAIL; -// } -// } -// if (!correct_written_data) { -// ESP_LOGE(TAG, "Written data are incorrect"); -// error = ESP_FAIL; -// } -// } + if (coding_error_occurred) { + ESP_LOGW(TAG, "Coding error was not fixed"); + if (num_block == 0) { + ESP_LOGE(TAG, "BLOCK0 got a coding error, which might be critical for security"); + error = ESP_FAIL; + } + } + if (!correct_written_data) { + ESP_LOGE(TAG, "Written data are incorrect"); + error = ESP_FAIL; + } + } } #endif // CONFIG_EFUSE_VIRTUAL -// esp_efuse_utility_reset(); + esp_efuse_utility_reset(); return error; } @@ -193,24 +187,22 @@ esp_err_t esp_efuse_utility_burn_chip_opt(bool ignore_coding_errors, bool verify // They will be filled during the burn operation. esp_err_t esp_efuse_utility_apply_new_coding_scheme() { - // TODO: [ESP32C5] IDF-8674 - abort(); - // // start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE. - // for (int num_block = EFUSE_BLK1; num_block < EFUSE_BLK_MAX; num_block++) { - // if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { - // for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { - // if (REG_READ(addr_wr_block)) { - // int num_reg = 0; - // for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) { - // if (esp_efuse_utility_read_reg(num_block, num_reg)) { - // ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden."); - // return ESP_ERR_CODING; - // } - // } - // break; - // } - // } - // } - // } + // start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE. + for (int num_block = EFUSE_BLK1; num_block < EFUSE_BLK_MAX; num_block++) { + if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { + for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { + if (REG_READ(addr_wr_block)) { + int num_reg = 0; + for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) { + if (esp_efuse_utility_read_reg(num_block, num_reg)) { + ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden."); + return ESP_ERR_CODING; + } + } + break; + } + } + } + } return ESP_OK; } diff --git a/components/efuse/esp32c5/include/esp_efuse_chip.h b/components/efuse/esp32c5/include/esp_efuse_chip.h index c0f9ecb170..4950badde9 100644 --- a/components/efuse/esp32c5/include/esp_efuse_chip.h +++ b/components/efuse/esp32c5/include/esp_efuse_chip.h @@ -10,8 +10,6 @@ extern "C" { #endif -// TODO: [ESP32C5] IDF-8674 - /** * @brief Type of eFuse blocks ESP32C5 */ @@ -64,7 +62,7 @@ typedef enum { */ typedef enum { ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */ - ESP_EFUSE_KEY_PURPOSE_RESERVED = 1, /**< Reserved */ + ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, /**< ECDSA private key (Expected in little endian order)*/ ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */ ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, /**< HMAC Downstream mode */ ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, /**< JTAG soft enable key (uses HMAC Downstream mode) */ diff --git a/components/efuse/esp32c5/include/esp_efuse_rtc_calib.h b/components/efuse/esp32c5/include/esp_efuse_rtc_calib.h index b31cab7672..392a09d49a 100644 --- a/components/efuse/esp32c5/include/esp_efuse_rtc_calib.h +++ b/components/efuse/esp32c5/include/esp_efuse_rtc_calib.h @@ -11,7 +11,7 @@ extern "C" { #endif -// TODO: [ESP32C5] IDF-8674, IDF-8702 +// TODO: [ESP32C5] IDF-8702 //This is the ADC calibration value version burnt in efuse #define ESP_EFUSE_ADC_CALIB_VER1 1 diff --git a/components/efuse/esp32c5/include/esp_efuse_table.h b/components/efuse/esp32c5/include/esp_efuse_table.h index f2f652f101..9da2fda348 100644 --- a/components/efuse/esp32c5/include/esp_efuse_table.h +++ b/components/efuse/esp32c5/include/esp_efuse_table.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,9 +10,7 @@ extern "C" { #include "esp_efuse.h" -// TODO: [ESP32C5] IDF-8674 - -// md5_digest_table fd5a35cea89bfad954e834bc92bed385 +// md5_digest_table eb005412b657c9be0ce4bb699e5813c9 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -21,15 +19,10 @@ extern "C" { extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SWAP_UART_SDIO_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[]; -#define ESP_EFUSE_WR_DIS_DIS_CAN ESP_EFUSE_WR_DIS_DIS_TWAI extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; @@ -51,7 +44,6 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[]; #define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[]; -#define ESP_EFUSE_WR_DIS_DPA_SEC_LEVEL ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[]; @@ -59,46 +51,18 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; -#define ESP_EFUSE_WR_DIS_DIS_USB_PRINT ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; #define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH6[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[]; #define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; @@ -136,21 +100,22 @@ extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[]; #define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5 extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[]; #define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2 -extern const esp_efuse_desc_t* ESP_EFUSE_SWAP_UART_SDIO_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[]; -#define ESP_EFUSE_DIS_CAN ESP_EFUSE_DIS_TWAI extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[]; extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[]; extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[]; @@ -169,52 +134,32 @@ extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; #define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5 extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[]; -#define ESP_EFUSE_DPA_SEC_LEVEL ESP_EFUSE_SEC_DPA_LEVEL -extern const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KM_XTS_KEY_LENGTH_256[]; extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; -#define ESP_EFUSE_DIS_USB_PRINT ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT +extern const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_HUK_GEN_STATE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_XTAL_48M_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_XTAL_48M_SEL_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_DISABLE_P192[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[]; extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; #define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; -extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[]; -extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH6[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK_SYS_DATA1[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; #define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; diff --git a/components/efuse/esp32c61/esp_efuse_fields.c b/components/efuse/esp32c61/esp_efuse_fields.c index 223fab34e3..8d376b672f 100644 --- a/components/efuse/esp32c61/esp_efuse_fields.c +++ b/components/efuse/esp32c61/esp_efuse_fields.c @@ -23,7 +23,9 @@ static __attribute__((unused)) const char *TAG = "efuse"; uint32_t esp_efuse_get_pkg_ver(void) { uint32_t pkg_ver = 0; +#ifdef EFUSE_PKG_VERSION esp_efuse_read_field_blob(ESP_EFUSE_PKG_VERSION, &pkg_ver, ESP_EFUSE_PKG_VERSION[0]->bit_count); +#endif return pkg_ver; } diff --git a/components/efuse/esp32c61/esp_efuse_rtc_calib.c b/components/efuse/esp32c61/esp_efuse_rtc_calib.c index 3980b3c9b3..1146540149 100644 --- a/components/efuse/esp32c61/esp_efuse_rtc_calib.c +++ b/components/efuse/esp32c61/esp_efuse_rtc_calib.c @@ -20,119 +20,38 @@ int esp_efuse_rtc_calib_get_ver(void) { uint32_t cali_version = 0; - uint32_t blk_ver = efuse_hal_blk_version(); - if (blk_ver == 1) { - cali_version = ESP_EFUSE_ADC_CALIB_VER1; - } else if (blk_ver >= 2) { - cali_version = ESP_EFUSE_ADC_CALIB_VER2; - } else { - ESP_LOGW("eFuse", "calibration efuse version does not match, set default version to 0"); - } + // TODO: [ESP32C61] IDF-9303 + abort(); return cali_version; } uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten) { - /* Version validation should be guaranteed in the caller */ - assert(atten >=0 && atten < 4); - (void) adc_unit; - - const esp_efuse_desc_t** init_code_efuse; - if (atten == 0) { - init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0; - } else if (atten == 1) { - init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN1; - } else if (atten == 2) { - init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN2; - } else { - init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN3; - } - - int init_code_size = esp_efuse_get_field_size(init_code_efuse); - assert(init_code_size == 10); - - uint32_t init_code = 0; - ESP_ERROR_CHECK(esp_efuse_read_field_blob(init_code_efuse, &init_code, init_code_size)); - return init_code + 1600; // version 1 logic + // TODO: [ESP32C61] IDF-9303 + abort(); + return 0; } int esp_efuse_rtc_calib_get_chan_compens(int version, uint32_t adc_unit, uint32_t adc_channel, int atten) { - /* Version validation should be guaranteed in the caller */ - assert(atten < 4); - assert(adc_channel < SOC_ADC_CHANNEL_NUM(adc_unit)); - - const esp_efuse_desc_t** chan_diff_efuse = NULL; - switch (adc_channel) { - case 0: - chan_diff_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH0; - break; - case 1: - chan_diff_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH1; - break; - case 2: - chan_diff_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH2; - break; - case 3: - chan_diff_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH3; - break; - case 4: - chan_diff_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH4; - break; - case 5: - chan_diff_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH5; - break; - default: - chan_diff_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH6; - break; - } - - int chan_diff_size = esp_efuse_get_field_size(chan_diff_efuse); - assert(chan_diff_size == 4); - uint32_t chan_diff = 0; - ESP_ERROR_CHECK(esp_efuse_read_field_blob(chan_diff_efuse, &chan_diff, chan_diff_size)); - return RTC_CALIB_GET_SIGNED_VAL(chan_diff, 3) * (4 - atten); + // TODO: [ESP32C61] IDF-9303 + abort(); + return 0; } esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, uint32_t adc_unit, int atten, uint32_t* out_digi, uint32_t* out_vol_mv) { - (void) adc_unit; - const esp_efuse_desc_t** cal_vol_efuse[4] = { - ESP_EFUSE_ADC1_CAL_VOL_ATTEN0, - ESP_EFUSE_ADC1_CAL_VOL_ATTEN1, - ESP_EFUSE_ADC1_CAL_VOL_ATTEN2, - ESP_EFUSE_ADC1_CAL_VOL_ATTEN3, - }; - const uint32_t input_vout_mv[2][4] = { - {400, 550, 750, 1370}, // Calibration V1 coefficients - {750, 1000, 1500, 2800}, // Calibration V2 coefficients - }; - - if ((version < ESP_EFUSE_ADC_CALIB_VER_MIN) || - (version > ESP_EFUSE_ADC_CALIB_VER_MAX)) { - return ESP_ERR_INVALID_ARG; - } - if (atten >= 4 || atten < 0) { - return ESP_ERR_INVALID_ARG; - } - - assert(cal_vol_efuse[atten][0]->bit_count == 10); - - uint32_t cal_vol = 0; - esp_err_t ret = esp_efuse_read_field_blob(cal_vol_efuse[atten], &cal_vol, cal_vol_efuse[atten][0]->bit_count); - if (ret != ESP_OK) { - return ret; - } - uint32_t chk_offset = (version == ESP_EFUSE_ADC_CALIB_VER1) ? 1500 : (atten == 2) ? 2900 : 2850; - *out_digi = chk_offset + RTC_CALIB_GET_SIGNED_VAL(cal_vol, 9); - *out_vol_mv = input_vout_mv[VER2IDX(version)][atten]; + // TODO: [ESP32C61] IDF-9303 + abort(); return ESP_OK; } esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal) { - // Currently calibration is not supported on ESP32-C6, IDF-5236 + // TODO: [ESP32C61] IDF-9303 + abort(); + // Currently calibration is not supported on ESP32-C5, IDF-5236 *tsens_cal = 0; return ESP_OK; } diff --git a/components/efuse/esp32c61/esp_efuse_table.c b/components/efuse/esp32c61/esp_efuse_table.c index a0f5eb430d..f5245687fb 100644 --- a/components/efuse/esp32c61/esp_efuse_table.c +++ b/components/efuse/esp32c61/esp_efuse_table.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,9 +9,7 @@ #include #include "esp_efuse_table.h" -// TODO: [ESP32C61] IDF-9282, file inherit from verify code, pls check - -// md5_digest_table 873c3e466a4c31bca2e00afae2073f94 +// md5_digest_table 604cf47a9075de209e7b488c4c6a3cd6 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -25,14 +23,6 @@ static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { {EFUSE_BLK0, 0, 1}, // [] wr_dis of RD_DIS, }; -static const esp_efuse_desc_t WR_DIS_CRYPT_DPA_ENABLE[] = { - {EFUSE_BLK0, 1, 1}, // [] wr_dis of CRYPT_DPA_ENABLE, -}; - -static const esp_efuse_desc_t WR_DIS_SWAP_UART_SDIO_EN[] = { - {EFUSE_BLK0, 2, 1}, // [] wr_dis of SWAP_UART_SDIO_EN, -}; - static const esp_efuse_desc_t WR_DIS_DIS_ICACHE[] = { {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_ICACHE, }; @@ -41,22 +31,10 @@ static const esp_efuse_desc_t WR_DIS_DIS_USB_JTAG[] = { {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_USB_JTAG, }; -static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_ICACHE[] = { - {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_ICACHE, -}; - -static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG[] = { - {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_USB_SERIAL_JTAG, -}; - static const esp_efuse_desc_t WR_DIS_DIS_FORCE_DOWNLOAD[] = { {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_FORCE_DOWNLOAD, }; -static const esp_efuse_desc_t WR_DIS_DIS_TWAI[] = { - {EFUSE_BLK0, 2, 1}, // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI, -}; - static const esp_efuse_desc_t WR_DIS_JTAG_SEL_ENABLE[] = { {EFUSE_BLK0, 2, 1}, // [] wr_dis of JTAG_SEL_ENABLE, }; @@ -114,7 +92,7 @@ static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5[] = { }; static const esp_efuse_desc_t WR_DIS_SEC_DPA_LEVEL[] = { - {EFUSE_BLK0, 14, 1}, // [WR_DIS.DPA_SEC_LEVEL] wr_dis of SEC_DPA_LEVEL, + {EFUSE_BLK0, 14, 1}, // [] wr_dis of SEC_DPA_LEVEL, }; static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = { @@ -142,7 +120,7 @@ static const esp_efuse_desc_t WR_DIS_DIS_DIRECT_BOOT[] = { }; static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - {EFUSE_BLK0, 18, 1}, // [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT, + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT, }; static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { @@ -169,14 +147,6 @@ static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { {EFUSE_BLK0, 19, 1}, // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE, }; -static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK0, 19, 1}, // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR, -}; - -static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { - {EFUSE_BLK0, 19, 1}, // [] wr_dis of DISABLE_BLK_VERSION_MAJOR, -}; - static const esp_efuse_desc_t WR_DIS_BLK1[] = { {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLOCK1, }; @@ -185,116 +155,12 @@ static const esp_efuse_desc_t WR_DIS_MAC[] = { {EFUSE_BLK0, 20, 1}, // [WR_DIS.MAC_FACTORY] wr_dis of MAC, }; -static const esp_efuse_desc_t WR_DIS_MAC_EXT[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of MAC_EXT, -}; - -static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR, -}; - -static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MAJOR, -}; - -static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of PKG_VERSION, -}; - -static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MINOR, -}; - -static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MAJOR, -}; - -static const esp_efuse_desc_t WR_DIS_FLASH_CAP[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_CAP, -}; - -static const esp_efuse_desc_t WR_DIS_FLASH_TEMP[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_TEMP, -}; - -static const esp_efuse_desc_t WR_DIS_FLASH_VENDOR[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_VENDOR, -}; - static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2, }; -static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID, -}; - -static const esp_efuse_desc_t WR_DIS_TEMP_CALIB[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of TEMP_CALIB, -}; - -static const esp_efuse_desc_t WR_DIS_OCODE[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of OCODE, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN1[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN1, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN2[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN2, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN3[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN3, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN0[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN0, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN1[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN1, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN2[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN2, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN3[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN3, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH0[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH0, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH1[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH1, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH2[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH2, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH3[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH3, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH4[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH4, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH5[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH5, -}; - -static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH6[] = { - {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH6, +static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK_SYS_DATA1, }; static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = { @@ -341,10 +207,6 @@ static const esp_efuse_desc_t WR_DIS_VDD_SPI_AS_GPIO[] = { {EFUSE_BLK0, 30, 1}, // [] wr_dis of VDD_SPI_AS_GPIO, }; -static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG[] = { - {EFUSE_BLK0, 31, 1}, // [] wr_dis of SOFT_DIS_JTAG, -}; - static const esp_efuse_desc_t RD_DIS[] = { {EFUSE_BLK0, 32, 7}, // [] Disable reading from BlOCK4-10, }; @@ -378,55 +240,43 @@ static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = { }; static const esp_efuse_desc_t DIS_ICACHE[] = { - {EFUSE_BLK0, 39, 1}, // [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 39, 1}, // [] Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled, }; static const esp_efuse_desc_t DIS_USB_JTAG[] = { - {EFUSE_BLK0, 40, 1}, // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled, -}; - -static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG[] = { - {EFUSE_BLK0, 41, 1}, // [] Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 40, 1}, // [] Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled, }; static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = { - {EFUSE_BLK0, 42, 1}, // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 42, 1}, // [] Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled, }; static const esp_efuse_desc_t SPI_DOWNLOAD_MSPI_DIS[] = { - {EFUSE_BLK0, 43, 1}, // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 43, 1}, // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled, }; static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = { - {EFUSE_BLK0, 44, 1}, // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled, + {EFUSE_BLK0, 44, 1}, // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled, }; static const esp_efuse_desc_t DIS_PAD_JTAG[] = { - {EFUSE_BLK0, 45, 1}, // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled, + {EFUSE_BLK0, 45, 1}, // [] Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled, }; static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - {EFUSE_BLK0, 46, 1}, // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled, -}; - -static const esp_efuse_desc_t USB_DREFH[] = { - {EFUSE_BLK0, 47, 2}, // [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged, -}; - -static const esp_efuse_desc_t USB_DREFL[] = { - {EFUSE_BLK0, 49, 2}, // [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned, + {EFUSE_BLK0, 46, 1}, // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled, }; static const esp_efuse_desc_t USB_EXCHG_PINS[] = { - {EFUSE_BLK0, 51, 1}, // [] Represents whether the D+ and D- pins is exchanged., + {EFUSE_BLK0, 51, 1}, // [] Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged, }; static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = { - {EFUSE_BLK0, 52, 1}, // [] vdd spi as gpio, + {EFUSE_BLK0, 52, 1}, // [] Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned, }; static const esp_efuse_desc_t WDT_DELAY_SEL[] = { - {EFUSE_BLK0, 53, 2}, // [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected, + {EFUSE_BLK0, 53, 2}, // [] Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16, }; static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { @@ -470,47 +320,47 @@ static const esp_efuse_desc_t KEY_PURPOSE_5[] = { }; static const esp_efuse_desc_t SEC_DPA_LEVEL[] = { - {EFUSE_BLK0, 88, 2}, // [DPA_SEC_LEVEL] Represents the spa secure level by configuring the clock random divide mode, + {EFUSE_BLK0, 88, 2}, // [] Represents the spa secure level by configuring the clock random divide mode, }; static const esp_efuse_desc_t SECURE_BOOT_EN[] = { - {EFUSE_BLK0, 90, 1}, // [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled, + {EFUSE_BLK0, 90, 1}, // [] Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled, }; static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - {EFUSE_BLK0, 91, 1}, // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled, + {EFUSE_BLK0, 91, 1}, // [] Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled, }; static const esp_efuse_desc_t FLASH_TPUW[] = { - {EFUSE_BLK0, 92, 4}, // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value, + {EFUSE_BLK0, 92, 4}, // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is programmed value. Otherwise; the waiting time is 2 times the programmed value, }; static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 96, 1}, // [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 96, 1}, // [] Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable, }; static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = { - {EFUSE_BLK0, 97, 1}, // [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 97, 1}, // [] Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0: Enable, }; static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - {EFUSE_BLK0, 98, 1}, // [DIS_USB_PRINT] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 98, 1}, // [] Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1. Disable\\ 0: Enable, }; static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 99, 1}, // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 99, 1}, // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable, }; static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { - {EFUSE_BLK0, 100, 1}, // [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled, + {EFUSE_BLK0, 100, 1}, // [] Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0: Disable, }; static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { - {EFUSE_BLK0, 101, 2}, // [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"}, + {EFUSE_BLK0, 101, 2}, // [] Represents the types of UART printing, }; static const esp_efuse_desc_t FORCE_SEND_RESUME[] = { - {EFUSE_BLK0, 103, 1}, // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced, + {EFUSE_BLK0, 103, 1}, // [] Represents whether ROM code is forced to send a resume commmand during SPI boot, }; static const esp_efuse_desc_t SECURE_VERSION[] = { @@ -518,19 +368,31 @@ static const esp_efuse_desc_t SECURE_VERSION[] = { }; static const esp_efuse_desc_t SECURE_BOOT_DISABLE_FAST_WAKE[] = { - {EFUSE_BLK0, 120, 1}, // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled, + {EFUSE_BLK0, 120, 1}, // [] Represents whether FAST_VERIFY_ON_WAKE is disable or enable when Secure Boot is enable, }; static const esp_efuse_desc_t HYS_EN_PAD[] = { - {EFUSE_BLK0, 121, 1}, // [] Disables check of wafer version major, + {EFUSE_BLK0, 121, 1}, // [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled, }; static const esp_efuse_desc_t XTS_DPA_CLK_ENABLE[] = { - {EFUSE_BLK0, 122, 1}, // [] Disables check of blk version major, + {EFUSE_BLK0, 122, 1}, // [] Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0: Disable, }; static const esp_efuse_desc_t XTS_DPA_PSEUDO_LEVEL[] = { - {EFUSE_BLK0, 123, 1}, // [] Represents the anti-dpa attack pseudo function level., + {EFUSE_BLK0, 123, 2}, // [] Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1: Low\\ 0: Decided by register configuration, +}; + +static const esp_efuse_desc_t DIS_WIFI6[] = { + {EFUSE_BLK0, 125, 1}, // [] Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is disable\\ 0: WiFi 6 is enabled., +}; + +static const esp_efuse_desc_t ECDSA_DISABLE_P192[] = { + {EFUSE_BLK0, 126, 1}, // [] Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable, +}; + +static const esp_efuse_desc_t ECC_FORCE_CONST_TIME[] = { + {EFUSE_BLK0, 127, 1}, // [] Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable, }; static const esp_efuse_desc_t MAC[] = { @@ -542,113 +404,8 @@ static const esp_efuse_desc_t MAC[] = { {EFUSE_BLK1, 0, 8}, // [MAC_FACTORY] MAC address, }; -static const esp_efuse_desc_t MAC_EXT[] = { - {EFUSE_BLK1, 56, 8}, // [] Stores the extended bits of MAC address, - {EFUSE_BLK1, 48, 8}, // [] Stores the extended bits of MAC address, -}; - -static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { - {EFUSE_BLK1, 114, 4}, // [], -}; - -static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { - {EFUSE_BLK1, 118, 2}, // [], -}; - -static const esp_efuse_desc_t PKG_VERSION[] = { - {EFUSE_BLK1, 120, 3}, // [] Package version, -}; - -static const esp_efuse_desc_t BLK_VERSION_MINOR[] = { - {EFUSE_BLK1, 123, 3}, // [] BLK_VERSION_MINOR of BLOCK2, -}; - -static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { - {EFUSE_BLK1, 126, 2}, // [] BLK_VERSION_MAJOR of BLOCK2, -}; - -static const esp_efuse_desc_t FLASH_CAP[] = { - {EFUSE_BLK1, 128, 3}, // [], -}; - -static const esp_efuse_desc_t FLASH_TEMP[] = { - {EFUSE_BLK1, 131, 2}, // [], -}; - -static const esp_efuse_desc_t FLASH_VENDOR[] = { - {EFUSE_BLK1, 133, 3}, // [], -}; - -static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { - {EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID, -}; - -static const esp_efuse_desc_t TEMP_CALIB[] = { - {EFUSE_BLK2, 128, 9}, // [] Temperature calibration data, -}; - -static const esp_efuse_desc_t OCODE[] = { - {EFUSE_BLK2, 137, 8}, // [] ADC OCode, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = { - {EFUSE_BLK2, 145, 10}, // [] ADC1 init code at atten0, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = { - {EFUSE_BLK2, 155, 10}, // [] ADC1 init code at atten1, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = { - {EFUSE_BLK2, 165, 10}, // [] ADC1 init code at atten2, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = { - {EFUSE_BLK2, 175, 10}, // [] ADC1 init code at atten3, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = { - {EFUSE_BLK2, 185, 10}, // [] ADC1 calibration voltage at atten0, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = { - {EFUSE_BLK2, 195, 10}, // [] ADC1 calibration voltage at atten1, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = { - {EFUSE_BLK2, 205, 10}, // [] ADC1 calibration voltage at atten2, -}; - -static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = { - {EFUSE_BLK2, 215, 10}, // [] ADC1 calibration voltage at atten3, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH0[] = { - {EFUSE_BLK2, 225, 4}, // [] ADC1 init code at atten0 ch0, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH1[] = { - {EFUSE_BLK2, 229, 4}, // [] ADC1 init code at atten0 ch1, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH2[] = { - {EFUSE_BLK2, 233, 4}, // [] ADC1 init code at atten0 ch2, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH3[] = { - {EFUSE_BLK2, 237, 4}, // [] ADC1 init code at atten0 ch3, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH4[] = { - {EFUSE_BLK2, 241, 4}, // [] ADC1 init code at atten0 ch4, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH5[] = { - {EFUSE_BLK2, 245, 4}, // [] ADC1 init code at atten0 ch5, -}; - -static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH6[] = { - {EFUSE_BLK2, 249, 4}, // [] ADC1 init code at atten0 ch6, +static const esp_efuse_desc_t BLOCK_SYS_DATA1[] = { + {EFUSE_BLK2, 0, 256}, // [] System data part 1 (reserved), }; static const esp_efuse_desc_t USER_DATA[] = { @@ -701,16 +458,6 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[] = { - &WR_DIS_CRYPT_DPA_ENABLE[0], // [] wr_dis of CRYPT_DPA_ENABLE - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SWAP_UART_SDIO_EN[] = { - &WR_DIS_SWAP_UART_SDIO_EN[0], // [] wr_dis of SWAP_UART_SDIO_EN - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[] = { &WR_DIS_DIS_ICACHE[0], // [] wr_dis of DIS_ICACHE NULL @@ -721,26 +468,11 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[] = { - &WR_DIS_DIS_DOWNLOAD_ICACHE[0], // [] wr_dis of DIS_DOWNLOAD_ICACHE - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG[] = { - &WR_DIS_DIS_USB_SERIAL_JTAG[0], // [] wr_dis of DIS_USB_SERIAL_JTAG - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[] = { &WR_DIS_DIS_FORCE_DOWNLOAD[0], // [] wr_dis of DIS_FORCE_DOWNLOAD NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[] = { - &WR_DIS_DIS_TWAI[0], // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[] = { &WR_DIS_JTAG_SEL_ENABLE[0], // [] wr_dis of JTAG_SEL_ENABLE NULL @@ -812,7 +544,7 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[] = { }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[] = { - &WR_DIS_SEC_DPA_LEVEL[0], // [WR_DIS.DPA_SEC_LEVEL] wr_dis of SEC_DPA_LEVEL + &WR_DIS_SEC_DPA_LEVEL[0], // [] wr_dis of SEC_DPA_LEVEL NULL }; @@ -847,7 +579,7 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[] = { }; const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - &WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT + &WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT NULL }; @@ -881,16 +613,6 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { - &WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0], // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { - &WR_DIS_DISABLE_BLK_VERSION_MAJOR[0], // [] wr_dis of DISABLE_BLK_VERSION_MAJOR - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = { &WR_DIS_BLK1[0], // [] wr_dis of BLOCK1 NULL @@ -901,143 +623,13 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[] = { - &WR_DIS_MAC_EXT[0], // [] wr_dis of MAC_EXT - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[] = { - &WR_DIS_WAFER_VERSION_MINOR[0], // [] wr_dis of WAFER_VERSION_MINOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[] = { - &WR_DIS_WAFER_VERSION_MAJOR[0], // [] wr_dis of WAFER_VERSION_MAJOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = { - &WR_DIS_PKG_VERSION[0], // [] wr_dis of PKG_VERSION - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = { - &WR_DIS_BLK_VERSION_MINOR[0], // [] wr_dis of BLK_VERSION_MINOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = { - &WR_DIS_BLK_VERSION_MAJOR[0], // [] wr_dis of BLK_VERSION_MAJOR - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[] = { - &WR_DIS_FLASH_CAP[0], // [] wr_dis of FLASH_CAP - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[] = { - &WR_DIS_FLASH_TEMP[0], // [] wr_dis of FLASH_TEMP - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[] = { - &WR_DIS_FLASH_VENDOR[0], // [] wr_dis of FLASH_VENDOR - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { &WR_DIS_SYS_DATA_PART1[0], // [] wr_dis of BLOCK2 NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = { - &WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[] = { - &WR_DIS_TEMP_CALIB[0], // [] wr_dis of TEMP_CALIB - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[] = { - &WR_DIS_OCODE[0], // [] wr_dis of OCODE - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN0[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN1[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN2[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN3[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[] = { - &WR_DIS_ADC1_CAL_VOL_ATTEN0[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[] = { - &WR_DIS_ADC1_CAL_VOL_ATTEN1[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[] = { - &WR_DIS_ADC1_CAL_VOL_ATTEN2[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[] = { - &WR_DIS_ADC1_CAL_VOL_ATTEN3[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH0[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH0[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH1[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH1[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH2[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH2[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH3[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH3[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH4[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH4[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH4 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH5[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH5[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH5 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH6[] = { - &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH6[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH6 +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA1[] = { + &WR_DIS_BLOCK_SYS_DATA1[0], // [] wr_dis of BLOCK_SYS_DATA1 NULL }; @@ -1096,11 +688,6 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_AS_GPIO[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = { - &WR_DIS_SOFT_DIS_JTAG[0], // [] wr_dis of SOFT_DIS_JTAG - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = { &RD_DIS[0], // [] Disable reading from BlOCK4-10 NULL @@ -1142,67 +729,52 @@ const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = { }; const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { - &DIS_ICACHE[0], // [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled + &DIS_ICACHE[0], // [] Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = { - &DIS_USB_JTAG[0], // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[] = { - &DIS_USB_SERIAL_JTAG[0], // [] Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled + &DIS_USB_JTAG[0], // [] Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = { - &DIS_FORCE_DOWNLOAD[0], // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled + &DIS_FORCE_DOWNLOAD[0], // [] Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[] = { - &SPI_DOWNLOAD_MSPI_DIS[0], // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled + &SPI_DOWNLOAD_MSPI_DIS[0], // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = { - &JTAG_SEL_ENABLE[0], // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled + &JTAG_SEL_ENABLE[0], // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = { - &DIS_PAD_JTAG[0], // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled + &DIS_PAD_JTAG[0], // [] Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[] = { - &USB_DREFH[0], // [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[] = { - &USB_DREFL[0], // [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned + &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = { - &USB_EXCHG_PINS[0], // [] Represents whether the D+ and D- pins is exchanged. + &USB_EXCHG_PINS[0], // [] Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged NULL }; const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = { - &VDD_SPI_AS_GPIO[0], // [] vdd spi as gpio + &VDD_SPI_AS_GPIO[0], // [] Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned NULL }; const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { - &WDT_DELAY_SEL[0], // [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected + &WDT_DELAY_SEL[0], // [] Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16 NULL }; @@ -1257,57 +829,57 @@ const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = { }; const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = { - &SEC_DPA_LEVEL[0], // [DPA_SEC_LEVEL] Represents the spa secure level by configuring the clock random divide mode + &SEC_DPA_LEVEL[0], // [] Represents the spa secure level by configuring the clock random divide mode NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { - &SECURE_BOOT_EN[0], // [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled + &SECURE_BOOT_EN[0], // [] Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled + &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = { - &FLASH_TPUW[0], // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value + &FLASH_TPUW[0], // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is programmed value. Otherwise; the waiting time is 2 times the programmed value NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { - &DIS_DOWNLOAD_MODE[0], // [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled + &DIS_DOWNLOAD_MODE[0], // [] Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = { - &DIS_DIRECT_BOOT[0], // [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled + &DIS_DIRECT_BOOT[0], // [] Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0: Enable NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [DIS_USB_PRINT] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled + &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [] Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1. Disable\\ 0: Enable NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled + &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable NULL }; const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { - &ENABLE_SECURITY_DOWNLOAD[0], // [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled + &ENABLE_SECURITY_DOWNLOAD[0], // [] Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0: Disable NULL }; const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = { - &UART_PRINT_CONTROL[0], // [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"} + &UART_PRINT_CONTROL[0], // [] Represents the types of UART printing NULL }; const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = { - &FORCE_SEND_RESUME[0], // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced + &FORCE_SEND_RESUME[0], // [] Represents whether ROM code is forced to send a resume commmand during SPI boot NULL }; @@ -1317,22 +889,37 @@ const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[] = { - &SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled + &SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] Represents whether FAST_VERIFY_ON_WAKE is disable or enable when Secure Boot is enable NULL }; const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[] = { - &HYS_EN_PAD[0], // [] Disables check of wafer version major + &HYS_EN_PAD[0], // [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[] = { - &XTS_DPA_CLK_ENABLE[0], // [] Disables check of blk version major + &XTS_DPA_CLK_ENABLE[0], // [] Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0: Disable NULL }; const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[] = { - &XTS_DPA_PSEUDO_LEVEL[0], // [] Represents the anti-dpa attack pseudo function level. + &XTS_DPA_PSEUDO_LEVEL[0], // [] Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1: Low\\ 0: Decided by register configuration + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_WIFI6[] = { + &DIS_WIFI6[0], // [] Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is disable\\ 0: WiFi 6 is enabled. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ECDSA_DISABLE_P192[] = { + &ECDSA_DISABLE_P192[0], // [] Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[] = { + &ECC_FORCE_CONST_TIME[0], // [] Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable NULL }; @@ -1346,139 +933,8 @@ const esp_efuse_desc_t* ESP_EFUSE_MAC[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = { - &MAC_EXT[0], // [] Stores the extended bits of MAC address - &MAC_EXT[1], // [] Stores the extended bits of MAC address - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { - &WAFER_VERSION_MINOR[0], // [] - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { - &WAFER_VERSION_MAJOR[0], // [] - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { - &PKG_VERSION[0], // [] Package version - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = { - &BLK_VERSION_MINOR[0], // [] BLK_VERSION_MINOR of BLOCK2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { - &BLK_VERSION_MAJOR[0], // [] BLK_VERSION_MAJOR of BLOCK2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = { - &FLASH_CAP[0], // [] - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[] = { - &FLASH_TEMP[0], // [] - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = { - &FLASH_VENDOR[0], // [] - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { - &OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = { - &TEMP_CALIB[0], // [] Temperature calibration data - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { - &OCODE[0], // [] ADC OCode - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = { - &ADC1_INIT_CODE_ATTEN0[0], // [] ADC1 init code at atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = { - &ADC1_INIT_CODE_ATTEN1[0], // [] ADC1 init code at atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = { - &ADC1_INIT_CODE_ATTEN2[0], // [] ADC1 init code at atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = { - &ADC1_INIT_CODE_ATTEN3[0], // [] ADC1 init code at atten3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = { - &ADC1_CAL_VOL_ATTEN0[0], // [] ADC1 calibration voltage at atten0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = { - &ADC1_CAL_VOL_ATTEN1[0], // [] ADC1 calibration voltage at atten1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = { - &ADC1_CAL_VOL_ATTEN2[0], // [] ADC1 calibration voltage at atten2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = { - &ADC1_CAL_VOL_ATTEN3[0], // [] ADC1 calibration voltage at atten3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH0[] = { - &ADC1_INIT_CODE_ATTEN0_CH0[0], // [] ADC1 init code at atten0 ch0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH1[] = { - &ADC1_INIT_CODE_ATTEN0_CH1[0], // [] ADC1 init code at atten0 ch1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH2[] = { - &ADC1_INIT_CODE_ATTEN0_CH2[0], // [] ADC1 init code at atten0 ch2 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH3[] = { - &ADC1_INIT_CODE_ATTEN0_CH3[0], // [] ADC1 init code at atten0 ch3 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH4[] = { - &ADC1_INIT_CODE_ATTEN0_CH4[0], // [] ADC1 init code at atten0 ch4 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH5[] = { - &ADC1_INIT_CODE_ATTEN0_CH5[0], // [] ADC1 init code at atten0 ch5 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH6[] = { - &ADC1_INIT_CODE_ATTEN0_CH6[0], // [] ADC1 init code at atten0 ch6 +const esp_efuse_desc_t* ESP_EFUSE_BLOCK_SYS_DATA1[] = { + &BLOCK_SYS_DATA1[0], // [] System data part 1 (reserved) NULL }; diff --git a/components/efuse/esp32c61/esp_efuse_table.csv b/components/efuse/esp32c61/esp_efuse_table.csv index c1dd66939d..3b415029bb 100644 --- a/components/efuse/esp32c61/esp_efuse_table.csv +++ b/components/efuse/esp32c61/esp_efuse_table.csv @@ -9,20 +9,13 @@ # this will generate new source files, next rebuild all the sources. # !!!!!!!!!!! # -# This file was generated by regtools.py based on the efuses.yaml file with the version: df46b69f0ed3913114ba53d3a0b2b843 - -# TODO: [ESP32C61] IDF-9282, file inherit from verify code, pls check +# This file was generated by regtools.py based on the efuses.yaml file with the version: beb6fa3bf4a43a464c3365fda28815f5 WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS -WR_DIS.CRYPT_DPA_ENABLE, EFUSE_BLK0, 1, 1, [] wr_dis of CRYPT_DPA_ENABLE -WR_DIS.SWAP_UART_SDIO_EN, EFUSE_BLK0, 2, 1, [] wr_dis of SWAP_UART_SDIO_EN WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG -WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE -WR_DIS.DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_SERIAL_JTAG WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD -WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT @@ -37,59 +30,24 @@ WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.K WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 -WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [WR_DIS.DPA_SEC_LEVEL] wr_dis of SEC_DPA_LEVEL +WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of SEC_DPA_LEVEL WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 17, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DIRECT_BOOT -WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT +WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 19, 1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE -WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR -WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1 WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC -WR_DIS.MAC_EXT, EFUSE_BLK0, 20, 1, [] wr_dis of MAC_EXT -WR_DIS.ACTIVE_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_HP_DBIAS -WR_DIS.ACTIVE_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_LP_DBIAS -WR_DIS.LSLP_HP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBG -WR_DIS.LSLP_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBIAS -WR_DIS.DSLP_LP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBG -WR_DIS.DSLP_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBIAS -WR_DIS.DBIAS_VOL_GAP, EFUSE_BLK0, 20, 1, [] wr_dis of DBIAS_VOL_GAP -WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR -WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR -WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION -WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR -WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR -WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP -WR_DIS.FLASH_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_TEMP -WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 -WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID -WR_DIS.TEMP_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIB -WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE -WR_DIS.ADC1_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0 -WR_DIS.ADC1_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN1 -WR_DIS.ADC1_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN2 -WR_DIS.ADC1_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN3 -WR_DIS.ADC1_CAL_VOL_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN0 -WR_DIS.ADC1_CAL_VOL_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN1 -WR_DIS.ADC1_CAL_VOL_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN2 -WR_DIS.ADC1_CAL_VOL_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN3 -WR_DIS.ADC1_INIT_CODE_ATTEN0_CH0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH0 -WR_DIS.ADC1_INIT_CODE_ATTEN0_CH1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH1 -WR_DIS.ADC1_INIT_CODE_ATTEN0_CH2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH2 -WR_DIS.ADC1_INIT_CODE_ATTEN0_CH3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH3 -WR_DIS.ADC1_INIT_CODE_ATTEN0_CH4, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH4 -WR_DIS.ADC1_INIT_CODE_ATTEN0_CH5, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH5 -WR_DIS.ADC1_INIT_CODE_ATTEN0_CH6, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH6 +WR_DIS.BLOCK_SYS_DATA1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK_SYS_DATA1 WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 @@ -101,7 +59,6 @@ WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.K WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS WR_DIS.VDD_SPI_AS_GPIO, EFUSE_BLK0, 30, 1, [] wr_dis of VDD_SPI_AS_GPIO -WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10 RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 @@ -110,19 +67,16 @@ RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.K RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 -DIS_ICACHE, EFUSE_BLK0, 39, 1, [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled -DIS_USB_JTAG, EFUSE_BLK0, 40, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled -DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 41, 1, [] Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled -DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 42, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled -SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 43, 1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled -JTAG_SEL_ENABLE, EFUSE_BLK0, 44, 1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled -DIS_PAD_JTAG, EFUSE_BLK0, 45, 1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled -DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 46, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled -USB_DREFH, EFUSE_BLK0, 47, 2, [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged -USB_DREFL, EFUSE_BLK0, 49, 2, [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned -USB_EXCHG_PINS, EFUSE_BLK0, 51, 1, [] Represents whether the D+ and D- pins is exchanged. -VDD_SPI_AS_GPIO, EFUSE_BLK0, 52, 1, [] vdd spi as gpio -WDT_DELAY_SEL, EFUSE_BLK0, 53, 2, [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected +DIS_ICACHE, EFUSE_BLK0, 39, 1, [] Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ +DIS_USB_JTAG, EFUSE_BLK0, 40, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ +DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 42, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ +SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 43, 1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ +JTAG_SEL_ENABLE, EFUSE_BLK0, 44, 1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ +DIS_PAD_JTAG, EFUSE_BLK0, 45, 1, [] Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled\\ +DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 46, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled\\ +USB_EXCHG_PINS, EFUSE_BLK0, 51, 1, [] Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged\\ +VDD_SPI_AS_GPIO, EFUSE_BLK0, 52, 1, [] Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned\\ +WDT_DELAY_SEL, EFUSE_BLK0, 53, 2, [] Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16 \\ SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 55, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 58, 1, [] Revoke 1st secure boot key SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 59, 1, [] Revoke 2nd secure boot key @@ -133,63 +87,32 @@ KEY_PURPOSE_2, EFUSE_BLK0, 72, 4, [KEY2_PUR KEY_PURPOSE_3, EFUSE_BLK0, 76, 4, [KEY3_PURPOSE] Represents the purpose of Key3 KEY_PURPOSE_4, EFUSE_BLK0, 80, 4, [KEY4_PURPOSE] Represents the purpose of Key4 KEY_PURPOSE_5, EFUSE_BLK0, 84, 4, [KEY5_PURPOSE] Represents the purpose of Key5 -SEC_DPA_LEVEL, EFUSE_BLK0, 88, 2, [DPA_SEC_LEVEL] Represents the spa secure level by configuring the clock random divide mode -SECURE_BOOT_EN, EFUSE_BLK0, 90, 1, [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled -SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 91, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled -FLASH_TPUW, EFUSE_BLK0, 92, 4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value -DIS_DOWNLOAD_MODE, EFUSE_BLK0, 96, 1, [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled -DIS_DIRECT_BOOT, EFUSE_BLK0, 97, 1, [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled -DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 98, 1, [DIS_USB_PRINT] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled -DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 99, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled -ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 100, 1, [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled -UART_PRINT_CONTROL, EFUSE_BLK0, 101, 2, [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"} -FORCE_SEND_RESUME, EFUSE_BLK0, 103, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced +SEC_DPA_LEVEL, EFUSE_BLK0, 88, 2, [] Represents the spa secure level by configuring the clock random divide mode +SECURE_BOOT_EN, EFUSE_BLK0, 90, 1, [] Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ +SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 91, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled\\ +FLASH_TPUW, EFUSE_BLK0, 92, 4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is programmed value. Otherwise; the waiting time is 2 times the programmed value +DIS_DOWNLOAD_MODE, EFUSE_BLK0, 96, 1, [] Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable\\ +DIS_DIRECT_BOOT, EFUSE_BLK0, 97, 1, [] Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0: Enable\\ +DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 98, 1, [] Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1. Disable\\ 0: Enable\\ +DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 99, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable\\ +ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 100, 1, [] Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0: Disable\\ +UART_PRINT_CONTROL, EFUSE_BLK0, 101, 2, [] Represents the types of UART printing +FORCE_SEND_RESUME, EFUSE_BLK0, 103, 1, [] Represents whether ROM code is forced to send a resume commmand during SPI boot SECURE_VERSION, EFUSE_BLK0, 104, 16, [] Represents the version used by ESP-IDF anti-rollback feature -SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 120, 1, [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled -HYS_EN_PAD, EFUSE_BLK0, 121, 1, [] Disables check of wafer version major -XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 122, 1, [] Disables check of blk version major -XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 123, 1, [] Represents the anti-dpa attack pseudo function level. +SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 120, 1, [] Represents whether FAST_VERIFY_ON_WAKE is disable or enable when Secure Boot is enable +HYS_EN_PAD, EFUSE_BLK0, 121, 1, [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled\\ +XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 122, 1, [] Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0: Disable\\ +XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 123, 2, [] Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1: Low\\ 0: Decided by register configuration\\ +DIS_WIFI6, EFUSE_BLK0, 125, 1, [] Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is disable\\ 0: WiFi 6 is enabled.\\ +ECDSA_DISABLE_P192, EFUSE_BLK0, 126, 1, [] Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable +ECC_FORCE_CONST_TIME, EFUSE_BLK0, 127, 1, [] Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address -MAC_EXT, EFUSE_BLK1, 56, 8, [] Stores the extended bits of MAC address -, EFUSE_BLK1, 48, 8, [] Stores the extended bits of MAC address -ACTIVE_HP_DBIAS, EFUSE_BLK1, 64, 5, [] Stores the active hp dbias -ACTIVE_LP_DBIAS, EFUSE_BLK1, 69, 5, [] Stores the active lp dbias -LSLP_HP_DBG, EFUSE_BLK1, 74, 2, [] Stores the lslp hp dbg -LSLP_HP_DBIAS, EFUSE_BLK1, 76, 4, [] Stores the lslp hp dbias -DSLP_LP_DBG, EFUSE_BLK1, 80, 3, [] Stores the dslp lp dbg -DSLP_LP_DBIAS, EFUSE_BLK1, 83, 4, [] Stores the dslp lp dbias -DBIAS_VOL_GAP, EFUSE_BLK1, 87, 5, [] Stores the hp and lp dbias vol gap -WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 4, [] -WAFER_VERSION_MAJOR, EFUSE_BLK1, 118, 2, [] -PKG_VERSION, EFUSE_BLK1, 120, 3, [] Package version -BLK_VERSION_MINOR, EFUSE_BLK1, 123, 3, [] BLK_VERSION_MINOR of BLOCK2 -BLK_VERSION_MAJOR, EFUSE_BLK1, 126, 2, [] BLK_VERSION_MAJOR of BLOCK2 -FLASH_CAP, EFUSE_BLK1, 128, 3, [] -FLASH_TEMP, EFUSE_BLK1, 131, 2, [] -FLASH_VENDOR, EFUSE_BLK1, 133, 3, [] -OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID -TEMP_CALIB, EFUSE_BLK2, 128, 9, [] Temperature calibration data -OCODE, EFUSE_BLK2, 137, 8, [] ADC OCode -ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 145, 10, [] ADC1 init code at atten0 -ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 155, 10, [] ADC1 init code at atten1 -ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 165, 10, [] ADC1 init code at atten2 -ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 175, 10, [] ADC1 init code at atten3 -ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 185, 10, [] ADC1 calibration voltage at atten0 -ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 195, 10, [] ADC1 calibration voltage at atten1 -ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 205, 10, [] ADC1 calibration voltage at atten2 -ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 215, 10, [] ADC1 calibration voltage at atten3 -ADC1_INIT_CODE_ATTEN0_CH0, EFUSE_BLK2, 225, 4, [] ADC1 init code at atten0 ch0 -ADC1_INIT_CODE_ATTEN0_CH1, EFUSE_BLK2, 229, 4, [] ADC1 init code at atten0 ch1 -ADC1_INIT_CODE_ATTEN0_CH2, EFUSE_BLK2, 233, 4, [] ADC1 init code at atten0 ch2 -ADC1_INIT_CODE_ATTEN0_CH3, EFUSE_BLK2, 237, 4, [] ADC1 init code at atten0 ch3 -ADC1_INIT_CODE_ATTEN0_CH4, EFUSE_BLK2, 241, 4, [] ADC1 init code at atten0 ch4 -ADC1_INIT_CODE_ATTEN0_CH5, EFUSE_BLK2, 245, 4, [] ADC1 init code at atten0 ch5 -ADC1_INIT_CODE_ATTEN0_CH6, EFUSE_BLK2, 249, 4, [] ADC1 init code at atten0 ch6 +BLOCK_SYS_DATA1, EFUSE_BLK2, 0, 256, [] System data part 1 (reserved) USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data diff --git a/components/efuse/esp32c61/esp_efuse_utility.c b/components/efuse/esp32c61/esp_efuse_utility.c index 8778cddf9c..6ba812a65c 100644 --- a/components/efuse/esp32c61/esp_efuse_utility.c +++ b/components/efuse/esp32c61/esp_efuse_utility.c @@ -12,8 +12,6 @@ #include "soc/efuse_periph.h" #include "hal/efuse_hal.h" -// TODO: [ESP32C61] IDF-9282, file inherit from verify code, pls check - static const char *TAG = "efuse"; #ifdef CONFIG_EFUSE_VIRTUAL @@ -77,9 +75,16 @@ esp_err_t esp_efuse_utility_check_errors(void) // Burn values written to the efuse write registers esp_err_t esp_efuse_utility_burn_chip(void) +{ + return esp_efuse_utility_burn_chip_opt(false, true); +} + +esp_err_t esp_efuse_utility_burn_chip_opt(bool ignore_coding_errors, bool verify_written_data) { esp_err_t error = ESP_OK; #ifdef CONFIG_EFUSE_VIRTUAL + (void) ignore_coding_errors; + (void) verify_written_data; ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses"); for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) { int subblock = 0; @@ -127,7 +132,7 @@ esp_err_t esp_efuse_utility_burn_chip(void) hal_memcpy(backup_write_data, (void *)EFUSE_PGM_DATA0_REG, sizeof(backup_write_data)); int repeat_burn_op = 1; bool correct_written_data; - bool coding_error_before = efuse_hal_is_coding_error_in_block(num_block); + bool coding_error_before = !ignore_coding_errors && efuse_hal_is_coding_error_in_block(num_block); if (coding_error_before) { ESP_LOGW(TAG, "BLOCK%d already has a coding error", num_block); } @@ -145,12 +150,12 @@ esp_err_t esp_efuse_utility_burn_chip(void) break; } } - coding_error_occurred = (coding_error_before != coding_error_after) && coding_error_before == false; + coding_error_occurred = !ignore_coding_errors && (coding_error_before != coding_error_after) && !coding_error_before; if (coding_error_occurred) { ESP_LOGW(TAG, "BLOCK%d got a coding error", num_block); } - correct_written_data = esp_efuse_utility_is_correct_written_data(num_block, r_data_len); + correct_written_data = (verify_written_data) ? esp_efuse_utility_is_correct_written_data(num_block, r_data_len) : true; if (!correct_written_data || coding_error_occurred) { ESP_LOGW(TAG, "BLOCK%d: next retry to fix an error [%d/3]...", num_block, repeat_burn_op); hal_memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)backup_write_data, sizeof(backup_write_data)); diff --git a/components/efuse/esp32c61/include/esp_efuse_chip.h b/components/efuse/esp32c61/include/esp_efuse_chip.h index 2bc74db0b5..637080eebc 100644 --- a/components/efuse/esp32c61/include/esp_efuse_chip.h +++ b/components/efuse/esp32c61/include/esp_efuse_chip.h @@ -62,7 +62,7 @@ typedef enum { */ typedef enum { ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */ - ESP_EFUSE_KEY_PURPOSE_RESERVED = 1, /**< Reserved */ + ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, /**< ECDSA private key (Expected in little endian order)*/ ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */ ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, /**< HMAC Downstream mode */ ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, /**< JTAG soft enable key (uses HMAC Downstream mode) */ diff --git a/components/efuse/esp32c61/include/esp_efuse_rtc_calib.h b/components/efuse/esp32c61/include/esp_efuse_rtc_calib.h index 925fe4f889..e6eea86d2d 100644 --- a/components/efuse/esp32c61/include/esp_efuse_rtc_calib.h +++ b/components/efuse/esp32c61/include/esp_efuse_rtc_calib.h @@ -11,7 +11,7 @@ extern "C" { #endif -// TODO: [ESP32C61] IDF-9282, file inherit from verify code, pls check +// TODO: [ESP32C61] IDF-9303, file inherit from verify code, pls check //This is the ADC calibration value version burnt in efuse #define ESP_EFUSE_ADC_CALIB_VER1 1 diff --git a/components/efuse/esp32c61/include/esp_efuse_table.h b/components/efuse/esp32c61/include/esp_efuse_table.h index 694faec0bd..c06baca953 100644 --- a/components/efuse/esp32c61/include/esp_efuse_table.h +++ b/components/efuse/esp32c61/include/esp_efuse_table.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,9 +10,7 @@ extern "C" { #include "esp_efuse.h" -// TODO: [ESP32C61] IDF-9282, file inherit from verify code, pls check - -// md5_digest_table 873c3e466a4c31bca2e00afae2073f94 +// md5_digest_table 604cf47a9075de209e7b488c4c6a3cd6 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -21,15 +19,9 @@ extern "C" { extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SWAP_UART_SDIO_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[]; -#define ESP_EFUSE_WR_DIS_DIS_CAN ESP_EFUSE_WR_DIS_DIS_TWAI extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; @@ -51,7 +43,6 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[]; #define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[]; -#define ESP_EFUSE_WR_DIS_DPA_SEC_LEVEL ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[]; @@ -59,46 +50,17 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; -#define ESP_EFUSE_WR_DIS_DIS_USB_PRINT ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; #define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH6[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[]; #define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; @@ -120,7 +82,6 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[]; #define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_AS_GPIO[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[]; #define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0 @@ -138,14 +99,11 @@ extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[]; #define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[]; extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[]; extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[]; extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[]; @@ -166,14 +124,12 @@ extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; #define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5 extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[]; -#define ESP_EFUSE_DPA_SEC_LEVEL ESP_EFUSE_SEC_DPA_LEVEL extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; -#define ESP_EFUSE_DIS_USB_PRINT ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; @@ -183,35 +139,12 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[]; extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_WIFI6[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_DISABLE_P192[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[]; extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; #define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC -extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; -extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[]; -extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH4[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH5[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH6[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK_SYS_DATA1[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; #define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; diff --git a/components/hal/esp32c5/efuse_hal.c b/components/hal/esp32c5/efuse_hal.c index 5feb2c445a..df9595556d 100644 --- a/components/hal/esp32c5/efuse_hal.c +++ b/components/hal/esp32c5/efuse_hal.c @@ -38,75 +38,59 @@ IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void) void efuse_hal_set_timing(uint32_t apb_freq_hz) { (void) apb_freq_hz; - // TODO: [ESP32C5] IDF-8674 - abort(); - // efuse_ll_set_dac_num(0xFF); - // efuse_ll_set_dac_clk_div(0x28); - // efuse_ll_set_pwr_on_num(0x3000); - // efuse_ll_set_pwr_off_num(0x190); } void efuse_hal_read(void) { - // TODO: [ESP32C5] IDF-8674 - abort(); - // efuse_hal_set_timing(0); + efuse_hal_set_timing(0); - // efuse_ll_set_conf_read_op_code(); - // efuse_ll_set_read_cmd(); + efuse_ll_set_conf_read_op_code(); + efuse_ll_set_read_cmd(); - // while (efuse_ll_get_read_cmd() != 0) { } - // /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/ - // while (efuse_ll_get_read_cmd() != 0) { } + while (efuse_ll_get_read_cmd() != 0) { } + /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/ + while (efuse_ll_get_read_cmd() != 0) { } } void efuse_hal_clear_program_registers(void) { - // TODO: [ESP32C5] IDF-8674 - abort(); - // ets_efuse_clear_program_registers(); + ets_efuse_clear_program_registers(); } void efuse_hal_program(uint32_t block) { - // TODO: [ESP32C5] IDF-8674 - abort(); - // efuse_hal_set_timing(0); + efuse_hal_set_timing(0); - // efuse_ll_set_conf_write_op_code(); - // efuse_ll_set_pgm_cmd(block); + efuse_ll_set_conf_write_op_code(); + efuse_ll_set_pgm_cmd(block); - // while (efuse_ll_get_pgm_cmd() != 0) { } + while (efuse_ll_get_pgm_cmd() != 0) { } - // efuse_hal_clear_program_registers(); - // efuse_hal_read(); + efuse_hal_clear_program_registers(); + efuse_hal_read(); } void efuse_hal_rs_calculate(const void *data, void *rs_values) { - // TODO: [ESP32C5] IDF-8674 - abort(); - // ets_efuse_rs_calculate(data, rs_values); + ets_efuse_rs_calculate(data, rs_values); } /******************* eFuse control functions *************************/ bool efuse_hal_is_coding_error_in_block(unsigned block) { - // TODO: [ESP32C5] IDF-8674 - abort(); - // if (block == 0) { - // for (unsigned i = 0; i < 5; i++) { - // if (REG_READ(EFUSE_RD_REPEAT_ERR0_REG + i * 4)) { - // return true; - // } - // } - // } else if (block <= 10) { - // // EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low) - // // EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9 - // block--; - // uint32_t error_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4); - // return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block % 8) != 0; - // } + if (block == 0) { + for (unsigned i = 0; i < 5; i++) { + if (REG_READ(EFUSE_RD_REPEAT_DATA_ERR0_REG + i * 4)) { + return true; + } + } + } else if (block <= 10) { + // EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low) + // EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9 + block--; + uint32_t error_reg = REG_READ(EFUSE_RD_RS_DATA_ERR0_REG + (block / 8) * 4); + return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block % 8) != 0; + } return false; } diff --git a/components/hal/esp32c5/include/hal/efuse_hal.h b/components/hal/esp32c5/include/hal/efuse_hal.h new file mode 100644 index 0000000000..19c8ea42fa --- /dev/null +++ b/components/hal/esp32c5/include/hal/efuse_hal.h @@ -0,0 +1,69 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/soc_caps.h" +#include "hal/efuse_ll.h" +#include_next "hal/efuse_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief get chip version + */ +uint32_t efuse_hal_get_chip_revision(void); + +/** + * @brief set eFuse timings + * + * @param apb_freq_hz APB frequency in Hz + */ +void efuse_hal_set_timing(uint32_t apb_freq_hz); + +/** + * @brief trigger eFuse read operation + */ +void efuse_hal_read(void); + +/** + * @brief clear registers for programming eFuses + */ +void efuse_hal_clear_program_registers(void); + +/** + * @brief burn eFuses written in programming registers (one block at once) + * + * @param block block number + */ +void efuse_hal_program(uint32_t block); + +/** + * @brief Calculate Reed-Solomon Encoding values for a block of efuse data. + * + * @param data Pointer to data buffer (length 32 bytes) + * @param rs_values Pointer to write encoded data to (length 12 bytes) + */ +void efuse_hal_rs_calculate(const void *data, void *rs_values); + +/** + * @brief Checks coding error in a block + * + * @param block Index of efuse block + * + * @return True - block has an error. + * False - no error. + */ +bool efuse_hal_is_coding_error_in_block(unsigned block); + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/efuse_ll.h b/components/hal/esp32c5/include/hal/efuse_ll.h index cc75120eda..8e283d1a7a 100644 --- a/components/hal/esp32c5/include/hal/efuse_ll.h +++ b/components/hal/esp32c5/include/hal/efuse_ll.h @@ -8,8 +8,11 @@ #include #include +#include "soc/efuse_defs.h" +#include "soc/efuse_reg.h" #include "soc/efuse_periph.h" #include "hal/assert.h" +#include "rom/efuse.h" #ifdef __cplusplus extern "C" { @@ -21,148 +24,112 @@ extern "C" { __attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) - // return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt; - return (uint32_t)0; + return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void) { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) - // return EFUSE.rd_repeat_data1.wdt_delay_sel; - return (uint32_t)0; + return EFUSE.rd_repeat_data1.wdt_delay_sel; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) - // return EFUSE.rd_mac_sys_0.mac_0; - return (uint32_t)0; + return EFUSE.rd_mac_sys0.mac_0; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) - // return EFUSE.rd_mac_sys_1.mac_1; - return (uint32_t)0; + return EFUSE.rd_mac_sys1.mac_1; } __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) - // return EFUSE.rd_repeat_data2.secure_boot_en; - return (bool)0; + return EFUSE.rd_repeat_data2.secure_boot_en; } // use efuse_hal_get_major_chip_version() to get major chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void) { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) - // // return EFUSE.rd_mac_sys_5; - // return 0; return (uint32_t)0; } // use efuse_hal_get_minor_chip_version() to get minor chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) - // return 0; return (uint32_t)0; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) - // return 0; return (bool)0; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void) { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) - // return 0; return (uint32_t)0; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void) { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) - // return 0; return (uint32_t)0; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void) { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) - // return 0; return (bool)0; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) - // return 0; return (uint32_t)0; } __attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(int efuse_blk) { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) - // EFUSE.conf.cfg_ecdsa_blk = efuse_blk; + EFUSE.conf.cfg_ecdsa_blk = efuse_blk; } /******************* eFuse control functions *************************/ __attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void) { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) - // return EFUSE.cmd.read_cmd; - return (bool)0; + return EFUSE.cmd.read_cmd; } __attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void) { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) - // return EFUSE.cmd.pgm_cmd; - return (bool)0; + return EFUSE.cmd.pgm_cmd; } __attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void) { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) - // EFUSE.cmd.read_cmd = 1; + EFUSE.cmd.read_cmd = 1; } __attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block) { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) - // HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX); - // EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD; + HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX); + EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD; } __attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void) { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) - // EFUSE.conf.op_code = EFUSE_READ_OP_CODE; + EFUSE.conf.op_code = EFUSE_READ_OP_CODE; } __attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void) { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) - // EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE; + EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE; } __attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value) { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) - // EFUSE.wr_tim_conf2.pwr_off_num = value; + EFUSE.wr_tim_conf2.pwr_off_num = value; } __attribute__((always_inline)) static inline void efuse_ll_rs_bypass_update(void) { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) - // EFUSE.wr_tim_conf0_rs_bypass.update = 1; + EFUSE.wr_tim_conf0_rs_bypass.update = 1; } /******************* eFuse control functions *************************/ diff --git a/components/hal/esp32c61/include/hal/efuse_hal.h b/components/hal/esp32c61/include/hal/efuse_hal.h index e0b4a80b83..bcac5d8cde 100644 --- a/components/hal/esp32c61/include/hal/efuse_hal.h +++ b/components/hal/esp32c61/include/hal/efuse_hal.h @@ -16,8 +16,6 @@ extern "C" { #endif -// TODO: [ESP32C61] IDF-9282, inherit from c6 - /** * @brief get chip version */ diff --git a/components/hal/esp32c61/include/hal/efuse_ll.h b/components/hal/esp32c61/include/hal/efuse_ll.h index e477ffeb99..1c5238d2e6 100644 --- a/components/hal/esp32c61/include/hal/efuse_ll.h +++ b/components/hal/esp32c61/include/hal/efuse_ll.h @@ -14,8 +14,6 @@ #include "hal/assert.h" #include "rom/efuse.h" -// TODO: [ESP32C61] IDF-9282, inherit from c6 - #ifdef __cplusplus extern "C" { #endif @@ -52,92 +50,38 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en // use efuse_hal_get_major_chip_version() to get major chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void) { - return EFUSE0.rd_mac_sys3.mac_reserved_2; + return (uint32_t)0; } // use efuse_hal_get_minor_chip_version() to get minor chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) { - return EFUSE0.rd_mac_sys3.sys_data_part0_0; + return (uint32_t)0; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) { - return EFUSE0.rd_repeat_data4.rd_repeat_data4; -} - -__attribute__((always_inline)) static inline uint32_t efuse_ll_get_active_hp_dbias(void) -{ - HAL_ASSERT(0); - // return EFUSE0.rd_mac_spi_sys_2.active_hp_dbias; - return 0; -} - -__attribute__((always_inline)) static inline uint32_t efuse_ll_get_active_lp_dbias(void) -{ - HAL_ASSERT(0); - // return EFUSE0.rd_mac_spi_sys_2.active_lp_dbias; - return 0; -} - -__attribute__((always_inline)) static inline uint32_t efuse_ll_get_lslp_dbg(void) -{ - HAL_ASSERT(0); - // return EFUSE0.rd_mac_spi_sys_2.lslp_hp_dbg; - return 0; -} - -__attribute__((always_inline)) static inline uint32_t efuse_ll_get_lslp_hp_dbias(void) -{ - HAL_ASSERT(0); - // return EFUSE0.rd_mac_spi_sys_2.lslp_hp_dbias; - return 0; -} - -__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dslp_dbg(void) -{ - HAL_ASSERT(0); - // return EFUSE0.rd_mac_spi_sys_2.dslp_lp_dbg; - return 0; -} - -__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dslp_lp_dbias(void) -{ - HAL_ASSERT(0); - // return EFUSE0.rd_mac_spi_sys_2.dslp_lp_dbias; - return 0; -} - -__attribute__((always_inline)) static inline int32_t efuse_ll_get_dbias_vol_gap(void) -{ - HAL_ASSERT(0); - // return EFUSE0.rd_mac_spi_sys_2.dbias_vol_gap; - return 0; + return (uint32_t)0; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void) { - return EFUSE0.rd_mac_sys3.sys_data_part0_0; + return (uint32_t)0; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void) { - return EFUSE0.rd_mac_sys3.sys_data_part0_0; + return (uint32_t)0; } __attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void) { - return EFUSE0.rd_repeat_data4.rd_repeat_data4; + return false; } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) { - return EFUSE0.rd_mac_sys3.sys_data_part0_0; -} - -__attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void) -{ - return EFUSE0.rd_sys_part1_datan[4].sys_data_part1_n; + return (uint32_t)0; } /******************* eFuse control functions *************************/ diff --git a/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in index 3193adcca2..6b6100c8ac 100644 --- a/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in @@ -23,6 +23,10 @@ config SOC_ASYNC_MEMCPY_SUPPORTED bool default y +config SOC_SUPPORTS_SECURE_DL_MODE + bool + default y + config SOC_EFUSE_KEY_PURPOSE_FIELD bool default y diff --git a/components/soc/esp32c5/beta3/include/soc/efuse_defs.h b/components/soc/esp32c5/beta3/include/soc/efuse_defs.h new file mode 100644 index 0000000000..48cc4ce65d --- /dev/null +++ b/components/soc/esp32c5/beta3/include/soc/efuse_defs.h @@ -0,0 +1,17 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/beta3/include/soc/efuse_reg.h b/components/soc/esp32c5/beta3/include/soc/efuse_reg.h index 0d9424909a..c1454701a2 100644 --- a/components/soc/esp32c5/beta3/include/soc/efuse_reg.h +++ b/components/soc/esp32c5/beta3/include/soc/efuse_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -143,13 +143,13 @@ extern "C" { #define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_2_S 0 -/** EFUSE_RD_WR_DIS_REG register +/** EFUSE_RD_WR_DIS0_REG register * BLOCK0 data register 0. */ -#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) +#define EFUSE_RD_WR_DIS0_REG (DR_REG_EFUSE_BASE + 0x2c) /** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; * Represents whether programming of individual eFuse memory bit is disabled or - * enabled. 1: Disabled. 0 Enabled. + * enabled. 1: Disabled. 0: Enabled. */ #define EFUSE_WR_DIS 0xFFFFFFFFU #define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) @@ -157,7 +157,7 @@ extern "C" { #define EFUSE_WR_DIS_S 0 /** EFUSE_RD_REPEAT_DATA0_REG register - * BLOCK0 data register 1. + * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) /** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; @@ -168,6 +168,13 @@ extern "C" { #define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) #define EFUSE_RD_DIS_V 0x0000007FU #define EFUSE_RD_DIS_S 0 +/** EFUSE_RD_RESERVE_0_39 : RW; bitpos: [7]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_39 (BIT(7)) +#define EFUSE_RD_RESERVE_0_39_M (EFUSE_RD_RESERVE_0_39_V << EFUSE_RD_RESERVE_0_39_S) +#define EFUSE_RD_RESERVE_0_39_V 0x00000001U +#define EFUSE_RD_RESERVE_0_39_S 7 /** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; * Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. */ @@ -183,6 +190,21 @@ extern "C" { #define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) #define EFUSE_DIS_USB_JTAG_V 0x00000001U #define EFUSE_DIS_USB_JTAG_S 9 +/** EFUSE_RD_RESERVE_0_42 : RW; bitpos: [10]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_42 (BIT(10)) +#define EFUSE_RD_RESERVE_0_42_M (EFUSE_RD_RESERVE_0_42_V << EFUSE_RD_RESERVE_0_42_S) +#define EFUSE_RD_RESERVE_0_42_V 0x00000001U +#define EFUSE_RD_RESERVE_0_42_S 10 +/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0; + * Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: + * enabled. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG (BIT(11)) +#define EFUSE_DIS_USB_SERIAL_JTAG_M (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_S 11 /** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; * Represents whether the function that forces chip into download mode is disabled or * enabled. 1: disabled. 0: enabled. @@ -224,8 +246,8 @@ extern "C" { #define EFUSE_SOFT_DIS_JTAG_V 0x00000007U #define EFUSE_SOFT_DIS_JTAG_S 16 /** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; - * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: - * enabled. + * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. + * 0: enabled. */ #define EFUSE_DIS_PAD_JTAG (BIT(19)) #define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) @@ -239,8 +261,23 @@ extern "C" { #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 +/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; + * Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. + */ +#define EFUSE_USB_DREFH 0x00000003U +#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) +#define EFUSE_USB_DREFH_V 0x00000003U +#define EFUSE_USB_DREFH_S 21 +/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; + * Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. + */ +#define EFUSE_USB_DREFL 0x00000003U +#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) +#define EFUSE_USB_DREFL_V 0x00000003U +#define EFUSE_USB_DREFL_S 23 /** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0; - * Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. + * Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not + * exchanged. */ #define EFUSE_USB_EXCHG_PINS (BIT(25)) #define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) @@ -254,64 +291,69 @@ extern "C" { #define EFUSE_VDD_SPI_AS_GPIO_M (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S) #define EFUSE_VDD_SPI_AS_GPIO_V 0x00000001U #define EFUSE_VDD_SPI_AS_GPIO_S 26 -/** EFUSE_HUK_GEN_STATE_PART1 : RO; bitpos: [31:27]; default: 0; - * Represents the validation of HUK generate mode. +/** EFUSE_RD_RESERVE_0_59 : RW; bitpos: [31:27]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func */ -#define EFUSE_HUK_GEN_STATE_PART1 0x0000001FU -#define EFUSE_HUK_GEN_STATE_PART1_M (EFUSE_HUK_GEN_STATE_PART1_V << EFUSE_HUK_GEN_STATE_PART1_S) -#define EFUSE_HUK_GEN_STATE_PART1_V 0x0000001FU -#define EFUSE_HUK_GEN_STATE_PART1_S 27 +#define EFUSE_RD_RESERVE_0_59 0x0000001FU +#define EFUSE_RD_RESERVE_0_59_M (EFUSE_RD_RESERVE_0_59_V << EFUSE_RD_RESERVE_0_59_S) +#define EFUSE_RD_RESERVE_0_59_V 0x0000001FU +#define EFUSE_RD_RESERVE_0_59_S 27 /** EFUSE_RD_REPEAT_DATA1_REG register - * BLOCK0 data register 2. + * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) -/** EFUSE_HUK_GEN_STATE_PART2 : RO; bitpos: [3:0]; default: 0; - * Represents the validation of HUK generate mode. +/** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [3:0]; default: 0; + * Represents whether the deploy mode of key manager is disable or not. . 1: disabled + * . 0: enabled.. */ -#define EFUSE_HUK_GEN_STATE_PART2 0x0000000FU -#define EFUSE_HUK_GEN_STATE_PART2_M (EFUSE_HUK_GEN_STATE_PART2_V << EFUSE_HUK_GEN_STATE_PART2_S) -#define EFUSE_HUK_GEN_STATE_PART2_V 0x0000000FU -#define EFUSE_HUK_GEN_STATE_PART2_S 0 +#define EFUSE_KM_DISABLE_DEPLOY_MODE 0x0000000FU +#define EFUSE_KM_DISABLE_DEPLOY_MODE_M (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S) +#define EFUSE_KM_DISABLE_DEPLOY_MODE_V 0x0000000FU +#define EFUSE_KM_DISABLE_DEPLOY_MODE_S 0 /** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [5:4]; default: 0; - * Represents the key manager random number switch cycle. + * Set the bits to control key manager random number switch cycle. 0: control by + * register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles */ #define EFUSE_KM_RND_SWITCH_CYCLE 0x00000003U #define EFUSE_KM_RND_SWITCH_CYCLE_M (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S) #define EFUSE_KM_RND_SWITCH_CYCLE_V 0x00000003U #define EFUSE_KM_RND_SWITCH_CYCLE_S 4 /** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [9:6]; default: 0; - * Represents whether corresponding key can only be deployed once. + * Set each bit to control whether corresponding key can only be deployed once. 1 is + * true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds */ #define EFUSE_KM_DEPLOY_ONLY_ONCE 0x0000000FU #define EFUSE_KM_DEPLOY_ONLY_ONCE_M (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S) #define EFUSE_KM_DEPLOY_ONLY_ONCE_V 0x0000000FU #define EFUSE_KM_DEPLOY_ONLY_ONCE_S 6 /** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [13:10]; default: 0; - * Represents which corresponding key must come from key manager. + * Set each bit to control whether corresponding key must come from key manager. 1 is + * true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds */ #define EFUSE_FORCE_USE_KEY_MANAGER_KEY 0x0000000FU #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S) #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_V 0x0000000FU #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_S 10 /** EFUSE_FORCE_DISABLE_SW_INIT_KEY : RO; bitpos: [14]; default: 0; - * Represents whether to disable software written init key and force use - * efuse_init_key. + * Set this bit to disable software written init key, and force use efuse_init_key. */ #define EFUSE_FORCE_DISABLE_SW_INIT_KEY (BIT(14)) #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M (EFUSE_FORCE_DISABLE_SW_INIT_KEY_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_S) #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V 0x00000001U #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S 14 -/** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [15]; default: 0; - * TBD. +/** EFUSE_RD_RESERVE_0_79 : RW; bitpos: [15]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func */ -#define EFUSE_KM_DISABLE_DEPLOY_MODE (BIT(15)) -#define EFUSE_KM_DISABLE_DEPLOY_MODE_M (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S) -#define EFUSE_KM_DISABLE_DEPLOY_MODE_V 0x00000001U -#define EFUSE_KM_DISABLE_DEPLOY_MODE_S 15 +#define EFUSE_RD_RESERVE_0_79 (BIT(15)) +#define EFUSE_RD_RESERVE_0_79_M (EFUSE_RD_RESERVE_0_79_V << EFUSE_RD_RESERVE_0_79_S) +#define EFUSE_RD_RESERVE_0_79_V 0x00000001U +#define EFUSE_RD_RESERVE_0_79_S 15 /** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; - * Represents whether RTC watchdog timeout threshold is selected at startup. 1: - * selected. 0: not selected. + * Represents the threshold level of the RTC watchdog STG0 timeout. 0: Original + * threshold configuration value of STG0 *2 .1: Original threshold configuration + * value of STG0 *4 .2: Original threshold configuration value of STG0 *8 .3: + * Original threshold configuration value of STG0 *16 . */ #define EFUSE_WDT_DELAY_SEL 0x00000003U #define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) @@ -365,7 +407,7 @@ extern "C" { #define EFUSE_KEY_PURPOSE_1_S 28 /** EFUSE_RD_REPEAT_DATA2_REG register - * BLOCK0 data register 3. + * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) /** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; @@ -403,20 +445,13 @@ extern "C" { #define EFUSE_SEC_DPA_LEVEL_M (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S) #define EFUSE_SEC_DPA_LEVEL_V 0x00000003U #define EFUSE_SEC_DPA_LEVEL_S 16 -/** EFUSE_ECDSA_ENABLE_SOFT_K : RO; bitpos: [18]; default: 0; - * TBD. +/** EFUSE_RD_RESERVE_0_114 : RW; bitpos: [19:18]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func */ -#define EFUSE_ECDSA_ENABLE_SOFT_K (BIT(18)) -#define EFUSE_ECDSA_ENABLE_SOFT_K_M (EFUSE_ECDSA_ENABLE_SOFT_K_V << EFUSE_ECDSA_ENABLE_SOFT_K_S) -#define EFUSE_ECDSA_ENABLE_SOFT_K_V 0x00000001U -#define EFUSE_ECDSA_ENABLE_SOFT_K_S 18 -/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1; - * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. - */ -#define EFUSE_CRYPT_DPA_ENABLE (BIT(19)) -#define EFUSE_CRYPT_DPA_ENABLE_M (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S) -#define EFUSE_CRYPT_DPA_ENABLE_V 0x00000001U -#define EFUSE_CRYPT_DPA_ENABLE_S 19 +#define EFUSE_RD_RESERVE_0_114 0x00000003U +#define EFUSE_RD_RESERVE_0_114_M (EFUSE_RD_RESERVE_0_114_V << EFUSE_RD_RESERVE_0_114_S) +#define EFUSE_RD_RESERVE_0_114_V 0x00000003U +#define EFUSE_RD_RESERVE_0_114_S 18 /** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. */ @@ -432,6 +467,20 @@ extern "C" { #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 +/** EFUSE_RD_RESERVE_0_118 : RW; bitpos: [26:22]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_118 0x0000001FU +#define EFUSE_RD_RESERVE_0_118_M (EFUSE_RD_RESERVE_0_118_V << EFUSE_RD_RESERVE_0_118_S) +#define EFUSE_RD_RESERVE_0_118_V 0x0000001FU +#define EFUSE_RD_RESERVE_0_118_S 22 +/** EFUSE_KM_XTS_KEY_LENGTH_256 : RO; bitpos: [27]; default: 0; + * Set this bitto configure flash encryption use xts-128 key. else use xts-256 key. + */ +#define EFUSE_KM_XTS_KEY_LENGTH_256 (BIT(27)) +#define EFUSE_KM_XTS_KEY_LENGTH_256_M (EFUSE_KM_XTS_KEY_LENGTH_256_V << EFUSE_KM_XTS_KEY_LENGTH_256_S) +#define EFUSE_KM_XTS_KEY_LENGTH_256_V 0x00000001U +#define EFUSE_KM_XTS_KEY_LENGTH_256_S 27 /** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; * Represents the flash waiting time after power-up, in unit of ms. When the value * less than 15, the waiting time is the programmed value. Otherwise, the waiting time @@ -443,41 +492,43 @@ extern "C" { #define EFUSE_FLASH_TPUW_S 28 /** EFUSE_RD_REPEAT_DATA3_REG register - * BLOCK0 data register 4. + * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) /** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; - * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + * Represents whether Download mode is disabled or enabled. 1: disabled. 0: + * enabled. */ #define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) #define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_S 0 /** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: + * enabled. */ #define EFUSE_DIS_DIRECT_BOOT (BIT(1)) #define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) #define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U #define EFUSE_DIS_DIRECT_BOOT_S 1 /** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; - * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. - * 0: enabled. + * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: + * disabled. 0: enabled. */ #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 /** EFUSE_LOCK_KM_KEY : RO; bitpos: [3]; default: 0; - * TBD. + * Represetns whether to lock the efuse xts key. 1. Lock. 0: Unlock. */ #define EFUSE_LOCK_KM_KEY (BIT(3)) #define EFUSE_LOCK_KM_KEY_M (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S) #define EFUSE_LOCK_KM_KEY_V 0x00000001U #define EFUSE_LOCK_KM_KEY_S 3 /** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: - * disabled. 0: enabled. + * Represents whether the USB-Serial-JTAG download function is disabled or enabled.. + * 1: Disable. 0: Enable. */ #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) @@ -501,8 +552,8 @@ extern "C" { #define EFUSE_UART_PRINT_CONTROL_V 0x00000003U #define EFUSE_UART_PRINT_CONTROL_S 6 /** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot. 1: - * forced. 0:not forced. + * Represents whether ROM code is forced to send a resume command during SPI boot.. + * 1: forced. 0:not forced. */ #define EFUSE_FORCE_SEND_RESUME (BIT(8)) #define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) @@ -531,73 +582,136 @@ extern "C" { #define EFUSE_HYS_EN_PAD_M (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S) #define EFUSE_HYS_EN_PAD_V 0x00000001U #define EFUSE_HYS_EN_PAD_S 26 +/** EFUSE_XTS_DPA_PSEUDO_LEVEL : RO; bitpos: [28:27]; default: 0; + * Represents the pseudo round level of xts-aes anti-dpa attack. 3: High. 2: + * Moderate 1. Low. 0: Disabled. + */ +#define EFUSE_XTS_DPA_PSEUDO_LEVEL 0x00000003U +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S) +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_V 0x00000003U +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_S 27 +/** EFUSE_XTS_DPA_CLK_ENABLE : RO; bitpos: [29]; default: 0; + * Represents whether xts-aes anti-dpa attack clock is enabled. 1. Enable. 0: + * Disable.. + */ +#define EFUSE_XTS_DPA_CLK_ENABLE (BIT(29)) +#define EFUSE_XTS_DPA_CLK_ENABLE_M (EFUSE_XTS_DPA_CLK_ENABLE_V << EFUSE_XTS_DPA_CLK_ENABLE_S) +#define EFUSE_XTS_DPA_CLK_ENABLE_V 0x00000001U +#define EFUSE_XTS_DPA_CLK_ENABLE_S 29 +/** EFUSE_RD_RESERVE_0_158 : RW; bitpos: [31:30]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_158 0x00000003U +#define EFUSE_RD_RESERVE_0_158_M (EFUSE_RD_RESERVE_0_158_V << EFUSE_RD_RESERVE_0_158_S) +#define EFUSE_RD_RESERVE_0_158_V 0x00000003U +#define EFUSE_RD_RESERVE_0_158_S 30 /** EFUSE_RD_REPEAT_DATA4_REG register - * BLOCK0 data register 5. + * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) -/** EFUSE_RESERVED_0 : RO; bitpos: [31:24]; default: 0; - * Reserved. +/** EFUSE_HUK_GEN_STATE : RO; bitpos: [8:0]; default: 0; + * Set the bits to control validation of HUK generate mode. Odd of 1 is invalid.. + * Even of 1 is valid.. */ -#define EFUSE_RESERVED_0 0x000000FFU -#define EFUSE_RESERVED_0_M (EFUSE_RESERVED_0_V << EFUSE_RESERVED_0_S) -#define EFUSE_RESERVED_0_V 0x000000FFU -#define EFUSE_RESERVED_0_S 24 +#define EFUSE_HUK_GEN_STATE 0x000001FFU +#define EFUSE_HUK_GEN_STATE_M (EFUSE_HUK_GEN_STATE_V << EFUSE_HUK_GEN_STATE_S) +#define EFUSE_HUK_GEN_STATE_V 0x000001FFU +#define EFUSE_HUK_GEN_STATE_S 0 +/** EFUSE_XTAL_48M_SEL : RO; bitpos: [11:9]; default: 0; + * Represents whether XTAL frequency is 48MHz or not. If not, 40MHz XTAL will be used. + * If this field contains Odd number bit '1': Enable 48MHz XTAL. Even number bit '1': + * Enable 40MHz XTAL. + */ +#define EFUSE_XTAL_48M_SEL 0x00000007U +#define EFUSE_XTAL_48M_SEL_M (EFUSE_XTAL_48M_SEL_V << EFUSE_XTAL_48M_SEL_S) +#define EFUSE_XTAL_48M_SEL_V 0x00000007U +#define EFUSE_XTAL_48M_SEL_S 9 +/** EFUSE_XTAL_48M_SEL_MODE : RO; bitpos: [12]; default: 0; + * Specify the XTAL frequency selection is decided by eFuse or strapping-PAD-state. 1: + * eFuse. 0: strapping-PAD-state. + */ +#define EFUSE_XTAL_48M_SEL_MODE (BIT(12)) +#define EFUSE_XTAL_48M_SEL_MODE_M (EFUSE_XTAL_48M_SEL_MODE_V << EFUSE_XTAL_48M_SEL_MODE_S) +#define EFUSE_XTAL_48M_SEL_MODE_V 0x00000001U +#define EFUSE_XTAL_48M_SEL_MODE_S 12 +/** EFUSE_ECDSA_DISABLE_P192 : RO; bitpos: [13]; default: 0; + * Represents whether to disable P192 curve in ECDSA. 1: Disabled. 0: Not disable. + */ +#define EFUSE_ECDSA_DISABLE_P192 (BIT(13)) +#define EFUSE_ECDSA_DISABLE_P192_M (EFUSE_ECDSA_DISABLE_P192_V << EFUSE_ECDSA_DISABLE_P192_S) +#define EFUSE_ECDSA_DISABLE_P192_V 0x00000001U +#define EFUSE_ECDSA_DISABLE_P192_S 13 +/** EFUSE_ECC_FORCE_CONST_TIME : RO; bitpos: [14]; default: 0; + * Represents whether to force ecc to use const-time calculation mode. . 1: Enable. + * . 0: Disable. + */ +#define EFUSE_ECC_FORCE_CONST_TIME (BIT(14)) +#define EFUSE_ECC_FORCE_CONST_TIME_M (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S) +#define EFUSE_ECC_FORCE_CONST_TIME_V 0x00000001U +#define EFUSE_ECC_FORCE_CONST_TIME_S 14 +/** EFUSE_RD_RESERVE_0_175 : RW; bitpos: [31:15]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_175 0x0001FFFFU +#define EFUSE_RD_RESERVE_0_175_M (EFUSE_RD_RESERVE_0_175_V << EFUSE_RD_RESERVE_0_175_S) +#define EFUSE_RD_RESERVE_0_175_V 0x0001FFFFU +#define EFUSE_RD_RESERVE_0_175_S 15 -/** EFUSE_RD_MAC_SYS_0_REG register - * BLOCK1 data register $n. +/** EFUSE_RD_MAC_SYS0_REG register + * Represents rd_mac_sys */ -#define EFUSE_RD_MAC_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) +#define EFUSE_RD_MAC_SYS0_REG (DR_REG_EFUSE_BASE + 0x44) /** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; - * Stores the low 32 bits of MAC address. + * Represents MAC address. Low 32-bit. */ #define EFUSE_MAC_0 0xFFFFFFFFU #define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) #define EFUSE_MAC_0_V 0xFFFFFFFFU #define EFUSE_MAC_0_S 0 -/** EFUSE_RD_MAC_SYS_1_REG register - * BLOCK1 data register $n. +/** EFUSE_RD_MAC_SYS1_REG register + * Represents rd_mac_sys */ -#define EFUSE_RD_MAC_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) +#define EFUSE_RD_MAC_SYS1_REG (DR_REG_EFUSE_BASE + 0x48) /** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; - * Stores the high 16 bits of MAC address. + * Represents MAC address. High 16-bit. */ #define EFUSE_MAC_1 0x0000FFFFU #define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) #define EFUSE_MAC_1_V 0x0000FFFFU #define EFUSE_MAC_1_S 0 /** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0; - * Stores the extended bits of MAC address. + * Represents the extended bits of MAC address. */ #define EFUSE_MAC_EXT 0x0000FFFFU #define EFUSE_MAC_EXT_M (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S) #define EFUSE_MAC_EXT_V 0x0000FFFFU #define EFUSE_MAC_EXT_S 16 -/** EFUSE_RD_MAC_SYS_2_REG register - * BLOCK1 data register $n. +/** EFUSE_RD_MAC_SYS2_REG register + * Represents rd_mac_sys */ -#define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) -/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [13:0]; default: 0; +#define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE_BASE + 0x4c) +/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [13:0]; default: 0; * Reserved. */ -#define EFUSE_MAC_RESERVED_1 0x00003FFFU -#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S) -#define EFUSE_MAC_RESERVED_1_V 0x00003FFFU -#define EFUSE_MAC_RESERVED_1_S 0 -/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [31:14]; default: 0; - * Reserved. - */ -#define EFUSE_MAC_RESERVED_0 0x0003FFFFU +#define EFUSE_MAC_RESERVED_0 0x00003FFFU #define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S) -#define EFUSE_MAC_RESERVED_0_V 0x0003FFFFU -#define EFUSE_MAC_RESERVED_0_S 14 - -/** EFUSE_RD_MAC_SYS_3_REG register - * BLOCK1 data register $n. +#define EFUSE_MAC_RESERVED_0_V 0x00003FFFU +#define EFUSE_MAC_RESERVED_0_S 0 +/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [31:14]; default: 0; + * Reserved. */ -#define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) +#define EFUSE_MAC_RESERVED_1 0x0003FFFFU +#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S) +#define EFUSE_MAC_RESERVED_1_V 0x0003FFFFU +#define EFUSE_MAC_RESERVED_1_S 14 + +/** EFUSE_RD_MAC_SYS3_REG register + * Represents rd_mac_sys + */ +#define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE_BASE + 0x50) /** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0; * Reserved. */ @@ -606,31 +720,31 @@ extern "C" { #define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU #define EFUSE_MAC_RESERVED_2_S 0 /** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; - * Stores the first 14 bits of the zeroth part of system data. + * Represents the first 14-bit of zeroth part of system data. */ #define EFUSE_SYS_DATA_PART0_0 0x00003FFFU #define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) #define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU #define EFUSE_SYS_DATA_PART0_0_S 18 -/** EFUSE_RD_MAC_SYS_4_REG register - * BLOCK1 data register $n. +/** EFUSE_RD_MAC_SYS4_REG register + * Represents rd_mac_sys */ -#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) +#define EFUSE_RD_MAC_SYS4_REG (DR_REG_EFUSE_BASE + 0x54) /** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of the zeroth part of system data. + * Represents the first 14-bit of zeroth part of system data. */ #define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) #define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART0_1_S 0 -/** EFUSE_RD_MAC_SYS_5_REG register - * BLOCK1 data register $n. +/** EFUSE_RD_MAC_SYS5_REG register + * Represents rd_mac_sys */ -#define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) +#define EFUSE_RD_MAC_SYS5_REG (DR_REG_EFUSE_BASE + 0x58) /** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of the zeroth part of system data. + * Represents the second 32-bit of zeroth part of system data. */ #define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) @@ -638,11 +752,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART0_2_S 0 /** EFUSE_RD_SYS_PART1_DATA0_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data0 */ #define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) /** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of the first part of system data. + * Represents the zeroth 32-bit of first part of system data. */ #define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) @@ -650,11 +764,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART1_0_S 0 /** EFUSE_RD_SYS_PART1_DATA1_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data1 */ #define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) /** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of the first part of system data. + * Represents the zeroth 32-bit of first part of system data. */ #define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) @@ -662,11 +776,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART1_1_S 0 /** EFUSE_RD_SYS_PART1_DATA2_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data2 */ #define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) /** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of the first part of system data. + * Represents the zeroth 32-bit of first part of system data. */ #define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) @@ -674,11 +788,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART1_2_S 0 /** EFUSE_RD_SYS_PART1_DATA3_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data3 */ #define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) /** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of the first part of system data. + * Represents the zeroth 32-bit of first part of system data. */ #define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) @@ -686,11 +800,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART1_3_S 0 /** EFUSE_RD_SYS_PART1_DATA4_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data4 */ #define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) /** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of the first part of system data. + * Represents the zeroth 32-bit of first part of system data. */ #define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) @@ -698,11 +812,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART1_4_S 0 /** EFUSE_RD_SYS_PART1_DATA5_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data5 */ #define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) /** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of the first part of system data. + * Represents the zeroth 32-bit of first part of system data. */ #define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) @@ -710,11 +824,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART1_5_S 0 /** EFUSE_RD_SYS_PART1_DATA6_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data6 */ #define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) /** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of the first part of system data. + * Represents the zeroth 32-bit of first part of system data. */ #define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) @@ -722,11 +836,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART1_6_S 0 /** EFUSE_RD_SYS_PART1_DATA7_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data7 */ #define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) /** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of the first part of system data. + * Represents the zeroth 32-bit of first part of system data. */ #define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) @@ -734,11 +848,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART1_7_S 0 /** EFUSE_RD_USR_DATA0_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data0 */ #define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) /** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ #define EFUSE_USR_DATA0 0xFFFFFFFFU #define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) @@ -746,11 +860,11 @@ extern "C" { #define EFUSE_USR_DATA0_S 0 /** EFUSE_RD_USR_DATA1_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data1 */ #define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) /** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ #define EFUSE_USR_DATA1 0xFFFFFFFFU #define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) @@ -758,11 +872,11 @@ extern "C" { #define EFUSE_USR_DATA1_S 0 /** EFUSE_RD_USR_DATA2_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data2 */ #define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) /** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ #define EFUSE_USR_DATA2 0xFFFFFFFFU #define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) @@ -770,11 +884,11 @@ extern "C" { #define EFUSE_USR_DATA2_S 0 /** EFUSE_RD_USR_DATA3_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data3 */ #define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) /** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ #define EFUSE_USR_DATA3 0xFFFFFFFFU #define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) @@ -782,11 +896,11 @@ extern "C" { #define EFUSE_USR_DATA3_S 0 /** EFUSE_RD_USR_DATA4_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data4 */ #define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) /** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ #define EFUSE_USR_DATA4 0xFFFFFFFFU #define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) @@ -794,11 +908,11 @@ extern "C" { #define EFUSE_USR_DATA4_S 0 /** EFUSE_RD_USR_DATA5_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data5 */ #define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) /** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ #define EFUSE_USR_DATA5 0xFFFFFFFFU #define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) @@ -806,35 +920,49 @@ extern "C" { #define EFUSE_USR_DATA5_S 0 /** EFUSE_RD_USR_DATA6_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data6 */ #define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) -/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of BLOCK3 (user). +/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0; + * reserved */ -#define EFUSE_USR_DATA6 0xFFFFFFFFU -#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) -#define EFUSE_USR_DATA6_V 0xFFFFFFFFU -#define EFUSE_USR_DATA6_S 0 +#define EFUSE_RESERVED_3_192 0x000000FFU +#define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S) +#define EFUSE_RESERVED_3_192_V 0x000000FFU +#define EFUSE_RESERVED_3_192_S 0 +/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ +#define EFUSE_CUSTOM_MAC 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S) +#define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_S 8 /** EFUSE_RD_USR_DATA7_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data7 */ #define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) -/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of BLOCK3 (user). +/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC */ -#define EFUSE_USR_DATA7 0xFFFFFFFFU -#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) -#define EFUSE_USR_DATA7_V 0xFFFFFFFFU -#define EFUSE_USR_DATA7_S 0 +#define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S) +#define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_S 0 +/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_248 0x000000FFU +#define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S) +#define EFUSE_RESERVED_3_248_V 0x000000FFU +#define EFUSE_RESERVED_3_248_S 24 /** EFUSE_RD_KEY0_DATA0_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data0 */ #define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) /** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA0 0xFFFFFFFFU #define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) @@ -842,11 +970,11 @@ extern "C" { #define EFUSE_KEY0_DATA0_S 0 /** EFUSE_RD_KEY0_DATA1_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data1 */ #define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) /** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA1 0xFFFFFFFFU #define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) @@ -854,11 +982,11 @@ extern "C" { #define EFUSE_KEY0_DATA1_S 0 /** EFUSE_RD_KEY0_DATA2_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data2 */ #define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) /** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA2 0xFFFFFFFFU #define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) @@ -866,11 +994,11 @@ extern "C" { #define EFUSE_KEY0_DATA2_S 0 /** EFUSE_RD_KEY0_DATA3_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data3 */ #define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) /** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA3 0xFFFFFFFFU #define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) @@ -878,11 +1006,11 @@ extern "C" { #define EFUSE_KEY0_DATA3_S 0 /** EFUSE_RD_KEY0_DATA4_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data4 */ #define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) /** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA4 0xFFFFFFFFU #define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) @@ -890,11 +1018,11 @@ extern "C" { #define EFUSE_KEY0_DATA4_S 0 /** EFUSE_RD_KEY0_DATA5_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data5 */ #define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) /** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA5 0xFFFFFFFFU #define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) @@ -902,11 +1030,11 @@ extern "C" { #define EFUSE_KEY0_DATA5_S 0 /** EFUSE_RD_KEY0_DATA6_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data6 */ #define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) /** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA6 0xFFFFFFFFU #define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) @@ -914,11 +1042,11 @@ extern "C" { #define EFUSE_KEY0_DATA6_S 0 /** EFUSE_RD_KEY0_DATA7_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data7 */ #define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) /** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA7 0xFFFFFFFFU #define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) @@ -926,11 +1054,11 @@ extern "C" { #define EFUSE_KEY0_DATA7_S 0 /** EFUSE_RD_KEY1_DATA0_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data0 */ #define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) /** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA0 0xFFFFFFFFU #define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) @@ -938,11 +1066,11 @@ extern "C" { #define EFUSE_KEY1_DATA0_S 0 /** EFUSE_RD_KEY1_DATA1_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data1 */ #define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) /** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA1 0xFFFFFFFFU #define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) @@ -950,11 +1078,11 @@ extern "C" { #define EFUSE_KEY1_DATA1_S 0 /** EFUSE_RD_KEY1_DATA2_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data2 */ #define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) /** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA2 0xFFFFFFFFU #define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) @@ -962,11 +1090,11 @@ extern "C" { #define EFUSE_KEY1_DATA2_S 0 /** EFUSE_RD_KEY1_DATA3_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data3 */ #define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) /** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA3 0xFFFFFFFFU #define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) @@ -974,11 +1102,11 @@ extern "C" { #define EFUSE_KEY1_DATA3_S 0 /** EFUSE_RD_KEY1_DATA4_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data4 */ #define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) /** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA4 0xFFFFFFFFU #define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) @@ -986,11 +1114,11 @@ extern "C" { #define EFUSE_KEY1_DATA4_S 0 /** EFUSE_RD_KEY1_DATA5_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data5 */ #define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) /** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA5 0xFFFFFFFFU #define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) @@ -998,11 +1126,11 @@ extern "C" { #define EFUSE_KEY1_DATA5_S 0 /** EFUSE_RD_KEY1_DATA6_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data6 */ #define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) /** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA6 0xFFFFFFFFU #define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) @@ -1010,11 +1138,11 @@ extern "C" { #define EFUSE_KEY1_DATA6_S 0 /** EFUSE_RD_KEY1_DATA7_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data7 */ #define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) /** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA7 0xFFFFFFFFU #define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) @@ -1022,11 +1150,11 @@ extern "C" { #define EFUSE_KEY1_DATA7_S 0 /** EFUSE_RD_KEY2_DATA0_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data0 */ #define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) /** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA0 0xFFFFFFFFU #define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) @@ -1034,11 +1162,11 @@ extern "C" { #define EFUSE_KEY2_DATA0_S 0 /** EFUSE_RD_KEY2_DATA1_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data1 */ #define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) /** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA1 0xFFFFFFFFU #define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) @@ -1046,11 +1174,11 @@ extern "C" { #define EFUSE_KEY2_DATA1_S 0 /** EFUSE_RD_KEY2_DATA2_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data2 */ #define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) /** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA2 0xFFFFFFFFU #define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) @@ -1058,11 +1186,11 @@ extern "C" { #define EFUSE_KEY2_DATA2_S 0 /** EFUSE_RD_KEY2_DATA3_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data3 */ #define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) /** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA3 0xFFFFFFFFU #define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) @@ -1070,11 +1198,11 @@ extern "C" { #define EFUSE_KEY2_DATA3_S 0 /** EFUSE_RD_KEY2_DATA4_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data4 */ #define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) /** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA4 0xFFFFFFFFU #define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) @@ -1082,11 +1210,11 @@ extern "C" { #define EFUSE_KEY2_DATA4_S 0 /** EFUSE_RD_KEY2_DATA5_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data5 */ #define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) /** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA5 0xFFFFFFFFU #define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) @@ -1094,11 +1222,11 @@ extern "C" { #define EFUSE_KEY2_DATA5_S 0 /** EFUSE_RD_KEY2_DATA6_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data6 */ #define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) /** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA6 0xFFFFFFFFU #define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) @@ -1106,11 +1234,11 @@ extern "C" { #define EFUSE_KEY2_DATA6_S 0 /** EFUSE_RD_KEY2_DATA7_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data7 */ #define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) /** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA7 0xFFFFFFFFU #define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) @@ -1118,11 +1246,11 @@ extern "C" { #define EFUSE_KEY2_DATA7_S 0 /** EFUSE_RD_KEY3_DATA0_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data0 */ #define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) /** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA0 0xFFFFFFFFU #define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) @@ -1130,11 +1258,11 @@ extern "C" { #define EFUSE_KEY3_DATA0_S 0 /** EFUSE_RD_KEY3_DATA1_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data1 */ #define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) /** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA1 0xFFFFFFFFU #define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) @@ -1142,11 +1270,11 @@ extern "C" { #define EFUSE_KEY3_DATA1_S 0 /** EFUSE_RD_KEY3_DATA2_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data2 */ #define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) /** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA2 0xFFFFFFFFU #define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) @@ -1154,11 +1282,11 @@ extern "C" { #define EFUSE_KEY3_DATA2_S 0 /** EFUSE_RD_KEY3_DATA3_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data3 */ #define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) /** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA3 0xFFFFFFFFU #define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) @@ -1166,11 +1294,11 @@ extern "C" { #define EFUSE_KEY3_DATA3_S 0 /** EFUSE_RD_KEY3_DATA4_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data4 */ #define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) /** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA4 0xFFFFFFFFU #define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) @@ -1178,11 +1306,11 @@ extern "C" { #define EFUSE_KEY3_DATA4_S 0 /** EFUSE_RD_KEY3_DATA5_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data5 */ #define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) /** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA5 0xFFFFFFFFU #define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) @@ -1190,11 +1318,11 @@ extern "C" { #define EFUSE_KEY3_DATA5_S 0 /** EFUSE_RD_KEY3_DATA6_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data6 */ #define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) /** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA6 0xFFFFFFFFU #define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) @@ -1202,11 +1330,11 @@ extern "C" { #define EFUSE_KEY3_DATA6_S 0 /** EFUSE_RD_KEY3_DATA7_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data7 */ #define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) /** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA7 0xFFFFFFFFU #define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) @@ -1214,11 +1342,11 @@ extern "C" { #define EFUSE_KEY3_DATA7_S 0 /** EFUSE_RD_KEY4_DATA0_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data0 */ #define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) /** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA0 0xFFFFFFFFU #define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) @@ -1226,11 +1354,11 @@ extern "C" { #define EFUSE_KEY4_DATA0_S 0 /** EFUSE_RD_KEY4_DATA1_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data1 */ #define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) /** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA1 0xFFFFFFFFU #define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) @@ -1238,11 +1366,11 @@ extern "C" { #define EFUSE_KEY4_DATA1_S 0 /** EFUSE_RD_KEY4_DATA2_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data2 */ #define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) /** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA2 0xFFFFFFFFU #define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) @@ -1250,11 +1378,11 @@ extern "C" { #define EFUSE_KEY4_DATA2_S 0 /** EFUSE_RD_KEY4_DATA3_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data3 */ #define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) /** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA3 0xFFFFFFFFU #define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) @@ -1262,11 +1390,11 @@ extern "C" { #define EFUSE_KEY4_DATA3_S 0 /** EFUSE_RD_KEY4_DATA4_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data4 */ #define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) /** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA4 0xFFFFFFFFU #define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) @@ -1274,11 +1402,11 @@ extern "C" { #define EFUSE_KEY4_DATA4_S 0 /** EFUSE_RD_KEY4_DATA5_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data5 */ #define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) /** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA5 0xFFFFFFFFU #define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) @@ -1286,11 +1414,11 @@ extern "C" { #define EFUSE_KEY4_DATA5_S 0 /** EFUSE_RD_KEY4_DATA6_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data6 */ #define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) /** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA6 0xFFFFFFFFU #define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) @@ -1298,11 +1426,11 @@ extern "C" { #define EFUSE_KEY4_DATA6_S 0 /** EFUSE_RD_KEY4_DATA7_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data7 */ #define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) /** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA7 0xFFFFFFFFU #define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) @@ -1310,11 +1438,11 @@ extern "C" { #define EFUSE_KEY4_DATA7_S 0 /** EFUSE_RD_KEY5_DATA0_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data0 */ #define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) /** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA0 0xFFFFFFFFU #define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) @@ -1322,11 +1450,11 @@ extern "C" { #define EFUSE_KEY5_DATA0_S 0 /** EFUSE_RD_KEY5_DATA1_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data1 */ #define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) /** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA1 0xFFFFFFFFU #define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) @@ -1334,11 +1462,11 @@ extern "C" { #define EFUSE_KEY5_DATA1_S 0 /** EFUSE_RD_KEY5_DATA2_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data2 */ #define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) /** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA2 0xFFFFFFFFU #define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) @@ -1346,11 +1474,11 @@ extern "C" { #define EFUSE_KEY5_DATA2_S 0 /** EFUSE_RD_KEY5_DATA3_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data3 */ #define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) /** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA3 0xFFFFFFFFU #define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) @@ -1358,11 +1486,11 @@ extern "C" { #define EFUSE_KEY5_DATA3_S 0 /** EFUSE_RD_KEY5_DATA4_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data4 */ #define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) /** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA4 0xFFFFFFFFU #define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) @@ -1370,11 +1498,11 @@ extern "C" { #define EFUSE_KEY5_DATA4_S 0 /** EFUSE_RD_KEY5_DATA5_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data5 */ #define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) /** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA5 0xFFFFFFFFU #define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) @@ -1382,11 +1510,11 @@ extern "C" { #define EFUSE_KEY5_DATA5_S 0 /** EFUSE_RD_KEY5_DATA6_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data6 */ #define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) /** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA6 0xFFFFFFFFU #define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) @@ -1394,11 +1522,11 @@ extern "C" { #define EFUSE_KEY5_DATA6_S 0 /** EFUSE_RD_KEY5_DATA7_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data7 */ #define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) /** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA7 0xFFFFFFFFU #define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) @@ -1406,11 +1534,11 @@ extern "C" { #define EFUSE_KEY5_DATA7_S 0 /** EFUSE_RD_SYS_PART2_DATA0_REG register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data0 */ #define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) /** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ #define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) @@ -1418,11 +1546,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_0_S 0 /** EFUSE_RD_SYS_PART2_DATA1_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_sys_part2_data1 */ #define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) /** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ #define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) @@ -1430,11 +1558,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_1_S 0 /** EFUSE_RD_SYS_PART2_DATA2_REG register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data2 */ #define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) /** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ #define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) @@ -1442,11 +1570,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_2_S 0 /** EFUSE_RD_SYS_PART2_DATA3_REG register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data3 */ #define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) /** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ #define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) @@ -1454,11 +1582,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_3_S 0 /** EFUSE_RD_SYS_PART2_DATA4_REG register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data4 */ #define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) /** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ #define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) @@ -1466,11 +1594,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_4_S 0 /** EFUSE_RD_SYS_PART2_DATA5_REG register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data5 */ #define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) /** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ #define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) @@ -1478,11 +1606,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_5_S 0 /** EFUSE_RD_SYS_PART2_DATA6_REG register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data6 */ #define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) /** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ #define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) @@ -1490,537 +1618,600 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_6_S 0 /** EFUSE_RD_SYS_PART2_DATA7_REG register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data7 */ #define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) /** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ #define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) #define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_7_S 0 -/** EFUSE_RD_REPEAT_ERR0_REG register - * Programming error record register 0 of BLOCK0. +/** EFUSE_RD_REPEAT_DATA_ERR0_REG register + * Represents rd_repeat_data_err */ -#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) +#define EFUSE_RD_REPEAT_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) /** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; - * Indicates a programming error of RD_DIS. + * Represents the programming error of EFUSE_RD_DIS */ #define EFUSE_RD_DIS_ERR 0x0000007FU #define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) #define EFUSE_RD_DIS_ERR_V 0x0000007FU #define EFUSE_RD_DIS_ERR_S 0 /** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; - * Indicates a programming error of DIS_ICACHE. + * Represents the programming error of EFUSE_DIS_ICACHE */ #define EFUSE_DIS_ICACHE_ERR (BIT(8)) #define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) #define EFUSE_DIS_ICACHE_ERR_V 0x00000001U #define EFUSE_DIS_ICACHE_ERR_S 8 /** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0; - * Indicates a programming error of DIS_USB_JTAG. + * Represents the programming error of EFUSE_DIS_USB_JTAG */ #define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) #define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) #define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U #define EFUSE_DIS_USB_JTAG_ERR_S 9 +/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR (BIT(11)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S 11 /** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; - * Indicates a programming error of DIS_FORCE_DOWNLOAD. + * Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD */ #define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 /** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0; - * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + * Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS */ #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR (BIT(13)) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V 0x00000001U #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S 13 /** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0; - * Indicates a programming error of DIS_CAN. + * Represents the programming error of EFUSE_DIS_TWAI */ #define EFUSE_DIS_TWAI_ERR (BIT(14)) #define EFUSE_DIS_TWAI_ERR_M (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S) #define EFUSE_DIS_TWAI_ERR_V 0x00000001U #define EFUSE_DIS_TWAI_ERR_S 14 /** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0; - * Indicates a programming error of JTAG_SEL_ENABLE. + * Represents the programming error of EFUSE_JTAG_SEL_ENABLE */ #define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) #define EFUSE_JTAG_SEL_ENABLE_ERR_M (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S) #define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x00000001U #define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 /** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0; - * Indicates a programming error of SOFT_DIS_JTAG. + * Represents the programming error of EFUSE_SOFT_DIS_JTAG */ #define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007U #define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) #define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007U #define EFUSE_SOFT_DIS_JTAG_ERR_S 16 /** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0; - * Indicates a programming error of DIS_PAD_JTAG. + * Represents the programming error of EFUSE_DIS_PAD_JTAG */ #define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) #define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) #define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U #define EFUSE_DIS_PAD_JTAG_ERR_S 19 /** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0; - * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + * Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT */ #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 +/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0; + * Represents the programming error of EFUSE_USB_DREFH + */ +#define EFUSE_USB_DREFH_ERR 0x00000003U +#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) +#define EFUSE_USB_DREFH_ERR_V 0x00000003U +#define EFUSE_USB_DREFH_ERR_S 21 +/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0; + * Represents the programming error of EFUSE_USB_DREFL + */ +#define EFUSE_USB_DREFL_ERR 0x00000003U +#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) +#define EFUSE_USB_DREFL_ERR_V 0x00000003U +#define EFUSE_USB_DREFL_ERR_S 23 /** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0; - * Indicates a programming error of USB_EXCHG_PINS. + * Represents the programming error of EFUSE_USB_EXCHG_PINS */ #define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) #define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) #define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001U #define EFUSE_USB_EXCHG_PINS_ERR_S 25 /** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0; - * Indicates a programming error of VDD_SPI_AS_GPIO. + * Represents the programming error of EFUSE_VDD_SPI_AS_GPIO */ #define EFUSE_VDD_SPI_AS_GPIO_ERR (BIT(26)) #define EFUSE_VDD_SPI_AS_GPIO_ERR_M (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S) #define EFUSE_VDD_SPI_AS_GPIO_ERR_V 0x00000001U #define EFUSE_VDD_SPI_AS_GPIO_ERR_S 26 -/** EFUSE_HUK_GEN_STATE_PART1_ERR : RO; bitpos: [31:27]; default: 0; - * Indicates a programming error of EFUSE_HUK_GEN_STATE_PART1. - */ -#define EFUSE_HUK_GEN_STATE_PART1_ERR 0x0000001FU -#define EFUSE_HUK_GEN_STATE_PART1_ERR_M (EFUSE_HUK_GEN_STATE_PART1_ERR_V << EFUSE_HUK_GEN_STATE_PART1_ERR_S) -#define EFUSE_HUK_GEN_STATE_PART1_ERR_V 0x0000001FU -#define EFUSE_HUK_GEN_STATE_PART1_ERR_S 27 -/** EFUSE_RD_REPEAT_ERR1_REG register - * Programming error record register 1 of BLOCK0. +/** EFUSE_RD_REPEAT_DATA_ERR1_REG register + * Represents rd_repeat_data_err */ -#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) -/** EFUSE_HUK_GEN_STATE_PART2_ERR : RO; bitpos: [3:0]; default: 0; - * Indicates a programming error of EFUSE_HUK_GEN_STATE_PART2. +#define EFUSE_RD_REPEAT_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) +/** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [3:0]; default: 0; + * Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE */ -#define EFUSE_HUK_GEN_STATE_PART2_ERR 0x0000000FU -#define EFUSE_HUK_GEN_STATE_PART2_ERR_M (EFUSE_HUK_GEN_STATE_PART2_ERR_V << EFUSE_HUK_GEN_STATE_PART2_ERR_S) -#define EFUSE_HUK_GEN_STATE_PART2_ERR_V 0x0000000FU -#define EFUSE_HUK_GEN_STATE_PART2_ERR_S 0 +#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR 0x0000000FU +#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M (EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S) +#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V 0x0000000FU +#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S 0 /** EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO; bitpos: [5:4]; default: 0; - * Indicates a programming error of EFUSE_KM_RND_SWITCH_CYCLE. + * Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE */ #define EFUSE_KM_RND_SWITCH_CYCLE_ERR 0x00000003U #define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M (EFUSE_KM_RND_SWITCH_CYCLE_ERR_V << EFUSE_KM_RND_SWITCH_CYCLE_ERR_S) #define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V 0x00000003U #define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S 4 /** EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO; bitpos: [9:6]; default: 0; - * Indicates a programming error of EFUSE_KM_DEPLOY_ONLY_ONCE. + * Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE */ #define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR 0x0000000FU #define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M (EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V << EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S) #define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V 0x0000000FU #define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S 6 /** EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO; bitpos: [13:10]; default: 0; - * Indicates a programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY. + * Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY */ #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR 0x0000000FU #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M (EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S) #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V 0x0000000FU #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S 10 /** EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO; bitpos: [14]; default: 0; - * Indicates a programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY. + * Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY */ #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR (BIT(14)) #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M (EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S) #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V 0x00000001U #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S 14 -/** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [15]; default: 0; - * Indicates a programming error of EFUSE_KM_DISABLE_DEPLOY_MODE. - */ -#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR (BIT(15)) -#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M (EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S) -#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V 0x00000001U -#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S 15 /** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; - * Indicates a programming error of WDT_DELAY_SEL. + * Represents the programming error of EFUSE_WDT_DELAY_SEL */ #define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U #define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) #define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U #define EFUSE_WDT_DELAY_SEL_ERR_S 16 /** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; - * Indicates a programming error of SPI_BOOT_CRYPT_CNT. + * Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT */ #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 /** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0 */ #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 /** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1 */ #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 /** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2 */ #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 /** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; - * Indicates a programming error of KEY_PURPOSE_0. + * Represents the programming error of EFUSE_KEY_PURPOSE_0 */ #define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) #define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_0_ERR_S 24 /** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; - * Indicates a programming error of KEY_PURPOSE_1. + * Represents the programming error of EFUSE_KEY_PURPOSE_1 */ #define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) #define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_1_ERR_S 28 -/** EFUSE_RD_REPEAT_ERR2_REG register - * Programming error record register 2 of BLOCK0. +/** EFUSE_RD_REPEAT_DATA_ERR2_REG register + * Represents rd_repeat_data_err */ -#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) +#define EFUSE_RD_REPEAT_DATA_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) /** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; - * Indicates a programming error of KEY_PURPOSE_2. + * Represents the programming error of EFUSE_KEY_PURPOSE_2 */ #define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) #define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_ERR_S 0 /** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; - * Indicates a programming error of KEY_PURPOSE_3. + * Represents the programming error of EFUSE_KEY_PURPOSE_3 */ #define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) #define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_3_ERR_S 4 /** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; - * Indicates a programming error of KEY_PURPOSE_4. + * Represents the programming error of EFUSE_KEY_PURPOSE_4 */ #define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) #define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_4_ERR_S 8 /** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; - * Indicates a programming error of KEY_PURPOSE_5. + * Represents the programming error of EFUSE_KEY_PURPOSE_5 */ #define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) #define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_5_ERR_S 12 /** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0; - * Indicates a programming error of SEC_DPA_LEVEL. + * Represents the programming error of EFUSE_SEC_DPA_LEVEL */ #define EFUSE_SEC_DPA_LEVEL_ERR 0x00000003U #define EFUSE_SEC_DPA_LEVEL_ERR_M (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S) #define EFUSE_SEC_DPA_LEVEL_ERR_V 0x00000003U #define EFUSE_SEC_DPA_LEVEL_ERR_S 16 -/** EFUSE_ECDSA_ENABLE_SOFT_K_ERR : RO; bitpos: [18]; default: 0; - * Reserved. - */ -#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR (BIT(18)) -#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_M (EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V << EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S) -#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V 0x00000001U -#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S 18 -/** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0; - * Indicates a programming error of CRYPT_DPA_ENABLE. - */ -#define EFUSE_CRYPT_DPA_ENABLE_ERR (BIT(19)) -#define EFUSE_CRYPT_DPA_ENABLE_ERR_M (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S) -#define EFUSE_CRYPT_DPA_ENABLE_ERR_V 0x00000001U -#define EFUSE_CRYPT_DPA_ENABLE_ERR_S 19 /** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; - * Indicates a programming error of SECURE_BOOT_EN. + * Represents the programming error of EFUSE_SECURE_BOOT_EN */ #define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) #define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) #define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_EN_ERR_S 20 /** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; - * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + * Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE */ #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 +/** EFUSE_KM_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [27]; default: 0; + * Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256 + */ +#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR (BIT(27)) +#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_M (EFUSE_KM_XTS_KEY_LENGTH_256_ERR_V << EFUSE_KM_XTS_KEY_LENGTH_256_ERR_S) +#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_V 0x00000001U +#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_S 27 /** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; - * Indicates a programming error of FLASH_TPUW. + * Represents the programming error of EFUSE_FLASH_TPUW */ #define EFUSE_FLASH_TPUW_ERR 0x0000000FU #define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) #define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU #define EFUSE_FLASH_TPUW_ERR_S 28 -/** EFUSE_RD_REPEAT_ERR3_REG register - * Programming error record register 3 of BLOCK0. +/** EFUSE_RD_REPEAT_DATA_ERR3_REG register + * Represents rd_repeat_data_err */ -#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) +#define EFUSE_RD_REPEAT_DATA_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) /** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; - * Indicates a programming error of DIS_DOWNLOAD_MODE. + * Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE */ #define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) #define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 /** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0; - * Indicates a programming error of DIS_DIRECT_BOOT. + * Represents the programming error of EFUSE_DIS_DIRECT_BOOT */ #define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) #define EFUSE_DIS_DIRECT_BOOT_ERR_M (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S) #define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x00000001U #define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 -/** EFUSE_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0; - * Indicates a programming error of UART_PRINT_CHANNEL. +/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT */ -#define EFUSE_USB_SERIAL_JTAG_ROM_PRINT_ERR (BIT(2)) -#define EFUSE_USB_SERIAL_JTAG_ROM_PRINT_ERR_M (EFUSE_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_USB_SERIAL_JTAG_ROM_PRINT_ERR_S) -#define EFUSE_USB_SERIAL_JTAG_ROM_PRINT_ERR_V 0x00000001U -#define EFUSE_USB_SERIAL_JTAG_ROM_PRINT_ERR_S 2 +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR (BIT(2)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S 2 /** EFUSE_LOCK_KM_KEY_ERR : RO; bitpos: [3]; default: 0; - * TBD. + * Represents the programming error of EFUSE_LOCK_KM_KEY */ #define EFUSE_LOCK_KM_KEY_ERR (BIT(3)) #define EFUSE_LOCK_KM_KEY_ERR_M (EFUSE_LOCK_KM_KEY_ERR_V << EFUSE_LOCK_KM_KEY_ERR_S) #define EFUSE_LOCK_KM_KEY_ERR_V 0x00000001U #define EFUSE_LOCK_KM_KEY_ERR_S 3 /** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; - * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE */ #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(4)) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 4 /** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; - * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + * Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD */ #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 /** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; - * Indicates a programming error of UART_PRINT_CONTROL. + * Represents the programming error of EFUSE_UART_PRINT_CONTROL */ #define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U #define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) #define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U #define EFUSE_UART_PRINT_CONTROL_ERR_S 6 /** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0; - * Indicates a programming error of FORCE_SEND_RESUME. + * Represents the programming error of EFUSE_FORCE_SEND_RESUME */ #define EFUSE_FORCE_SEND_RESUME_ERR (BIT(8)) #define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) #define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U #define EFUSE_FORCE_SEND_RESUME_ERR_S 8 /** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0; - * Indicates a programming error of SECURE VERSION. + * Represents the programming error of EFUSE_SECURE_VERSION */ #define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU #define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) #define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU #define EFUSE_SECURE_VERSION_ERR_S 9 /** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0; - * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + * Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE */ #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR (BIT(25)) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S 25 /** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [26]; default: 0; - * Indicates a programming error of HYS_EN_PAD. + * Represents the programming error of EFUSE_HYS_EN_PAD */ #define EFUSE_HYS_EN_PAD_ERR (BIT(26)) #define EFUSE_HYS_EN_PAD_ERR_M (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S) #define EFUSE_HYS_EN_PAD_ERR_V 0x00000001U #define EFUSE_HYS_EN_PAD_ERR_S 26 -/** EFUSE_RD_REPEAT_ERR4_REG register - * Programming error record register 4 of BLOCK0. +/** EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR : RO; bitpos: [28:27]; default: 0; + * Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL */ -#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c) -/** EFUSE_RESERVED_0_ERR : RO; bitpos: [31:24]; default: 0; - * Reserved. +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR 0x00000003U +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S) +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V 0x00000003U +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S 27 +/** EFUSE_XTS_DPA_CLK_ENABLE_ERR : RO; bitpos: [29]; default: 0; + * Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE */ -#define EFUSE_RESERVED_0_ERR 0x000000FFU -#define EFUSE_RESERVED_0_ERR_M (EFUSE_RESERVED_0_ERR_V << EFUSE_RESERVED_0_ERR_S) -#define EFUSE_RESERVED_0_ERR_V 0x000000FFU -#define EFUSE_RESERVED_0_ERR_S 24 +#define EFUSE_XTS_DPA_CLK_ENABLE_ERR (BIT(29)) +#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_M (EFUSE_XTS_DPA_CLK_ENABLE_ERR_V << EFUSE_XTS_DPA_CLK_ENABLE_ERR_S) +#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_V 0x00000001U +#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_S 29 -/** EFUSE_RD_RS_ERR0_REG register - * Programming error record register 0 of BLOCK1-10. +/** EFUSE_RD_REPEAT_DATA_ERR4_REG register + * Represents rd_repeat_data_err */ -#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) -/** EFUSE_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_RD_REPEAT_DATA_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c) +/** EFUSE_HUK_GEN_STATE_ERR : RO; bitpos: [8:0]; default: 0; + * Represents the programming error of EFUSE_HUK_GEN_STATE */ -#define EFUSE_MAC_SYS_ERR_NUM 0x00000007U -#define EFUSE_MAC_SYS_ERR_NUM_M (EFUSE_MAC_SYS_ERR_NUM_V << EFUSE_MAC_SYS_ERR_NUM_S) -#define EFUSE_MAC_SYS_ERR_NUM_V 0x00000007U -#define EFUSE_MAC_SYS_ERR_NUM_S 0 -/** EFUSE_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of MAC_SYS is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. +#define EFUSE_HUK_GEN_STATE_ERR 0x000001FFU +#define EFUSE_HUK_GEN_STATE_ERR_M (EFUSE_HUK_GEN_STATE_ERR_V << EFUSE_HUK_GEN_STATE_ERR_S) +#define EFUSE_HUK_GEN_STATE_ERR_V 0x000001FFU +#define EFUSE_HUK_GEN_STATE_ERR_S 0 +/** EFUSE_XTAL_48M_SEL_ERR : RO; bitpos: [11:9]; default: 0; + * Represents the programming error of EFUSE_XTAL_48M_SEL */ -#define EFUSE_MAC_SYS_FAIL (BIT(3)) -#define EFUSE_MAC_SYS_FAIL_M (EFUSE_MAC_SYS_FAIL_V << EFUSE_MAC_SYS_FAIL_S) -#define EFUSE_MAC_SYS_FAIL_V 0x00000001U -#define EFUSE_MAC_SYS_FAIL_S 3 -/** EFUSE_SYS_PART1_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_XTAL_48M_SEL_ERR 0x00000007U +#define EFUSE_XTAL_48M_SEL_ERR_M (EFUSE_XTAL_48M_SEL_ERR_V << EFUSE_XTAL_48M_SEL_ERR_S) +#define EFUSE_XTAL_48M_SEL_ERR_V 0x00000007U +#define EFUSE_XTAL_48M_SEL_ERR_S 9 +/** EFUSE_XTAL_48M_SEL_MODE_ERR : RO; bitpos: [12]; default: 0; + * Represents the programming error of EFUSE_XTAL_48M_SEL_MODE */ -#define EFUSE_SYS_PART1_ERR_NUM 0x00000007U -#define EFUSE_SYS_PART1_ERR_NUM_M (EFUSE_SYS_PART1_ERR_NUM_V << EFUSE_SYS_PART1_ERR_NUM_S) -#define EFUSE_SYS_PART1_ERR_NUM_V 0x00000007U -#define EFUSE_SYS_PART1_ERR_NUM_S 4 -/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part1 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. +#define EFUSE_XTAL_48M_SEL_MODE_ERR (BIT(12)) +#define EFUSE_XTAL_48M_SEL_MODE_ERR_M (EFUSE_XTAL_48M_SEL_MODE_ERR_V << EFUSE_XTAL_48M_SEL_MODE_ERR_S) +#define EFUSE_XTAL_48M_SEL_MODE_ERR_V 0x00000001U +#define EFUSE_XTAL_48M_SEL_MODE_ERR_S 12 +/** EFUSE_ECDSA_DISABLE_P192_ERR : RO; bitpos: [13]; default: 0; + * Represents the programming error of EFUSE_ECDSA_DISABLE_P192 */ -#define EFUSE_SYS_PART1_FAIL (BIT(7)) -#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) -#define EFUSE_SYS_PART1_FAIL_V 0x00000001U -#define EFUSE_SYS_PART1_FAIL_S 7 -/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_ECDSA_DISABLE_P192_ERR (BIT(13)) +#define EFUSE_ECDSA_DISABLE_P192_ERR_M (EFUSE_ECDSA_DISABLE_P192_ERR_V << EFUSE_ECDSA_DISABLE_P192_ERR_S) +#define EFUSE_ECDSA_DISABLE_P192_ERR_V 0x00000001U +#define EFUSE_ECDSA_DISABLE_P192_ERR_S 13 +/** EFUSE_ECC_FORCE_CONST_TIME_ERR : RO; bitpos: [14]; default: 0; + * Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME */ -#define EFUSE_USR_DATA_ERR_NUM 0x00000007U -#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) -#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_USR_DATA_ERR_NUM_S 8 -/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; - * 0: Means no failure and that the user data is reliable 1: Means that programming - * user data failed and the number of error bytes is over 6. - */ -#define EFUSE_USR_DATA_FAIL (BIT(11)) -#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) -#define EFUSE_USR_DATA_FAIL_V 0x00000001U -#define EFUSE_USR_DATA_FAIL_S 11 -/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_KEY0_ERR_NUM 0x00000007U -#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) -#define EFUSE_KEY0_ERR_NUM_V 0x00000007U -#define EFUSE_KEY0_ERR_NUM_S 12 -/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; - * 0: Means no failure and that the data of key0 is reliable 1: Means that programming - * key0 failed and the number of error bytes is over 6. - */ -#define EFUSE_KEY0_FAIL (BIT(15)) -#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) -#define EFUSE_KEY0_FAIL_V 0x00000001U -#define EFUSE_KEY0_FAIL_S 15 -/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_KEY1_ERR_NUM 0x00000007U -#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) -#define EFUSE_KEY1_ERR_NUM_V 0x00000007U -#define EFUSE_KEY1_ERR_NUM_S 16 -/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; - * 0: Means no failure and that the data of key1 is reliable 1: Means that programming - * key1 failed and the number of error bytes is over 6. - */ -#define EFUSE_KEY1_FAIL (BIT(19)) -#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) -#define EFUSE_KEY1_FAIL_V 0x00000001U -#define EFUSE_KEY1_FAIL_S 19 -/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_KEY2_ERR_NUM 0x00000007U -#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) -#define EFUSE_KEY2_ERR_NUM_V 0x00000007U -#define EFUSE_KEY2_ERR_NUM_S 20 -/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; - * 0: Means no failure and that the data of key2 is reliable 1: Means that programming - * key2 failed and the number of error bytes is over 6. - */ -#define EFUSE_KEY2_FAIL (BIT(23)) -#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) -#define EFUSE_KEY2_FAIL_V 0x00000001U -#define EFUSE_KEY2_FAIL_S 23 -/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_KEY3_ERR_NUM 0x00000007U -#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) -#define EFUSE_KEY3_ERR_NUM_V 0x00000007U -#define EFUSE_KEY3_ERR_NUM_S 24 -/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; - * 0: Means no failure and that the data of key3 is reliable 1: Means that programming - * key3 failed and the number of error bytes is over 6. - */ -#define EFUSE_KEY3_FAIL (BIT(27)) -#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) -#define EFUSE_KEY3_FAIL_V 0x00000001U -#define EFUSE_KEY3_FAIL_S 27 -/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; - * The value of this signal means the number of error bytes. - */ -#define EFUSE_KEY4_ERR_NUM 0x00000007U -#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) -#define EFUSE_KEY4_ERR_NUM_V 0x00000007U -#define EFUSE_KEY4_ERR_NUM_S 28 -/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; - * 0: Means no failure and that the data of key4 is reliable 1: Means that programming - * key4 failed and the number of error bytes is over 6. - */ -#define EFUSE_KEY4_FAIL (BIT(31)) -#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) -#define EFUSE_KEY4_FAIL_V 0x00000001U -#define EFUSE_KEY4_FAIL_S 31 +#define EFUSE_ECC_FORCE_CONST_TIME_ERR (BIT(14)) +#define EFUSE_ECC_FORCE_CONST_TIME_ERR_M (EFUSE_ECC_FORCE_CONST_TIME_ERR_V << EFUSE_ECC_FORCE_CONST_TIME_ERR_S) +#define EFUSE_ECC_FORCE_CONST_TIME_ERR_V 0x00000001U +#define EFUSE_ECC_FORCE_CONST_TIME_ERR_S 14 -/** EFUSE_RD_RS_ERR1_REG register - * Programming error record register 1 of BLOCK1-10. +/** EFUSE_RD_RS_DATA_ERR0_REG register + * Represents rd_rs_data_err */ -#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) -/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_RD_RS_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) +/** EFUSE_RD_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * Represents the error number of registers..The value of this signal means the + * number of error bytes in rd_mac_sys */ -#define EFUSE_KEY5_ERR_NUM 0x00000007U -#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) -#define EFUSE_KEY5_ERR_NUM_V 0x00000007U -#define EFUSE_KEY5_ERR_NUM_S 0 -/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of key5 is reliable 1: Means that programming - * key5 failed and the number of error bytes is over 6. +#define EFUSE_RD_MAC_SYS_ERR_NUM 0x00000007U +#define EFUSE_RD_MAC_SYS_ERR_NUM_M (EFUSE_RD_MAC_SYS_ERR_NUM_V << EFUSE_RD_MAC_SYS_ERR_NUM_S) +#define EFUSE_RD_MAC_SYS_ERR_NUM_V 0x00000007U +#define EFUSE_RD_MAC_SYS_ERR_NUM_S 0 +/** EFUSE_RD_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0; + * Represents error status of register..0: Means no failure and that the data of + * rd_mac_sys is reliable. 1: Means that programming rd_mac_sys failed and the number + * of error bytes is over 6. */ -#define EFUSE_KEY5_FAIL (BIT(3)) -#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) -#define EFUSE_KEY5_FAIL_V 0x00000001U -#define EFUSE_KEY5_FAIL_S 3 -/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_RD_MAC_SYS_FAIL (BIT(3)) +#define EFUSE_RD_MAC_SYS_FAIL_M (EFUSE_RD_MAC_SYS_FAIL_V << EFUSE_RD_MAC_SYS_FAIL_S) +#define EFUSE_RD_MAC_SYS_FAIL_V 0x00000001U +#define EFUSE_RD_MAC_SYS_FAIL_S 3 +/** EFUSE_RD_SYS_PART1_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * Represents the error number of registers..The value of this signal means the + * number of error bytes in rd_sys_part1_data */ -#define EFUSE_SYS_PART2_ERR_NUM 0x00000007U -#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) -#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007U -#define EFUSE_SYS_PART2_ERR_NUM_S 4 -/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part2 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. +#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S) +#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S 4 +/** EFUSE_RD_SYS_PART1_DATA_FAIL : RO; bitpos: [7]; default: 0; + * Represents error status of register..0: Means no failure and that the data of + * rd_sys_part1_data is reliable. 1: Means that programming rd_sys_part1_data failed + * and the number of error bytes is over 6. */ -#define EFUSE_SYS_PART2_FAIL (BIT(7)) -#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) -#define EFUSE_SYS_PART2_FAIL_V 0x00000001U -#define EFUSE_SYS_PART2_FAIL_S 7 +#define EFUSE_RD_SYS_PART1_DATA_FAIL (BIT(7)) +#define EFUSE_RD_SYS_PART1_DATA_FAIL_M (EFUSE_RD_SYS_PART1_DATA_FAIL_V << EFUSE_RD_SYS_PART1_DATA_FAIL_S) +#define EFUSE_RD_SYS_PART1_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_SYS_PART1_DATA_FAIL_S 7 +/** EFUSE_RD_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * Represents the error number of registers..The value of this signal means the + * number of error bytes in rd_usr_data + */ +#define EFUSE_RD_USR_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_USR_DATA_ERR_NUM_M (EFUSE_RD_USR_DATA_ERR_NUM_V << EFUSE_RD_USR_DATA_ERR_NUM_S) +#define EFUSE_RD_USR_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_USR_DATA_ERR_NUM_S 8 +/** EFUSE_RD_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; + * Represents error status of register..0: Means no failure and that the data of + * rd_usr_data is reliable. 1: Means that programming rd_usr_data failed and the + * number of error bytes is over 6. + */ +#define EFUSE_RD_USR_DATA_FAIL (BIT(11)) +#define EFUSE_RD_USR_DATA_FAIL_M (EFUSE_RD_USR_DATA_FAIL_V << EFUSE_RD_USR_DATA_FAIL_S) +#define EFUSE_RD_USR_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_USR_DATA_FAIL_S 11 +/** EFUSE_RD_KEY0_DATA_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * Represents the error number of registers..The value of this signal means the + * number of error bytes in rd_key0_data + */ +#define EFUSE_RD_KEY0_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY0_DATA_ERR_NUM_M (EFUSE_RD_KEY0_DATA_ERR_NUM_V << EFUSE_RD_KEY0_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY0_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY0_DATA_ERR_NUM_S 12 +/** EFUSE_RD_KEY0_DATA_FAIL : RO; bitpos: [15]; default: 0; + * Represents error status of register..0: Means no failure and that the data of + * rd_key0_data is reliable. 1: Means that programming rd_key0_data failed and the + * number of error bytes is over 6. + */ +#define EFUSE_RD_KEY0_DATA_FAIL (BIT(15)) +#define EFUSE_RD_KEY0_DATA_FAIL_M (EFUSE_RD_KEY0_DATA_FAIL_V << EFUSE_RD_KEY0_DATA_FAIL_S) +#define EFUSE_RD_KEY0_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY0_DATA_FAIL_S 15 +/** EFUSE_RD_KEY1_DATA_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * Represents the error number of registers..The value of this signal means the + * number of error bytes in rd_key1_data + */ +#define EFUSE_RD_KEY1_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY1_DATA_ERR_NUM_M (EFUSE_RD_KEY1_DATA_ERR_NUM_V << EFUSE_RD_KEY1_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY1_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY1_DATA_ERR_NUM_S 16 +/** EFUSE_RD_KEY1_DATA_FAIL : RO; bitpos: [19]; default: 0; + * Represents error status of register..0: Means no failure and that the data of + * rd_key1_data is reliable. 1: Means that programming rd_key1_data failed and the + * number of error bytes is over 6. + */ +#define EFUSE_RD_KEY1_DATA_FAIL (BIT(19)) +#define EFUSE_RD_KEY1_DATA_FAIL_M (EFUSE_RD_KEY1_DATA_FAIL_V << EFUSE_RD_KEY1_DATA_FAIL_S) +#define EFUSE_RD_KEY1_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY1_DATA_FAIL_S 19 +/** EFUSE_RD_KEY2_DATA_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * Represents the error number of registers..The value of this signal means the + * number of error bytes in rd_key2_data + */ +#define EFUSE_RD_KEY2_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY2_DATA_ERR_NUM_M (EFUSE_RD_KEY2_DATA_ERR_NUM_V << EFUSE_RD_KEY2_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY2_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY2_DATA_ERR_NUM_S 20 +/** EFUSE_RD_KEY2_DATA_FAIL : RO; bitpos: [23]; default: 0; + * Represents error status of register..0: Means no failure and that the data of + * rd_key2_data is reliable. 1: Means that programming rd_key2_data failed and the + * number of error bytes is over 6. + */ +#define EFUSE_RD_KEY2_DATA_FAIL (BIT(23)) +#define EFUSE_RD_KEY2_DATA_FAIL_M (EFUSE_RD_KEY2_DATA_FAIL_V << EFUSE_RD_KEY2_DATA_FAIL_S) +#define EFUSE_RD_KEY2_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY2_DATA_FAIL_S 23 +/** EFUSE_RD_KEY3_DATA_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * Represents the error number of registers..The value of this signal means the + * number of error bytes in rd_key3_data + */ +#define EFUSE_RD_KEY3_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY3_DATA_ERR_NUM_M (EFUSE_RD_KEY3_DATA_ERR_NUM_V << EFUSE_RD_KEY3_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY3_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY3_DATA_ERR_NUM_S 24 +/** EFUSE_RD_KEY3_DATA_FAIL : RO; bitpos: [27]; default: 0; + * Represents error status of register..0: Means no failure and that the data of + * rd_key3_data is reliable. 1: Means that programming rd_key3_data failed and the + * number of error bytes is over 6. + */ +#define EFUSE_RD_KEY3_DATA_FAIL (BIT(27)) +#define EFUSE_RD_KEY3_DATA_FAIL_M (EFUSE_RD_KEY3_DATA_FAIL_V << EFUSE_RD_KEY3_DATA_FAIL_S) +#define EFUSE_RD_KEY3_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY3_DATA_FAIL_S 27 +/** EFUSE_RD_KEY4_DATA_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * Represents the error number of registers..The value of this signal means the + * number of error bytes in rd_key4_data + */ +#define EFUSE_RD_KEY4_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY4_DATA_ERR_NUM_M (EFUSE_RD_KEY4_DATA_ERR_NUM_V << EFUSE_RD_KEY4_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY4_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY4_DATA_ERR_NUM_S 28 +/** EFUSE_RD_KEY4_DATA_FAIL : RO; bitpos: [31]; default: 0; + * Represents error status of register..0: Means no failure and that the data of + * rd_key4_data is reliable. 1: Means that programming rd_key4_data failed and the + * number of error bytes is over 6. + */ +#define EFUSE_RD_KEY4_DATA_FAIL (BIT(31)) +#define EFUSE_RD_KEY4_DATA_FAIL_M (EFUSE_RD_KEY4_DATA_FAIL_V << EFUSE_RD_KEY4_DATA_FAIL_S) +#define EFUSE_RD_KEY4_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY4_DATA_FAIL_S 31 + +/** EFUSE_RD_RS_DATA_ERR1_REG register + * Represents rd_rs_data_err + */ +#define EFUSE_RD_RS_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) +/** EFUSE_RD_KEY5_DATA_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * Represents the error number of registers..The value of this signal means the + * number of error bytes in rd_key5_data + */ +#define EFUSE_RD_KEY5_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY5_DATA_ERR_NUM_M (EFUSE_RD_KEY5_DATA_ERR_NUM_V << EFUSE_RD_KEY5_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY5_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY5_DATA_ERR_NUM_S 0 +/** EFUSE_RD_KEY5_DATA_FAIL : RO; bitpos: [3]; default: 0; + * Represents error status of register..0: Means no failure and that the data of + * rd_key5_data is reliable. 1: Means that programming rd_key5_data failed and the + * number of error bytes is over 6. + */ +#define EFUSE_RD_KEY5_DATA_FAIL (BIT(3)) +#define EFUSE_RD_KEY5_DATA_FAIL_M (EFUSE_RD_KEY5_DATA_FAIL_V << EFUSE_RD_KEY5_DATA_FAIL_S) +#define EFUSE_RD_KEY5_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY5_DATA_FAIL_S 3 +/** EFUSE_RD_SYS_PART2_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * Represents the error number of registers..The value of this signal means the + * number of error bytes in rd_sys_part2_data + */ +#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S) +#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S 4 +/** EFUSE_RD_SYS_PART2_DATA_FAIL : RO; bitpos: [7]; default: 0; + * Represents error status of register..0: Means no failure and that the data of + * rd_sys_part2_data is reliable. 1: Means that programming rd_sys_part2_data failed + * and the number of error bytes is over 6. + */ +#define EFUSE_RD_SYS_PART2_DATA_FAIL (BIT(7)) +#define EFUSE_RD_SYS_PART2_DATA_FAIL_M (EFUSE_RD_SYS_PART2_DATA_FAIL_V << EFUSE_RD_SYS_PART2_DATA_FAIL_S) +#define EFUSE_RD_SYS_PART2_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_SYS_PART2_DATA_FAIL_S 7 /** EFUSE_CLK_REG register * eFuse clcok configuration register. diff --git a/components/soc/esp32c5/beta3/include/soc/efuse_struct.h b/components/soc/esp32c5/beta3/include/soc/efuse_struct.h index 56bdc22ca2..88e48c0452 100644 --- a/components/soc/esp32c5/beta3/include/soc/efuse_struct.h +++ b/components/soc/esp32c5/beta3/include/soc/efuse_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,9 +10,9 @@ extern "C" { #endif -/** Group: PGM Data Register */ +/** Group: buffer0 registers */ /** Type of pgm_data0 register - * Register 0 that stores data to be programmed. + * Represents pgm_data0 */ typedef union { struct { @@ -25,12 +25,12 @@ typedef union { } efuse_pgm_data0_reg_t; /** Type of pgm_data1 register - * Register 1 that stores data to be programmed. + * Represents pgm_data1 */ typedef union { struct { /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1st 32-bit data to be programmed. + * Configures the 0th 32-bit data to be programmed. */ uint32_t pgm_data_1:32; }; @@ -38,12 +38,12 @@ typedef union { } efuse_pgm_data1_reg_t; /** Type of pgm_data2 register - * Register 2 that stores data to be programmed. + * Represents pgm_data2 */ typedef union { struct { /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2nd 32-bit data to be programmed. + * Configures the 0th 32-bit data to be programmed. */ uint32_t pgm_data_2:32; }; @@ -51,12 +51,12 @@ typedef union { } efuse_pgm_data2_reg_t; /** Type of pgm_data3 register - * Register 3 that stores data to be programmed. + * Represents pgm_data3 */ typedef union { struct { /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; - * Configures the 3rd 32-bit data to be programmed. + * Configures the 0th 32-bit data to be programmed. */ uint32_t pgm_data_3:32; }; @@ -64,12 +64,12 @@ typedef union { } efuse_pgm_data3_reg_t; /** Type of pgm_data4 register - * Register 4 that stores data to be programmed. + * Represents pgm_data4 */ typedef union { struct { /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; - * Configures the 4th 32-bit data to be programmed. + * Configures the 0th 32-bit data to be programmed. */ uint32_t pgm_data_4:32; }; @@ -77,12 +77,12 @@ typedef union { } efuse_pgm_data4_reg_t; /** Type of pgm_data5 register - * Register 5 that stores data to be programmed. + * Represents pgm_data5 */ typedef union { struct { /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; - * Configures the 5th 32-bit data to be programmed. + * Configures the 0th 32-bit data to be programmed. */ uint32_t pgm_data_5:32; }; @@ -90,12 +90,12 @@ typedef union { } efuse_pgm_data5_reg_t; /** Type of pgm_data6 register - * Register 6 that stores data to be programmed. + * Represents pgm_data6 */ typedef union { struct { /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; - * Configures the 6th 32-bit data to be programmed. + * Configures the 0th 32-bit data to be programmed. */ uint32_t pgm_data_6:32; }; @@ -103,25 +103,27 @@ typedef union { } efuse_pgm_data6_reg_t; /** Type of pgm_data7 register - * Register 7 that stores data to be programmed. + * Represents pgm_data7 */ typedef union { struct { /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; - * Configures the 7th 32-bit data to be programmed. + * Configures the 0th 32-bit data to be programmed. */ uint32_t pgm_data_7:32; }; uint32_t val; } efuse_pgm_data7_reg_t; + +/** Group: buffer1 registers */ /** Type of pgm_check_value0 register - * Register 0 that stores the RS code to be programmed. + * Represents pgm_check_value0 */ typedef union { struct { /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th 32-bit RS code to be programmed. + * Configures the 0th RS code to be programmed. */ uint32_t pgm_rs_data_0:32; }; @@ -129,12 +131,12 @@ typedef union { } efuse_pgm_check_value0_reg_t; /** Type of pgm_check_value1 register - * Register 1 that stores the RS code to be programmed. + * Represents pgm_check_value1 */ typedef union { struct { /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1st 32-bit RS code to be programmed. + * Configures the 0th RS code to be programmed. */ uint32_t pgm_rs_data_1:32; }; @@ -142,12 +144,12 @@ typedef union { } efuse_pgm_check_value1_reg_t; /** Type of pgm_check_value2 register - * Register 2 that stores the RS code to be programmed. + * Represents pgm_check_value2 */ typedef union { struct { /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2nd 32-bit RS code to be programmed. + * Configures the 0th RS code to be programmed. */ uint32_t pgm_rs_data_2:32; }; @@ -155,23 +157,23 @@ typedef union { } efuse_pgm_check_value2_reg_t; -/** Group: ******** Registers */ -/** Type of rd_wr_dis register - * BLOCK0 data register 0. +/** Group: block0 registers */ +/** Type of rd_wr_dis0 register + * Represents rd_wr_dis */ typedef union { struct { /** wr_dis : RO; bitpos: [31:0]; default: 0; * Represents whether programming of individual eFuse memory bit is disabled or - * enabled. 1: Disabled. 0 Enabled. + * enabled. 1: Disabled. 0: Enabled. */ uint32_t wr_dis:32; }; uint32_t val; -} efuse_rd_wr_dis_reg_t; +} efuse_rd_wr_dis0_reg_t; /** Type of rd_repeat_data0 register - * BLOCK0 data register 1. + * Represents rd_repeat_data */ typedef union { struct { @@ -180,7 +182,10 @@ typedef union { * enabled. 1: disabled. 0: enabled. */ uint32_t rd_dis:7; - uint32_t reserved_7:1; + /** rd_reserve_0_39 : RW; bitpos: [7]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_39:1; /** dis_icache : RO; bitpos: [8]; default: 0; * Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. */ @@ -190,7 +195,15 @@ typedef union { * disabled. 0: enabled. */ uint32_t dis_usb_jtag:1; - uint32_t reserved_10:2; + /** rd_reserve_0_42 : RW; bitpos: [10]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_42:1; + /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0; + * Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: + * enabled. + */ + uint32_t dis_usb_serial_jtag:1; /** dis_force_download : RO; bitpos: [12]; default: 0; * Represents whether the function that forces chip into download mode is disabled or * enabled. 1: disabled. 0: enabled. @@ -202,7 +215,8 @@ typedef union { */ uint32_t spi_download_mspi_dis:1; /** dis_twai : RO; bitpos: [14]; default: 0; - * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: + * enabled. */ uint32_t dis_twai:1; /** jtag_sel_enable : RO; bitpos: [15]; default: 0; @@ -212,13 +226,13 @@ typedef union { */ uint32_t jtag_sel_enable:1; /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; - * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: - * enabled. + * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even + * number: enabled. */ uint32_t soft_dis_jtag:3; /** dis_pad_jtag : RO; bitpos: [19]; default: 0; - * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: - * enabled. + * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. + * 0: enabled. */ uint32_t dis_pad_jtag:1; /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; @@ -226,9 +240,17 @@ typedef union { * mode). 1: disabled. 0: enabled. */ uint32_t dis_download_manual_encrypt:1; - uint32_t reserved_21:4; + /** usb_drefh : RO; bitpos: [22:21]; default: 0; + * Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. + */ + uint32_t usb_drefh:2; + /** usb_drefl : RO; bitpos: [24:23]; default: 0; + * Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. + */ + uint32_t usb_drefl:2; /** usb_exchg_pins : RO; bitpos: [25]; default: 0; - * Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. + * Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not + * exchanged. */ uint32_t usb_exchg_pins:1; /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0; @@ -236,47 +258,52 @@ typedef union { * functioned. */ uint32_t vdd_spi_as_gpio:1; - /** huk_gen_state_part1 : RO; bitpos: [31:27]; default: 0; - * Represents the validation of HUK generate mode. + /** rd_reserve_0_59 : RW; bitpos: [31:27]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func */ - uint32_t huk_gen_state_part1:5; + uint32_t rd_reserve_0_59:5; }; uint32_t val; } efuse_rd_repeat_data0_reg_t; /** Type of rd_repeat_data1 register - * BLOCK0 data register 2. + * Represents rd_repeat_data */ typedef union { struct { - /** huk_gen_state_part2 : RO; bitpos: [3:0]; default: 0; - * Represents the validation of HUK generate mode. + /** km_disable_deploy_mode : RO; bitpos: [3:0]; default: 0; + * Represents whether the deploy mode of key manager is disable or not. . 1: disabled + * . 0: enabled.. */ - uint32_t huk_gen_state_part2:4; + uint32_t km_disable_deploy_mode:4; /** km_rnd_switch_cycle : RO; bitpos: [5:4]; default: 0; - * Represents the key manager random number switch cycle. + * Set the bits to control key manager random number switch cycle. 0: control by + * register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles */ uint32_t km_rnd_switch_cycle:2; /** km_deploy_only_once : RO; bitpos: [9:6]; default: 0; - * Represents whether corresponding key can only be deployed once. + * Set each bit to control whether corresponding key can only be deployed once. 1 is + * true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds */ uint32_t km_deploy_only_once:4; /** force_use_key_manager_key : RO; bitpos: [13:10]; default: 0; - * Represents which corresponding key must come from key manager. + * Set each bit to control whether corresponding key must come from key manager. 1 is + * true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds */ uint32_t force_use_key_manager_key:4; /** force_disable_sw_init_key : RO; bitpos: [14]; default: 0; - * Represents whether to disable software written init key and force use - * efuse_init_key. + * Set this bit to disable software written init key, and force use efuse_init_key. */ uint32_t force_disable_sw_init_key:1; - /** km_disable_deploy_mode : RO; bitpos: [15]; default: 0; - * TBD. + /** rd_reserve_0_79 : RW; bitpos: [15]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func */ - uint32_t km_disable_deploy_mode:1; + uint32_t rd_reserve_0_79:1; /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; - * Represents whether RTC watchdog timeout threshold is selected at startup. 1: - * selected. 0: not selected. + * Represents the threshold level of the RTC watchdog STG0 timeout. 0: Original + * threshold configuration value of STG0 *2 .1: Original threshold configuration + * value of STG0 *4 .2: Original threshold configuration value of STG0 *8 .3: + * Original threshold configuration value of STG0 *16 . */ uint32_t wdt_delay_sel:2; /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; @@ -312,7 +339,7 @@ typedef union { } efuse_rd_repeat_data1_reg_t; /** Type of rd_repeat_data2 register - * BLOCK0 data register 3. + * Represents rd_repeat_data */ typedef union { struct { @@ -336,14 +363,10 @@ typedef union { * Represents the spa secure level by configuring the clock random divide mode. */ uint32_t sec_dpa_level:2; - /** ecdsa_enable_soft_k : RO; bitpos: [18]; default: 0; - * TBD. + /** rd_reserve_0_114 : RW; bitpos: [19:18]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func */ - uint32_t ecdsa_enable_soft_k:1; - /** crypt_dpa_enable : RO; bitpos: [19]; default: 1; - * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. - */ - uint32_t crypt_dpa_enable:1; + uint32_t rd_reserve_0_114:2; /** secure_boot_en : RO; bitpos: [20]; default: 0; * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. */ @@ -353,7 +376,14 @@ typedef union { * enabled. 0: disabled. */ uint32_t secure_boot_aggressive_revoke:1; - uint32_t reserved_22:6; + /** rd_reserve_0_118 : RW; bitpos: [26:22]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_118:5; + /** km_xts_key_length_256 : RO; bitpos: [27]; default: 0; + * Set this bitto configure flash encryption use xts-128 key. else use xts-256 key. + */ + uint32_t km_xts_key_length_256:1; /** flash_tpuw : RO; bitpos: [31:28]; default: 0; * Represents the flash waiting time after power-up, in unit of ms. When the value * less than 15, the waiting time is the programmed value. Otherwise, the waiting time @@ -365,30 +395,32 @@ typedef union { } efuse_rd_repeat_data2_reg_t; /** Type of rd_repeat_data3 register - * BLOCK0 data register 4. + * Represents rd_repeat_data */ typedef union { struct { /** dis_download_mode : RO; bitpos: [0]; default: 0; - * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + * Represents whether Download mode is disabled or enabled. 1: disabled. 0: + * enabled. */ uint32_t dis_download_mode:1; /** dis_direct_boot : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: + * enabled. */ uint32_t dis_direct_boot:1; /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; - * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. - * 0: enabled. + * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: + * disabled. 0: enabled. */ uint32_t dis_usb_serial_jtag_rom_print:1; /** lock_km_key : RO; bitpos: [3]; default: 0; - * TBD. + * Represetns whether to lock the efuse xts key. 1. Lock. 0: Unlock. */ uint32_t lock_km_key:1; /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: - * disabled. 0: enabled. + * Represents whether the USB-Serial-JTAG download function is disabled or enabled.. + * 1: Disable. 0: Enable. */ uint32_t dis_usb_serial_jtag_download_mode:1; /** enable_security_download : RO; bitpos: [5]; default: 0; @@ -403,8 +435,8 @@ typedef union { */ uint32_t uart_print_control:2; /** force_send_resume : RO; bitpos: [8]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot. 1: - * forced. 0:not forced. + * Represents whether ROM code is forced to send a resume command during SPI boot.. + * 1: forced. 0:not forced. */ uint32_t force_send_resume:1; /** secure_version : RO; bitpos: [24:9]; default: 0; @@ -421,75 +453,113 @@ typedef union { * enabled. 0:disabled. */ uint32_t hys_en_pad:1; - uint32_t reserved_27:5; + /** xts_dpa_pseudo_level : RO; bitpos: [28:27]; default: 0; + * Represents the pseudo round level of xts-aes anti-dpa attack. 3: High. 2: + * Moderate 1. Low. 0: Disabled. + */ + uint32_t xts_dpa_pseudo_level:2; + /** xts_dpa_clk_enable : RO; bitpos: [29]; default: 0; + * Represents whether xts-aes anti-dpa attack clock is enabled. 1. Enable. 0: + * Disable.. + */ + uint32_t xts_dpa_clk_enable:1; + /** rd_reserve_0_158 : RW; bitpos: [31:30]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_158:2; }; uint32_t val; } efuse_rd_repeat_data3_reg_t; /** Type of rd_repeat_data4 register - * BLOCK0 data register 5. + * Represents rd_repeat_data */ typedef union { struct { - // TODO: [ESP32C5] IDF-8674 (inherit from C6) seems an error in csv, need to check - uint32_t reserved_0:24; - /** reserved_0 : RO; bitpos: [31:24]; default: 0; - * Reserved. + /** huk_gen_state : RO; bitpos: [8:0]; default: 0; + * Set the bits to control validation of HUK generate mode. Odd of 1 is invalid.. + * Even of 1 is valid.. */ - uint32_t reserved_24:8; + uint32_t huk_gen_state:9; + /** xtal_48m_sel : RO; bitpos: [11:9]; default: 0; + * Represents whether XTAL frequency is 48MHz or not. If not, 40MHz XTAL will be used. + * If this field contains Odd number bit '1': Enable 48MHz XTAL. Even number bit '1': + * Enable 40MHz XTAL. + */ + uint32_t xtal_48m_sel:3; + /** xtal_48m_sel_mode : RO; bitpos: [12]; default: 0; + * Specify the XTAL frequency selection is decided by eFuse or strapping-PAD-state. 1: + * eFuse. 0: strapping-PAD-state. + */ + uint32_t xtal_48m_sel_mode:1; + /** ecdsa_disable_p192 : RO; bitpos: [13]; default: 0; + * Represents whether to disable P192 curve in ECDSA. 1: Disabled. 0: Not disable. + */ + uint32_t ecdsa_disable_p192:1; + /** ecc_force_const_time : RO; bitpos: [14]; default: 0; + * Represents whether to force ecc to use const-time calculation mode. . 1: Enable. + * . 0: Disable. + */ + uint32_t ecc_force_const_time:1; + /** rd_reserve_0_175 : RW; bitpos: [31:15]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_175:17; }; uint32_t val; } efuse_rd_repeat_data4_reg_t; -/** Type of rd_mac_sys_0 register - * BLOCK1 data register $n. + +/** Group: block1 registers */ +/** Type of rd_mac_sys0 register + * Represents rd_mac_sys */ typedef union { struct { /** mac_0 : RO; bitpos: [31:0]; default: 0; - * Stores the low 32 bits of MAC address. + * Represents MAC address. Low 32-bit. */ uint32_t mac_0:32; }; uint32_t val; -} efuse_rd_mac_sys_0_reg_t; +} efuse_rd_mac_sys0_reg_t; -/** Type of rd_mac_sys_1 register - * BLOCK1 data register $n. +/** Type of rd_mac_sys1 register + * Represents rd_mac_sys */ typedef union { struct { /** mac_1 : RO; bitpos: [15:0]; default: 0; - * Stores the high 16 bits of MAC address. + * Represents MAC address. High 16-bit. */ uint32_t mac_1:16; /** mac_ext : RO; bitpos: [31:16]; default: 0; - * Stores the extended bits of MAC address. + * Represents the extended bits of MAC address. */ uint32_t mac_ext:16; }; uint32_t val; -} efuse_rd_mac_sys_1_reg_t; +} efuse_rd_mac_sys1_reg_t; -/** Type of rd_mac_sys_2 register - * BLOCK1 data register $n. +/** Type of rd_mac_sys2 register + * Represents rd_mac_sys */ typedef union { struct { - /** mac_reserved_1 : RO; bitpos: [13:0]; default: 0; + /** mac_reserved_0 : RO; bitpos: [13:0]; default: 0; * Reserved. */ - uint32_t mac_reserved_1:14; - /** mac_reserved_0 : RO; bitpos: [31:14]; default: 0; + uint32_t mac_reserved_0:14; + /** mac_reserved_1 : RO; bitpos: [31:14]; default: 0; * Reserved. */ - uint32_t mac_reserved_0:18; + uint32_t mac_reserved_1:18; }; uint32_t val; -} efuse_rd_mac_sys_2_reg_t; +} efuse_rd_mac_sys2_reg_t; -/** Type of rd_mac_sys_3 register - * BLOCK1 data register $n. +/** Type of rd_mac_sys3 register + * Represents rd_mac_sys */ typedef union { struct { @@ -498,46 +568,48 @@ typedef union { */ uint32_t mac_reserved_2:18; /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; - * Stores the first 14 bits of the zeroth part of system data. + * Represents the first 14-bit of zeroth part of system data. */ uint32_t sys_data_part0_0:14; }; uint32_t val; -} efuse_rd_mac_sys_3_reg_t; +} efuse_rd_mac_sys3_reg_t; -/** Type of rd_mac_sys_4 register - * BLOCK1 data register $n. +/** Type of rd_mac_sys4 register + * Represents rd_mac_sys */ typedef union { struct { /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of the zeroth part of system data. + * Represents the first 14-bit of zeroth part of system data. */ uint32_t sys_data_part0_1:32; }; uint32_t val; -} efuse_rd_mac_sys_4_reg_t; +} efuse_rd_mac_sys4_reg_t; -/** Type of rd_mac_sys_5 register - * BLOCK1 data register $n. +/** Type of rd_mac_sys5 register + * Represents rd_mac_sys */ typedef union { struct { /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of the zeroth part of system data. + * Represents the second 32-bit of zeroth part of system data. */ uint32_t sys_data_part0_2:32; }; uint32_t val; -} efuse_rd_mac_sys_5_reg_t; +} efuse_rd_mac_sys5_reg_t; + +/** Group: block2 registers */ /** Type of rd_sys_part1_data0 register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data0 */ typedef union { struct { /** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of the first part of system data. + * Represents the zeroth 32-bit of first part of system data. */ uint32_t sys_data_part1_0:32; }; @@ -545,12 +617,12 @@ typedef union { } efuse_rd_sys_part1_data0_reg_t; /** Type of rd_sys_part1_data1 register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data1 */ typedef union { struct { /** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of the first part of system data. + * Represents the zeroth 32-bit of first part of system data. */ uint32_t sys_data_part1_1:32; }; @@ -558,12 +630,12 @@ typedef union { } efuse_rd_sys_part1_data1_reg_t; /** Type of rd_sys_part1_data2 register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data2 */ typedef union { struct { /** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of the first part of system data. + * Represents the zeroth 32-bit of first part of system data. */ uint32_t sys_data_part1_2:32; }; @@ -571,12 +643,12 @@ typedef union { } efuse_rd_sys_part1_data2_reg_t; /** Type of rd_sys_part1_data3 register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data3 */ typedef union { struct { /** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of the first part of system data. + * Represents the zeroth 32-bit of first part of system data. */ uint32_t sys_data_part1_3:32; }; @@ -584,12 +656,12 @@ typedef union { } efuse_rd_sys_part1_data3_reg_t; /** Type of rd_sys_part1_data4 register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data4 */ typedef union { struct { /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of the first part of system data. + * Represents the zeroth 32-bit of first part of system data. */ uint32_t sys_data_part1_4:32; }; @@ -597,12 +669,12 @@ typedef union { } efuse_rd_sys_part1_data4_reg_t; /** Type of rd_sys_part1_data5 register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data5 */ typedef union { struct { /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of the first part of system data. + * Represents the zeroth 32-bit of first part of system data. */ uint32_t sys_data_part1_5:32; }; @@ -610,12 +682,12 @@ typedef union { } efuse_rd_sys_part1_data5_reg_t; /** Type of rd_sys_part1_data6 register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data6 */ typedef union { struct { /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of the first part of system data. + * Represents the zeroth 32-bit of first part of system data. */ uint32_t sys_data_part1_6:32; }; @@ -623,25 +695,27 @@ typedef union { } efuse_rd_sys_part1_data6_reg_t; /** Type of rd_sys_part1_data7 register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data7 */ typedef union { struct { /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of the first part of system data. + * Represents the zeroth 32-bit of first part of system data. */ uint32_t sys_data_part1_7:32; }; uint32_t val; } efuse_rd_sys_part1_data7_reg_t; + +/** Group: block3 registers */ /** Type of rd_usr_data0 register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data0 */ typedef union { struct { /** usr_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ uint32_t usr_data0:32; }; @@ -649,12 +723,12 @@ typedef union { } efuse_rd_usr_data0_reg_t; /** Type of rd_usr_data1 register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data1 */ typedef union { struct { /** usr_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ uint32_t usr_data1:32; }; @@ -662,12 +736,12 @@ typedef union { } efuse_rd_usr_data1_reg_t; /** Type of rd_usr_data2 register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data2 */ typedef union { struct { /** usr_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ uint32_t usr_data2:32; }; @@ -675,12 +749,12 @@ typedef union { } efuse_rd_usr_data2_reg_t; /** Type of rd_usr_data3 register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data3 */ typedef union { struct { /** usr_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ uint32_t usr_data3:32; }; @@ -688,12 +762,12 @@ typedef union { } efuse_rd_usr_data3_reg_t; /** Type of rd_usr_data4 register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data4 */ typedef union { struct { /** usr_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ uint32_t usr_data4:32; }; @@ -701,12 +775,12 @@ typedef union { } efuse_rd_usr_data4_reg_t; /** Type of rd_usr_data5 register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data5 */ typedef union { struct { /** usr_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ uint32_t usr_data5:32; }; @@ -714,38 +788,48 @@ typedef union { } efuse_rd_usr_data5_reg_t; /** Type of rd_usr_data6 register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data6 */ typedef union { struct { - /** usr_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of BLOCK3 (user). + /** reserved_3_192 : R; bitpos: [7:0]; default: 0; + * reserved */ - uint32_t usr_data6:32; + uint32_t reserved_3_192:8; + /** custom_mac : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ + uint32_t custom_mac:24; }; uint32_t val; } efuse_rd_usr_data6_reg_t; /** Type of rd_usr_data7 register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data7 */ typedef union { struct { - /** usr_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of BLOCK3 (user). + /** custom_mac_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC */ - uint32_t usr_data7:32; + uint32_t custom_mac_1:24; + /** reserved_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ + uint32_t reserved_3_248:8; }; uint32_t val; } efuse_rd_usr_data7_reg_t; + +/** Group: block4 registers */ /** Type of rd_key0_data0 register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data0 */ typedef union { struct { /** key0_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ uint32_t key0_data0:32; }; @@ -753,12 +837,12 @@ typedef union { } efuse_rd_key0_data0_reg_t; /** Type of rd_key0_data1 register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data1 */ typedef union { struct { /** key0_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ uint32_t key0_data1:32; }; @@ -766,12 +850,12 @@ typedef union { } efuse_rd_key0_data1_reg_t; /** Type of rd_key0_data2 register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data2 */ typedef union { struct { /** key0_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ uint32_t key0_data2:32; }; @@ -779,12 +863,12 @@ typedef union { } efuse_rd_key0_data2_reg_t; /** Type of rd_key0_data3 register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data3 */ typedef union { struct { /** key0_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ uint32_t key0_data3:32; }; @@ -792,12 +876,12 @@ typedef union { } efuse_rd_key0_data3_reg_t; /** Type of rd_key0_data4 register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data4 */ typedef union { struct { /** key0_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ uint32_t key0_data4:32; }; @@ -805,12 +889,12 @@ typedef union { } efuse_rd_key0_data4_reg_t; /** Type of rd_key0_data5 register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data5 */ typedef union { struct { /** key0_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ uint32_t key0_data5:32; }; @@ -818,12 +902,12 @@ typedef union { } efuse_rd_key0_data5_reg_t; /** Type of rd_key0_data6 register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data6 */ typedef union { struct { /** key0_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ uint32_t key0_data6:32; }; @@ -831,25 +915,27 @@ typedef union { } efuse_rd_key0_data6_reg_t; /** Type of rd_key0_data7 register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data7 */ typedef union { struct { /** key0_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ uint32_t key0_data7:32; }; uint32_t val; } efuse_rd_key0_data7_reg_t; + +/** Group: block5 registers */ /** Type of rd_key1_data0 register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data0 */ typedef union { struct { /** key1_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ uint32_t key1_data0:32; }; @@ -857,12 +943,12 @@ typedef union { } efuse_rd_key1_data0_reg_t; /** Type of rd_key1_data1 register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data1 */ typedef union { struct { /** key1_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ uint32_t key1_data1:32; }; @@ -870,12 +956,12 @@ typedef union { } efuse_rd_key1_data1_reg_t; /** Type of rd_key1_data2 register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data2 */ typedef union { struct { /** key1_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ uint32_t key1_data2:32; }; @@ -883,12 +969,12 @@ typedef union { } efuse_rd_key1_data2_reg_t; /** Type of rd_key1_data3 register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data3 */ typedef union { struct { /** key1_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ uint32_t key1_data3:32; }; @@ -896,12 +982,12 @@ typedef union { } efuse_rd_key1_data3_reg_t; /** Type of rd_key1_data4 register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data4 */ typedef union { struct { /** key1_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ uint32_t key1_data4:32; }; @@ -909,12 +995,12 @@ typedef union { } efuse_rd_key1_data4_reg_t; /** Type of rd_key1_data5 register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data5 */ typedef union { struct { /** key1_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ uint32_t key1_data5:32; }; @@ -922,12 +1008,12 @@ typedef union { } efuse_rd_key1_data5_reg_t; /** Type of rd_key1_data6 register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data6 */ typedef union { struct { /** key1_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ uint32_t key1_data6:32; }; @@ -935,25 +1021,27 @@ typedef union { } efuse_rd_key1_data6_reg_t; /** Type of rd_key1_data7 register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data7 */ typedef union { struct { /** key1_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ uint32_t key1_data7:32; }; uint32_t val; } efuse_rd_key1_data7_reg_t; + +/** Group: block6 registers */ /** Type of rd_key2_data0 register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data0 */ typedef union { struct { /** key2_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ uint32_t key2_data0:32; }; @@ -961,12 +1049,12 @@ typedef union { } efuse_rd_key2_data0_reg_t; /** Type of rd_key2_data1 register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data1 */ typedef union { struct { /** key2_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ uint32_t key2_data1:32; }; @@ -974,12 +1062,12 @@ typedef union { } efuse_rd_key2_data1_reg_t; /** Type of rd_key2_data2 register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data2 */ typedef union { struct { /** key2_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ uint32_t key2_data2:32; }; @@ -987,12 +1075,12 @@ typedef union { } efuse_rd_key2_data2_reg_t; /** Type of rd_key2_data3 register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data3 */ typedef union { struct { /** key2_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ uint32_t key2_data3:32; }; @@ -1000,12 +1088,12 @@ typedef union { } efuse_rd_key2_data3_reg_t; /** Type of rd_key2_data4 register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data4 */ typedef union { struct { /** key2_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ uint32_t key2_data4:32; }; @@ -1013,12 +1101,12 @@ typedef union { } efuse_rd_key2_data4_reg_t; /** Type of rd_key2_data5 register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data5 */ typedef union { struct { /** key2_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ uint32_t key2_data5:32; }; @@ -1026,12 +1114,12 @@ typedef union { } efuse_rd_key2_data5_reg_t; /** Type of rd_key2_data6 register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data6 */ typedef union { struct { /** key2_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ uint32_t key2_data6:32; }; @@ -1039,25 +1127,27 @@ typedef union { } efuse_rd_key2_data6_reg_t; /** Type of rd_key2_data7 register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data7 */ typedef union { struct { /** key2_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ uint32_t key2_data7:32; }; uint32_t val; } efuse_rd_key2_data7_reg_t; + +/** Group: block7 registers */ /** Type of rd_key3_data0 register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data0 */ typedef union { struct { /** key3_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ uint32_t key3_data0:32; }; @@ -1065,12 +1155,12 @@ typedef union { } efuse_rd_key3_data0_reg_t; /** Type of rd_key3_data1 register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data1 */ typedef union { struct { /** key3_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ uint32_t key3_data1:32; }; @@ -1078,12 +1168,12 @@ typedef union { } efuse_rd_key3_data1_reg_t; /** Type of rd_key3_data2 register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data2 */ typedef union { struct { /** key3_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ uint32_t key3_data2:32; }; @@ -1091,12 +1181,12 @@ typedef union { } efuse_rd_key3_data2_reg_t; /** Type of rd_key3_data3 register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data3 */ typedef union { struct { /** key3_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ uint32_t key3_data3:32; }; @@ -1104,12 +1194,12 @@ typedef union { } efuse_rd_key3_data3_reg_t; /** Type of rd_key3_data4 register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data4 */ typedef union { struct { /** key3_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ uint32_t key3_data4:32; }; @@ -1117,12 +1207,12 @@ typedef union { } efuse_rd_key3_data4_reg_t; /** Type of rd_key3_data5 register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data5 */ typedef union { struct { /** key3_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ uint32_t key3_data5:32; }; @@ -1130,12 +1220,12 @@ typedef union { } efuse_rd_key3_data5_reg_t; /** Type of rd_key3_data6 register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data6 */ typedef union { struct { /** key3_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ uint32_t key3_data6:32; }; @@ -1143,25 +1233,27 @@ typedef union { } efuse_rd_key3_data6_reg_t; /** Type of rd_key3_data7 register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data7 */ typedef union { struct { /** key3_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ uint32_t key3_data7:32; }; uint32_t val; } efuse_rd_key3_data7_reg_t; + +/** Group: block8 registers */ /** Type of rd_key4_data0 register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data0 */ typedef union { struct { /** key4_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ uint32_t key4_data0:32; }; @@ -1169,12 +1261,12 @@ typedef union { } efuse_rd_key4_data0_reg_t; /** Type of rd_key4_data1 register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data1 */ typedef union { struct { /** key4_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ uint32_t key4_data1:32; }; @@ -1182,12 +1274,12 @@ typedef union { } efuse_rd_key4_data1_reg_t; /** Type of rd_key4_data2 register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data2 */ typedef union { struct { /** key4_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ uint32_t key4_data2:32; }; @@ -1195,12 +1287,12 @@ typedef union { } efuse_rd_key4_data2_reg_t; /** Type of rd_key4_data3 register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data3 */ typedef union { struct { /** key4_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ uint32_t key4_data3:32; }; @@ -1208,12 +1300,12 @@ typedef union { } efuse_rd_key4_data3_reg_t; /** Type of rd_key4_data4 register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data4 */ typedef union { struct { /** key4_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ uint32_t key4_data4:32; }; @@ -1221,12 +1313,12 @@ typedef union { } efuse_rd_key4_data4_reg_t; /** Type of rd_key4_data5 register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data5 */ typedef union { struct { /** key4_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ uint32_t key4_data5:32; }; @@ -1234,12 +1326,12 @@ typedef union { } efuse_rd_key4_data5_reg_t; /** Type of rd_key4_data6 register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data6 */ typedef union { struct { /** key4_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ uint32_t key4_data6:32; }; @@ -1247,25 +1339,27 @@ typedef union { } efuse_rd_key4_data6_reg_t; /** Type of rd_key4_data7 register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data7 */ typedef union { struct { /** key4_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ uint32_t key4_data7:32; }; uint32_t val; } efuse_rd_key4_data7_reg_t; + +/** Group: block9 registers */ /** Type of rd_key5_data0 register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data0 */ typedef union { struct { /** key5_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ uint32_t key5_data0:32; }; @@ -1273,12 +1367,12 @@ typedef union { } efuse_rd_key5_data0_reg_t; /** Type of rd_key5_data1 register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data1 */ typedef union { struct { /** key5_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ uint32_t key5_data1:32; }; @@ -1286,12 +1380,12 @@ typedef union { } efuse_rd_key5_data1_reg_t; /** Type of rd_key5_data2 register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data2 */ typedef union { struct { /** key5_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ uint32_t key5_data2:32; }; @@ -1299,12 +1393,12 @@ typedef union { } efuse_rd_key5_data2_reg_t; /** Type of rd_key5_data3 register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data3 */ typedef union { struct { /** key5_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ uint32_t key5_data3:32; }; @@ -1312,12 +1406,12 @@ typedef union { } efuse_rd_key5_data3_reg_t; /** Type of rd_key5_data4 register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data4 */ typedef union { struct { /** key5_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ uint32_t key5_data4:32; }; @@ -1325,12 +1419,12 @@ typedef union { } efuse_rd_key5_data4_reg_t; /** Type of rd_key5_data5 register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data5 */ typedef union { struct { /** key5_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ uint32_t key5_data5:32; }; @@ -1338,12 +1432,12 @@ typedef union { } efuse_rd_key5_data5_reg_t; /** Type of rd_key5_data6 register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data6 */ typedef union { struct { /** key5_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ uint32_t key5_data6:32; }; @@ -1351,25 +1445,27 @@ typedef union { } efuse_rd_key5_data6_reg_t; /** Type of rd_key5_data7 register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data7 */ typedef union { struct { /** key5_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ uint32_t key5_data7:32; }; uint32_t val; } efuse_rd_key5_data7_reg_t; + +/** Group: block10 registers */ /** Type of rd_sys_part2_data0 register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data0 */ typedef union { struct { /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ uint32_t sys_data_part2_0:32; }; @@ -1377,12 +1473,12 @@ typedef union { } efuse_rd_sys_part2_data0_reg_t; /** Type of rd_sys_part2_data1 register - * Register $n of BLOCK9 (KEY5). + * Represents rd_sys_part2_data1 */ typedef union { struct { /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ uint32_t sys_data_part2_1:32; }; @@ -1390,12 +1486,12 @@ typedef union { } efuse_rd_sys_part2_data1_reg_t; /** Type of rd_sys_part2_data2 register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data2 */ typedef union { struct { /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ uint32_t sys_data_part2_2:32; }; @@ -1403,12 +1499,12 @@ typedef union { } efuse_rd_sys_part2_data2_reg_t; /** Type of rd_sys_part2_data3 register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data3 */ typedef union { struct { /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ uint32_t sys_data_part2_3:32; }; @@ -1416,12 +1512,12 @@ typedef union { } efuse_rd_sys_part2_data3_reg_t; /** Type of rd_sys_part2_data4 register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data4 */ typedef union { struct { /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ uint32_t sys_data_part2_4:32; }; @@ -1429,12 +1525,12 @@ typedef union { } efuse_rd_sys_part2_data4_reg_t; /** Type of rd_sys_part2_data5 register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data5 */ typedef union { struct { /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ uint32_t sys_data_part2_5:32; }; @@ -1442,12 +1538,12 @@ typedef union { } efuse_rd_sys_part2_data5_reg_t; /** Type of rd_sys_part2_data6 register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data6 */ typedef union { struct { /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ uint32_t sys_data_part2_6:32; }; @@ -1455,369 +1551,419 @@ typedef union { } efuse_rd_sys_part2_data6_reg_t; /** Type of rd_sys_part2_data7 register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data7 */ typedef union { struct { /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the zeroth 32-bit of second part of system data. */ uint32_t sys_data_part2_7:32; }; uint32_t val; } efuse_rd_sys_part2_data7_reg_t; -/** Type of rd_repeat_err0 register - * Programming error record register 0 of BLOCK0. + +/** Group: block0 error report registers */ +/** Type of rd_repeat_data_err0 register + * Represents rd_repeat_data_err */ typedef union { struct { /** rd_dis_err : RO; bitpos: [6:0]; default: 0; - * Indicates a programming error of RD_DIS. + * Represents the programming error of EFUSE_RD_DIS */ uint32_t rd_dis_err:7; uint32_t reserved_7:1; /** dis_icache_err : RO; bitpos: [8]; default: 0; - * Indicates a programming error of DIS_ICACHE. + * Represents the programming error of EFUSE_DIS_ICACHE */ uint32_t dis_icache_err:1; /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0; - * Indicates a programming error of DIS_USB_JTAG. + * Represents the programming error of EFUSE_DIS_USB_JTAG */ uint32_t dis_usb_jtag_err:1; - uint32_t reserved_10:2; + uint32_t reserved_10:1; + /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG + */ + uint32_t dis_usb_serial_jtag_err:1; /** dis_force_download_err : RO; bitpos: [12]; default: 0; - * Indicates a programming error of DIS_FORCE_DOWNLOAD. + * Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD */ uint32_t dis_force_download_err:1; /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0; - * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + * Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS */ uint32_t spi_download_mspi_dis_err:1; /** dis_twai_err : RO; bitpos: [14]; default: 0; - * Indicates a programming error of DIS_CAN. + * Represents the programming error of EFUSE_DIS_TWAI */ uint32_t dis_twai_err:1; /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0; - * Indicates a programming error of JTAG_SEL_ENABLE. + * Represents the programming error of EFUSE_JTAG_SEL_ENABLE */ uint32_t jtag_sel_enable_err:1; /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; - * Indicates a programming error of SOFT_DIS_JTAG. + * Represents the programming error of EFUSE_SOFT_DIS_JTAG */ uint32_t soft_dis_jtag_err:3; /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; - * Indicates a programming error of DIS_PAD_JTAG. + * Represents the programming error of EFUSE_DIS_PAD_JTAG */ uint32_t dis_pad_jtag_err:1; /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; - * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + * Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT */ uint32_t dis_download_manual_encrypt_err:1; - uint32_t reserved_21:4; + /** usb_drefh_err : RO; bitpos: [22:21]; default: 0; + * Represents the programming error of EFUSE_USB_DREFH + */ + uint32_t usb_drefh_err:2; + /** usb_drefl_err : RO; bitpos: [24:23]; default: 0; + * Represents the programming error of EFUSE_USB_DREFL + */ + uint32_t usb_drefl_err:2; /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; - * Indicates a programming error of USB_EXCHG_PINS. + * Represents the programming error of EFUSE_USB_EXCHG_PINS */ uint32_t usb_exchg_pins_err:1; /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0; - * Indicates a programming error of VDD_SPI_AS_GPIO. + * Represents the programming error of EFUSE_VDD_SPI_AS_GPIO */ uint32_t vdd_spi_as_gpio_err:1; - /** huk_gen_state_part1_err : RO; bitpos: [31:27]; default: 0; - * Indicates a programming error of EFUSE_HUK_GEN_STATE_PART1. - */ - uint32_t huk_gen_state_part1_err:5; + uint32_t reserved_27:5; }; uint32_t val; -} efuse_rd_repeat_err0_reg_t; +} efuse_rd_repeat_data_err0_reg_t; -/** Type of rd_repeat_err1 register - * Programming error record register 1 of BLOCK0. +/** Type of rd_repeat_data_err1 register + * Represents rd_repeat_data_err */ typedef union { struct { - /** huk_gen_state_part2_err : RO; bitpos: [3:0]; default: 0; - * Indicates a programming error of EFUSE_HUK_GEN_STATE_PART2. + /** km_disable_deploy_mode_err : RO; bitpos: [3:0]; default: 0; + * Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE */ - uint32_t huk_gen_state_part2_err:4; + uint32_t km_disable_deploy_mode_err:4; /** km_rnd_switch_cycle_err : RO; bitpos: [5:4]; default: 0; - * Indicates a programming error of EFUSE_KM_RND_SWITCH_CYCLE. + * Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE */ uint32_t km_rnd_switch_cycle_err:2; /** km_deploy_only_once_err : RO; bitpos: [9:6]; default: 0; - * Indicates a programming error of EFUSE_KM_DEPLOY_ONLY_ONCE. + * Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE */ uint32_t km_deploy_only_once_err:4; /** force_use_key_manager_key_err : RO; bitpos: [13:10]; default: 0; - * Indicates a programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY. + * Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY */ uint32_t force_use_key_manager_key_err:4; /** force_disable_sw_init_key_err : RO; bitpos: [14]; default: 0; - * Indicates a programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY. + * Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY */ uint32_t force_disable_sw_init_key_err:1; - /** km_disable_deploy_mode_err : RO; bitpos: [15]; default: 0; - * Indicates a programming error of EFUSE_KM_DISABLE_DEPLOY_MODE. - */ - uint32_t km_disable_deploy_mode_err:1; + uint32_t reserved_15:1; /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; - * Indicates a programming error of WDT_DELAY_SEL. + * Represents the programming error of EFUSE_WDT_DELAY_SEL */ uint32_t wdt_delay_sel_err:2; /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; - * Indicates a programming error of SPI_BOOT_CRYPT_CNT. + * Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT */ uint32_t spi_boot_crypt_cnt_err:3; /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0 */ uint32_t secure_boot_key_revoke0_err:1; /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1 */ uint32_t secure_boot_key_revoke1_err:1; /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2 */ uint32_t secure_boot_key_revoke2_err:1; /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; - * Indicates a programming error of KEY_PURPOSE_0. + * Represents the programming error of EFUSE_KEY_PURPOSE_0 */ uint32_t key_purpose_0_err:4; /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; - * Indicates a programming error of KEY_PURPOSE_1. + * Represents the programming error of EFUSE_KEY_PURPOSE_1 */ uint32_t key_purpose_1_err:4; }; uint32_t val; -} efuse_rd_repeat_err1_reg_t; +} efuse_rd_repeat_data_err1_reg_t; -/** Type of rd_repeat_err2 register - * Programming error record register 2 of BLOCK0. +/** Type of rd_repeat_data_err2 register + * Represents rd_repeat_data_err */ typedef union { struct { /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; - * Indicates a programming error of KEY_PURPOSE_2. + * Represents the programming error of EFUSE_KEY_PURPOSE_2 */ uint32_t key_purpose_2_err:4; /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; - * Indicates a programming error of KEY_PURPOSE_3. + * Represents the programming error of EFUSE_KEY_PURPOSE_3 */ uint32_t key_purpose_3_err:4; /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; - * Indicates a programming error of KEY_PURPOSE_4. + * Represents the programming error of EFUSE_KEY_PURPOSE_4 */ uint32_t key_purpose_4_err:4; /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; - * Indicates a programming error of KEY_PURPOSE_5. + * Represents the programming error of EFUSE_KEY_PURPOSE_5 */ uint32_t key_purpose_5_err:4; /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0; - * Indicates a programming error of SEC_DPA_LEVEL. + * Represents the programming error of EFUSE_SEC_DPA_LEVEL */ uint32_t sec_dpa_level_err:2; - /** ecdsa_enable_soft_k_err : RO; bitpos: [18]; default: 0; - * Reserved. - */ - uint32_t ecdsa_enable_soft_k_err:1; - /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0; - * Indicates a programming error of CRYPT_DPA_ENABLE. - */ - uint32_t crypt_dpa_enable_err:1; + uint32_t reserved_18:2; /** secure_boot_en_err : RO; bitpos: [20]; default: 0; - * Indicates a programming error of SECURE_BOOT_EN. + * Represents the programming error of EFUSE_SECURE_BOOT_EN */ uint32_t secure_boot_en_err:1; /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; - * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + * Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE */ uint32_t secure_boot_aggressive_revoke_err:1; - uint32_t reserved_22:6; + uint32_t reserved_22:5; + /** km_xts_key_length_256_err : RO; bitpos: [27]; default: 0; + * Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256 + */ + uint32_t km_xts_key_length_256_err:1; /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; - * Indicates a programming error of FLASH_TPUW. + * Represents the programming error of EFUSE_FLASH_TPUW */ uint32_t flash_tpuw_err:4; }; uint32_t val; -} efuse_rd_repeat_err2_reg_t; +} efuse_rd_repeat_data_err2_reg_t; -/** Type of rd_repeat_err3 register - * Programming error record register 3 of BLOCK0. +/** Type of rd_repeat_data_err3 register + * Represents rd_repeat_data_err */ typedef union { struct { /** dis_download_mode_err : RO; bitpos: [0]; default: 0; - * Indicates a programming error of DIS_DOWNLOAD_MODE. + * Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE */ uint32_t dis_download_mode_err:1; /** dis_direct_boot_err : RO; bitpos: [1]; default: 0; - * Indicates a programming error of DIS_DIRECT_BOOT. + * Represents the programming error of EFUSE_DIS_DIRECT_BOOT */ uint32_t dis_direct_boot_err:1; - /** usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0; - * Indicates a programming error of UART_PRINT_CHANNEL. + /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0; + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT */ - uint32_t usb_serial_jtag_rom_print_err:1; + uint32_t dis_usb_serial_jtag_rom_print_err:1; /** lock_km_key_err : RO; bitpos: [3]; default: 0; - * TBD. + * Represents the programming error of EFUSE_LOCK_KM_KEY */ uint32_t lock_km_key_err:1; /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0; - * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE */ uint32_t dis_usb_serial_jtag_download_mode_err:1; /** enable_security_download_err : RO; bitpos: [5]; default: 0; - * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + * Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD */ uint32_t enable_security_download_err:1; /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; - * Indicates a programming error of UART_PRINT_CONTROL. + * Represents the programming error of EFUSE_UART_PRINT_CONTROL */ uint32_t uart_print_control_err:2; /** force_send_resume_err : RO; bitpos: [8]; default: 0; - * Indicates a programming error of FORCE_SEND_RESUME. + * Represents the programming error of EFUSE_FORCE_SEND_RESUME */ uint32_t force_send_resume_err:1; /** secure_version_err : RO; bitpos: [24:9]; default: 0; - * Indicates a programming error of SECURE VERSION. + * Represents the programming error of EFUSE_SECURE_VERSION */ uint32_t secure_version_err:16; /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0; - * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + * Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE */ uint32_t secure_boot_disable_fast_wake_err:1; /** hys_en_pad_err : RO; bitpos: [26]; default: 0; - * Indicates a programming error of HYS_EN_PAD. + * Represents the programming error of EFUSE_HYS_EN_PAD */ uint32_t hys_en_pad_err:1; - uint32_t reserved_27:5; + /** xts_dpa_pseudo_level_err : RO; bitpos: [28:27]; default: 0; + * Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL + */ + uint32_t xts_dpa_pseudo_level_err:2; + /** xts_dpa_clk_enable_err : RO; bitpos: [29]; default: 0; + * Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE + */ + uint32_t xts_dpa_clk_enable_err:1; + uint32_t reserved_30:2; }; uint32_t val; -} efuse_rd_repeat_err3_reg_t; +} efuse_rd_repeat_data_err3_reg_t; -/** Type of rd_repeat_err4 register - * Programming error record register 4 of BLOCK0. +/** Type of rd_repeat_data_err4 register + * Represents rd_repeat_data_err */ typedef union { struct { - uint32_t reserved_0:24; - /** reserved_0_err : RO; bitpos: [31:24]; default: 0; - * Reserved. + /** huk_gen_state_err : RO; bitpos: [8:0]; default: 0; + * Represents the programming error of EFUSE_HUK_GEN_STATE */ - uint32_t reserved_0_err:8; + uint32_t huk_gen_state_err:9; + /** xtal_48m_sel_err : RO; bitpos: [11:9]; default: 0; + * Represents the programming error of EFUSE_XTAL_48M_SEL + */ + uint32_t xtal_48m_sel_err:3; + /** xtal_48m_sel_mode_err : RO; bitpos: [12]; default: 0; + * Represents the programming error of EFUSE_XTAL_48M_SEL_MODE + */ + uint32_t xtal_48m_sel_mode_err:1; + /** ecdsa_disable_p192_err : RO; bitpos: [13]; default: 0; + * Represents the programming error of EFUSE_ECDSA_DISABLE_P192 + */ + uint32_t ecdsa_disable_p192_err:1; + /** ecc_force_const_time_err : RO; bitpos: [14]; default: 0; + * Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME + */ + uint32_t ecc_force_const_time_err:1; + uint32_t reserved_15:17; }; uint32_t val; -} efuse_rd_repeat_err4_reg_t; +} efuse_rd_repeat_data_err4_reg_t; -/** Type of rd_rs_err0 register - * Programming error record register 0 of BLOCK1-10. + +/** Group: RS block error report registers */ +/** Type of rd_rs_data_err0 register + * Represents rd_rs_data_err */ typedef union { struct { - /** mac_sys_err_num : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. + /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0; + * Represents the error number of registers..The value of this signal means the + * number of error bytes in rd_mac_sys */ - uint32_t mac_sys_err_num:3; - /** mac_sys_fail : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of MAC_SYS is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. + uint32_t rd_mac_sys_err_num:3; + /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0; + * Represents error status of register..0: Means no failure and that the data of + * rd_mac_sys is reliable. 1: Means that programming rd_mac_sys failed and the number + * of error bytes is over 6. */ - uint32_t mac_sys_fail:1; - /** sys_part1_err_num : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. + uint32_t rd_mac_sys_fail:1; + /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0; + * Represents the error number of registers..The value of this signal means the + * number of error bytes in rd_sys_part1_data */ - uint32_t sys_part1_err_num:3; - /** sys_part1_fail : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part1 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. + uint32_t rd_sys_part1_data_err_num:3; + /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0; + * Represents error status of register..0: Means no failure and that the data of + * rd_sys_part1_data is reliable. 1: Means that programming rd_sys_part1_data failed + * and the number of error bytes is over 6. */ - uint32_t sys_part1_fail:1; - /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; - * The value of this signal means the number of error bytes. + uint32_t rd_sys_part1_data_fail:1; + /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0; + * Represents the error number of registers..The value of this signal means the + * number of error bytes in rd_usr_data */ - uint32_t usr_data_err_num:3; - /** usr_data_fail : RO; bitpos: [11]; default: 0; - * 0: Means no failure and that the user data is reliable 1: Means that programming - * user data failed and the number of error bytes is over 6. + uint32_t rd_usr_data_err_num:3; + /** rd_usr_data_fail : RO; bitpos: [11]; default: 0; + * Represents error status of register..0: Means no failure and that the data of + * rd_usr_data is reliable. 1: Means that programming rd_usr_data failed and the + * number of error bytes is over 6. */ - uint32_t usr_data_fail:1; - /** key0_err_num : RO; bitpos: [14:12]; default: 0; - * The value of this signal means the number of error bytes. + uint32_t rd_usr_data_fail:1; + /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0; + * Represents the error number of registers..The value of this signal means the + * number of error bytes in rd_key0_data */ - uint32_t key0_err_num:3; - /** key0_fail : RO; bitpos: [15]; default: 0; - * 0: Means no failure and that the data of key0 is reliable 1: Means that programming - * key0 failed and the number of error bytes is over 6. + uint32_t rd_key0_data_err_num:3; + /** rd_key0_data_fail : RO; bitpos: [15]; default: 0; + * Represents error status of register..0: Means no failure and that the data of + * rd_key0_data is reliable. 1: Means that programming rd_key0_data failed and the + * number of error bytes is over 6. */ - uint32_t key0_fail:1; - /** key1_err_num : RO; bitpos: [18:16]; default: 0; - * The value of this signal means the number of error bytes. + uint32_t rd_key0_data_fail:1; + /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0; + * Represents the error number of registers..The value of this signal means the + * number of error bytes in rd_key1_data */ - uint32_t key1_err_num:3; - /** key1_fail : RO; bitpos: [19]; default: 0; - * 0: Means no failure and that the data of key1 is reliable 1: Means that programming - * key1 failed and the number of error bytes is over 6. + uint32_t rd_key1_data_err_num:3; + /** rd_key1_data_fail : RO; bitpos: [19]; default: 0; + * Represents error status of register..0: Means no failure and that the data of + * rd_key1_data is reliable. 1: Means that programming rd_key1_data failed and the + * number of error bytes is over 6. */ - uint32_t key1_fail:1; - /** key2_err_num : RO; bitpos: [22:20]; default: 0; - * The value of this signal means the number of error bytes. + uint32_t rd_key1_data_fail:1; + /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0; + * Represents the error number of registers..The value of this signal means the + * number of error bytes in rd_key2_data */ - uint32_t key2_err_num:3; - /** key2_fail : RO; bitpos: [23]; default: 0; - * 0: Means no failure and that the data of key2 is reliable 1: Means that programming - * key2 failed and the number of error bytes is over 6. + uint32_t rd_key2_data_err_num:3; + /** rd_key2_data_fail : RO; bitpos: [23]; default: 0; + * Represents error status of register..0: Means no failure and that the data of + * rd_key2_data is reliable. 1: Means that programming rd_key2_data failed and the + * number of error bytes is over 6. */ - uint32_t key2_fail:1; - /** key3_err_num : RO; bitpos: [26:24]; default: 0; - * The value of this signal means the number of error bytes. + uint32_t rd_key2_data_fail:1; + /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0; + * Represents the error number of registers..The value of this signal means the + * number of error bytes in rd_key3_data */ - uint32_t key3_err_num:3; - /** key3_fail : RO; bitpos: [27]; default: 0; - * 0: Means no failure and that the data of key3 is reliable 1: Means that programming - * key3 failed and the number of error bytes is over 6. + uint32_t rd_key3_data_err_num:3; + /** rd_key3_data_fail : RO; bitpos: [27]; default: 0; + * Represents error status of register..0: Means no failure and that the data of + * rd_key3_data is reliable. 1: Means that programming rd_key3_data failed and the + * number of error bytes is over 6. */ - uint32_t key3_fail:1; - /** key4_err_num : RO; bitpos: [30:28]; default: 0; - * The value of this signal means the number of error bytes. + uint32_t rd_key3_data_fail:1; + /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0; + * Represents the error number of registers..The value of this signal means the + * number of error bytes in rd_key4_data */ - uint32_t key4_err_num:3; - /** key4_fail : RO; bitpos: [31]; default: 0; - * 0: Means no failure and that the data of key4 is reliable 1: Means that programming - * key4 failed and the number of error bytes is over 6. + uint32_t rd_key4_data_err_num:3; + /** rd_key4_data_fail : RO; bitpos: [31]; default: 0; + * Represents error status of register..0: Means no failure and that the data of + * rd_key4_data is reliable. 1: Means that programming rd_key4_data failed and the + * number of error bytes is over 6. */ - uint32_t key4_fail:1; + uint32_t rd_key4_data_fail:1; }; uint32_t val; -} efuse_rd_rs_err0_reg_t; +} efuse_rd_rs_data_err0_reg_t; -/** Type of rd_rs_err1 register - * Programming error record register 1 of BLOCK1-10. +/** Type of rd_rs_data_err1 register + * Represents rd_rs_data_err */ typedef union { struct { - /** key5_err_num : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. + /** rd_key5_data_err_num : RO; bitpos: [2:0]; default: 0; + * Represents the error number of registers..The value of this signal means the + * number of error bytes in rd_key5_data */ - uint32_t key5_err_num:3; - /** key5_fail : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of key5 is reliable 1: Means that programming - * key5 failed and the number of error bytes is over 6. + uint32_t rd_key5_data_err_num:3; + /** rd_key5_data_fail : RO; bitpos: [3]; default: 0; + * Represents error status of register..0: Means no failure and that the data of + * rd_key5_data is reliable. 1: Means that programming rd_key5_data failed and the + * number of error bytes is over 6. */ - uint32_t key5_fail:1; - /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. + uint32_t rd_key5_data_fail:1; + /** rd_sys_part2_data_err_num : RO; bitpos: [6:4]; default: 0; + * Represents the error number of registers..The value of this signal means the + * number of error bytes in rd_sys_part2_data */ - uint32_t sys_part2_err_num:3; - /** sys_part2_fail : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part2 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. + uint32_t rd_sys_part2_data_err_num:3; + /** rd_sys_part2_data_fail : RO; bitpos: [7]; default: 0; + * Represents error status of register..0: Means no failure and that the data of + * rd_sys_part2_data is reliable. 1: Means that programming rd_sys_part2_data failed + * and the number of error bytes is over 6. */ - uint32_t sys_part2_fail:1; + uint32_t rd_sys_part2_data_fail:1; uint32_t reserved_8:24; }; uint32_t val; -} efuse_rd_rs_err1_reg_t; +} efuse_rd_rs_data_err1_reg_t; /** Type of clk register * eFuse clcok configuration register. @@ -2125,18 +2271,18 @@ typedef struct efuse_dev_t { volatile efuse_pgm_check_value0_reg_t pgm_check_value0; volatile efuse_pgm_check_value1_reg_t pgm_check_value1; volatile efuse_pgm_check_value2_reg_t pgm_check_value2; - volatile efuse_rd_wr_dis_reg_t rd_wr_dis; + volatile efuse_rd_wr_dis0_reg_t rd_wr_dis0; volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; - volatile efuse_rd_mac_sys_0_reg_t rd_mac_sys_0; - volatile efuse_rd_mac_sys_1_reg_t rd_mac_sys_1; - volatile efuse_rd_mac_sys_2_reg_t rd_mac_sys_2; - volatile efuse_rd_mac_sys_3_reg_t rd_mac_sys_3; - volatile efuse_rd_mac_sys_4_reg_t rd_mac_sys_4; - volatile efuse_rd_mac_sys_5_reg_t rd_mac_sys_5; + volatile efuse_rd_mac_sys0_reg_t rd_mac_sys0; + volatile efuse_rd_mac_sys1_reg_t rd_mac_sys1; + volatile efuse_rd_mac_sys2_reg_t rd_mac_sys2; + volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3; + volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4; + volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5; volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; @@ -2209,14 +2355,14 @@ typedef struct efuse_dev_t { volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; - volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; - volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; - volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; - volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; - volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; + volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0; + volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1; + volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2; + volatile efuse_rd_repeat_data_err3_reg_t rd_repeat_data_err3; + volatile efuse_rd_repeat_data_err4_reg_t rd_repeat_data_err4; uint32_t reserved_190[12]; - volatile efuse_rd_rs_err0_reg_t rd_rs_err0; - volatile efuse_rd_rs_err1_reg_t rd_rs_err1; + volatile efuse_rd_rs_data_err0_reg_t rd_rs_data_err0; + volatile efuse_rd_rs_data_err1_reg_t rd_rs_data_err1; volatile efuse_clk_reg_t clk; volatile efuse_conf_reg_t conf; volatile efuse_status_reg_t status; diff --git a/components/soc/esp32c5/beta3/include/soc/soc_caps.h b/components/soc/esp32c5/beta3/include/soc/soc_caps.h index 2e898fcabb..54215b540e 100644 --- a/components/soc/esp32c5/beta3/include/soc/soc_caps.h +++ b/components/soc/esp32c5/beta3/include/soc/soc_caps.h @@ -32,10 +32,10 @@ // #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 // TODO: [ESP32C5] IDF-8721 // #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: [ESP32C5] IDF-8727 // #define SOC_WIFI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8851 -// #define SOC_SUPPORTS_SECURE_DL_MODE 1 // TODO: [ESP32C5] IDF-8622, IDF-8674 +#define SOC_SUPPORTS_SECURE_DL_MODE 1 // #define SOC_LP_CORE_SUPPORTED 1 // TODO: [ESP32C5] IDF-8637 -#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 // TODO: [ESP32C5] IDF-8674, need check -#define SOC_EFUSE_SUPPORTED 1 // TODO: [ESP32C5] IDF-8674 +#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 +#define SOC_EFUSE_SUPPORTED 1 #define SOC_RTC_FAST_MEM_SUPPORTED 1 #define SOC_RTC_MEM_SUPPORTED 1 // #define SOC_I2S_SUPPORTED 1 // TODO: [ESP32C5] IDF-8713, IDF-8714 @@ -460,7 +460,7 @@ /*-------------------------- Secure Boot CAPS----------------------------*/ // #define SOC_SECURE_BOOT_V2_RSA 1 // #define SOC_SECURE_BOOT_V2_ECC 1 -#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 // TODO: [ESP32C5] IDF-8674 +#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 // #define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 // #define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 diff --git a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in index 63296fe170..509e443f1c 100644 --- a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in @@ -7,6 +7,10 @@ config SOC_UART_SUPPORTED bool default y +config SOC_SUPPORTS_SECURE_DL_MODE + bool + default y + config SOC_EFUSE_KEY_PURPOSE_FIELD bool default y diff --git a/components/soc/esp32c5/mp/include/soc/efuse_defs.h b/components/soc/esp32c5/mp/include/soc/efuse_defs.h new file mode 100644 index 0000000000..48cc4ce65d --- /dev/null +++ b/components/soc/esp32c5/mp/include/soc/efuse_defs.h @@ -0,0 +1,17 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/mp/include/soc/efuse_reg.h b/components/soc/esp32c5/mp/include/soc/efuse_reg.h index 2707cedac1..2ade523d2a 100644 --- a/components/soc/esp32c5/mp/include/soc/efuse_reg.h +++ b/components/soc/esp32c5/mp/include/soc/efuse_reg.h @@ -168,6 +168,13 @@ extern "C" { #define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) #define EFUSE_RD_DIS_V 0x0000007FU #define EFUSE_RD_DIS_S 0 +/** EFUSE_RD_RESERVE_0_39 : RW; bitpos: [7]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_39 (BIT(7)) +#define EFUSE_RD_RESERVE_0_39_M (EFUSE_RD_RESERVE_0_39_V << EFUSE_RD_RESERVE_0_39_S) +#define EFUSE_RD_RESERVE_0_39_V 0x00000001U +#define EFUSE_RD_RESERVE_0_39_S 7 /** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; * Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ */ @@ -183,6 +190,13 @@ extern "C" { #define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) #define EFUSE_DIS_USB_JTAG_V 0x00000001U #define EFUSE_DIS_USB_JTAG_S 9 +/** EFUSE_RD_RESERVE_0_42 : RW; bitpos: [10]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_42 (BIT(10)) +#define EFUSE_RD_RESERVE_0_42_M (EFUSE_RD_RESERVE_0_42_V << EFUSE_RD_RESERVE_0_42_S) +#define EFUSE_RD_RESERVE_0_42_V 0x00000001U +#define EFUSE_RD_RESERVE_0_42_S 10 /** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0; * Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: * enabled\\ @@ -278,6 +292,13 @@ extern "C" { #define EFUSE_VDD_SPI_AS_GPIO_M (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S) #define EFUSE_VDD_SPI_AS_GPIO_V 0x00000001U #define EFUSE_VDD_SPI_AS_GPIO_S 26 +/** EFUSE_RD_RESERVE_0_59 : RW; bitpos: [31:27]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_59 0x0000001FU +#define EFUSE_RD_RESERVE_0_59_M (EFUSE_RD_RESERVE_0_59_V << EFUSE_RD_RESERVE_0_59_S) +#define EFUSE_RD_RESERVE_0_59_V 0x0000001FU +#define EFUSE_RD_RESERVE_0_59_S 27 /** EFUSE_RD_REPEAT_DATA1_REG register * Represents rd_repeat_data @@ -322,6 +343,13 @@ extern "C" { #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M (EFUSE_FORCE_DISABLE_SW_INIT_KEY_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_S) #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V 0x00000001U #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S 14 +/** EFUSE_RD_RESERVE_0_79 : RW; bitpos: [15]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_79 (BIT(15)) +#define EFUSE_RD_RESERVE_0_79_M (EFUSE_RD_RESERVE_0_79_V << EFUSE_RD_RESERVE_0_79_S) +#define EFUSE_RD_RESERVE_0_79_V 0x00000001U +#define EFUSE_RD_RESERVE_0_79_S 15 /** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; * Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original * threshold configuration value of STG0 *2 \\1: Original threshold configuration @@ -418,6 +446,13 @@ extern "C" { #define EFUSE_SEC_DPA_LEVEL_M (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S) #define EFUSE_SEC_DPA_LEVEL_V 0x00000003U #define EFUSE_SEC_DPA_LEVEL_S 16 +/** EFUSE_RD_RESERVE_0_114 : RW; bitpos: [19:18]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_114 0x00000003U +#define EFUSE_RD_RESERVE_0_114_M (EFUSE_RD_RESERVE_0_114_V << EFUSE_RD_RESERVE_0_114_S) +#define EFUSE_RD_RESERVE_0_114_V 0x00000003U +#define EFUSE_RD_RESERVE_0_114_S 18 /** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; * Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ */ @@ -433,6 +468,13 @@ extern "C" { #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 +/** EFUSE_RD_RESERVE_0_118 : RW; bitpos: [26:22]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_118 0x0000001FU +#define EFUSE_RD_RESERVE_0_118_M (EFUSE_RD_RESERVE_0_118_V << EFUSE_RD_RESERVE_0_118_S) +#define EFUSE_RD_RESERVE_0_118_V 0x0000001FU +#define EFUSE_RD_RESERVE_0_118_S 22 /** EFUSE_KM_XTS_KEY_LENGTH_256 : RO; bitpos: [27]; default: 0; * Set this bitto configure flash encryption use xts-128 key. else use xts-256 key. */ @@ -557,6 +599,13 @@ extern "C" { #define EFUSE_XTS_DPA_CLK_ENABLE_M (EFUSE_XTS_DPA_CLK_ENABLE_V << EFUSE_XTS_DPA_CLK_ENABLE_S) #define EFUSE_XTS_DPA_CLK_ENABLE_V 0x00000001U #define EFUSE_XTS_DPA_CLK_ENABLE_S 29 +/** EFUSE_RD_RESERVE_0_158 : RW; bitpos: [31:30]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_158 0x00000003U +#define EFUSE_RD_RESERVE_0_158_M (EFUSE_RD_RESERVE_0_158_V << EFUSE_RD_RESERVE_0_158_S) +#define EFUSE_RD_RESERVE_0_158_V 0x00000003U +#define EFUSE_RD_RESERVE_0_158_S 30 /** EFUSE_RD_REPEAT_DATA4_REG register * Represents rd_repeat_data @@ -602,6 +651,13 @@ extern "C" { #define EFUSE_ECC_FORCE_CONST_TIME_M (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S) #define EFUSE_ECC_FORCE_CONST_TIME_V 0x00000001U #define EFUSE_ECC_FORCE_CONST_TIME_S 14 +/** EFUSE_RD_RESERVE_0_175 : RW; bitpos: [31:15]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_175 0x0001FFFFU +#define EFUSE_RD_RESERVE_0_175_M (EFUSE_RD_RESERVE_0_175_V << EFUSE_RD_RESERVE_0_175_S) +#define EFUSE_RD_RESERVE_0_175_V 0x0001FFFFU +#define EFUSE_RD_RESERVE_0_175_S 15 /** EFUSE_RD_MAC_SYS0_REG register * Represents rd_mac_sys @@ -868,25 +924,39 @@ extern "C" { * Represents rd_usr_data6 */ #define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) -/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). +/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0; + * reserved */ -#define EFUSE_USR_DATA6 0xFFFFFFFFU -#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) -#define EFUSE_USR_DATA6_V 0xFFFFFFFFU -#define EFUSE_USR_DATA6_S 0 +#define EFUSE_RESERVED_3_192 0x000000FFU +#define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S) +#define EFUSE_RESERVED_3_192_V 0x000000FFU +#define EFUSE_RESERVED_3_192_S 0 +/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ +#define EFUSE_CUSTOM_MAC 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S) +#define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_S 8 /** EFUSE_RD_USR_DATA7_REG register * Represents rd_usr_data7 */ #define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) -/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). +/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC */ -#define EFUSE_USR_DATA7 0xFFFFFFFFU -#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) -#define EFUSE_USR_DATA7_V 0xFFFFFFFFU -#define EFUSE_USR_DATA7_S 0 +#define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S) +#define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_S 0 +/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_248 0x000000FFU +#define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S) +#define EFUSE_RESERVED_3_248_V 0x000000FFU +#define EFUSE_RESERVED_3_248_S 24 /** EFUSE_RD_KEY0_DATA0_REG register * Represents rd_key0_data0 diff --git a/components/soc/esp32c5/mp/include/soc/efuse_struct.h b/components/soc/esp32c5/mp/include/soc/efuse_struct.h index 56c641c813..f4525d6b4d 100644 --- a/components/soc/esp32c5/mp/include/soc/efuse_struct.h +++ b/components/soc/esp32c5/mp/include/soc/efuse_struct.h @@ -11,33 +11,150 @@ extern "C" { #endif /** Group: buffer0 registers */ -/** Type of pgm_datan register - * Represents pgm_datan +/** Type of pgm_data0 register + * Represents pgm_data0 */ typedef union { struct { - /** pgm_data_n : R/W; bitpos: [31:0]; default: 0; - * Configures the nth 32-bit data to be programmed. + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. */ - uint32_t pgm_data_n:32; + uint32_t pgm_data_0:32; }; uint32_t val; -} efuse_pgm_datan_reg_t; +} efuse_pgm_data0_reg_t; + +/** Type of pgm_data1 register + * Represents pgm_data1 + */ +typedef union { + struct { + /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_1:32; + }; + uint32_t val; +} efuse_pgm_data1_reg_t; + +/** Type of pgm_data2 register + * Represents pgm_data2 + */ +typedef union { + struct { + /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_2:32; + }; + uint32_t val; +} efuse_pgm_data2_reg_t; + +/** Type of pgm_data3 register + * Represents pgm_data3 + */ +typedef union { + struct { + /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_3:32; + }; + uint32_t val; +} efuse_pgm_data3_reg_t; + +/** Type of pgm_data4 register + * Represents pgm_data4 + */ +typedef union { + struct { + /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_4:32; + }; + uint32_t val; +} efuse_pgm_data4_reg_t; + +/** Type of pgm_data5 register + * Represents pgm_data5 + */ +typedef union { + struct { + /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_5:32; + }; + uint32_t val; +} efuse_pgm_data5_reg_t; + +/** Type of pgm_data6 register + * Represents pgm_data6 + */ +typedef union { + struct { + /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_6:32; + }; + uint32_t val; +} efuse_pgm_data6_reg_t; + +/** Type of pgm_data7 register + * Represents pgm_data7 + */ +typedef union { + struct { + /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_7:32; + }; + uint32_t val; +} efuse_pgm_data7_reg_t; /** Group: buffer1 registers */ -/** Type of pgm_check_valuen register - * Represents pgm_check_valuen +/** Type of pgm_check_value0 register + * Represents pgm_check_value0 */ typedef union { struct { - /** pgm_rs_data_n : R/W; bitpos: [31:0]; default: 0; - * Configures the nth RS code to be programmed. + /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th RS code to be programmed. */ - uint32_t pgm_rs_data_n:32; + uint32_t pgm_rs_data_0:32; }; uint32_t val; -} efuse_pgm_check_valuen_reg_t; +} efuse_pgm_check_value0_reg_t; + +/** Type of pgm_check_value1 register + * Represents pgm_check_value1 + */ +typedef union { + struct { + /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th RS code to be programmed. + */ + uint32_t pgm_rs_data_1:32; + }; + uint32_t val; +} efuse_pgm_check_value1_reg_t; + +/** Type of pgm_check_value2 register + * Represents pgm_check_value2 + */ +typedef union { + struct { + /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th RS code to be programmed. + */ + uint32_t pgm_rs_data_2:32; + }; + uint32_t val; +} efuse_pgm_check_value2_reg_t; /** Group: block0 registers */ @@ -65,7 +182,10 @@ typedef union { * enabled.\\ 1: disabled\\ 0: enabled\\ */ uint32_t rd_dis:7; - uint32_t reserved_7:1; + /** rd_reserve_0_39 : RW; bitpos: [7]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_39:1; /** dis_icache : RO; bitpos: [8]; default: 0; * Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ */ @@ -75,7 +195,10 @@ typedef union { * disabled\\ 0: enabled\\ */ uint32_t dis_usb_jtag:1; - uint32_t reserved_10:1; + /** rd_reserve_0_42 : RW; bitpos: [10]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_42:1; /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0; * Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: * enabled\\ @@ -135,7 +258,10 @@ typedef union { * functioned\\ */ uint32_t vdd_spi_as_gpio:1; - uint32_t reserved_27:5; + /** rd_reserve_0_59 : RW; bitpos: [31:27]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_59:5; }; uint32_t val; } efuse_rd_repeat_data0_reg_t; @@ -169,7 +295,10 @@ typedef union { * Set this bit to disable software written init key, and force use efuse_init_key. */ uint32_t force_disable_sw_init_key:1; - uint32_t reserved_15:1; + /** rd_reserve_0_79 : RW; bitpos: [15]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_79:1; /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; * Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original * threshold configuration value of STG0 *2 \\1: Original threshold configuration @@ -234,7 +363,10 @@ typedef union { * Represents the spa secure level by configuring the clock random divide mode. */ uint32_t sec_dpa_level:2; - uint32_t reserved_18:2; + /** rd_reserve_0_114 : RW; bitpos: [19:18]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_114:2; /** secure_boot_en : RO; bitpos: [20]; default: 0; * Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ */ @@ -244,7 +376,10 @@ typedef union { * enabled.\\ 0: disabled\\ */ uint32_t secure_boot_aggressive_revoke:1; - uint32_t reserved_22:5; + /** rd_reserve_0_118 : RW; bitpos: [26:22]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_118:5; /** km_xts_key_length_256 : RO; bitpos: [27]; default: 0; * Set this bitto configure flash encryption use xts-128 key. else use xts-256 key. */ @@ -328,7 +463,10 @@ typedef union { * Disable.\\ */ uint32_t xts_dpa_clk_enable:1; - uint32_t reserved_30:2; + /** rd_reserve_0_158 : RW; bitpos: [31:30]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_158:2; }; uint32_t val; } efuse_rd_repeat_data3_reg_t; @@ -363,7 +501,10 @@ typedef union { * \\ 0: Disable. */ uint32_t ecc_force_const_time:1; - uint32_t reserved_15:17; + /** rd_reserve_0_175 : RW; bitpos: [31:15]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_175:17; }; uint32_t val; } efuse_rd_repeat_data4_reg_t; @@ -462,138 +603,965 @@ typedef union { /** Group: block2 registers */ -/** Type of rd_sys_part1_datan register - * Represents rd_sys_part1_datan +/** Type of rd_sys_part1_data0 register + * Represents rd_sys_part1_data0 */ typedef union { struct { - /** sys_data_part1_n : RO; bitpos: [31:0]; default: 0; + /** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of first part of system data. */ - uint32_t sys_data_part1_n:32; + uint32_t sys_data_part1_0:32; }; uint32_t val; -} efuse_rd_sys_part1_datan_reg_t; +} efuse_rd_sys_part1_data0_reg_t; + +/** Type of rd_sys_part1_data1 register + * Represents rd_sys_part1_data1 + */ +typedef union { + struct { + /** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_1:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data1_reg_t; + +/** Type of rd_sys_part1_data2 register + * Represents rd_sys_part1_data2 + */ +typedef union { + struct { + /** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_2:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data2_reg_t; + +/** Type of rd_sys_part1_data3 register + * Represents rd_sys_part1_data3 + */ +typedef union { + struct { + /** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_3:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data3_reg_t; + +/** Type of rd_sys_part1_data4 register + * Represents rd_sys_part1_data4 + */ +typedef union { + struct { + /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_4:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data4_reg_t; + +/** Type of rd_sys_part1_data5 register + * Represents rd_sys_part1_data5 + */ +typedef union { + struct { + /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_5:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data5_reg_t; + +/** Type of rd_sys_part1_data6 register + * Represents rd_sys_part1_data6 + */ +typedef union { + struct { + /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_6:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data6_reg_t; + +/** Type of rd_sys_part1_data7 register + * Represents rd_sys_part1_data7 + */ +typedef union { + struct { + /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_7:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data7_reg_t; /** Group: block3 registers */ -/** Type of rd_usr_datan register - * Represents rd_usr_datan +/** Type of rd_usr_data0 register + * Represents rd_usr_data0 */ typedef union { struct { - /** usr_datan : RO; bitpos: [31:0]; default: 0; + /** usr_data0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of block3 (user). */ - uint32_t usr_datan:32; + uint32_t usr_data0:32; }; uint32_t val; -} efuse_rd_usr_datan_reg_t; +} efuse_rd_usr_data0_reg_t; + +/** Type of rd_usr_data1 register + * Represents rd_usr_data1 + */ +typedef union { + struct { + /** usr_data1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_data1:32; + }; + uint32_t val; +} efuse_rd_usr_data1_reg_t; + +/** Type of rd_usr_data2 register + * Represents rd_usr_data2 + */ +typedef union { + struct { + /** usr_data2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_data2:32; + }; + uint32_t val; +} efuse_rd_usr_data2_reg_t; + +/** Type of rd_usr_data3 register + * Represents rd_usr_data3 + */ +typedef union { + struct { + /** usr_data3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_data3:32; + }; + uint32_t val; +} efuse_rd_usr_data3_reg_t; + +/** Type of rd_usr_data4 register + * Represents rd_usr_data4 + */ +typedef union { + struct { + /** usr_data4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_data4:32; + }; + uint32_t val; +} efuse_rd_usr_data4_reg_t; + +/** Type of rd_usr_data5 register + * Represents rd_usr_data5 + */ +typedef union { + struct { + /** usr_data5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_data5:32; + }; + uint32_t val; +} efuse_rd_usr_data5_reg_t; + +/** Type of rd_usr_data6 register + * Represents rd_usr_data6 + */ +typedef union { + struct { + /** reserved_3_192 : R; bitpos: [7:0]; default: 0; + * reserved + */ + uint32_t reserved_3_192:8; + /** custom_mac : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ + uint32_t custom_mac:24; + }; + uint32_t val; +} efuse_rd_usr_data6_reg_t; + +/** Type of rd_usr_data7 register + * Represents rd_usr_data7 + */ +typedef union { + struct { + /** custom_mac_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC + */ + uint32_t custom_mac_1:24; + /** reserved_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ + uint32_t reserved_3_248:8; + }; + uint32_t val; +} efuse_rd_usr_data7_reg_t; /** Group: block4 registers */ -/** Type of rd_key0_datan register - * Represents rd_key0_datan +/** Type of rd_key0_data0 register + * Represents rd_key0_data0 */ typedef union { struct { - /** key0_datan : RO; bitpos: [31:0]; default: 0; + /** key0_data0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key0. */ - uint32_t key0_datan:32; + uint32_t key0_data0:32; }; uint32_t val; -} efuse_rd_key0_datan_reg_t; +} efuse_rd_key0_data0_reg_t; + +/** Type of rd_key0_data1 register + * Represents rd_key0_data1 + */ +typedef union { + struct { + /** key0_data1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ + uint32_t key0_data1:32; + }; + uint32_t val; +} efuse_rd_key0_data1_reg_t; + +/** Type of rd_key0_data2 register + * Represents rd_key0_data2 + */ +typedef union { + struct { + /** key0_data2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ + uint32_t key0_data2:32; + }; + uint32_t val; +} efuse_rd_key0_data2_reg_t; + +/** Type of rd_key0_data3 register + * Represents rd_key0_data3 + */ +typedef union { + struct { + /** key0_data3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ + uint32_t key0_data3:32; + }; + uint32_t val; +} efuse_rd_key0_data3_reg_t; + +/** Type of rd_key0_data4 register + * Represents rd_key0_data4 + */ +typedef union { + struct { + /** key0_data4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ + uint32_t key0_data4:32; + }; + uint32_t val; +} efuse_rd_key0_data4_reg_t; + +/** Type of rd_key0_data5 register + * Represents rd_key0_data5 + */ +typedef union { + struct { + /** key0_data5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ + uint32_t key0_data5:32; + }; + uint32_t val; +} efuse_rd_key0_data5_reg_t; + +/** Type of rd_key0_data6 register + * Represents rd_key0_data6 + */ +typedef union { + struct { + /** key0_data6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ + uint32_t key0_data6:32; + }; + uint32_t val; +} efuse_rd_key0_data6_reg_t; + +/** Type of rd_key0_data7 register + * Represents rd_key0_data7 + */ +typedef union { + struct { + /** key0_data7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ + uint32_t key0_data7:32; + }; + uint32_t val; +} efuse_rd_key0_data7_reg_t; /** Group: block5 registers */ -/** Type of rd_key1_datan register - * Represents rd_key1_datan +/** Type of rd_key1_data0 register + * Represents rd_key1_data0 */ typedef union { struct { - /** key1_datan : RO; bitpos: [31:0]; default: 0; + /** key1_data0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key1. */ - uint32_t key1_datan:32; + uint32_t key1_data0:32; }; uint32_t val; -} efuse_rd_key1_datan_reg_t; +} efuse_rd_key1_data0_reg_t; + +/** Type of rd_key1_data1 register + * Represents rd_key1_data1 + */ +typedef union { + struct { + /** key1_data1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ + uint32_t key1_data1:32; + }; + uint32_t val; +} efuse_rd_key1_data1_reg_t; + +/** Type of rd_key1_data2 register + * Represents rd_key1_data2 + */ +typedef union { + struct { + /** key1_data2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ + uint32_t key1_data2:32; + }; + uint32_t val; +} efuse_rd_key1_data2_reg_t; + +/** Type of rd_key1_data3 register + * Represents rd_key1_data3 + */ +typedef union { + struct { + /** key1_data3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ + uint32_t key1_data3:32; + }; + uint32_t val; +} efuse_rd_key1_data3_reg_t; + +/** Type of rd_key1_data4 register + * Represents rd_key1_data4 + */ +typedef union { + struct { + /** key1_data4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ + uint32_t key1_data4:32; + }; + uint32_t val; +} efuse_rd_key1_data4_reg_t; + +/** Type of rd_key1_data5 register + * Represents rd_key1_data5 + */ +typedef union { + struct { + /** key1_data5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ + uint32_t key1_data5:32; + }; + uint32_t val; +} efuse_rd_key1_data5_reg_t; + +/** Type of rd_key1_data6 register + * Represents rd_key1_data6 + */ +typedef union { + struct { + /** key1_data6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ + uint32_t key1_data6:32; + }; + uint32_t val; +} efuse_rd_key1_data6_reg_t; + +/** Type of rd_key1_data7 register + * Represents rd_key1_data7 + */ +typedef union { + struct { + /** key1_data7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ + uint32_t key1_data7:32; + }; + uint32_t val; +} efuse_rd_key1_data7_reg_t; /** Group: block6 registers */ -/** Type of rd_key2_datan register - * Represents rd_key2_datan +/** Type of rd_key2_data0 register + * Represents rd_key2_data0 */ typedef union { struct { - /** key2_datan : RO; bitpos: [31:0]; default: 0; + /** key2_data0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key2. */ - uint32_t key2_datan:32; + uint32_t key2_data0:32; }; uint32_t val; -} efuse_rd_key2_datan_reg_t; +} efuse_rd_key2_data0_reg_t; + +/** Type of rd_key2_data1 register + * Represents rd_key2_data1 + */ +typedef union { + struct { + /** key2_data1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ + uint32_t key2_data1:32; + }; + uint32_t val; +} efuse_rd_key2_data1_reg_t; + +/** Type of rd_key2_data2 register + * Represents rd_key2_data2 + */ +typedef union { + struct { + /** key2_data2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ + uint32_t key2_data2:32; + }; + uint32_t val; +} efuse_rd_key2_data2_reg_t; + +/** Type of rd_key2_data3 register + * Represents rd_key2_data3 + */ +typedef union { + struct { + /** key2_data3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ + uint32_t key2_data3:32; + }; + uint32_t val; +} efuse_rd_key2_data3_reg_t; + +/** Type of rd_key2_data4 register + * Represents rd_key2_data4 + */ +typedef union { + struct { + /** key2_data4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ + uint32_t key2_data4:32; + }; + uint32_t val; +} efuse_rd_key2_data4_reg_t; + +/** Type of rd_key2_data5 register + * Represents rd_key2_data5 + */ +typedef union { + struct { + /** key2_data5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ + uint32_t key2_data5:32; + }; + uint32_t val; +} efuse_rd_key2_data5_reg_t; + +/** Type of rd_key2_data6 register + * Represents rd_key2_data6 + */ +typedef union { + struct { + /** key2_data6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ + uint32_t key2_data6:32; + }; + uint32_t val; +} efuse_rd_key2_data6_reg_t; + +/** Type of rd_key2_data7 register + * Represents rd_key2_data7 + */ +typedef union { + struct { + /** key2_data7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ + uint32_t key2_data7:32; + }; + uint32_t val; +} efuse_rd_key2_data7_reg_t; /** Group: block7 registers */ -/** Type of rd_key3_datan register - * Represents rd_key3_datan +/** Type of rd_key3_data0 register + * Represents rd_key3_data0 */ typedef union { struct { - /** key3_datan : RO; bitpos: [31:0]; default: 0; + /** key3_data0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key3. */ - uint32_t key3_datan:32; + uint32_t key3_data0:32; }; uint32_t val; -} efuse_rd_key3_datan_reg_t; +} efuse_rd_key3_data0_reg_t; + +/** Type of rd_key3_data1 register + * Represents rd_key3_data1 + */ +typedef union { + struct { + /** key3_data1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ + uint32_t key3_data1:32; + }; + uint32_t val; +} efuse_rd_key3_data1_reg_t; + +/** Type of rd_key3_data2 register + * Represents rd_key3_data2 + */ +typedef union { + struct { + /** key3_data2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ + uint32_t key3_data2:32; + }; + uint32_t val; +} efuse_rd_key3_data2_reg_t; + +/** Type of rd_key3_data3 register + * Represents rd_key3_data3 + */ +typedef union { + struct { + /** key3_data3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ + uint32_t key3_data3:32; + }; + uint32_t val; +} efuse_rd_key3_data3_reg_t; + +/** Type of rd_key3_data4 register + * Represents rd_key3_data4 + */ +typedef union { + struct { + /** key3_data4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ + uint32_t key3_data4:32; + }; + uint32_t val; +} efuse_rd_key3_data4_reg_t; + +/** Type of rd_key3_data5 register + * Represents rd_key3_data5 + */ +typedef union { + struct { + /** key3_data5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ + uint32_t key3_data5:32; + }; + uint32_t val; +} efuse_rd_key3_data5_reg_t; + +/** Type of rd_key3_data6 register + * Represents rd_key3_data6 + */ +typedef union { + struct { + /** key3_data6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ + uint32_t key3_data6:32; + }; + uint32_t val; +} efuse_rd_key3_data6_reg_t; + +/** Type of rd_key3_data7 register + * Represents rd_key3_data7 + */ +typedef union { + struct { + /** key3_data7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ + uint32_t key3_data7:32; + }; + uint32_t val; +} efuse_rd_key3_data7_reg_t; /** Group: block8 registers */ -/** Type of rd_key4_datan register - * Represents rd_key4_datan +/** Type of rd_key4_data0 register + * Represents rd_key4_data0 */ typedef union { struct { - /** key4_datan : RO; bitpos: [31:0]; default: 0; + /** key4_data0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key4. */ - uint32_t key4_datan:32; + uint32_t key4_data0:32; }; uint32_t val; -} efuse_rd_key4_datan_reg_t; +} efuse_rd_key4_data0_reg_t; + +/** Type of rd_key4_data1 register + * Represents rd_key4_data1 + */ +typedef union { + struct { + /** key4_data1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ + uint32_t key4_data1:32; + }; + uint32_t val; +} efuse_rd_key4_data1_reg_t; + +/** Type of rd_key4_data2 register + * Represents rd_key4_data2 + */ +typedef union { + struct { + /** key4_data2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ + uint32_t key4_data2:32; + }; + uint32_t val; +} efuse_rd_key4_data2_reg_t; + +/** Type of rd_key4_data3 register + * Represents rd_key4_data3 + */ +typedef union { + struct { + /** key4_data3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ + uint32_t key4_data3:32; + }; + uint32_t val; +} efuse_rd_key4_data3_reg_t; + +/** Type of rd_key4_data4 register + * Represents rd_key4_data4 + */ +typedef union { + struct { + /** key4_data4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ + uint32_t key4_data4:32; + }; + uint32_t val; +} efuse_rd_key4_data4_reg_t; + +/** Type of rd_key4_data5 register + * Represents rd_key4_data5 + */ +typedef union { + struct { + /** key4_data5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ + uint32_t key4_data5:32; + }; + uint32_t val; +} efuse_rd_key4_data5_reg_t; + +/** Type of rd_key4_data6 register + * Represents rd_key4_data6 + */ +typedef union { + struct { + /** key4_data6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ + uint32_t key4_data6:32; + }; + uint32_t val; +} efuse_rd_key4_data6_reg_t; + +/** Type of rd_key4_data7 register + * Represents rd_key4_data7 + */ +typedef union { + struct { + /** key4_data7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ + uint32_t key4_data7:32; + }; + uint32_t val; +} efuse_rd_key4_data7_reg_t; /** Group: block9 registers */ -/** Type of rd_key5_datan register - * Represents rd_key5_datan +/** Type of rd_key5_data0 register + * Represents rd_key5_data0 */ typedef union { struct { - /** key5_datan : RO; bitpos: [31:0]; default: 0; + /** key5_data0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key5. */ - uint32_t key5_datan:32; + uint32_t key5_data0:32; }; uint32_t val; -} efuse_rd_key5_datan_reg_t; +} efuse_rd_key5_data0_reg_t; + +/** Type of rd_key5_data1 register + * Represents rd_key5_data1 + */ +typedef union { + struct { + /** key5_data1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ + uint32_t key5_data1:32; + }; + uint32_t val; +} efuse_rd_key5_data1_reg_t; + +/** Type of rd_key5_data2 register + * Represents rd_key5_data2 + */ +typedef union { + struct { + /** key5_data2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ + uint32_t key5_data2:32; + }; + uint32_t val; +} efuse_rd_key5_data2_reg_t; + +/** Type of rd_key5_data3 register + * Represents rd_key5_data3 + */ +typedef union { + struct { + /** key5_data3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ + uint32_t key5_data3:32; + }; + uint32_t val; +} efuse_rd_key5_data3_reg_t; + +/** Type of rd_key5_data4 register + * Represents rd_key5_data4 + */ +typedef union { + struct { + /** key5_data4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ + uint32_t key5_data4:32; + }; + uint32_t val; +} efuse_rd_key5_data4_reg_t; + +/** Type of rd_key5_data5 register + * Represents rd_key5_data5 + */ +typedef union { + struct { + /** key5_data5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ + uint32_t key5_data5:32; + }; + uint32_t val; +} efuse_rd_key5_data5_reg_t; + +/** Type of rd_key5_data6 register + * Represents rd_key5_data6 + */ +typedef union { + struct { + /** key5_data6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ + uint32_t key5_data6:32; + }; + uint32_t val; +} efuse_rd_key5_data6_reg_t; + +/** Type of rd_key5_data7 register + * Represents rd_key5_data7 + */ +typedef union { + struct { + /** key5_data7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ + uint32_t key5_data7:32; + }; + uint32_t val; +} efuse_rd_key5_data7_reg_t; /** Group: block10 registers */ -/** Type of rd_sys_part2_datan register - * Represents rd_sys_part2_datan +/** Type of rd_sys_part2_data0 register + * Represents rd_sys_part2_data0 */ typedef union { struct { - /** sys_data_part2_n : RO; bitpos: [31:0]; default: 0; + /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of second part of system data. */ - uint32_t sys_data_part2_n:32; + uint32_t sys_data_part2_0:32; }; uint32_t val; -} efuse_rd_sys_part2_datan_reg_t; +} efuse_rd_sys_part2_data0_reg_t; + +/** Type of rd_sys_part2_data1 register + * Represents rd_sys_part2_data1 + */ +typedef union { + struct { + /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ + uint32_t sys_data_part2_1:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data1_reg_t; + +/** Type of rd_sys_part2_data2 register + * Represents rd_sys_part2_data2 + */ +typedef union { + struct { + /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ + uint32_t sys_data_part2_2:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data2_reg_t; + +/** Type of rd_sys_part2_data3 register + * Represents rd_sys_part2_data3 + */ +typedef union { + struct { + /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ + uint32_t sys_data_part2_3:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data3_reg_t; + +/** Type of rd_sys_part2_data4 register + * Represents rd_sys_part2_data4 + */ +typedef union { + struct { + /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ + uint32_t sys_data_part2_4:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data4_reg_t; + +/** Type of rd_sys_part2_data5 register + * Represents rd_sys_part2_data5 + */ +typedef union { + struct { + /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ + uint32_t sys_data_part2_5:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data5_reg_t; + +/** Type of rd_sys_part2_data6 register + * Represents rd_sys_part2_data6 + */ +typedef union { + struct { + /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ + uint32_t sys_data_part2_6:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data6_reg_t; + +/** Type of rd_sys_part2_data7 register + * Represents rd_sys_part2_data7 + */ +typedef union { + struct { + /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ + uint32_t sys_data_part2_7:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data7_reg_t; /** Group: block0 error report registers */ @@ -1062,6 +2030,7 @@ typedef union { uint32_t val; } efuse_conf_reg_t; +/** Group: EFUSE Configure Registers */ /** Type of dac_conf register * Controls the eFuse programming voltage. */ @@ -1940,6 +2909,7 @@ typedef union { uint32_t val; } efuse_apb2otp_blk2_w11_reg_t; +/** Group: EFUSE_APB2OTP Block2 Word11 Data */ /** Type of apb2otp_blk10_w11 register * eFuse apb2otp block10 data register11. */ @@ -3410,8 +4380,17 @@ typedef struct { } otp_debug_dev_t; typedef struct { - volatile efuse_pgm_datan_reg_t pgm_datan[8]; - volatile efuse_pgm_check_valuen_reg_t pgm_check_valuen[3]; + volatile efuse_pgm_data0_reg_t pgm_data0; + volatile efuse_pgm_data1_reg_t pgm_data1; + volatile efuse_pgm_data2_reg_t pgm_data2; + volatile efuse_pgm_data3_reg_t pgm_data3; + volatile efuse_pgm_data4_reg_t pgm_data4; + volatile efuse_pgm_data5_reg_t pgm_data5; + volatile efuse_pgm_data6_reg_t pgm_data6; + volatile efuse_pgm_data7_reg_t pgm_data7; + volatile efuse_pgm_check_value0_reg_t pgm_check_value0; + volatile efuse_pgm_check_value1_reg_t pgm_check_value1; + volatile efuse_pgm_check_value2_reg_t pgm_check_value2; volatile efuse_rd_wr_dis0_reg_t rd_wr_dis0; volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; @@ -3424,15 +4403,78 @@ typedef struct { volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3; volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4; volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5; - volatile efuse_rd_sys_part1_datan_reg_t rd_sys_part1_datan[8]; - volatile efuse_rd_usr_datan_reg_t rd_usr_datan[8]; - volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8]; - volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8]; - volatile efuse_rd_key2_datan_reg_t rd_key2_datan[8]; - volatile efuse_rd_key3_datan_reg_t rd_key3_datan[8]; - volatile efuse_rd_key4_datan_reg_t rd_key4_datan[8]; - volatile efuse_rd_key5_datan_reg_t rd_key5_datan[8]; - volatile efuse_rd_sys_part2_datan_reg_t rd_sys_part2_datan[8]; + volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; + volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; + volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; + volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; + volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; + volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; + volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; + volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; + volatile efuse_rd_usr_data0_reg_t rd_usr_data0; + volatile efuse_rd_usr_data1_reg_t rd_usr_data1; + volatile efuse_rd_usr_data2_reg_t rd_usr_data2; + volatile efuse_rd_usr_data3_reg_t rd_usr_data3; + volatile efuse_rd_usr_data4_reg_t rd_usr_data4; + volatile efuse_rd_usr_data5_reg_t rd_usr_data5; + volatile efuse_rd_usr_data6_reg_t rd_usr_data6; + volatile efuse_rd_usr_data7_reg_t rd_usr_data7; + volatile efuse_rd_key0_data0_reg_t rd_key0_data0; + volatile efuse_rd_key0_data1_reg_t rd_key0_data1; + volatile efuse_rd_key0_data2_reg_t rd_key0_data2; + volatile efuse_rd_key0_data3_reg_t rd_key0_data3; + volatile efuse_rd_key0_data4_reg_t rd_key0_data4; + volatile efuse_rd_key0_data5_reg_t rd_key0_data5; + volatile efuse_rd_key0_data6_reg_t rd_key0_data6; + volatile efuse_rd_key0_data7_reg_t rd_key0_data7; + volatile efuse_rd_key1_data0_reg_t rd_key1_data0; + volatile efuse_rd_key1_data1_reg_t rd_key1_data1; + volatile efuse_rd_key1_data2_reg_t rd_key1_data2; + volatile efuse_rd_key1_data3_reg_t rd_key1_data3; + volatile efuse_rd_key1_data4_reg_t rd_key1_data4; + volatile efuse_rd_key1_data5_reg_t rd_key1_data5; + volatile efuse_rd_key1_data6_reg_t rd_key1_data6; + volatile efuse_rd_key1_data7_reg_t rd_key1_data7; + volatile efuse_rd_key2_data0_reg_t rd_key2_data0; + volatile efuse_rd_key2_data1_reg_t rd_key2_data1; + volatile efuse_rd_key2_data2_reg_t rd_key2_data2; + volatile efuse_rd_key2_data3_reg_t rd_key2_data3; + volatile efuse_rd_key2_data4_reg_t rd_key2_data4; + volatile efuse_rd_key2_data5_reg_t rd_key2_data5; + volatile efuse_rd_key2_data6_reg_t rd_key2_data6; + volatile efuse_rd_key2_data7_reg_t rd_key2_data7; + volatile efuse_rd_key3_data0_reg_t rd_key3_data0; + volatile efuse_rd_key3_data1_reg_t rd_key3_data1; + volatile efuse_rd_key3_data2_reg_t rd_key3_data2; + volatile efuse_rd_key3_data3_reg_t rd_key3_data3; + volatile efuse_rd_key3_data4_reg_t rd_key3_data4; + volatile efuse_rd_key3_data5_reg_t rd_key3_data5; + volatile efuse_rd_key3_data6_reg_t rd_key3_data6; + volatile efuse_rd_key3_data7_reg_t rd_key3_data7; + volatile efuse_rd_key4_data0_reg_t rd_key4_data0; + volatile efuse_rd_key4_data1_reg_t rd_key4_data1; + volatile efuse_rd_key4_data2_reg_t rd_key4_data2; + volatile efuse_rd_key4_data3_reg_t rd_key4_data3; + volatile efuse_rd_key4_data4_reg_t rd_key4_data4; + volatile efuse_rd_key4_data5_reg_t rd_key4_data5; + volatile efuse_rd_key4_data6_reg_t rd_key4_data6; + volatile efuse_rd_key4_data7_reg_t rd_key4_data7; + volatile efuse_rd_key5_data0_reg_t rd_key5_data0; + volatile efuse_rd_key5_data1_reg_t rd_key5_data1; + volatile efuse_rd_key5_data2_reg_t rd_key5_data2; + volatile efuse_rd_key5_data3_reg_t rd_key5_data3; + volatile efuse_rd_key5_data4_reg_t rd_key5_data4; + volatile efuse_rd_key5_data5_reg_t rd_key5_data5; + volatile efuse_rd_key5_data6_reg_t rd_key5_data6; + volatile efuse_rd_key5_data7_reg_t rd_key5_data7; + volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; + volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; + volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; + volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; + volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; + volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; + volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; + volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0; volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1; volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2; diff --git a/components/soc/esp32c5/mp/include/soc/soc_caps.h b/components/soc/esp32c5/mp/include/soc/soc_caps.h index 991108a73b..0e463a6763 100644 --- a/components/soc/esp32c5/mp/include/soc/soc_caps.h +++ b/components/soc/esp32c5/mp/include/soc/soc_caps.h @@ -32,10 +32,10 @@ // #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 // TODO: [ESP32C5] IDF-8721 // #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: [ESP32C5] IDF-8727 // #define SOC_WIFI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8851 -// #define SOC_SUPPORTS_SECURE_DL_MODE 1 // TODO: [ESP32C5] IDF-8622, IDF-8674 +#define SOC_SUPPORTS_SECURE_DL_MODE 1 // #define SOC_LP_CORE_SUPPORTED 1 // TODO: [ESP32C5] IDF-8637 -#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 // TODO: [ESP32C5] IDF-8674, need check -#define SOC_EFUSE_SUPPORTED 1 // TODO: [ESP32C5] IDF-8674 +#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 +#define SOC_EFUSE_SUPPORTED 1 #define SOC_RTC_FAST_MEM_SUPPORTED 1 #define SOC_RTC_MEM_SUPPORTED 1 // #define SOC_I2S_SUPPORTED 1 // TODO: [ESP32C5] IDF-8713, IDF-8714 @@ -454,7 +454,7 @@ /*-------------------------- Secure Boot CAPS----------------------------*/ // #define SOC_SECURE_BOOT_V2_RSA 1 // #define SOC_SECURE_BOOT_V2_ECC 1 -#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 // TODO: [ESP32C5] IDF-8674 +#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 // #define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 // #define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index be1a58170f..866e4626c2 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -7,6 +7,10 @@ config SOC_UART_SUPPORTED bool default y +config SOC_SUPPORTS_SECURE_DL_MODE + bool + default y + config SOC_EFUSE_KEY_PURPOSE_FIELD bool default y @@ -873,7 +877,7 @@ config SOC_TWAI_SUPPORTS_RX_STATUS config SOC_EFUSE_DIS_DOWNLOAD_ICACHE bool - default y + default n config SOC_EFUSE_DIS_PAD_JTAG bool @@ -889,7 +893,7 @@ config SOC_EFUSE_DIS_DIRECT_BOOT config SOC_EFUSE_SOFT_DIS_JTAG bool - default y + default n config SOC_EFUSE_DIS_ICACHE bool diff --git a/components/soc/esp32c61/include/soc/efuse_reg.h b/components/soc/esp32c61/include/soc/efuse_reg.h index b154df3092..838224fe98 100644 --- a/components/soc/esp32c61/include/soc/efuse_reg.h +++ b/components/soc/esp32c61/include/soc/efuse_reg.h @@ -28,7 +28,7 @@ extern "C" { */ #define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE0_BASE + 0x4) /** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1th 32-bit data to be programmed. + * Configures the 0th 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_1 0xFFFFFFFFU #define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) @@ -40,7 +40,7 @@ extern "C" { */ #define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE0_BASE + 0x8) /** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2th 32-bit data to be programmed. + * Configures the 0th 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_2 0xFFFFFFFFU #define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) @@ -52,7 +52,7 @@ extern "C" { */ #define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE0_BASE + 0xc) /** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; - * Configures the 3th 32-bit data to be programmed. + * Configures the 0th 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_3 0xFFFFFFFFU #define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) @@ -64,7 +64,7 @@ extern "C" { */ #define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE0_BASE + 0x10) /** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; - * Configures the 4th 32-bit data to be programmed. + * Configures the 0th 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_4 0xFFFFFFFFU #define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) @@ -76,7 +76,7 @@ extern "C" { */ #define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE0_BASE + 0x14) /** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; - * Configures the 5th 32-bit data to be programmed. + * Configures the 0th 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_5 0xFFFFFFFFU #define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) @@ -88,7 +88,7 @@ extern "C" { */ #define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE0_BASE + 0x18) /** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; - * Configures the 6th 32-bit data to be programmed. + * Configures the 0th 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_6 0xFFFFFFFFU #define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) @@ -100,7 +100,7 @@ extern "C" { */ #define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE0_BASE + 0x1c) /** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; - * Configures the 7th 32-bit data to be programmed. + * Configures the 0th 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_7 0xFFFFFFFFU #define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) @@ -124,7 +124,7 @@ extern "C" { */ #define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE0_BASE + 0x24) /** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1th RS code to be programmed. + * Configures the 0th RS code to be programmed. */ #define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) @@ -136,7 +136,7 @@ extern "C" { */ #define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE0_BASE + 0x28) /** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2th RS code to be programmed. + * Configures the 0th RS code to be programmed. */ #define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) @@ -280,30 +280,37 @@ extern "C" { #define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) #define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_S 23 -/** EFUSE_SECURE_BOOT_KEY_REVOKE_0 : RO; bitpos: [26]; default: 0; +/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [26]; default: 0; * Represents whether revoking first secure boot key is enabled or disabled.\\ 1: * enabled\\ 0: disabled\\ */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE_0 (BIT(26)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE_0_M (EFUSE_SECURE_BOOT_KEY_REVOKE_0_V << EFUSE_SECURE_BOOT_KEY_REVOKE_0_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE_0_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE_0_S 26 -/** EFUSE_SECURE_BOOT_KEY_REVOKE_1 : RO; bitpos: [27]; default: 0; +#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(26)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 26 +/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [27]; default: 0; * Represents whether revoking second secure boot key is enabled or disabled.\\ 1: * enabled\\ 0: disabled\\ */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE_1 (BIT(27)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE_1_M (EFUSE_SECURE_BOOT_KEY_REVOKE_1_V << EFUSE_SECURE_BOOT_KEY_REVOKE_1_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE_1_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE_1_S 27 -/** EFUSE_SECURE_BOOT_KEY_REVOKE_2 : RO; bitpos: [28]; default: 0; +#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(27)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 27 +/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [28]; default: 0; * Represents whether revoking third secure boot key is enabled or disabled.\\ 1: * enabled\\ 0: disabled\\ */ -#define EFUSE_SECURE_BOOT_KEY_REVOKE_2 (BIT(28)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE_2_M (EFUSE_SECURE_BOOT_KEY_REVOKE_2_V << EFUSE_SECURE_BOOT_KEY_REVOKE_2_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE_2_V 0x00000001U -#define EFUSE_SECURE_BOOT_KEY_REVOKE_2_S 28 +#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(28)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 28 +/** EFUSE_RD_RESERVE_0_61 : RW; bitpos: [31:29]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_61 0x00000007U +#define EFUSE_RD_RESERVE_0_61_M (EFUSE_RD_RESERVE_0_61_V << EFUSE_RD_RESERVE_0_61_S) +#define EFUSE_RD_RESERVE_0_61_V 0x00000007U +#define EFUSE_RD_RESERVE_0_61_S 29 /** EFUSE_RD_REPEAT_DATA1_REG register * Represents rd_repeat_data @@ -550,13 +557,13 @@ extern "C" { #define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) #define EFUSE_MAC_1_V 0x0000FFFFU #define EFUSE_MAC_1_S 0 -/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0; - * Represents the extended bits of MAC address. +/** EFUSE_RD_RESERVE_1_48 : RW; bitpos: [31:16]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func */ -#define EFUSE_MAC_EXT 0x0000FFFFU -#define EFUSE_MAC_EXT_M (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S) -#define EFUSE_MAC_EXT_V 0x0000FFFFU -#define EFUSE_MAC_EXT_S 16 +#define EFUSE_RD_RESERVE_1_48 0x0000FFFFU +#define EFUSE_RD_RESERVE_1_48_M (EFUSE_RD_RESERVE_1_48_V << EFUSE_RD_RESERVE_1_48_S) +#define EFUSE_RD_RESERVE_1_48_V 0x0000FFFFU +#define EFUSE_RD_RESERVE_1_48_S 16 /** EFUSE_RD_MAC_SYS2_REG register * Represents rd_mac_sys @@ -792,25 +799,39 @@ extern "C" { * Represents rd_usr_data6 */ #define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE0_BASE + 0x94) -/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). +/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0; + * reserved */ -#define EFUSE_USR_DATA6 0xFFFFFFFFU -#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) -#define EFUSE_USR_DATA6_V 0xFFFFFFFFU -#define EFUSE_USR_DATA6_S 0 +#define EFUSE_RESERVED_3_192 0x000000FFU +#define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S) +#define EFUSE_RESERVED_3_192_V 0x000000FFU +#define EFUSE_RESERVED_3_192_S 0 +/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ +#define EFUSE_CUSTOM_MAC 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S) +#define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_S 8 /** EFUSE_RD_USR_DATA7_REG register * Represents rd_usr_data7 */ #define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE0_BASE + 0x98) -/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). +/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC */ -#define EFUSE_USR_DATA7 0xFFFFFFFFU -#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) -#define EFUSE_USR_DATA7_V 0xFFFFFFFFU -#define EFUSE_USR_DATA7_S 0 +#define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S) +#define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_S 0 +/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_248 0x000000FFU +#define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S) +#define EFUSE_RESERVED_3_248_V 0x000000FFU +#define EFUSE_RESERVED_3_248_S 24 /** EFUSE_RD_KEY0_DATA0_REG register * Represents rd_key0_data0 diff --git a/components/soc/esp32c61/include/soc/efuse_struct.h b/components/soc/esp32c61/include/soc/efuse_struct.h index a03db5bcf2..4ec7e8d221 100644 --- a/components/soc/esp32c61/include/soc/efuse_struct.h +++ b/components/soc/esp32c61/include/soc/efuse_struct.h @@ -11,33 +11,150 @@ extern "C" { #endif /** Group: buffer0 registers */ -/** Type of pgm_datan register - * Represents pgm_datan +/** Type of pgm_data0 register + * Represents pgm_data0 */ typedef union { struct { - /** pgm_data_n : R/W; bitpos: [31:0]; default: 0; - * Configures the nth 32-bit data to be programmed. + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. */ - uint32_t pgm_data_n:32; + uint32_t pgm_data_0:32; }; uint32_t val; -} efuse_pgm_datan_reg_t; +} efuse_pgm_data0_reg_t; + +/** Type of pgm_data1 register + * Represents pgm_data1 + */ +typedef union { + struct { + /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_1:32; + }; + uint32_t val; +} efuse_pgm_data1_reg_t; + +/** Type of pgm_data2 register + * Represents pgm_data2 + */ +typedef union { + struct { + /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_2:32; + }; + uint32_t val; +} efuse_pgm_data2_reg_t; + +/** Type of pgm_data3 register + * Represents pgm_data3 + */ +typedef union { + struct { + /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_3:32; + }; + uint32_t val; +} efuse_pgm_data3_reg_t; + +/** Type of pgm_data4 register + * Represents pgm_data4 + */ +typedef union { + struct { + /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_4:32; + }; + uint32_t val; +} efuse_pgm_data4_reg_t; + +/** Type of pgm_data5 register + * Represents pgm_data5 + */ +typedef union { + struct { + /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_5:32; + }; + uint32_t val; +} efuse_pgm_data5_reg_t; + +/** Type of pgm_data6 register + * Represents pgm_data6 + */ +typedef union { + struct { + /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_6:32; + }; + uint32_t val; +} efuse_pgm_data6_reg_t; + +/** Type of pgm_data7 register + * Represents pgm_data7 + */ +typedef union { + struct { + /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. + */ + uint32_t pgm_data_7:32; + }; + uint32_t val; +} efuse_pgm_data7_reg_t; /** Group: buffer1 registers */ -/** Type of pgm_check_valuen register - * Represents pgm_check_valuen +/** Type of pgm_check_value0 register + * Represents pgm_check_value0 */ typedef union { struct { - /** pgm_rs_data_n : R/W; bitpos: [31:0]; default: 0; - * Configures the nth RS code to be programmed. + /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th RS code to be programmed. */ - uint32_t pgm_rs_data_n:32; + uint32_t pgm_rs_data_0:32; }; uint32_t val; -} efuse_pgm_check_valuen_reg_t; +} efuse_pgm_check_value0_reg_t; + +/** Type of pgm_check_value1 register + * Represents pgm_check_value1 + */ +typedef union { + struct { + /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th RS code to be programmed. + */ + uint32_t pgm_rs_data_1:32; + }; + uint32_t val; +} efuse_pgm_check_value1_reg_t; + +/** Type of pgm_check_value2 register + * Represents pgm_check_value2 + */ +typedef union { + struct { + /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th RS code to be programmed. + */ + uint32_t pgm_rs_data_2:32; + }; + uint32_t val; +} efuse_pgm_check_value2_reg_t; /** Group: block0 registers */ @@ -135,22 +252,25 @@ typedef union { * 1: enabled\\ Even number of 1: disabled\\ */ uint32_t spi_boot_crypt_cnt:3; - /** secure_boot_key_revoke_0 : RO; bitpos: [26]; default: 0; + /** secure_boot_key_revoke0 : RO; bitpos: [26]; default: 0; * Represents whether revoking first secure boot key is enabled or disabled.\\ 1: * enabled\\ 0: disabled\\ */ - uint32_t secure_boot_key_revoke_0:1; - /** secure_boot_key_revoke_1 : RO; bitpos: [27]; default: 0; + uint32_t secure_boot_key_revoke0:1; + /** secure_boot_key_revoke1 : RO; bitpos: [27]; default: 0; * Represents whether revoking second secure boot key is enabled or disabled.\\ 1: * enabled\\ 0: disabled\\ */ - uint32_t secure_boot_key_revoke_1:1; - /** secure_boot_key_revoke_2 : RO; bitpos: [28]; default: 0; + uint32_t secure_boot_key_revoke1:1; + /** secure_boot_key_revoke2 : RO; bitpos: [28]; default: 0; * Represents whether revoking third secure boot key is enabled or disabled.\\ 1: * enabled\\ 0: disabled\\ */ - uint32_t secure_boot_key_revoke_2:1; - uint32_t reserved_29:3; + uint32_t secure_boot_key_revoke2:1; + /** rd_reserve_0_61 : RW; bitpos: [31:29]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_61:3; }; uint32_t val; } efuse_rd_repeat_data0_reg_t; @@ -336,10 +456,10 @@ typedef union { * Represents MAC address. High 16-bit. */ uint32_t mac_1:16; - /** mac_ext : RO; bitpos: [31:16]; default: 0; - * Represents the extended bits of MAC address. + /** rd_reserve_1_48 : RW; bitpos: [31:16]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func */ - uint32_t mac_ext:16; + uint32_t rd_reserve_1_48:16; }; uint32_t val; } efuse_rd_mac_sys1_reg_t; @@ -406,138 +526,965 @@ typedef union { /** Group: block2 registers */ -/** Type of rd_sys_part1_datan register - * Represents rd_sys_part1_datan +/** Type of rd_sys_part1_data0 register + * Represents rd_sys_part1_data0 */ typedef union { struct { - /** sys_data_part1_n : RO; bitpos: [31:0]; default: 0; + /** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of first part of system data. */ - uint32_t sys_data_part1_n:32; + uint32_t sys_data_part1_0:32; }; uint32_t val; -} efuse_rd_sys_part1_datan_reg_t; +} efuse_rd_sys_part1_data0_reg_t; + +/** Type of rd_sys_part1_data1 register + * Represents rd_sys_part1_data1 + */ +typedef union { + struct { + /** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_1:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data1_reg_t; + +/** Type of rd_sys_part1_data2 register + * Represents rd_sys_part1_data2 + */ +typedef union { + struct { + /** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_2:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data2_reg_t; + +/** Type of rd_sys_part1_data3 register + * Represents rd_sys_part1_data3 + */ +typedef union { + struct { + /** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_3:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data3_reg_t; + +/** Type of rd_sys_part1_data4 register + * Represents rd_sys_part1_data4 + */ +typedef union { + struct { + /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_4:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data4_reg_t; + +/** Type of rd_sys_part1_data5 register + * Represents rd_sys_part1_data5 + */ +typedef union { + struct { + /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_5:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data5_reg_t; + +/** Type of rd_sys_part1_data6 register + * Represents rd_sys_part1_data6 + */ +typedef union { + struct { + /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_6:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data6_reg_t; + +/** Type of rd_sys_part1_data7 register + * Represents rd_sys_part1_data7 + */ +typedef union { + struct { + /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. + */ + uint32_t sys_data_part1_7:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data7_reg_t; /** Group: block3 registers */ -/** Type of rd_usr_datan register - * Represents rd_usr_datan +/** Type of rd_usr_data0 register + * Represents rd_usr_data0 */ typedef union { struct { - /** usr_datan : RO; bitpos: [31:0]; default: 0; + /** usr_data0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of block3 (user). */ - uint32_t usr_datan:32; + uint32_t usr_data0:32; }; uint32_t val; -} efuse_rd_usr_datan_reg_t; +} efuse_rd_usr_data0_reg_t; + +/** Type of rd_usr_data1 register + * Represents rd_usr_data1 + */ +typedef union { + struct { + /** usr_data1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_data1:32; + }; + uint32_t val; +} efuse_rd_usr_data1_reg_t; + +/** Type of rd_usr_data2 register + * Represents rd_usr_data2 + */ +typedef union { + struct { + /** usr_data2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_data2:32; + }; + uint32_t val; +} efuse_rd_usr_data2_reg_t; + +/** Type of rd_usr_data3 register + * Represents rd_usr_data3 + */ +typedef union { + struct { + /** usr_data3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_data3:32; + }; + uint32_t val; +} efuse_rd_usr_data3_reg_t; + +/** Type of rd_usr_data4 register + * Represents rd_usr_data4 + */ +typedef union { + struct { + /** usr_data4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_data4:32; + }; + uint32_t val; +} efuse_rd_usr_data4_reg_t; + +/** Type of rd_usr_data5 register + * Represents rd_usr_data5 + */ +typedef union { + struct { + /** usr_data5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of block3 (user). + */ + uint32_t usr_data5:32; + }; + uint32_t val; +} efuse_rd_usr_data5_reg_t; + +/** Type of rd_usr_data6 register + * Represents rd_usr_data6 + */ +typedef union { + struct { + /** reserved_3_192 : R; bitpos: [7:0]; default: 0; + * reserved + */ + uint32_t reserved_3_192:8; + /** custom_mac : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ + uint32_t custom_mac:24; + }; + uint32_t val; +} efuse_rd_usr_data6_reg_t; + +/** Type of rd_usr_data7 register + * Represents rd_usr_data7 + */ +typedef union { + struct { + /** custom_mac_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC + */ + uint32_t custom_mac_1:24; + /** reserved_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ + uint32_t reserved_3_248:8; + }; + uint32_t val; +} efuse_rd_usr_data7_reg_t; /** Group: block4 registers */ -/** Type of rd_key0_datan register - * Represents rd_key0_datan +/** Type of rd_key0_data0 register + * Represents rd_key0_data0 */ typedef union { struct { - /** key0_datan : RO; bitpos: [31:0]; default: 0; + /** key0_data0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key0. */ - uint32_t key0_datan:32; + uint32_t key0_data0:32; }; uint32_t val; -} efuse_rd_key0_datan_reg_t; +} efuse_rd_key0_data0_reg_t; + +/** Type of rd_key0_data1 register + * Represents rd_key0_data1 + */ +typedef union { + struct { + /** key0_data1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ + uint32_t key0_data1:32; + }; + uint32_t val; +} efuse_rd_key0_data1_reg_t; + +/** Type of rd_key0_data2 register + * Represents rd_key0_data2 + */ +typedef union { + struct { + /** key0_data2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ + uint32_t key0_data2:32; + }; + uint32_t val; +} efuse_rd_key0_data2_reg_t; + +/** Type of rd_key0_data3 register + * Represents rd_key0_data3 + */ +typedef union { + struct { + /** key0_data3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ + uint32_t key0_data3:32; + }; + uint32_t val; +} efuse_rd_key0_data3_reg_t; + +/** Type of rd_key0_data4 register + * Represents rd_key0_data4 + */ +typedef union { + struct { + /** key0_data4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ + uint32_t key0_data4:32; + }; + uint32_t val; +} efuse_rd_key0_data4_reg_t; + +/** Type of rd_key0_data5 register + * Represents rd_key0_data5 + */ +typedef union { + struct { + /** key0_data5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ + uint32_t key0_data5:32; + }; + uint32_t val; +} efuse_rd_key0_data5_reg_t; + +/** Type of rd_key0_data6 register + * Represents rd_key0_data6 + */ +typedef union { + struct { + /** key0_data6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ + uint32_t key0_data6:32; + }; + uint32_t val; +} efuse_rd_key0_data6_reg_t; + +/** Type of rd_key0_data7 register + * Represents rd_key0_data7 + */ +typedef union { + struct { + /** key0_data7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. + */ + uint32_t key0_data7:32; + }; + uint32_t val; +} efuse_rd_key0_data7_reg_t; /** Group: block5 registers */ -/** Type of rd_key1_datan register - * Represents rd_key1_datan +/** Type of rd_key1_data0 register + * Represents rd_key1_data0 */ typedef union { struct { - /** key1_datan : RO; bitpos: [31:0]; default: 0; + /** key1_data0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key1. */ - uint32_t key1_datan:32; + uint32_t key1_data0:32; }; uint32_t val; -} efuse_rd_key1_datan_reg_t; +} efuse_rd_key1_data0_reg_t; + +/** Type of rd_key1_data1 register + * Represents rd_key1_data1 + */ +typedef union { + struct { + /** key1_data1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ + uint32_t key1_data1:32; + }; + uint32_t val; +} efuse_rd_key1_data1_reg_t; + +/** Type of rd_key1_data2 register + * Represents rd_key1_data2 + */ +typedef union { + struct { + /** key1_data2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ + uint32_t key1_data2:32; + }; + uint32_t val; +} efuse_rd_key1_data2_reg_t; + +/** Type of rd_key1_data3 register + * Represents rd_key1_data3 + */ +typedef union { + struct { + /** key1_data3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ + uint32_t key1_data3:32; + }; + uint32_t val; +} efuse_rd_key1_data3_reg_t; + +/** Type of rd_key1_data4 register + * Represents rd_key1_data4 + */ +typedef union { + struct { + /** key1_data4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ + uint32_t key1_data4:32; + }; + uint32_t val; +} efuse_rd_key1_data4_reg_t; + +/** Type of rd_key1_data5 register + * Represents rd_key1_data5 + */ +typedef union { + struct { + /** key1_data5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ + uint32_t key1_data5:32; + }; + uint32_t val; +} efuse_rd_key1_data5_reg_t; + +/** Type of rd_key1_data6 register + * Represents rd_key1_data6 + */ +typedef union { + struct { + /** key1_data6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ + uint32_t key1_data6:32; + }; + uint32_t val; +} efuse_rd_key1_data6_reg_t; + +/** Type of rd_key1_data7 register + * Represents rd_key1_data7 + */ +typedef union { + struct { + /** key1_data7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. + */ + uint32_t key1_data7:32; + }; + uint32_t val; +} efuse_rd_key1_data7_reg_t; /** Group: block6 registers */ -/** Type of rd_key2_datan register - * Represents rd_key2_datan +/** Type of rd_key2_data0 register + * Represents rd_key2_data0 */ typedef union { struct { - /** key2_datan : RO; bitpos: [31:0]; default: 0; + /** key2_data0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key2. */ - uint32_t key2_datan:32; + uint32_t key2_data0:32; }; uint32_t val; -} efuse_rd_key2_datan_reg_t; +} efuse_rd_key2_data0_reg_t; + +/** Type of rd_key2_data1 register + * Represents rd_key2_data1 + */ +typedef union { + struct { + /** key2_data1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ + uint32_t key2_data1:32; + }; + uint32_t val; +} efuse_rd_key2_data1_reg_t; + +/** Type of rd_key2_data2 register + * Represents rd_key2_data2 + */ +typedef union { + struct { + /** key2_data2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ + uint32_t key2_data2:32; + }; + uint32_t val; +} efuse_rd_key2_data2_reg_t; + +/** Type of rd_key2_data3 register + * Represents rd_key2_data3 + */ +typedef union { + struct { + /** key2_data3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ + uint32_t key2_data3:32; + }; + uint32_t val; +} efuse_rd_key2_data3_reg_t; + +/** Type of rd_key2_data4 register + * Represents rd_key2_data4 + */ +typedef union { + struct { + /** key2_data4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ + uint32_t key2_data4:32; + }; + uint32_t val; +} efuse_rd_key2_data4_reg_t; + +/** Type of rd_key2_data5 register + * Represents rd_key2_data5 + */ +typedef union { + struct { + /** key2_data5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ + uint32_t key2_data5:32; + }; + uint32_t val; +} efuse_rd_key2_data5_reg_t; + +/** Type of rd_key2_data6 register + * Represents rd_key2_data6 + */ +typedef union { + struct { + /** key2_data6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ + uint32_t key2_data6:32; + }; + uint32_t val; +} efuse_rd_key2_data6_reg_t; + +/** Type of rd_key2_data7 register + * Represents rd_key2_data7 + */ +typedef union { + struct { + /** key2_data7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. + */ + uint32_t key2_data7:32; + }; + uint32_t val; +} efuse_rd_key2_data7_reg_t; /** Group: block7 registers */ -/** Type of rd_key3_datan register - * Represents rd_key3_datan +/** Type of rd_key3_data0 register + * Represents rd_key3_data0 */ typedef union { struct { - /** key3_datan : RO; bitpos: [31:0]; default: 0; + /** key3_data0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key3. */ - uint32_t key3_datan:32; + uint32_t key3_data0:32; }; uint32_t val; -} efuse_rd_key3_datan_reg_t; +} efuse_rd_key3_data0_reg_t; + +/** Type of rd_key3_data1 register + * Represents rd_key3_data1 + */ +typedef union { + struct { + /** key3_data1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ + uint32_t key3_data1:32; + }; + uint32_t val; +} efuse_rd_key3_data1_reg_t; + +/** Type of rd_key3_data2 register + * Represents rd_key3_data2 + */ +typedef union { + struct { + /** key3_data2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ + uint32_t key3_data2:32; + }; + uint32_t val; +} efuse_rd_key3_data2_reg_t; + +/** Type of rd_key3_data3 register + * Represents rd_key3_data3 + */ +typedef union { + struct { + /** key3_data3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ + uint32_t key3_data3:32; + }; + uint32_t val; +} efuse_rd_key3_data3_reg_t; + +/** Type of rd_key3_data4 register + * Represents rd_key3_data4 + */ +typedef union { + struct { + /** key3_data4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ + uint32_t key3_data4:32; + }; + uint32_t val; +} efuse_rd_key3_data4_reg_t; + +/** Type of rd_key3_data5 register + * Represents rd_key3_data5 + */ +typedef union { + struct { + /** key3_data5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ + uint32_t key3_data5:32; + }; + uint32_t val; +} efuse_rd_key3_data5_reg_t; + +/** Type of rd_key3_data6 register + * Represents rd_key3_data6 + */ +typedef union { + struct { + /** key3_data6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ + uint32_t key3_data6:32; + }; + uint32_t val; +} efuse_rd_key3_data6_reg_t; + +/** Type of rd_key3_data7 register + * Represents rd_key3_data7 + */ +typedef union { + struct { + /** key3_data7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. + */ + uint32_t key3_data7:32; + }; + uint32_t val; +} efuse_rd_key3_data7_reg_t; /** Group: block8 registers */ -/** Type of rd_key4_datan register - * Represents rd_key4_datan +/** Type of rd_key4_data0 register + * Represents rd_key4_data0 */ typedef union { struct { - /** key4_datan : RO; bitpos: [31:0]; default: 0; + /** key4_data0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key4. */ - uint32_t key4_datan:32; + uint32_t key4_data0:32; }; uint32_t val; -} efuse_rd_key4_datan_reg_t; +} efuse_rd_key4_data0_reg_t; + +/** Type of rd_key4_data1 register + * Represents rd_key4_data1 + */ +typedef union { + struct { + /** key4_data1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ + uint32_t key4_data1:32; + }; + uint32_t val; +} efuse_rd_key4_data1_reg_t; + +/** Type of rd_key4_data2 register + * Represents rd_key4_data2 + */ +typedef union { + struct { + /** key4_data2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ + uint32_t key4_data2:32; + }; + uint32_t val; +} efuse_rd_key4_data2_reg_t; + +/** Type of rd_key4_data3 register + * Represents rd_key4_data3 + */ +typedef union { + struct { + /** key4_data3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ + uint32_t key4_data3:32; + }; + uint32_t val; +} efuse_rd_key4_data3_reg_t; + +/** Type of rd_key4_data4 register + * Represents rd_key4_data4 + */ +typedef union { + struct { + /** key4_data4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ + uint32_t key4_data4:32; + }; + uint32_t val; +} efuse_rd_key4_data4_reg_t; + +/** Type of rd_key4_data5 register + * Represents rd_key4_data5 + */ +typedef union { + struct { + /** key4_data5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ + uint32_t key4_data5:32; + }; + uint32_t val; +} efuse_rd_key4_data5_reg_t; + +/** Type of rd_key4_data6 register + * Represents rd_key4_data6 + */ +typedef union { + struct { + /** key4_data6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ + uint32_t key4_data6:32; + }; + uint32_t val; +} efuse_rd_key4_data6_reg_t; + +/** Type of rd_key4_data7 register + * Represents rd_key4_data7 + */ +typedef union { + struct { + /** key4_data7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. + */ + uint32_t key4_data7:32; + }; + uint32_t val; +} efuse_rd_key4_data7_reg_t; /** Group: block9 registers */ -/** Type of rd_key5_datan register - * Represents rd_key5_datan +/** Type of rd_key5_data0 register + * Represents rd_key5_data0 */ typedef union { struct { - /** key5_datan : RO; bitpos: [31:0]; default: 0; + /** key5_data0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of key5. */ - uint32_t key5_datan:32; + uint32_t key5_data0:32; }; uint32_t val; -} efuse_rd_key5_datan_reg_t; +} efuse_rd_key5_data0_reg_t; + +/** Type of rd_key5_data1 register + * Represents rd_key5_data1 + */ +typedef union { + struct { + /** key5_data1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ + uint32_t key5_data1:32; + }; + uint32_t val; +} efuse_rd_key5_data1_reg_t; + +/** Type of rd_key5_data2 register + * Represents rd_key5_data2 + */ +typedef union { + struct { + /** key5_data2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ + uint32_t key5_data2:32; + }; + uint32_t val; +} efuse_rd_key5_data2_reg_t; + +/** Type of rd_key5_data3 register + * Represents rd_key5_data3 + */ +typedef union { + struct { + /** key5_data3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ + uint32_t key5_data3:32; + }; + uint32_t val; +} efuse_rd_key5_data3_reg_t; + +/** Type of rd_key5_data4 register + * Represents rd_key5_data4 + */ +typedef union { + struct { + /** key5_data4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ + uint32_t key5_data4:32; + }; + uint32_t val; +} efuse_rd_key5_data4_reg_t; + +/** Type of rd_key5_data5 register + * Represents rd_key5_data5 + */ +typedef union { + struct { + /** key5_data5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ + uint32_t key5_data5:32; + }; + uint32_t val; +} efuse_rd_key5_data5_reg_t; + +/** Type of rd_key5_data6 register + * Represents rd_key5_data6 + */ +typedef union { + struct { + /** key5_data6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ + uint32_t key5_data6:32; + }; + uint32_t val; +} efuse_rd_key5_data6_reg_t; + +/** Type of rd_key5_data7 register + * Represents rd_key5_data7 + */ +typedef union { + struct { + /** key5_data7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. + */ + uint32_t key5_data7:32; + }; + uint32_t val; +} efuse_rd_key5_data7_reg_t; /** Group: block10 registers */ -/** Type of rd_sys_part2_datan register - * Represents rd_sys_part2_datan +/** Type of rd_sys_part2_data0 register + * Represents rd_sys_part2_data0 */ typedef union { struct { - /** sys_data_part2_n : RO; bitpos: [31:0]; default: 0; + /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of second part of system data. */ - uint32_t sys_data_part2_n:32; + uint32_t sys_data_part2_0:32; }; uint32_t val; -} efuse_rd_sys_part2_datan_reg_t; +} efuse_rd_sys_part2_data0_reg_t; + +/** Type of rd_sys_part2_data1 register + * Represents rd_sys_part2_data1 + */ +typedef union { + struct { + /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ + uint32_t sys_data_part2_1:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data1_reg_t; + +/** Type of rd_sys_part2_data2 register + * Represents rd_sys_part2_data2 + */ +typedef union { + struct { + /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ + uint32_t sys_data_part2_2:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data2_reg_t; + +/** Type of rd_sys_part2_data3 register + * Represents rd_sys_part2_data3 + */ +typedef union { + struct { + /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ + uint32_t sys_data_part2_3:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data3_reg_t; + +/** Type of rd_sys_part2_data4 register + * Represents rd_sys_part2_data4 + */ +typedef union { + struct { + /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ + uint32_t sys_data_part2_4:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data4_reg_t; + +/** Type of rd_sys_part2_data5 register + * Represents rd_sys_part2_data5 + */ +typedef union { + struct { + /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ + uint32_t sys_data_part2_5:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data5_reg_t; + +/** Type of rd_sys_part2_data6 register + * Represents rd_sys_part2_data6 + */ +typedef union { + struct { + /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ + uint32_t sys_data_part2_6:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data6_reg_t; + +/** Type of rd_sys_part2_data7 register + * Represents rd_sys_part2_data7 + */ +typedef union { + struct { + /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of second part of system data. + */ + uint32_t sys_data_part2_7:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data7_reg_t; /** Group: block0 error report registers */ @@ -963,122 +1910,6 @@ typedef union { uint32_t val; } efuse_conf_reg_t; -/** Type of dac_conf register - * Controls the eFuse programming voltage. - */ -typedef union { - struct { - /** dac_clk_div : R/W; bitpos: [7:0]; default: 23; - * Controls the division factor of the rising clock of the programming voltage. - */ - uint32_t dac_clk_div:8; - /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; - * Don't care. - */ - uint32_t dac_clk_pad_sel:1; - /** dac_num : R/W; bitpos: [16:9]; default: 255; - * Controls the rising period of the programming voltage. - */ - uint32_t dac_num:8; - /** oe_clr : R/W; bitpos: [17]; default: 0; - * Reduces the power supply of the programming voltage. - */ - uint32_t oe_clr:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} efuse_dac_conf_reg_t; - -/** Type of rd_tim_conf register - * Configures read timing parameters. - */ -typedef union { - struct { - /** thr_a : R/W; bitpos: [7:0]; default: 1; - * Configures the read hold time. - */ - uint32_t thr_a:8; - /** trd : R/W; bitpos: [15:8]; default: 2; - * Configures the read time. - */ - uint32_t trd:8; - /** tsur_a : R/W; bitpos: [23:16]; default: 1; - * Configures the read setup time. - */ - uint32_t tsur_a:8; - /** read_init_num : R/W; bitpos: [31:24]; default: 18; - * Configures the waiting time of reading eFuse memory. - */ - uint32_t read_init_num:8; - }; - uint32_t val; -} efuse_rd_tim_conf_reg_t; - -/** Type of wr_tim_conf1 register - * Configurarion register 1 of eFuse programming timing parameters. - */ -typedef union { - struct { - /** tsup_a : R/W; bitpos: [7:0]; default: 1; - * Configures the programming setup time. - */ - uint32_t tsup_a:8; - /** pwr_on_num : R/W; bitpos: [23:8]; default: 12288; - * Configures the power up time for VDDQ. - */ - uint32_t pwr_on_num:16; - /** thp_a : R/W; bitpos: [31:24]; default: 1; - * Configures the programming hold time. - */ - uint32_t thp_a:8; - }; - uint32_t val; -} efuse_wr_tim_conf1_reg_t; - -/** Type of wr_tim_conf2 register - * Configurarion register 2 of eFuse programming timing parameters. - */ -typedef union { - struct { - /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; - * Configures the power outage time for VDDQ. - */ - uint32_t pwr_off_num:16; - /** tpgm : R/W; bitpos: [31:16]; default: 200; - * Configures the active programming time. - */ - uint32_t tpgm:16; - }; - uint32_t val; -} efuse_wr_tim_conf2_reg_t; - -/** Type of wr_tim_conf0_rs_bypass register - * Configurarion register0 of eFuse programming time parameters and rs bypass - * operation. - */ -typedef union { - struct { - /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; - * Set this bit to bypass reed solomon correction step. - */ - uint32_t bypass_rs_correction:1; - /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; - * Configures block number of programming twice operation. - */ - uint32_t bypass_rs_blk_num:11; - /** update : WT; bitpos: [12]; default: 0; - * Set this bit to update multi-bit register signals. - */ - uint32_t update:1; - /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; - * Configures the inactive programming time. - */ - uint32_t tpgm_inactive:8; - uint32_t reserved_21:11; - }; - uint32_t val; -} efuse_wr_tim_conf0_rs_bypass_reg_t; - /** Group: EFUSE Status Registers */ /** Type of status register @@ -1227,6 +2058,124 @@ typedef union { } efuse_int_clr_reg_t; +/** Group: EFUSE Configure Registers */ +/** Type of dac_conf register + * Controls the eFuse programming voltage. + */ +typedef union { + struct { + /** dac_clk_div : R/W; bitpos: [7:0]; default: 23; + * Controls the division factor of the rising clock of the programming voltage. + */ + uint32_t dac_clk_div:8; + /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + uint32_t dac_clk_pad_sel:1; + /** dac_num : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ + uint32_t dac_num:8; + /** oe_clr : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ + uint32_t oe_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_dac_conf_reg_t; + +/** Type of rd_tim_conf register + * Configures read timing parameters. + */ +typedef union { + struct { + /** thr_a : R/W; bitpos: [7:0]; default: 1; + * Configures the read hold time. + */ + uint32_t thr_a:8; + /** trd : R/W; bitpos: [15:8]; default: 2; + * Configures the read time. + */ + uint32_t trd:8; + /** tsur_a : R/W; bitpos: [23:16]; default: 1; + * Configures the read setup time. + */ + uint32_t tsur_a:8; + /** read_init_num : R/W; bitpos: [31:24]; default: 18; + * Configures the waiting time of reading eFuse memory. + */ + uint32_t read_init_num:8; + }; + uint32_t val; +} efuse_rd_tim_conf_reg_t; + +/** Type of wr_tim_conf1 register + * Configurarion register 1 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** tsup_a : R/W; bitpos: [7:0]; default: 1; + * Configures the programming setup time. + */ + uint32_t tsup_a:8; + /** pwr_on_num : R/W; bitpos: [23:8]; default: 12288; + * Configures the power up time for VDDQ. + */ + uint32_t pwr_on_num:16; + /** thp_a : R/W; bitpos: [31:24]; default: 1; + * Configures the programming hold time. + */ + uint32_t thp_a:8; + }; + uint32_t val; +} efuse_wr_tim_conf1_reg_t; + +/** Type of wr_tim_conf2 register + * Configurarion register 2 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ + uint32_t pwr_off_num:16; + /** tpgm : R/W; bitpos: [31:16]; default: 200; + * Configures the active programming time. + */ + uint32_t tpgm:16; + }; + uint32_t val; +} efuse_wr_tim_conf2_reg_t; + +/** Type of wr_tim_conf0_rs_bypass register + * Configurarion register0 of eFuse programming time parameters and rs bypass + * operation. + */ +typedef union { + struct { + /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; + * Set this bit to bypass reed solomon correction step. + */ + uint32_t bypass_rs_correction:1; + /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; + * Configures block number of programming twice operation. + */ + uint32_t bypass_rs_blk_num:11; + /** update : WT; bitpos: [12]; default: 0; + * Set this bit to update multi-bit register signals. + */ + uint32_t update:1; + /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; + * Configures the inactive programming time. + */ + uint32_t tpgm_inactive:8; + uint32_t reserved_21:11; + }; + uint32_t val; +} efuse_wr_tim_conf0_rs_bypass_reg_t; + + /** Group: EFUSE_APB2OTP Block0 Write Disable Data */ /** Type of apb2otp_wr_dis register * eFuse apb2otp block0 data register1. @@ -1841,19 +2790,6 @@ typedef union { uint32_t val; } efuse_apb2otp_blk2_w11_reg_t; -/** Type of apb2otp_blk10_w11 register - * eFuse apb2otp block10 data register11. - */ -typedef union { - struct { - /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word11 data. - */ - uint32_t apb2otp_block10_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w11_reg_t; - /** Group: EFUSE_APB2OTP Block3 Word1 Data */ /** Type of apb2otp_blk3_w1 register @@ -3160,6 +4096,21 @@ typedef union { } efuse_apb2otp_blk10_w10_reg_t; +/** Group: EFUSE_APB2OTP Block2 Word11 Data */ +/** Type of apb2otp_blk10_w11 register + * eFuse apb2otp block10 data register11. + */ +typedef union { + struct { + /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word11 data. + */ + uint32_t apb2otp_block10_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w11_reg_t; + + /** Group: EFUSE_APB2OTP Function Enable Singal */ /** Type of apb2otp_en register * eFuse apb2otp enable configuration register. @@ -3177,8 +4128,17 @@ typedef union { typedef struct { - volatile efuse_pgm_datan_reg_t pgm_datan[8]; - volatile efuse_pgm_check_valuen_reg_t pgm_check_valuen[3]; + volatile efuse_pgm_data0_reg_t pgm_data0; + volatile efuse_pgm_data1_reg_t pgm_data1; + volatile efuse_pgm_data2_reg_t pgm_data2; + volatile efuse_pgm_data3_reg_t pgm_data3; + volatile efuse_pgm_data4_reg_t pgm_data4; + volatile efuse_pgm_data5_reg_t pgm_data5; + volatile efuse_pgm_data6_reg_t pgm_data6; + volatile efuse_pgm_data7_reg_t pgm_data7; + volatile efuse_pgm_check_value0_reg_t pgm_check_value0; + volatile efuse_pgm_check_value1_reg_t pgm_check_value1; + volatile efuse_pgm_check_value2_reg_t pgm_check_value2; volatile efuse_rd_wr_dis0_reg_t rd_wr_dis0; volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; @@ -3191,15 +4151,78 @@ typedef struct { volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3; volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4; volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5; - volatile efuse_rd_sys_part1_datan_reg_t rd_sys_part1_datan[8]; - volatile efuse_rd_usr_datan_reg_t rd_usr_datan[8]; - volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8]; - volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8]; - volatile efuse_rd_key2_datan_reg_t rd_key2_datan[8]; - volatile efuse_rd_key3_datan_reg_t rd_key3_datan[8]; - volatile efuse_rd_key4_datan_reg_t rd_key4_datan[8]; - volatile efuse_rd_key5_datan_reg_t rd_key5_datan[8]; - volatile efuse_rd_sys_part2_datan_reg_t rd_sys_part2_datan[8]; + volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; + volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; + volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; + volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; + volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; + volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; + volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; + volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; + volatile efuse_rd_usr_data0_reg_t rd_usr_data0; + volatile efuse_rd_usr_data1_reg_t rd_usr_data1; + volatile efuse_rd_usr_data2_reg_t rd_usr_data2; + volatile efuse_rd_usr_data3_reg_t rd_usr_data3; + volatile efuse_rd_usr_data4_reg_t rd_usr_data4; + volatile efuse_rd_usr_data5_reg_t rd_usr_data5; + volatile efuse_rd_usr_data6_reg_t rd_usr_data6; + volatile efuse_rd_usr_data7_reg_t rd_usr_data7; + volatile efuse_rd_key0_data0_reg_t rd_key0_data0; + volatile efuse_rd_key0_data1_reg_t rd_key0_data1; + volatile efuse_rd_key0_data2_reg_t rd_key0_data2; + volatile efuse_rd_key0_data3_reg_t rd_key0_data3; + volatile efuse_rd_key0_data4_reg_t rd_key0_data4; + volatile efuse_rd_key0_data5_reg_t rd_key0_data5; + volatile efuse_rd_key0_data6_reg_t rd_key0_data6; + volatile efuse_rd_key0_data7_reg_t rd_key0_data7; + volatile efuse_rd_key1_data0_reg_t rd_key1_data0; + volatile efuse_rd_key1_data1_reg_t rd_key1_data1; + volatile efuse_rd_key1_data2_reg_t rd_key1_data2; + volatile efuse_rd_key1_data3_reg_t rd_key1_data3; + volatile efuse_rd_key1_data4_reg_t rd_key1_data4; + volatile efuse_rd_key1_data5_reg_t rd_key1_data5; + volatile efuse_rd_key1_data6_reg_t rd_key1_data6; + volatile efuse_rd_key1_data7_reg_t rd_key1_data7; + volatile efuse_rd_key2_data0_reg_t rd_key2_data0; + volatile efuse_rd_key2_data1_reg_t rd_key2_data1; + volatile efuse_rd_key2_data2_reg_t rd_key2_data2; + volatile efuse_rd_key2_data3_reg_t rd_key2_data3; + volatile efuse_rd_key2_data4_reg_t rd_key2_data4; + volatile efuse_rd_key2_data5_reg_t rd_key2_data5; + volatile efuse_rd_key2_data6_reg_t rd_key2_data6; + volatile efuse_rd_key2_data7_reg_t rd_key2_data7; + volatile efuse_rd_key3_data0_reg_t rd_key3_data0; + volatile efuse_rd_key3_data1_reg_t rd_key3_data1; + volatile efuse_rd_key3_data2_reg_t rd_key3_data2; + volatile efuse_rd_key3_data3_reg_t rd_key3_data3; + volatile efuse_rd_key3_data4_reg_t rd_key3_data4; + volatile efuse_rd_key3_data5_reg_t rd_key3_data5; + volatile efuse_rd_key3_data6_reg_t rd_key3_data6; + volatile efuse_rd_key3_data7_reg_t rd_key3_data7; + volatile efuse_rd_key4_data0_reg_t rd_key4_data0; + volatile efuse_rd_key4_data1_reg_t rd_key4_data1; + volatile efuse_rd_key4_data2_reg_t rd_key4_data2; + volatile efuse_rd_key4_data3_reg_t rd_key4_data3; + volatile efuse_rd_key4_data4_reg_t rd_key4_data4; + volatile efuse_rd_key4_data5_reg_t rd_key4_data5; + volatile efuse_rd_key4_data6_reg_t rd_key4_data6; + volatile efuse_rd_key4_data7_reg_t rd_key4_data7; + volatile efuse_rd_key5_data0_reg_t rd_key5_data0; + volatile efuse_rd_key5_data1_reg_t rd_key5_data1; + volatile efuse_rd_key5_data2_reg_t rd_key5_data2; + volatile efuse_rd_key5_data3_reg_t rd_key5_data3; + volatile efuse_rd_key5_data4_reg_t rd_key5_data4; + volatile efuse_rd_key5_data5_reg_t rd_key5_data5; + volatile efuse_rd_key5_data6_reg_t rd_key5_data6; + volatile efuse_rd_key5_data7_reg_t rd_key5_data7; + volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; + volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; + volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; + volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; + volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; + volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; + volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; + volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0; volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1; volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2; diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 505474d50d..18fbba19d4 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -29,10 +29,10 @@ // #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 //TODO: [ESP32C61] IDF-9319 // #define SOC_TEMP_SENSOR_SUPPORTED 1 //TODO: [ESP32C61] IDF-9322 // #define SOC_WIFI_SUPPORTED 1 -// #define SOC_SUPPORTS_SECURE_DL_MODE 1 +#define SOC_SUPPORTS_SECURE_DL_MODE 1 // #define SOC_ULP_SUPPORTED 1 #define SOC_EFUSE_KEY_PURPOSE_FIELD 1 -#define SOC_EFUSE_SUPPORTED 1 //TODO: [ESP32C61] IDF-9282 +#define SOC_EFUSE_SUPPORTED 1 #define SOC_RTC_FAST_MEM_SUPPORTED 1 #define SOC_RTC_MEM_SUPPORTED 1 //TODO: [ESP32C61] IDF-9274 // #define SOC_I2S_SUPPORTED 1 //TODO: [ESP32C61] IDF-9312, IDF-9313 @@ -443,11 +443,11 @@ /*-------------------------- eFuse CAPS----------------------------*/ -#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1 +#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 0 #define SOC_EFUSE_DIS_PAD_JTAG 1 #define SOC_EFUSE_DIS_USB_JTAG 1 #define SOC_EFUSE_DIS_DIRECT_BOOT 1 -#define SOC_EFUSE_SOFT_DIS_JTAG 1 +#define SOC_EFUSE_SOFT_DIS_JTAG 0 #define SOC_EFUSE_DIS_ICACHE 1 #define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES key purpose not supported for this block