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feat(efuse): Add flash&psram efuses for S3

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KonstantinKondrashov 2023-07-06 15:27:24 +08:00 committed by Konstantin Kondrashov
parent d922d4178f
commit 24f6995fb5
7 changed files with 210 additions and 20 deletions
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110
components/efuse/esp32s3/esp_efuse_table.c
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@ -9,7 +9,7 @@
#include <assert.h> #include <assert.h>
#include "esp_efuse_table.h" #include "esp_efuse_table.h"
// md5_digest_table 7f80667718451ae522bb4d60ced03d49 // md5_digest_table e0674ff40a1e124670c6eecf33410e76
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file // If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -275,6 +275,30 @@ static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MINOR, {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MINOR,
}; };
static const esp_efuse_desc_t WR_DIS_FLASH_CAP[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_CAP,
};
static const esp_efuse_desc_t WR_DIS_FLASH_TEMP[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_TEMP,
};
static const esp_efuse_desc_t WR_DIS_FLASH_VENDOR[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_VENDOR,
};
static const esp_efuse_desc_t WR_DIS_PSRAM_CAP[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_CAP,
};
static const esp_efuse_desc_t WR_DIS_PSRAM_TEMP[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_TEMP,
};
static const esp_efuse_desc_t WR_DIS_PSRAM_VENDOR[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_VENDOR,
};
static const esp_efuse_desc_t WR_DIS_K_RTC_LDO[] = { static const esp_efuse_desc_t WR_DIS_K_RTC_LDO[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of K_RTC_LDO, {EFUSE_BLK0, 20, 1}, // [] wr_dis of K_RTC_LDO,
}; };
@ -732,6 +756,30 @@ static const esp_efuse_desc_t BLK_VERSION_MINOR[] = {
{EFUSE_BLK1, 120, 3}, // [] BLK_VERSION_MINOR, {EFUSE_BLK1, 120, 3}, // [] BLK_VERSION_MINOR,
}; };
static const esp_efuse_desc_t FLASH_CAP[] = {
{EFUSE_BLK1, 123, 3}, // [] Flash capacity {0: "None"; 1: "8M"; 2: "4M"},
};
static const esp_efuse_desc_t FLASH_TEMP[] = {
{EFUSE_BLK1, 126, 2}, // [] Flash temperature {0: "None"; 1: "105C"; 2: "85C"},
};
static const esp_efuse_desc_t FLASH_VENDOR[] = {
{EFUSE_BLK1, 128, 3}, // [] Flash vendor {0: "None"; 1: "XMC"; 2: "GD"; 3: "FM"; 4: "TT"; 5: "BY"},
};
static const esp_efuse_desc_t PSRAM_CAP[] = {
{EFUSE_BLK1, 131, 2}, // [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"},
};
static const esp_efuse_desc_t PSRAM_TEMP[] = {
{EFUSE_BLK1, 133, 2}, // [] PSRAM temperature {0: "None"; 1: "105C"; 2: "85C"},
};
static const esp_efuse_desc_t PSRAM_VENDOR[] = {
{EFUSE_BLK1, 135, 2}, // [] PSRAM vendor {0: "None"; 1: "AP_3v3"; 2: "AP_1v8"},
};
static const esp_efuse_desc_t K_RTC_LDO[] = { static const esp_efuse_desc_t K_RTC_LDO[] = {
{EFUSE_BLK1, 141, 7}, // [] BLOCK1 K_RTC_LDO, {EFUSE_BLK1, 141, 7}, // [] BLOCK1 K_RTC_LDO,
}; };
@ -1205,6 +1253,36 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = {
NULL NULL
}; };
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[] = {
&WR_DIS_FLASH_CAP[0], // [] wr_dis of FLASH_CAP
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[] = {
&WR_DIS_FLASH_TEMP[0], // [] wr_dis of FLASH_TEMP
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[] = {
&WR_DIS_FLASH_VENDOR[0], // [] wr_dis of FLASH_VENDOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[] = {
&WR_DIS_PSRAM_CAP[0], // [] wr_dis of PSRAM_CAP
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_TEMP[] = {
&WR_DIS_PSRAM_TEMP[0], // [] wr_dis of PSRAM_TEMP
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[] = {
&WR_DIS_PSRAM_VENDOR[0], // [] wr_dis of PSRAM_VENDOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_RTC_LDO[] = { const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_RTC_LDO[] = {
&WR_DIS_K_RTC_LDO[0], // [] wr_dis of K_RTC_LDO &WR_DIS_K_RTC_LDO[0], // [] wr_dis of K_RTC_LDO
NULL NULL
@ -1775,6 +1853,36 @@ const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = {
NULL NULL
}; };
const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = {
&FLASH_CAP[0], // [] Flash capacity {0: "None"; 1: "8M"; 2: "4M"}
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[] = {
&FLASH_TEMP[0], // [] Flash temperature {0: "None"; 1: "105C"; 2: "85C"}
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = {
&FLASH_VENDOR[0], // [] Flash vendor {0: "None"; 1: "XMC"; 2: "GD"; 3: "FM"; 4: "TT"; 5: "BY"}
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[] = {
&PSRAM_CAP[0], // [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"}
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_PSRAM_TEMP[] = {
&PSRAM_TEMP[0], // [] PSRAM temperature {0: "None"; 1: "105C"; 2: "85C"}
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[] = {
&PSRAM_VENDOR[0], // [] PSRAM vendor {0: "None"; 1: "AP_3v3"; 2: "AP_1v8"}
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[] = { const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[] = {
&K_RTC_LDO[0], // [] BLOCK1 K_RTC_LDO &K_RTC_LDO[0], // [] BLOCK1 K_RTC_LDO
NULL NULL

14
components/efuse/esp32s3/esp_efuse_table.csv
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@ -9,7 +9,7 @@
# this will generate new source files, next rebuild all the sources. # this will generate new source files, next rebuild all the sources.
# !!!!!!!!!!! # # !!!!!!!!!!! #
# This file was generated by regtools.py based on the efuses.yaml file with the version: 6925129eca795b8b087d31be539740ec # This file was generated by regtools.py based on the efuses.yaml file with the version: f75f74727101326a187188a23f4a6c70
WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
@ -76,6 +76,12 @@ WR_DIS.SPI_PAD_CONFIG_D7, EFUSE_BLK0, 20, 1, [] wr_dis
WR_DIS.WAFER_VERSION_MINOR_LO, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_LO WR_DIS.WAFER_VERSION_MINOR_LO, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_LO
WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR
WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP
WR_DIS.FLASH_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_TEMP
WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR
WR_DIS.PSRAM_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_CAP
WR_DIS.PSRAM_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_TEMP
WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VENDOR
WR_DIS.K_RTC_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_RTC_LDO WR_DIS.K_RTC_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_RTC_LDO
WR_DIS.K_DIG_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_DIG_LDO WR_DIS.K_DIG_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_DIG_LDO
WR_DIS.V_RTC_DBIAS20, EFUSE_BLK0, 20, 1, [] wr_dis of V_RTC_DBIAS20 WR_DIS.V_RTC_DBIAS20, EFUSE_BLK0, 20, 1, [] wr_dis of V_RTC_DBIAS20
@ -194,6 +200,12 @@ SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, [] SPI_PA
WAFER_VERSION_MINOR_LO, EFUSE_BLK1, 114, 3, [] WAFER_VERSION_MINOR least significant bits WAFER_VERSION_MINOR_LO, EFUSE_BLK1, 114, 3, [] WAFER_VERSION_MINOR least significant bits
PKG_VERSION, EFUSE_BLK1, 117, 3, [] Package version PKG_VERSION, EFUSE_BLK1, 117, 3, [] Package version
BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, [] BLK_VERSION_MINOR BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, [] BLK_VERSION_MINOR
FLASH_CAP, EFUSE_BLK1, 123, 3, [] Flash capacity {0: "None"; 1: "8M"; 2: "4M"}
FLASH_TEMP, EFUSE_BLK1, 126, 2, [] Flash temperature {0: "None"; 1: "105C"; 2: "85C"}
FLASH_VENDOR, EFUSE_BLK1, 128, 3, [] Flash vendor {0: "None"; 1: "XMC"; 2: "GD"; 3: "FM"; 4: "TT"; 5: "BY"}
PSRAM_CAP, EFUSE_BLK1, 131, 2, [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"}
PSRAM_TEMP, EFUSE_BLK1, 133, 2, [] PSRAM temperature {0: "None"; 1: "105C"; 2: "85C"}
PSRAM_VENDOR, EFUSE_BLK1, 135, 2, [] PSRAM vendor {0: "None"; 1: "AP_3v3"; 2: "AP_1v8"}
K_RTC_LDO, EFUSE_BLK1, 141, 7, [] BLOCK1 K_RTC_LDO K_RTC_LDO, EFUSE_BLK1, 141, 7, [] BLOCK1 K_RTC_LDO
K_DIG_LDO, EFUSE_BLK1, 148, 7, [] BLOCK1 K_DIG_LDO K_DIG_LDO, EFUSE_BLK1, 148, 7, [] BLOCK1 K_DIG_LDO
V_RTC_DBIAS20, EFUSE_BLK1, 155, 8, [] BLOCK1 voltage of rtc dbias20 V_RTC_DBIAS20, EFUSE_BLK1, 155, 8, [] BLOCK1 voltage of rtc dbias20

Can't render this file because it contains an unexpected character in line 8 and column 53.

14
components/efuse/esp32s3/include/esp_efuse_table.h
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@ -10,7 +10,7 @@ extern "C" {
#include "esp_efuse.h" #include "esp_efuse.h"
// md5_digest_table 7f80667718451ae522bb4d60ced03d49 // md5_digest_table e0674ff40a1e124670c6eecf33410e76
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file // If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -96,6 +96,12 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D7[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_LO[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_LO[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_TEMP[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_RTC_LDO[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_RTC_LDO[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_DIG_LDO[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_DIG_LDO[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_RTC_DBIAS20[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_RTC_DBIAS20[];
@ -242,6 +248,12 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_LO[]; extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_LO[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_TEMP[];
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[]; extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[];
extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[]; extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[];
extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[]; extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[];

2
components/hal/esp32s3/include/hal/efuse_ll.h
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@ -84,7 +84,7 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_versi
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
{ {
return 0; return EFUSE.rd_mac_spi_sys_3.pkg_version;
} }
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void) __attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void)

3
components/soc/esp32s3/include/soc/efuse_defs.h
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@ -12,6 +12,9 @@ extern "C" {
#define EFUSE_WRITE_OP_CODE 0x5a5a #define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5 #define EFUSE_READ_OP_CODE 0x5aa5
#define EFUSE_PKG_VERSION_ESP32S3 0 // QFN56
#define EFUSE_PKG_VERSION_ESP32S3PICO 1 // LGA56
/** EFUSE_RD_MAC_SPI_SYS_2_REG register /** EFUSE_RD_MAC_SPI_SYS_2_REG register
* BLOCK1 data register 2. * BLOCK1 data register 2.
*/ */

57
components/soc/esp32s3/include/soc/efuse_reg.h
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@ -816,25 +816,60 @@ extern "C" {
#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S) #define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U #define EFUSE_BLK_VERSION_MINOR_V 0x00000007U
#define EFUSE_BLK_VERSION_MINOR_S 24 #define EFUSE_BLK_VERSION_MINOR_S 24
/** EFUSE_RESERVED_1_123 : R; bitpos: [31:27]; default: 0; /** EFUSE_FLASH_CAP : R; bitpos: [29:27]; default: 0;
* reserved * Flash capacity
*/ */
#define EFUSE_RESERVED_1_123 0x0000001FU #define EFUSE_FLASH_CAP 0x00000007U
#define EFUSE_RESERVED_1_123_M (EFUSE_RESERVED_1_123_V << EFUSE_RESERVED_1_123_S) #define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
#define EFUSE_RESERVED_1_123_V 0x0000001FU #define EFUSE_FLASH_CAP_V 0x00000007U
#define EFUSE_RESERVED_1_123_S 27 #define EFUSE_FLASH_CAP_S 27
/** EFUSE_FLASH_TEMP : R; bitpos: [31:30]; default: 0;
* Flash temperature
*/
#define EFUSE_FLASH_TEMP 0x00000003U
#define EFUSE_FLASH_TEMP_M (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S)
#define EFUSE_FLASH_TEMP_V 0x00000003U
#define EFUSE_FLASH_TEMP_S 30
/** EFUSE_RD_MAC_SPI_SYS_4_REG register /** EFUSE_RD_MAC_SPI_SYS_4_REG register
* BLOCK1 data register 4. * BLOCK1 data register 4.
*/ */
#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) #define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
/** EFUSE_RESERVED_1_128 : R; bitpos: [12:0]; default: 0; /** EFUSE_FLASH_VENDOR : R; bitpos: [2:0]; default: 0;
* Flash vendor
*/
#define EFUSE_FLASH_VENDOR 0x00000007U
#define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
#define EFUSE_FLASH_VENDOR_V 0x00000007U
#define EFUSE_FLASH_VENDOR_S 0
/** EFUSE_PSRAM_CAP : R; bitpos: [4:3]; default: 0;
* PSRAM capacity
*/
#define EFUSE_PSRAM_CAP 0x00000003U
#define EFUSE_PSRAM_CAP_M (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S)
#define EFUSE_PSRAM_CAP_V 0x00000003U
#define EFUSE_PSRAM_CAP_S 3
/** EFUSE_PSRAM_TEMP : R; bitpos: [6:5]; default: 0;
* PSRAM temperature
*/
#define EFUSE_PSRAM_TEMP 0x00000003U
#define EFUSE_PSRAM_TEMP_M (EFUSE_PSRAM_TEMP_V << EFUSE_PSRAM_TEMP_S)
#define EFUSE_PSRAM_TEMP_V 0x00000003U
#define EFUSE_PSRAM_TEMP_S 5
/** EFUSE_PSRAM_VENDOR : R; bitpos: [8:7]; default: 0;
* PSRAM vendor
*/
#define EFUSE_PSRAM_VENDOR 0x00000003U
#define EFUSE_PSRAM_VENDOR_M (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S)
#define EFUSE_PSRAM_VENDOR_V 0x00000003U
#define EFUSE_PSRAM_VENDOR_S 7
/** EFUSE_RESERVED_1_137 : R; bitpos: [12:9]; default: 0;
* reserved * reserved
*/ */
#define EFUSE_RESERVED_1_128 0x00001FFFU #define EFUSE_RESERVED_1_137 0x0000000FU
#define EFUSE_RESERVED_1_128_M (EFUSE_RESERVED_1_128_V << EFUSE_RESERVED_1_128_S) #define EFUSE_RESERVED_1_137_M (EFUSE_RESERVED_1_137_V << EFUSE_RESERVED_1_137_S)
#define EFUSE_RESERVED_1_128_V 0x00001FFFU #define EFUSE_RESERVED_1_137_V 0x0000000FU
#define EFUSE_RESERVED_1_128_S 0 #define EFUSE_RESERVED_1_137_S 9
/** EFUSE_K_RTC_LDO : R; bitpos: [19:13]; default: 0; /** EFUSE_K_RTC_LDO : R; bitpos: [19:13]; default: 0;
* BLOCK1 K_RTC_LDO * BLOCK1 K_RTC_LDO
*/ */

30
components/soc/esp32s3/include/soc/efuse_struct.h
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@ -602,10 +602,14 @@ typedef union {
* BLK_VERSION_MINOR * BLK_VERSION_MINOR
*/ */
uint32_t blk_version_minor:3; uint32_t blk_version_minor:3;
/** reserved_1_123 : R; bitpos: [31:27]; default: 0; /** flash_cap : R; bitpos: [29:27]; default: 0;
* reserved * Flash capacity
*/ */
uint32_t reserved_1_123:5; uint32_t flash_cap:3;
/** flash_temp : R; bitpos: [31:30]; default: 0;
* Flash temperature
*/
uint32_t flash_temp:2;
}; };
uint32_t val; uint32_t val;
} efuse_rd_mac_spi_sys_3_reg_t; } efuse_rd_mac_spi_sys_3_reg_t;
@ -615,10 +619,26 @@ typedef union {
*/ */
typedef union { typedef union {
struct { struct {
/** reserved_1_128 : R; bitpos: [12:0]; default: 0; /** flash_vendor : R; bitpos: [2:0]; default: 0;
* Flash vendor
*/
uint32_t flash_vendor:3;
/** psram_cap : R; bitpos: [4:3]; default: 0;
* PSRAM capacity
*/
uint32_t psram_cap:2;
/** psram_temp : R; bitpos: [6:5]; default: 0;
* PSRAM temperature
*/
uint32_t psram_temp:2;
/** psram_vendor : R; bitpos: [8:7]; default: 0;
* PSRAM vendor
*/
uint32_t psram_vendor:2;
/** reserved_1_137 : R; bitpos: [12:9]; default: 0;
* reserved * reserved
*/ */
uint32_t reserved_1_128:13; uint32_t reserved_1_137:4;
/** k_rtc_ldo : R; bitpos: [19:13]; default: 0; /** k_rtc_ldo : R; bitpos: [19:13]; default: 0;
* BLOCK1 K_RTC_LDO * BLOCK1 K_RTC_LDO
*/ */