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Merge branch 'refactor/panic_handler_follow_ups' into 'master'
Panic handler follow ups See merge request espressif/esp-idf!7732
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commit
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@ -111,7 +111,7 @@ static void print_debug_exception_details(const void *f)
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#if CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK
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int core = 0;
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#if !CONFIG_FREERTOS_UNICORE
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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if (f == xt_exc_frames[1]) {
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core = 1;
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}
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@ -209,11 +209,11 @@ static void print_registers(const void *f, int core)
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// If the core which triggers the interrupt watchpoint was in ISR context, dump the epc registers.
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if (xPortInterruptedFromISRContext()
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#if !CONFIG_FREERTOS_UNICORE
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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&& ((core == 0 && frame->exccause == PANIC_RSN_INTWDT_CPU0) ||
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(core == 1 && frame->exccause == PANIC_RSN_INTWDT_CPU1))
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#endif //!CONFIG_FREERTOS_UNICORE
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) {
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#endif //!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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) {
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panic_print_str("\r\n");
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@ -251,7 +251,7 @@ static void print_state_for_core(const void *f, int core)
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static void print_state(const void *f)
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{
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#if !CONFIG_FREERTOS_UNICORE
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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int err_core = f == xt_exc_frames[0] ? 0 : 1;
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#else
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int err_core = 0;
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@ -261,7 +261,7 @@ static void print_state(const void *f)
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panic_print_str("\r\n");
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#if !CONFIG_FREERTOS_UNICORE
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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// If there are other frame info, print them as well
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for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
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// `f` is the frame for the offending core, see note above.
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@ -478,7 +478,7 @@ static void panic_handler(XtExcFrame *frame, bool pseudo_excause)
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// If multiple cores arrive at panic handler, save frames for all of them
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xt_exc_frames[core_id] = frame;
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#if !CONFIG_FREERTOS_UNICORE
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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// These are cases where both CPUs both go into panic handler. The following code ensures
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// only one core proceeds to the system panic handler.
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if (pseudo_excause) {
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