diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt
index 944999f154..76f70665f6 100644
--- a/components/esp_rom/CMakeLists.txt
+++ b/components/esp_rom/CMakeLists.txt
@@ -70,7 +70,7 @@ if(CONFIG_HAL_WDT_USE_ROM_IMPL)
     list(APPEND sources "patches/esp_rom_wdt.c")
 endif()
 
-if(CONFIG_ESP_ROM_CLIC_INT_TYPE_PATCH OR CONFIG_ESP_ROM_CLIC_INT_THRESH_PATCH)
+if(CONFIG_ESP_ROM_CLIC_INT_TYPE_PATCH)
     list(APPEND sources "patches/esp_rom_clic.c")
 endif()
 
diff --git a/components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in b/components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in
index e3c3d9b6f1..688612fcdb 100644
--- a/components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in
+++ b/components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in
@@ -86,7 +86,3 @@ config ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB
 config ESP_ROM_HAS_OUTPUT_PUTC_FUNC
     bool
     default y
-
-config ESP_ROM_CLIC_INT_THRESH_PATCH
-    bool
-    default y
diff --git a/components/esp_rom/esp32c5/mp/esp32c5/esp_rom_caps.h b/components/esp_rom/esp32c5/mp/esp32c5/esp_rom_caps.h
index 5b1c3db40f..9006d78b2f 100644
--- a/components/esp_rom/esp32c5/mp/esp32c5/esp_rom_caps.h
+++ b/components/esp_rom/esp32c5/mp/esp32c5/esp_rom_caps.h
@@ -27,4 +27,3 @@
 #define ESP_ROM_HAS_VERSION                 (1) // ROM has version/eco information
 #define ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB  (1) // ROM supports the HP core to jump to the RTC memory to execute stub code after waking up from deepsleep.
 #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC        (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
-#define ESP_ROM_CLIC_INT_THRESH_PATCH       (1) // ROM version of esprv_intc_int_set_threshold incorrectly assumes lowest MINTTHRESH is 0x1F, should be 0xF
diff --git a/components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.ld b/components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.ld
index 8724419cc6..3f5b833a29 100644
--- a/components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.ld
+++ b/components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.ld
@@ -276,6 +276,7 @@ gpio_pad_hold = 0x40000740;
 
 /* Functions */
 esprv_intc_int_set_priority = 0x40000744;
+esprv_intc_int_set_threshold = 0x40000748;
 esprv_intc_int_enable = 0x4000074c;
 esprv_intc_int_disable = 0x40000750;
 esprv_intc_int_set_type = 0x40000754;
diff --git a/components/esp_rom/esp32c61/Kconfig.soc_caps.in b/components/esp_rom/esp32c61/Kconfig.soc_caps.in
index aa0401e081..67076708db 100644
--- a/components/esp_rom/esp32c61/Kconfig.soc_caps.in
+++ b/components/esp_rom/esp32c61/Kconfig.soc_caps.in
@@ -90,7 +90,3 @@ config ESP_ROM_USB_OTG_NUM
 config ESP_ROM_HAS_OUTPUT_PUTC_FUNC
     bool
     default y
-
-config ESP_ROM_CLIC_INT_THRESH_PATCH
-    bool
-    default y
diff --git a/components/esp_rom/esp32c61/esp_rom_caps.h b/components/esp_rom/esp32c61/esp_rom_caps.h
index 27f71c271c..aea1da0391 100644
--- a/components/esp_rom/esp32c61/esp_rom_caps.h
+++ b/components/esp_rom/esp32c61/esp_rom_caps.h
@@ -30,4 +30,3 @@
 #define ESP_ROM_HAS_SW_FLOAT                (1) // ROM has libgcc software floating point emulation functions
 #define ESP_ROM_USB_OTG_NUM                 (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.
 #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC        (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
-#define ESP_ROM_CLIC_INT_THRESH_PATCH       (1) // ROM version of esprv_intc_int_set_threshold incorrectly assumes lowest MINTTHRESH is 0x1F, should be 0xF
diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.ld
index a90b5b65b7..fae956570c 100644
--- a/components/esp_rom/esp32c61/ld/esp32c61.rom.ld
+++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.ld
@@ -278,6 +278,7 @@ gpio_pad_hold = 0x40000724;
 
 /* Functions */
 esprv_intc_int_set_priority = 0x40000728;
+esprv_intc_int_set_threshold = 0x4000072c;
 esprv_intc_int_enable = 0x40000730;
 esprv_intc_int_disable = 0x40000734;
 esprv_intc_int_set_type = 0x40000738;
diff --git a/components/esp_rom/patches/esp_rom_clic.c b/components/esp_rom/patches/esp_rom_clic.c
index 7160931c66..d4643e3ef5 100644
--- a/components/esp_rom/patches/esp_rom_clic.c
+++ b/components/esp_rom/patches/esp_rom_clic.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,7 +7,6 @@
 #include "esp_rom_caps.h"
 #include "soc/clic_reg.h"
 #include "riscv/interrupt.h"
-#include "riscv/rv_utils.h"
 
 #if ESP_ROM_CLIC_INT_TYPE_PATCH
 
@@ -21,11 +20,3 @@ void esprv_int_set_type(int rv_int_num, enum intr_type type)
     REG_SET_FIELD(CLIC_INT_CTRL_REG(rv_int_num + CLIC_EXT_INTR_NUM_OFFSET), CLIC_INT_ATTR_TRIG, type);
 }
 #endif
-
-#if ESP_ROM_CLIC_INT_THRESH_PATCH
-void esprv_int_set_threshold(int priority_threshold)
-{
-    /* ROM functions assume minimum MINTTHRESH is 0x1F, but it is actually 0xF */
-    rv_utils_set_intlevel(priority_threshold);
-}
-#endif //ESP_ROM_CLIC_INT_THRESH_PATCH
diff --git a/components/soc/esp32c5/mp/include/soc/clic_reg.h b/components/soc/esp32c5/mp/include/soc/clic_reg.h
index 35b8003fee..324cfd8c8a 100644
--- a/components/soc/esp32c5/mp/include/soc/clic_reg.h
+++ b/components/soc/esp32c5/mp/include/soc/clic_reg.h
@@ -10,7 +10,7 @@
 extern "C" {
 #endif
 
-#define NLBITS                   4
+#define NLBITS                   3
 #define CLIC_EXT_INTR_NUM_OFFSET 16
 #define DUALCORE_CLIC_CTRL_OFF   0x10000
 
diff --git a/components/soc/esp32c61/include/soc/clic_reg.h b/components/soc/esp32c61/include/soc/clic_reg.h
index 219c175647..5ce606a178 100644
--- a/components/soc/esp32c61/include/soc/clic_reg.h
+++ b/components/soc/esp32c61/include/soc/clic_reg.h
@@ -10,7 +10,7 @@
 extern "C" {
 #endif
 
-#define NLBITS                   4
+#define NLBITS                   3
 #define CLIC_EXT_INTR_NUM_OFFSET 16
 
 #define DR_REG_CLIC_BASE      (0x20800000)