diff --git a/components/hal/include/hal/usb_dwc_hal.h b/components/hal/include/hal/usb_dwc_hal.h
index 133fe2bc45..38fd1fe341 100644
--- a/components/hal/include/hal/usb_dwc_hal.h
+++ b/components/hal/include/hal/usb_dwc_hal.h
@@ -191,7 +191,7 @@ typedef struct {
     struct {
         int num_allocd;                             /**< Number of channels currently allocated */
         uint32_t chan_pend_intrs_msk;               /**< Bit mask of channels with pending interrupts */
-        usb_dwc_hal_chan_t *hdls[USB_DWC_NUM_HOST_CHAN];    /**< Handles of each channel. Set to NULL if channel has not been allocated */
+        usb_dwc_hal_chan_t *hdls[OTG_NUM_HOST_CHAN];    /**< Handles of each channel. Set to NULL if channel has not been allocated */
     } channels;
 } usb_dwc_hal_context_t;
 
diff --git a/components/hal/include/hal/usb_dwc_ll.h b/components/hal/include/hal/usb_dwc_ll.h
index 2900ff65f2..7d0b021f47 100644
--- a/components/hal/include/hal/usb_dwc_ll.h
+++ b/components/hal/include/hal/usb_dwc_ll.h
@@ -102,19 +102,6 @@ Todo: Check sizes again and express this macro in terms of DWC config options (I
 #define USB_DWC_FIFO_NPTX_LINES_BIASTX   16
 #define USB_DWC_FIFO_PTX_LINES_BIASTX    150
 
-
-/*
- * List of relevant DWC configurations. See DWC OTG databook Chapter 3 for more
- * details.
- */
-#define USB_DWC_FSPHY_INTERFACE             1
-#define USB_DWC_NUM_EPS                     6
-#define USB_DWC_NUM_IN_EPS                  5       // Todo: Add check for when number of IN channels exceeds limit (IDF-8556)
-#define USB_DWC_NUM_HOST_CHAN               8
-#define USB_DWC_DFIFO_DEPTH                 256
-#define USB_DWC_RX_DFIFO_DEPTH              256
-#define USB_DWC_TX_DFIFO_DEPTH              256     // Same value applies to HNPERIO, NPERIO, HPERIO, and DINEP
-
 /* -----------------------------------------------------------------------------
 ------------------------------- Global Registers -------------------------------
 ----------------------------------------------------------------------------- */
diff --git a/components/hal/usb_dwc_hal.c b/components/hal/usb_dwc_hal.c
index 6dfc1a5fba..5875d9e6fe 100644
--- a/components/hal/usb_dwc_hal.c
+++ b/components/hal/usb_dwc_hal.c
@@ -188,7 +188,7 @@ void usb_dwc_hal_core_soft_reset(usb_dwc_hal_context_t *hal)
     hal->flags.val = 0;
     hal->channels.num_allocd = 0;
     hal->channels.chan_pend_intrs_msk = 0;
-    memset(hal->channels.hdls, 0, sizeof(usb_dwc_hal_chan_t *) * USB_DWC_NUM_HOST_CHAN);
+    memset(hal->channels.hdls, 0, sizeof(usb_dwc_hal_chan_t *) * OTG_NUM_HOST_CHAN);
 }
 
 void usb_dwc_hal_set_fifo_bias(usb_dwc_hal_context_t *hal, const usb_hal_fifo_bias_t fifo_bias)
@@ -210,7 +210,7 @@ void usb_dwc_hal_set_fifo_bias(usb_dwc_hal_context_t *hal, const usb_hal_fifo_bi
 
     HAL_ASSERT((fifo_config->rx_fifo_lines + fifo_config->nptx_fifo_lines + fifo_config->ptx_fifo_lines) <= USB_DWC_FIFO_TOTAL_USABLE_LINES);
     //Check that none of the channels are active
-    for (int i = 0; i < USB_DWC_NUM_HOST_CHAN; i++) {
+    for (int i = 0; i < OTG_NUM_HOST_CHAN; i++) {
         if (hal->channels.hdls[i] != NULL) {
             HAL_ASSERT(!hal->channels.hdls[i]->flags.active);
         }
@@ -264,11 +264,11 @@ bool usb_dwc_hal_chan_alloc(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan
 {
     HAL_ASSERT(hal->flags.fifo_sizes_set);  //FIFO sizes should be set befor attempting to allocate a channel
     //Attempt to allocate channel
-    if (hal->channels.num_allocd == USB_DWC_NUM_HOST_CHAN) {
+    if (hal->channels.num_allocd == OTG_NUM_HOST_CHAN) {
         return false;    //Out of free channels
     }
     int chan_idx = -1;
-    for (int i = 0; i < USB_DWC_NUM_HOST_CHAN; i++) {
+    for (int i = 0; i < OTG_NUM_HOST_CHAN; i++) {
         if (hal->channels.hdls[i] == NULL) {
             hal->channels.hdls[i] = chan_obj;
             chan_idx = i;