diff --git a/components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/CMakeLists.txt b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/CMakeLists.txt index b4687d1c66..e0307f0483 100644 --- a/components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/CMakeLists.txt +++ b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/CMakeLists.txt @@ -6,7 +6,12 @@ if(CONFIG_ANA_CMPR_ISR_IRAM_SAFE) list(APPEND srcs "test_ana_cmpr_iram.c") endif() +if(CONFIG_SOC_ANA_CMPR_SUPPORT_ETM AND CONFIG_SOC_TIMER_SUPPORT_ETM) + # Analog Comparator event test relies on GPTIMER task + list(APPEND srcs "test_ana_cmpr_etm.c") +endif() + idf_component_register(SRCS ${srcs} INCLUDE_DIRS "." - PRIV_REQUIRES unity esp_driver_gpio esp_driver_ana_cmpr + PRIV_REQUIRES unity esp_driver_gpio esp_driver_ana_cmpr esp_driver_gptimer WHOLE_ARCHIVE) diff --git a/components/esp_hw_support/test_apps/etm/main/test_ana_cmpr_etm.c b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/test_ana_cmpr_etm.c similarity index 100% rename from components/esp_hw_support/test_apps/etm/main/test_ana_cmpr_etm.c rename to components/esp_driver_ana_cmpr/test_apps/analog_comparator/main/test_ana_cmpr_etm.c diff --git a/components/esp_driver_gpio/test_apps/gpio_extensions/main/CMakeLists.txt b/components/esp_driver_gpio/test_apps/gpio_extensions/main/CMakeLists.txt index 3b4bd6d620..c61fee0bb5 100644 --- a/components/esp_driver_gpio/test_apps/gpio_extensions/main/CMakeLists.txt +++ b/components/esp_driver_gpio/test_apps/gpio_extensions/main/CMakeLists.txt @@ -12,6 +12,10 @@ if(CONFIG_SOC_GPIO_SUPPORT_PIN_HYS_FILTER) list(APPEND srcs "test_hysteresis.c") endif() +if(CONFIG_SOC_GPIO_SUPPORT_ETM) + list(APPEND srcs "test_gpio_etm.c") +endif() + # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} diff --git a/components/esp_hw_support/test_apps/etm/main/test_gpio_etm.c b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_gpio_etm.c similarity index 98% rename from components/esp_hw_support/test_apps/etm/main/test_gpio_etm.c rename to components/esp_driver_gpio/test_apps/gpio_extensions/main/test_gpio_etm.c index cd2c0d1bcb..9d13f09b36 100644 --- a/components/esp_hw_support/test_apps/etm/main/test_gpio_etm.c +++ b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_gpio_etm.c @@ -94,10 +94,10 @@ TEST_CASE("gpio_etm_self_trigger", "[etm]") TEST_CASE("gpio_etm_self_trigger_multi_action", "[etm]") { // GPIO 0 pos edge event ---> GPIO 1 set level task - // GPIO 22 pos edge event ---> GPIO 1 clear level task + // GPIO 2 pos edge event ---> GPIO 1 clear level task const uint32_t input_gpio1 = 0; - const uint32_t input_gpio2 = 22; + const uint32_t input_gpio2 = 2; const uint32_t output_gpio = 1; printf("allocate etm channels\r\n"); esp_etm_channel_config_t etm_config = {}; diff --git a/components/esp_driver_gptimer/test_apps/gptimer/main/CMakeLists.txt b/components/esp_driver_gptimer/test_apps/gptimer/main/CMakeLists.txt index 39337b4ce6..3fb34ea479 100644 --- a/components/esp_driver_gptimer/test_apps/gptimer/main/CMakeLists.txt +++ b/components/esp_driver_gptimer/test_apps/gptimer/main/CMakeLists.txt @@ -5,6 +5,10 @@ if(CONFIG_GPTIMER_ISR_IRAM_SAFE) list(APPEND srcs "test_gptimer_iram.c") endif() +if(CONFIG_SOC_TIMER_SUPPORT_ETM) + list(APPEND srcs "test_gptimer_etm.c") +endif() + if(CONFIG_SOC_LIGHT_SLEEP_SUPPORTED AND CONFIG_PM_ENABLE) list(APPEND srcs "test_gptimer_sleep.c") endif() @@ -12,5 +16,5 @@ endif() # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} - PRIV_REQUIRES unity esp_driver_gptimer + PRIV_REQUIRES unity esp_driver_gptimer esp_driver_gpio WHOLE_ARCHIVE) diff --git a/components/esp_hw_support/test_apps/etm/main/test_gptimer_etm.c b/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer_etm.c similarity index 96% rename from components/esp_hw_support/test_apps/etm/main/test_gptimer_etm.c rename to components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer_etm.c index 536a6e18ad..f9057f8d7e 100644 --- a/components/esp_hw_support/test_apps/etm/main/test_gptimer_etm.c +++ b/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer_etm.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,12 +13,19 @@ #include "driver/gpio_etm.h" #include "driver/gpio.h" +#if CONFIG_GPTIMER_ISR_IRAM_SAFE +#define TEST_ALARM_CALLBACK_ATTR IRAM_ATTR +#else +#define TEST_ALARM_CALLBACK_ATTR +#endif // CONFIG_GPTIMER_ISR_IRAM_SAFE + +TEST_ALARM_CALLBACK_ATTR static bool on_gptimer_alarm_cb(gptimer_handle_t timer, const gptimer_alarm_event_data_t *edata, void *user_ctx) { return false; } -TEST_CASE("gptimer_etm_alarm_event_with_interrupt_enabled", "[etm]") +TEST_CASE("gptimer_etm_alarm_event_with_interrupt_enabled", "[gptimer][etm]") { const uint32_t output_gpio = 1; // GPTimer alarm ---> ETM channel A ---> GPIO toggle @@ -100,11 +107,11 @@ TEST_CASE("gptimer_etm_alarm_event_with_interrupt_enabled", "[etm]") TEST_ESP_OK(esp_etm_del_channel(etm_channel_a)); } -TEST_CASE("gptimer_etm_alarm_event_without_interrupt", "[etm]") +TEST_CASE("gptimer_etm_alarm_event_without_interrupt", "[gptimer][etm]") { const uint32_t output_gpio = 1; // GPTimer alarm ---> ETM channel A ---> GPIO toggle - // GPTimer alarm ---> ETM channel B ---> GPTimer alarm reenable + // GPTimer alarm ---> ETM channel B ---> GPTimer alarm re-enable printf("allocate etm channel\r\n"); esp_etm_channel_config_t etm_config = {}; esp_etm_channel_handle_t etm_channel_a, etm_channel_b; @@ -188,11 +195,11 @@ TEST_CASE("gptimer_etm_alarm_event_without_interrupt", "[etm]") TEST_ESP_OK(esp_etm_del_channel(etm_channel_b)); } -TEST_CASE("gptimer_auto_reload_by_etm", "[etm]") +TEST_CASE("gptimer_auto_reload_by_etm", "[gptimer][etm]") { const uint32_t output_gpio = 1; // GPTimer alarm ---> ETM channel A ---> GPIO toggle - // GPTimer alarm ---> ETM channel B ---> GPTimer alarm reenable + // GPTimer alarm ---> ETM channel B ---> GPTimer alarm re-enable // GPTimer alarm ---> ETM channel C ---> GPTimer reload printf("allocate etm channel\r\n"); esp_etm_channel_config_t etm_config = {}; @@ -289,7 +296,7 @@ TEST_CASE("gptimer_auto_reload_by_etm", "[etm]") TEST_ESP_OK(esp_etm_del_channel(etm_channel_c)); } -TEST_CASE("gptimer_etm_task_capture", "[etm]") +TEST_CASE("gptimer_etm_task_capture", "[gptimer][etm]") { const uint32_t input_gpio = 0; // GPIO Posedge ---> ETM channel A ---> GPTimer capture @@ -366,7 +373,7 @@ TEST_CASE("gptimer_etm_task_capture", "[etm]") TEST_ESP_OK(esp_etm_del_channel(etm_channel_a)); } -TEST_CASE("gptimer_start_stop_by_etm_task", "[etm]") +TEST_CASE("gptimer_start_stop_by_etm_task", "[gptimer][etm]") { const uint32_t input_gpio = 0; // GPIO pos edge ---> ETM channel A ---> GPTimer start diff --git a/components/esp_hw_support/test_apps/.build-test-rules.yml b/components/esp_hw_support/test_apps/.build-test-rules.yml index b7e85dae37..09fb702931 100644 --- a/components/esp_hw_support/test_apps/.build-test-rules.yml +++ b/components/esp_hw_support/test_apps/.build-test-rules.yml @@ -14,20 +14,6 @@ components/esp_hw_support/test_apps/dma2d: depends_filepatterns: - components/esp_hw_support/dma/**/* -components/esp_hw_support/test_apps/esp_hw_support_unity_tests: - disable: - - if: SOC_GPSPI_SUPPORTED != 1 - -components/esp_hw_support/test_apps/etm: - disable: - - if: SOC_ETM_SUPPORTED != 1 - depends_components: - - esp_driver_gptimer - - esp_driver_gpio - - esp_driver_mcpwm - - esp_timer - - esp_driver_ana_cmpr - components/esp_hw_support/test_apps/host_test_linux: enable: - if: IDF_TARGET == "linux" diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/CMakeLists.txt b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/CMakeLists.txt index fb724b12bb..c6bda239bd 100644 --- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/CMakeLists.txt +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/CMakeLists.txt @@ -8,3 +8,8 @@ list(PREPEND SDKCONFIG_DEFAULTS "$ENV{IDF_PATH}/tools/test_apps/configs/sdkconfi include($ENV{IDF_PATH}/tools/cmake/project.cmake) project(esp_hw_support_unity) + +message(STATUS "Checking etm registers are not read-write by half-word") +include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake) +check_register_rw_half_word(SOC_MODULES "*etm" "pcr" "hp_sys_clkrst" + HAL_MODULES "etm") diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/CMakeLists.txt b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/CMakeLists.txt index daa7c071a1..26c3f712a8 100644 --- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/CMakeLists.txt +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/CMakeLists.txt @@ -17,6 +17,10 @@ if(CONFIG_SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX OR CONFIG_SOC_GPIO_CLOCKOUT_BY_IO_MUX list(APPEND srcs "test_esp_clock_output.c") endif() +if(CONFIG_SOC_ETM_SUPPORTED) + list(APPEND srcs "test_etm_core.c") +endif() + # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} diff --git a/components/esp_hw_support/test_apps/etm/main/test_etm_core.c b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_etm_core.c similarity index 100% rename from components/esp_hw_support/test_apps/etm/main/test_etm_core.c rename to components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_etm_core.c diff --git a/components/esp_hw_support/test_apps/etm/CMakeLists.txt b/components/esp_hw_support/test_apps/etm/CMakeLists.txt deleted file mode 100644 index 4505a9f1a0..0000000000 --- a/components/esp_hw_support/test_apps/etm/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -# This is the project CMakeLists.txt file for the test subproject -cmake_minimum_required(VERSION 3.16) - -include($ENV{IDF_PATH}/tools/cmake/project.cmake) - -# "Trim" the build. Include the minimal set of components, main, and anything it depends on. We also depend on esp_pm -# as we set CONFIG_PM_... options. -set(COMPONENTS main esp_pm) - -project(etm_test) - -message(STATUS "Checking etm registers are not read-write by half-word") -include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake) -check_register_rw_half_word(SOC_MODULES "*etm" "pcr" "hp_sys_clkrst" - HAL_MODULES "etm") diff --git a/components/esp_hw_support/test_apps/etm/README.md b/components/esp_hw_support/test_apps/etm/README.md deleted file mode 100644 index 7b822bdb0e..0000000000 --- a/components/esp_hw_support/test_apps/etm/README.md +++ /dev/null @@ -1,2 +0,0 @@ -| Supported Targets | ESP32-C6 | ESP32-H2 | ESP32-P4 | -| ----------------- | -------- | -------- | -------- | diff --git a/components/esp_hw_support/test_apps/etm/main/CMakeLists.txt b/components/esp_hw_support/test_apps/etm/main/CMakeLists.txt deleted file mode 100644 index 3e09a61352..0000000000 --- a/components/esp_hw_support/test_apps/etm/main/CMakeLists.txt +++ /dev/null @@ -1,26 +0,0 @@ -set(srcs "test_app_main.c" - "test_etm_core.c") - -if(CONFIG_SOC_GPIO_SUPPORT_ETM) - list(APPEND srcs "test_gpio_etm.c") -endif() - -if(CONFIG_SOC_TIMER_SUPPORT_ETM) - list(APPEND srcs "test_gptimer_etm.c") -endif() - -if(CONFIG_SOC_SYSTIMER_SUPPORT_ETM) - list(APPEND srcs "test_systimer_etm.c") -endif() - -if(CONFIG_SOC_ANA_CMPR_SUPPORT_ETM AND CONFIG_SOC_TIMER_SUPPORT_ETM) - # Analog Comparator event test relies on GPTIMER task - list(APPEND srcs "test_ana_cmpr_etm.c") -endif() - -# In order for the cases defined by `TEST_CASE` to be linked into the final elf, -# the component can be registered as WHOLE_ARCHIVE -idf_component_register(SRCS ${srcs} - PRIV_REQUIRES unity esp_timer esp_driver_gptimer esp_driver_gpio - esp_driver_mcpwm esp_driver_ana_cmpr - WHOLE_ARCHIVE) diff --git a/components/esp_hw_support/test_apps/etm/main/test_app_main.c b/components/esp_hw_support/test_apps/etm/main/test_app_main.c deleted file mode 100644 index be7beff893..0000000000 --- a/components/esp_hw_support/test_apps/etm/main/test_app_main.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "unity.h" -#include "unity_test_runner.h" -#include "esp_heap_caps.h" -#include "esp_newlib.h" -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" - -// Some resources are lazy allocated in pulse_cnt driver, the threshold is left for that case -#define TEST_MEMORY_LEAK_THRESHOLD (-300) - -static size_t before_free_8bit; -static size_t before_free_32bit; - -static void check_leak(size_t before_free, size_t after_free, const char *type) -{ - ssize_t delta = after_free - before_free; - printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta); - TEST_ASSERT_MESSAGE(delta >= TEST_MEMORY_LEAK_THRESHOLD, "memory leak"); -} - -void setUp(void) -{ - before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); - before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); -} - -void tearDown(void) -{ - /* some FreeRTOS stuff is cleaned up by idle task */ - vTaskDelay(5); - - /* clean up some of the newlib's lazy allocations */ - esp_reent_cleanup(); - - size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); - size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); - check_leak(before_free_8bit, after_free_8bit, "8BIT"); - check_leak(before_free_32bit, after_free_32bit, "32BIT"); -} - -void app_main(void) -{ - // _____ _____ __ __ _____ _ - // | ____|_ _| \/ | |_ _|__ ___| |_ - // | _| | | | |\/| | | |/ _ \/ __| __| - // | |___ | | | | | | | | __/\__ \ |_ - // |_____| |_| |_| |_| |_|\___||___/\__| - printf(" _____ _____ __ __ _____ _\r\n"); - printf("| ____|_ _| \\/ | |_ _|__ ___| |_\r\n"); - printf("| _| | | | |\\/| | | |/ _ \\/ __| __|\r\n"); - printf("| |___ | | | | | | | | __/\\__ \\ |_\r\n"); - printf("|_____| |_| |_| |_| |_|\\___||___/\\__|\r\n"); - unity_run_menu(); -} diff --git a/components/esp_hw_support/test_apps/etm/pytest_etm.py b/components/esp_hw_support/test_apps/etm/pytest_etm.py deleted file mode 100644 index c209342a4c..0000000000 --- a/components/esp_hw_support/test_apps/etm/pytest_etm.py +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD -# SPDX-License-Identifier: CC0-1.0 -import pytest -from pytest_embedded import Dut - - -@pytest.mark.esp32c6 -@pytest.mark.esp32h2 -@pytest.mark.esp32p4 -@pytest.mark.generic -@pytest.mark.parametrize( - 'config', - [ - 'release', - ], - indirect=True, -) -def test_etm(dut: Dut) -> None: - dut.run_all_single_board_cases() diff --git a/components/esp_hw_support/test_apps/etm/sdkconfig.ci.release b/components/esp_hw_support/test_apps/etm/sdkconfig.ci.release deleted file mode 100644 index 91d93f163e..0000000000 --- a/components/esp_hw_support/test_apps/etm/sdkconfig.ci.release +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_PM_ENABLE=y -CONFIG_FREERTOS_USE_TICKLESS_IDLE=y -CONFIG_COMPILER_OPTIMIZATION_SIZE=y -CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y -CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y diff --git a/components/esp_hw_support/test_apps/etm/sdkconfig.defaults b/components/esp_hw_support/test_apps/etm/sdkconfig.defaults deleted file mode 100644 index b308cb2ddd..0000000000 --- a/components/esp_hw_support/test_apps/etm/sdkconfig.defaults +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_FREERTOS_HZ=1000 -CONFIG_ESP_TASK_WDT=n diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.systimer.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.systimer.ld index 7be47b1110..9f260f5ecd 100644 --- a/components/esp_rom/esp32c5/ld/esp32c5.rom.systimer.ld +++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.systimer.ld @@ -9,8 +9,9 @@ ***************************************/ /* Functions */ -systimer_hal_init = 0x400003d0; -systimer_hal_deinit = 0x400003d4; +/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */ +/* systimer_hal_init = 0x400003d0; */ +/* systimer_hal_deinit = 0x400003d4; */ systimer_hal_set_tick_rate_ops = 0x400003d8; systimer_hal_get_counter_value = 0x400003dc; systimer_hal_get_time = 0x400003e0; diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/CMakeLists.txt b/components/esp_system/test_apps/esp_system_unity_tests/main/CMakeLists.txt index 7bccda3753..0e7335e2f4 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/main/CMakeLists.txt +++ b/components/esp_system/test_apps/esp_system_unity_tests/main/CMakeLists.txt @@ -17,6 +17,10 @@ set(SRC "test_app_main.c" "test_system_time.c" "test_task_wdt.c") +if(CONFIG_SOC_SYSTIMER_SUPPORT_ETM) + list(APPEND SRC "test_systick_etm.c") +endif() + if(CONFIG_ESP_IPC_ISR_ENABLE) list(APPEND SRC "test_ipc_isr.c") if(CONFIG_IDF_TARGET_ARCH_XTENSA) diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_systick_etm.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_systick_etm.c new file mode 100644 index 0000000000..d82cf13d62 --- /dev/null +++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_systick_etm.c @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "unity.h" +#include "unity_test_utils.h" +#include "freertos/FreeRTOS.h" +#include "esp_attr.h" +#include "esp_etm.h" +#include "esp_systick_etm.h" +#include "driver/gpio_etm.h" +#include "driver/gpio.h" + +TEST_CASE("rtos_systick_etm_event", "[etm]") +{ + // systimer alarm ---> EMT channel ---> GPIO toggle + const uint32_t output_gpio = 1; + printf("allocate etm channels\r\n"); + esp_etm_channel_config_t etm_config = {}; + esp_etm_channel_handle_t etm_channel_a = NULL; + TEST_ESP_OK(esp_etm_new_channel(&etm_config, &etm_channel_a)); + + printf("allocate GPIO etm task\r\n"); + esp_etm_task_handle_t gpio_task = NULL; + gpio_etm_task_config_t gpio_task_config = { + .action = GPIO_ETM_TASK_ACTION_TOG, + }; + TEST_ESP_OK(gpio_new_etm_task(&gpio_task_config, &gpio_task)); + + // bind GPIO to the task + TEST_ESP_OK(gpio_etm_task_add_gpio(gpio_task, output_gpio)); + + printf("initialize gpio\r\n"); + gpio_config_t task_gpio_config = { + .intr_type = GPIO_INTR_DISABLE, + .mode = GPIO_MODE_OUTPUT, + .pin_bit_mask = 1ULL << output_gpio, + }; + TEST_ESP_OK(gpio_config(&task_gpio_config)); + + printf("acquire systick etm event\r\n"); + esp_etm_event_handle_t systick_event = NULL; + TEST_ESP_OK(esp_systick_new_etm_alarm_event(0, &systick_event)); + + printf("connect event and task to the channel\r\n"); + TEST_ESP_OK(esp_etm_channel_connect(etm_channel_a, systick_event, gpio_task)); + + TEST_ESP_OK(esp_etm_channel_enable(etm_channel_a)); + + // should see a 500Hz square wave on the GPIO (if RTOS systick is set to 1000Hz) + vTaskDelay(pdMS_TO_TICKS(1000)); + + // delete etm primitives + TEST_ESP_OK(gpio_etm_task_rm_gpio(gpio_task, output_gpio)); + TEST_ESP_OK(esp_etm_del_task(gpio_task)); + TEST_ESP_OK(esp_etm_del_event(systick_event)); + TEST_ESP_OK(esp_etm_channel_disable(etm_channel_a)); + TEST_ESP_OK(esp_etm_del_channel(etm_channel_a)); +} diff --git a/components/esp_timer/test_apps/main/CMakeLists.txt b/components/esp_timer/test_apps/main/CMakeLists.txt index 041c23bb57..15fc56ac95 100644 --- a/components/esp_timer/test_apps/main/CMakeLists.txt +++ b/components/esp_timer/test_apps/main/CMakeLists.txt @@ -1,4 +1,14 @@ -idf_component_register(SRC_DIRS "." +set(srcs "test_app_main.c" "test_esp_timer.c" "test_ets_timer.c") + +if(CONFIG_SOC_LIGHT_SLEEP_SUPPORTED) + list(APPEND srcs "test_esp_timer_light_sleep.c") +endif() + +if(CONFIG_SOC_SYSTIMER_SUPPORT_ETM) + list(APPEND srcs "test_esp_timer_etm.c") +endif() + +idf_component_register(SRCS ${srcs} PRIV_INCLUDE_DIRS "../../private_include" - PRIV_REQUIRES cmock test_utils esp_timer spi_flash esp_psram + PRIV_REQUIRES cmock test_utils esp_timer spi_flash esp_psram esp_driver_gpio WHOLE_ARCHIVE) diff --git a/components/esp_hw_support/test_apps/etm/main/test_systimer_etm.c b/components/esp_timer/test_apps/main/test_esp_timer_etm.c similarity index 60% rename from components/esp_hw_support/test_apps/etm/main/test_systimer_etm.c rename to components/esp_timer/test_apps/main/test_esp_timer_etm.c index 23b0cba960..10f8f68bcf 100644 --- a/components/esp_hw_support/test_apps/etm/main/test_systimer_etm.c +++ b/components/esp_timer/test_apps/main/test_esp_timer_etm.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,54 +14,6 @@ #include "driver/gpio_etm.h" #include "driver/gpio.h" #include "esp_timer.h" -#include "esp_systick_etm.h" - -TEST_CASE("rtos_systick_etm_event", "[etm]") -{ - // systimer alarm ---> EMT channel ---> GPIO toggle - const uint32_t output_gpio = 1; - printf("allocate etm channels\r\n"); - esp_etm_channel_config_t etm_config = {}; - esp_etm_channel_handle_t etm_channel_a = NULL; - TEST_ESP_OK(esp_etm_new_channel(&etm_config, &etm_channel_a)); - - printf("allocate GPIO etm task\r\n"); - esp_etm_task_handle_t gpio_task = NULL; - gpio_etm_task_config_t gpio_task_config = { - .action = GPIO_ETM_TASK_ACTION_TOG, - }; - TEST_ESP_OK(gpio_new_etm_task(&gpio_task_config, &gpio_task)); - - // bind GPIO to the task - TEST_ESP_OK(gpio_etm_task_add_gpio(gpio_task, output_gpio)); - - printf("initialize gpio\r\n"); - gpio_config_t task_gpio_config = { - .intr_type = GPIO_INTR_DISABLE, - .mode = GPIO_MODE_OUTPUT, - .pin_bit_mask = 1ULL << output_gpio, - }; - TEST_ESP_OK(gpio_config(&task_gpio_config)); - - printf("acquire systick etm event\r\n"); - esp_etm_event_handle_t systick_event = NULL; - TEST_ESP_OK(esp_systick_new_etm_alarm_event(0, &systick_event)); - - printf("connect event and task to the channel\r\n"); - TEST_ESP_OK(esp_etm_channel_connect(etm_channel_a, systick_event, gpio_task)); - - TEST_ESP_OK(esp_etm_channel_enable(etm_channel_a)); - - // should see a 500Hz square wave on the GPIO (if RTOS systick is set to 1000Hz) - vTaskDelay(pdMS_TO_TICKS(1000)); - - // delete etm primitives - TEST_ESP_OK(gpio_etm_task_rm_gpio(gpio_task, output_gpio)); - TEST_ESP_OK(esp_etm_del_task(gpio_task)); - TEST_ESP_OK(esp_etm_del_event(systick_event)); - TEST_ESP_OK(esp_etm_channel_disable(etm_channel_a)); - TEST_ESP_OK(esp_etm_del_channel(etm_channel_a)); -} static void periodic_timer_callback(void *arg) { diff --git a/components/esp_timer/test_apps/main/test_esp_timer_light_sleep.c b/components/esp_timer/test_apps/main/test_esp_timer_light_sleep.c index b7dd0bc2e8..6aa8ca9a78 100644 --- a/components/esp_timer/test_apps/main/test_esp_timer_light_sleep.c +++ b/components/esp_timer/test_apps/main/test_esp_timer_light_sleep.c @@ -16,8 +16,6 @@ #include "esp_sleep.h" #include "soc/soc_caps.h" -#if SOC_LIGHT_SLEEP_SUPPORTED - static void timer_cb1(void *arg) { ++*((int*) arg); @@ -58,5 +56,3 @@ TEST_CASE("Test the periodic timer does not handle lost events during light slee TEST_ESP_OK(esp_timer_delete(periodic_timer)); vTaskDelay(3); // wait for the esp_timer task to delete all timers } - -#endif // SOC_LIGHT_SLEEP_SUPPORTED diff --git a/components/hal/esp32c5/include/hal/etm_ll.h b/components/hal/esp32c5/include/hal/etm_ll.h new file mode 100644 index 0000000000..6708cd7f17 --- /dev/null +++ b/components/hal/esp32c5/include/hal/etm_ll.h @@ -0,0 +1,117 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/soc_etm_struct.h" +#include "soc/pcr_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable the clock for ETM register + * + * @param group_id Group ID + * @param enable true to enable, false to disable + */ +static inline void etm_ll_enable_bus_clock(int group_id, bool enable) +{ + (void)group_id; + PCR.etm_conf.etm_clk_en = enable; +} + +/** + * @brief Reset the ETM register + * + * @param group_id Group ID + */ +static inline void etm_ll_reset_register(int group_id) +{ + (void)group_id; + PCR.etm_conf.etm_rst_en = 1; + PCR.etm_conf.etm_rst_en = 0; +} + +/** + * @brief Enable ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + */ +static inline void etm_ll_enable_channel(soc_etm_dev_t *hw, uint32_t chan) +{ + if (chan < 32) { + hw->ch_ena_ad0_set.val = 1 << chan; + } else { + hw->ch_ena_ad1_set.val = 1 << (chan - 32); + } +} + +/** + * @brief Disable ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + */ +static inline void etm_ll_disable_channel(soc_etm_dev_t *hw, uint32_t chan) +{ + if (chan < 32) { + hw->ch_ena_ad0_clr.val = 1 << chan; + } else { + hw->ch_ena_ad1_clr.val = 1 << (chan - 32); + } +} + +/** + * @brief Check whether the ETM channel is enabled or not + * + * @param hw ETM register base address + * @param chan Channel ID + * @return true if the channel is enabled, false otherwise + */ +static inline bool etm_ll_is_channel_enabled(soc_etm_dev_t *hw, uint32_t chan) +{ + if (chan < 32) { + return hw->ch_ena_ad0.val & (1 << chan); + } else { + return hw->ch_ena_ad1.val & (1 << (chan - 32)); + } +} + +/** + * @brief Set the input event for the ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + * @param event Event ID + */ +static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, uint32_t event) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].eid, chn_evt_id, event); +} + +/** + * @brief Set the output task for the ETM channel + * + * @param hw ETM register base address + * @param chan Channel ID + * @param task Task ID + */ +static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uint32_t task) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].tid, chn_task_id, task); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/gpio_etm_ll.h b/components/hal/esp32c5/include/hal/gpio_etm_ll.h new file mode 100644 index 0000000000..52a06e7fc3 --- /dev/null +++ b/components/hal/esp32c5/include/hal/gpio_etm_ll.h @@ -0,0 +1,136 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#include +#include "hal/assert.h" +#include "hal/misc.h" +#include "soc/gpio_ext_struct.h" +#include "soc/soc_etm_source.h" + +#define GPIO_LL_ETM_EVENT_ID_POS_EDGE(ch) (GPIO_EVT_CH0_RISE_EDGE + (ch)) +#define GPIO_LL_ETM_EVENT_ID_NEG_EDGE(ch) (GPIO_EVT_CH0_FALL_EDGE + (ch)) +#define GPIO_LL_ETM_EVENT_ID_ANY_EDGE(ch) (GPIO_EVT_CH0_ANY_EDGE + (ch)) + +#define GPIO_LL_ETM_TASK_ID_SET(ch) (GPIO_TASK_CH0_SET + (ch)) +#define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch)) +#define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch)) + +#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP 8 +#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP 8 + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Set which GPIO to be bound to the event channel + * + * @note Different channels can be bound to one GPIO + * + * @param dev Register base address + * @param chan GPIO ETM Event channel number + * @param gpio_num GPIO number + */ +static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint32_t chan, uint32_t gpio_num) +{ + dev->etm_event_chn_cfg[chan].etm_chn_event_sel = gpio_num; +} + +/** + * @brief Whether to enable the event channel + * + * @param dev Register base address + * @param chan GPIO ETM Event channel number + * @param enable True to enable, false to disable + */ +static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_t chan, bool enable) +{ + dev->etm_event_chn_cfg[chan].etm_chn_event_en = enable; +} + +/** + * @brief Get which GPIO is bound to the event channel + * + * @param dev Register base address + * @param chan GPIO ETM Event channel number + * @return GPIO number + */ +static inline uint32_t gpio_ll_etm_event_channel_get_gpio(gpio_etm_dev_t *dev, uint32_t chan) +{ + return dev->etm_event_chn_cfg[chan].etm_chn_event_sel; +} + +/** + * @brief Set which GPIO to be bound to the task channel + * + * @note One channel can be bound to multiple different GPIOs + * + * @param dev Register base address + * @param chan GPIO ETM Task channel number + * @param gpio_num GPIO number + */ +static inline void gpio_ll_etm_gpio_set_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num, uint32_t chan) +{ + int g_p = gpio_num / 5; + int g_idx = gpio_num % 5; + uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val; + reg_val &= ~(0x07 << (g_idx * 6)); + reg_val |= ((chan & 0x07) << (g_idx * 6)); + dev->etm_task_pn_cfg[g_p].val = reg_val; +} + +/** + * @brief Whether to enable the GPIO to be managed by the task channel + * + * @param dev Register base address + * @param gpio_num GPIO number + * @param enable True to enable, false to disable + */ +static inline void gpio_ll_etm_enable_task_gpio(gpio_etm_dev_t *dev, uint32_t gpio_num, bool enable) +{ + int g_p = gpio_num / 5; + int g_idx = gpio_num % 5; + uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val; + reg_val &= ~(0x01 << (g_idx * 6 + 5)); + reg_val |= ((enable & 0x01) << (g_idx * 6 + 5)); + dev->etm_task_pn_cfg[g_p].val = reg_val; +} + +/** + * @brief Check whether a GPIO has been enabled and managed by a task channel + * + * @param dev Register base address + * @param gpio_num GPIO number + * @return True if enabled, false otherwise + */ +static inline bool gpio_ll_etm_is_task_gpio_enabled(gpio_etm_dev_t *dev, uint32_t gpio_num) +{ + int g_p = gpio_num / 5; + int g_idx = gpio_num % 5; + return dev->etm_task_pn_cfg[g_p].val & (0x01 << (g_idx * 6 + 5)); +} + +/** + * @brief Get the channel number that the GPIO is bound to + * + * @param dev Register base address + * @param gpio_num GPIO number + * @return GPIO ETM Task channel number + */ +static inline uint32_t gpio_ll_etm_gpio_get_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num) +{ + int g_p = gpio_num / 5; + int g_idx = gpio_num % 5; + return (dev->etm_task_pn_cfg[g_p].val >> (g_idx * 6)) & 0x07; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/timer_ll.h b/components/hal/esp32c5/include/hal/timer_ll.h index 9915ddbce2..7798f6c7ba 100644 --- a/components/hal/esp32c5/include/hal/timer_ll.h +++ b/components/hal/esp32c5/include/hal/timer_ll.h @@ -25,30 +25,30 @@ extern "C" { #define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1)) #define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id)) -#define TIMER_LL_ETM_TASK_TABLE(group, timer, task) \ - (uint32_t [2][1][GPTIMER_ETM_TASK_MAX]){{{ \ - [GPTIMER_ETM_TASK_START_COUNT] = TIMER0_TASK_CNT_START_TIMER0, \ - [GPTIMER_ETM_TASK_STOP_COUNT] = TIMER0_TASK_CNT_STOP_TIMER0, \ - [GPTIMER_ETM_TASK_EN_ALARM] = TIMER0_TASK_ALARM_START_TIMER0, \ - [GPTIMER_ETM_TASK_RELOAD] = TIMER0_TASK_CNT_RELOAD_TIMER0, \ - [GPTIMER_ETM_TASK_CAPTURE] = TIMER0_TASK_CNT_CAP_TIMER0, \ - }}, \ - {{ \ - [GPTIMER_ETM_TASK_START_COUNT] = TIMER1_TASK_CNT_START_TIMER0, \ - [GPTIMER_ETM_TASK_STOP_COUNT] = TIMER1_TASK_CNT_STOP_TIMER0, \ - [GPTIMER_ETM_TASK_EN_ALARM] = TIMER1_TASK_ALARM_START_TIMER0, \ - [GPTIMER_ETM_TASK_RELOAD] = TIMER1_TASK_CNT_RELOAD_TIMER0, \ - [GPTIMER_ETM_TASK_CAPTURE] = TIMER1_TASK_CNT_CAP_TIMER0, \ - }}, \ +#define TIMER_LL_ETM_TASK_TABLE(group, timer, task) \ + (uint32_t [2][1][GPTIMER_ETM_TASK_MAX]){{{ \ + [GPTIMER_ETM_TASK_START_COUNT] = TG0_TASK_CNT_START_TIMER0, \ + [GPTIMER_ETM_TASK_STOP_COUNT] = TG0_TASK_CNT_STOP_TIMER0, \ + [GPTIMER_ETM_TASK_EN_ALARM] = TG0_TASK_ALARM_START_TIMER0, \ + [GPTIMER_ETM_TASK_RELOAD] = TG0_TASK_CNT_RELOAD_TIMER0, \ + [GPTIMER_ETM_TASK_CAPTURE] = TG0_TASK_CNT_CAP_TIMER0, \ + }}, \ + {{ \ + [GPTIMER_ETM_TASK_START_COUNT] = TG1_TASK_CNT_START_TIMER0, \ + [GPTIMER_ETM_TASK_STOP_COUNT] = TG1_TASK_CNT_STOP_TIMER0, \ + [GPTIMER_ETM_TASK_EN_ALARM] = TG1_TASK_ALARM_START_TIMER0, \ + [GPTIMER_ETM_TASK_RELOAD] = TG1_TASK_CNT_RELOAD_TIMER0, \ + [GPTIMER_ETM_TASK_CAPTURE] = TG1_TASK_CNT_CAP_TIMER0, \ + }}, \ }[group][timer][task] -#define TIMER_LL_ETM_EVENT_TABLE(group, timer, event) \ - (uint32_t [2][1][GPTIMER_ETM_EVENT_MAX]){{{ \ - [GPTIMER_ETM_EVENT_ALARM_MATCH] = TIMER0_EVT_CNT_CMP_TIMER0, \ - }}, \ - {{ \ - [GPTIMER_ETM_EVENT_ALARM_MATCH] = TIMER1_EVT_CNT_CMP_TIMER0, \ - }}, \ +#define TIMER_LL_ETM_EVENT_TABLE(group, timer, event) \ + (uint32_t [2][1][GPTIMER_ETM_EVENT_MAX]){{{ \ + [GPTIMER_ETM_EVENT_ALARM_MATCH] = TG0_EVT_CNT_CMP_TIMER0, \ + }}, \ + {{ \ + [GPTIMER_ETM_EVENT_ALARM_MATCH] = TG1_EVT_CNT_CMP_TIMER0, \ + }}, \ }[group][timer][event] /** diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index b59bbf060f..9563ff9a9b 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -27,6 +27,10 @@ config SOC_MCPWM_SUPPORTED bool default y +config SOC_ETM_SUPPORTED + bool + default y + config SOC_PARLIO_SUPPORTED bool default y @@ -295,6 +299,18 @@ config SOC_GDMA_PAIRS_PER_GROUP_MAX int default 3 +config SOC_GDMA_SUPPORT_ETM + bool + default y + +config SOC_ETM_GROUPS + int + default 1 + +config SOC_ETM_CHANNELS_PER_GROUP + int + default 50 + config SOC_GPIO_PORT int default 1 @@ -307,6 +323,10 @@ config SOC_GPIO_SUPPORT_PIN_HYS_FILTER bool default y +config SOC_GPIO_SUPPORT_ETM + bool + default y + config SOC_GPIO_SUPPORT_RTC_INDEPENDENT bool default y @@ -635,6 +655,10 @@ config SOC_MCPWM_SWSYNC_CAN_PROPAGATE bool default y +config SOC_MCPWM_SUPPORT_ETM + bool + default y + config SOC_MCPWM_SUPPORT_EVENT_COMPARATOR bool default y @@ -831,6 +855,10 @@ config SOC_SYSTIMER_ALARM_MISS_COMPENSATE bool default y +config SOC_SYSTIMER_SUPPORT_ETM + bool + default y + config SOC_LP_TIMER_BIT_WIDTH_LO int default 32 @@ -855,10 +883,18 @@ config SOC_TIMER_GROUP_SUPPORT_XTAL bool default y +config SOC_TIMER_GROUP_SUPPORT_RC_FAST + bool + default y + config SOC_TIMER_GROUP_TOTAL_TIMERS int default 2 +config SOC_TIMER_SUPPORT_ETM + bool + default y + config SOC_EFUSE_ECDSA_KEY bool default y diff --git a/components/soc/esp32c5/include/soc/gpio_ext_struct.h b/components/soc/esp32c5/include/soc/gpio_ext_struct.h index d8004b7325..56aa2ecdd9 100644 --- a/components/soc/esp32c5/include/soc/gpio_ext_struct.h +++ b/components/soc/esp32c5/include/soc/gpio_ext_struct.h @@ -192,20 +192,20 @@ typedef union { * 28: Select GPIO28\\ * 29 ~ 63: Reserved\\ */ - uint32_t etm_ch0_event_sel:6; + uint32_t etm_chn_event_sel:6; uint32_t reserved_6:1; /** etm_ch0_event_en : R/W; bitpos: [7]; default: 0; * Configures whether or not to enable ETM event send.\\ * 0: Not enable\\ * 1: Enable\\ */ - uint32_t etm_ch0_event_en:1; + uint32_t etm_chn_event_en:1; uint32_t reserved_8:24; }; uint32_t val; } gpio_ext_etm_event_chn_cfg_reg_t; -/** Type of etm_task_p0_cfg register +/** Type of etm_task_pn_cfg register * GPIO selection register 0 for ETM */ typedef union { @@ -333,633 +333,8 @@ typedef union { uint32_t reserved_30:2; }; uint32_t val; -} gpio_ext_etm_task_p0_cfg_reg_t; +} gpio_ext_etm_task_pn_cfg_reg_t; -/** Type of etm_task_p1_cfg register - * GPIO selection register 1 for ETM - */ -typedef union { - struct { - /** etm_task_gpio5_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio5_sel:3; - uint32_t reserved_3:2; - /** etm_task_gpio5_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio5_en:1; - /** etm_task_gpio6_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio6_sel:3; - uint32_t reserved_9:2; - /** etm_task_gpio6_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio6_en:1; - /** etm_task_gpio7_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio7_sel:3; - uint32_t reserved_15:2; - /** etm_task_gpio7_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio7_en:1; - /** etm_task_gpio8_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio8_sel:3; - uint32_t reserved_21:2; - /** etm_task_gpio8_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio8_en:1; - /** etm_task_gpio9_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio9_sel:3; - uint32_t reserved_27:2; - /** etm_task_gpio9_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio9_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p1_cfg_reg_t; - -/** Type of etm_task_p2_cfg register - * GPIO selection register 2 for ETM - */ -typedef union { - struct { - /** etm_task_gpio10_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio10_sel:3; - uint32_t reserved_3:2; - /** etm_task_gpio10_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio10_en:1; - /** etm_task_gpio11_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio11_sel:3; - uint32_t reserved_9:2; - /** etm_task_gpio11_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio11_en:1; - /** etm_task_gpio12_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio12_sel:3; - uint32_t reserved_15:2; - /** etm_task_gpio12_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio12_en:1; - /** etm_task_gpio13_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio13_sel:3; - uint32_t reserved_21:2; - /** etm_task_gpio13_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio13_en:1; - /** etm_task_gpio14_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio14_sel:3; - uint32_t reserved_27:2; - /** etm_task_gpio14_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio14_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p2_cfg_reg_t; - -/** Type of etm_task_p3_cfg register - * GPIO selection register 3 for ETM - */ -typedef union { - struct { - /** etm_task_gpio15_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio15_sel:3; - uint32_t reserved_3:2; - /** etm_task_gpio15_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio15_en:1; - /** etm_task_gpio16_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio16_sel:3; - uint32_t reserved_9:2; - /** etm_task_gpio16_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio16_en:1; - /** etm_task_gpio17_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio17_sel:3; - uint32_t reserved_15:2; - /** etm_task_gpio17_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio17_en:1; - /** etm_task_gpio18_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio18_sel:3; - uint32_t reserved_21:2; - /** etm_task_gpio18_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio18_en:1; - /** etm_task_gpio19_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio19_sel:3; - uint32_t reserved_27:2; - /** etm_task_gpio19_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio19_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p3_cfg_reg_t; - -/** Type of etm_task_p4_cfg register - * GPIO selection register 4 for ETM - */ -typedef union { - struct { - /** etm_task_gpio20_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio20_sel:3; - uint32_t reserved_3:2; - /** etm_task_gpio20_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio20_en:1; - /** etm_task_gpio21_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio21_sel:3; - uint32_t reserved_9:2; - /** etm_task_gpio21_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio21_en:1; - /** etm_task_gpio22_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio22_sel:3; - uint32_t reserved_15:2; - /** etm_task_gpio22_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio22_en:1; - /** etm_task_gpio23_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio23_sel:3; - uint32_t reserved_21:2; - /** etm_task_gpio23_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio23_en:1; - /** etm_task_gpio24_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio24_sel:3; - uint32_t reserved_27:2; - /** etm_task_gpio24_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio24_en:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} gpio_ext_etm_task_p4_cfg_reg_t; - -/** Type of etm_task_p5_cfg register - * GPIO selection register 5 for ETM - */ -typedef union { - struct { - /** etm_task_gpio25_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio25_sel:3; - uint32_t reserved_3:2; - /** etm_task_gpio25_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio25_en:1; - /** etm_task_gpio26_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio26_sel:3; - uint32_t reserved_9:2; - /** etm_task_gpio26_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio26_en:1; - /** etm_task_gpio27_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio27_sel:3; - uint32_t reserved_15:2; - /** etm_task_gpio27_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio27_en:1; - /** etm_task_gpio28_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO$n.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}- - * [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}- - * [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a - * etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item - * [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task. - * %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO - * choose a etm task channel. - */ - uint32_t etm_task_gpio28_sel:3; - uint32_t reserved_21:2; - /** etm_task_gpio28_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO$n to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ - */ - uint32_t etm_task_gpio28_en:1; - uint32_t reserved_24:8; - }; - uint32_t val; -} gpio_ext_etm_task_p5_cfg_reg_t; /** Group: Interrupt Registers */ @@ -1073,6 +448,12 @@ typedef struct gpio_sd_dev_t { volatile gpio_ext_sigmadeltan_reg_t channel[4]; } gpio_sd_dev_t; +typedef struct gpio_etm_dev_t { + volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8]; + uint32_t reserved_080[8]; + volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[6]; +} gpio_etm_dev_t; + typedef struct { volatile gpio_sd_dev_t sigma_delta; uint32_t reserved_018[16]; @@ -1081,14 +462,7 @@ typedef struct { uint32_t reserved_060[30]; volatile gpio_ext_glitch_filter_chn_reg_t glitch_filter_chn[8]; uint32_t reserved_0f8[8]; - volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8]; - uint32_t reserved_138[8]; - volatile gpio_ext_etm_task_p0_cfg_reg_t etm_task_p0_cfg; - volatile gpio_ext_etm_task_p1_cfg_reg_t etm_task_p1_cfg; - volatile gpio_ext_etm_task_p2_cfg_reg_t etm_task_p2_cfg; - volatile gpio_ext_etm_task_p3_cfg_reg_t etm_task_p3_cfg; - volatile gpio_ext_etm_task_p4_cfg_reg_t etm_task_p4_cfg; - volatile gpio_ext_etm_task_p5_cfg_reg_t etm_task_p5_cfg; + volatile gpio_etm_dev_t etm; uint32_t reserved_170[24]; volatile gpio_ext_int_raw_reg_t int_raw; volatile gpio_ext_int_st_reg_t int_st; @@ -1100,6 +474,7 @@ typedef struct { } gpio_ext_dev_t; extern gpio_sd_dev_t SDM; +extern gpio_etm_dev_t GPIO_ETM; extern gpio_ext_dev_t GPIO_EXT; #ifndef __cplusplus diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index 751341a7e8..d64a2d6613 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -26,7 +26,7 @@ #define SOC_PCNT_SUPPORTED 1 #define SOC_MCPWM_SUPPORTED 1 // #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8691 -// #define SOC_ETM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8693 +#define SOC_ETM_SUPPORTED 1 #define SOC_PARLIO_SUPPORTED 1 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 @@ -177,12 +177,12 @@ #define SOC_AHB_GDMA_VERSION 2 #define SOC_GDMA_NUM_GROUPS_MAX 1U #define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 -// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule TODO: IDF-9224 +#define SOC_GDMA_SUPPORT_ETM 1 // #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 // TODO: IDF-9225 /*-------------------------- ETM CAPS --------------------------------------*/ -// #define SOC_ETM_GROUPS 1U // Number of ETM groups -// #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group +#define SOC_ETM_GROUPS 1U // Number of ETM groups +#define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-C5 has 1 GPIO peripheral @@ -193,7 +193,7 @@ #define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1 // GPIO peripheral has the ETM extension -// #define SOC_GPIO_SUPPORT_ETM 1 +#define SOC_GPIO_SUPPORT_ETM 1 // Target has the full LP IO subsystem // On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. @@ -338,7 +338,7 @@ #define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER 3 ///< The number of capture channels that each capture timer has #define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP 3 ///< The number of GPIO synchros that each group has #define SOC_MCPWM_SWSYNC_CAN_PROPAGATE 1 ///< Software sync event can be routed to its output -// #define SOC_MCPWM_SUPPORT_ETM 1 ///< Support ETM (Event Task Matrix) +#define SOC_MCPWM_SUPPORT_ETM 1 ///< Support ETM (Event Task Matrix) #define SOC_MCPWM_SUPPORT_EVENT_COMPARATOR 1 ///< Support event comparator (based on ETM) #define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP 1 ///< Capture timer shares clock with other PWM timers @@ -438,7 +438,7 @@ #define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source #define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt #define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) -// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event +#define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event /*-------------------------- LP_TIMER CAPS ----------------------------------*/ #define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part @@ -449,9 +449,9 @@ #define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U) #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) #define SOC_TIMER_GROUP_SUPPORT_XTAL (1) -// #define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1) +#define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1) #define SOC_TIMER_GROUP_TOTAL_TIMERS (2) -// #define SOC_TIMER_SUPPORT_ETM (1) +#define SOC_TIMER_SUPPORT_ETM (1) // #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1) /*--------------------------- WATCHDOG CAPS ---------------------------------------*/ diff --git a/components/soc/esp32c5/include/soc/soc_etm_struct.h b/components/soc/esp32c5/include/soc/soc_etm_struct.h index e3d65f06c1..01ece71a0a 100644 --- a/components/soc/esp32c5/include/soc/soc_etm_struct.h +++ b/components/soc/esp32c5/include/soc/soc_etm_struct.h @@ -3602,113 +3602,17 @@ typedef union { } soc_etm_date_reg_t; -typedef struct { +typedef struct soc_etm_dev_t { volatile soc_etm_ch_ena_ad0_reg_t ch_ena_ad0; volatile soc_etm_ch_ena_ad0_set_reg_t ch_ena_ad0_set; volatile soc_etm_ch_ena_ad0_clr_reg_t ch_ena_ad0_clr; volatile soc_etm_ch_ena_ad1_reg_t ch_ena_ad1; volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set; volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr; - volatile soc_etm_chn_evt_id_reg_t ch0_evt_id; - volatile soc_etm_chn_task_id_reg_t ch0_task_id; - volatile soc_etm_chn_evt_id_reg_t ch1_evt_id; - volatile soc_etm_chn_task_id_reg_t ch1_task_id; - volatile soc_etm_chn_evt_id_reg_t ch2_evt_id; - volatile soc_etm_chn_task_id_reg_t ch2_task_id; - volatile soc_etm_chn_evt_id_reg_t ch3_evt_id; - volatile soc_etm_chn_task_id_reg_t ch3_task_id; - volatile soc_etm_chn_evt_id_reg_t ch4_evt_id; - volatile soc_etm_chn_task_id_reg_t ch4_task_id; - volatile soc_etm_chn_evt_id_reg_t ch5_evt_id; - volatile soc_etm_chn_task_id_reg_t ch5_task_id; - volatile soc_etm_chn_evt_id_reg_t ch6_evt_id; - volatile soc_etm_chn_task_id_reg_t ch6_task_id; - volatile soc_etm_chn_evt_id_reg_t ch7_evt_id; - volatile soc_etm_chn_task_id_reg_t ch7_task_id; - volatile soc_etm_chn_evt_id_reg_t ch8_evt_id; - volatile soc_etm_chn_task_id_reg_t ch8_task_id; - volatile soc_etm_chn_evt_id_reg_t ch9_evt_id; - volatile soc_etm_chn_task_id_reg_t ch9_task_id; - volatile soc_etm_chn_evt_id_reg_t ch10_evt_id; - volatile soc_etm_chn_task_id_reg_t ch10_task_id; - volatile soc_etm_chn_evt_id_reg_t ch11_evt_id; - volatile soc_etm_chn_task_id_reg_t ch11_task_id; - volatile soc_etm_chn_evt_id_reg_t ch12_evt_id; - volatile soc_etm_chn_task_id_reg_t ch12_task_id; - volatile soc_etm_chn_evt_id_reg_t ch13_evt_id; - volatile soc_etm_chn_task_id_reg_t ch13_task_id; - volatile soc_etm_chn_evt_id_reg_t ch14_evt_id; - volatile soc_etm_chn_task_id_reg_t ch14_task_id; - volatile soc_etm_chn_evt_id_reg_t ch15_evt_id; - volatile soc_etm_chn_task_id_reg_t ch15_task_id; - volatile soc_etm_chn_evt_id_reg_t ch16_evt_id; - volatile soc_etm_chn_task_id_reg_t ch16_task_id; - volatile soc_etm_chn_evt_id_reg_t ch17_evt_id; - volatile soc_etm_chn_task_id_reg_t ch17_task_id; - volatile soc_etm_chn_evt_id_reg_t ch18_evt_id; - volatile soc_etm_chn_task_id_reg_t ch18_task_id; - volatile soc_etm_chn_evt_id_reg_t ch19_evt_id; - volatile soc_etm_chn_task_id_reg_t ch19_task_id; - volatile soc_etm_chn_evt_id_reg_t ch20_evt_id; - volatile soc_etm_chn_task_id_reg_t ch20_task_id; - volatile soc_etm_chn_evt_id_reg_t ch21_evt_id; - volatile soc_etm_chn_task_id_reg_t ch21_task_id; - volatile soc_etm_chn_evt_id_reg_t ch22_evt_id; - volatile soc_etm_chn_task_id_reg_t ch22_task_id; - volatile soc_etm_chn_evt_id_reg_t ch23_evt_id; - volatile soc_etm_chn_task_id_reg_t ch23_task_id; - volatile soc_etm_chn_evt_id_reg_t ch24_evt_id; - volatile soc_etm_chn_task_id_reg_t ch24_task_id; - volatile soc_etm_chn_evt_id_reg_t ch25_evt_id; - volatile soc_etm_chn_task_id_reg_t ch25_task_id; - volatile soc_etm_chn_evt_id_reg_t ch26_evt_id; - volatile soc_etm_chn_task_id_reg_t ch26_task_id; - volatile soc_etm_chn_evt_id_reg_t ch27_evt_id; - volatile soc_etm_chn_task_id_reg_t ch27_task_id; - volatile soc_etm_chn_evt_id_reg_t ch28_evt_id; - volatile soc_etm_chn_task_id_reg_t ch28_task_id; - volatile soc_etm_chn_evt_id_reg_t ch29_evt_id; - volatile soc_etm_chn_task_id_reg_t ch29_task_id; - volatile soc_etm_chn_evt_id_reg_t ch30_evt_id; - volatile soc_etm_chn_task_id_reg_t ch30_task_id; - volatile soc_etm_chn_evt_id_reg_t ch31_evt_id; - volatile soc_etm_chn_task_id_reg_t ch31_task_id; - volatile soc_etm_chn_evt_id_reg_t ch32_evt_id; - volatile soc_etm_chn_task_id_reg_t ch32_task_id; - volatile soc_etm_chn_evt_id_reg_t ch33_evt_id; - volatile soc_etm_chn_task_id_reg_t ch33_task_id; - volatile soc_etm_chn_evt_id_reg_t ch34_evt_id; - volatile soc_etm_chn_task_id_reg_t ch34_task_id; - volatile soc_etm_chn_evt_id_reg_t ch35_evt_id; - volatile soc_etm_chn_task_id_reg_t ch35_task_id; - volatile soc_etm_chn_evt_id_reg_t ch36_evt_id; - volatile soc_etm_chn_task_id_reg_t ch36_task_id; - volatile soc_etm_chn_evt_id_reg_t ch37_evt_id; - volatile soc_etm_chn_task_id_reg_t ch37_task_id; - volatile soc_etm_chn_evt_id_reg_t ch38_evt_id; - volatile soc_etm_chn_task_id_reg_t ch38_task_id; - volatile soc_etm_chn_evt_id_reg_t ch39_evt_id; - volatile soc_etm_chn_task_id_reg_t ch39_task_id; - volatile soc_etm_chn_evt_id_reg_t ch40_evt_id; - volatile soc_etm_chn_task_id_reg_t ch40_task_id; - volatile soc_etm_chn_evt_id_reg_t ch41_evt_id; - volatile soc_etm_chn_task_id_reg_t ch41_task_id; - volatile soc_etm_chn_evt_id_reg_t ch42_evt_id; - volatile soc_etm_chn_task_id_reg_t ch42_task_id; - volatile soc_etm_chn_evt_id_reg_t ch43_evt_id; - volatile soc_etm_chn_task_id_reg_t ch43_task_id; - volatile soc_etm_chn_evt_id_reg_t ch44_evt_id; - volatile soc_etm_chn_task_id_reg_t ch44_task_id; - volatile soc_etm_chn_evt_id_reg_t ch45_evt_id; - volatile soc_etm_chn_task_id_reg_t ch45_task_id; - volatile soc_etm_chn_evt_id_reg_t ch46_evt_id; - volatile soc_etm_chn_task_id_reg_t ch46_task_id; - volatile soc_etm_chn_evt_id_reg_t ch47_evt_id; - volatile soc_etm_chn_task_id_reg_t ch47_task_id; - volatile soc_etm_chn_evt_id_reg_t ch48_evt_id; - volatile soc_etm_chn_task_id_reg_t ch48_task_id; - volatile soc_etm_chn_evt_id_reg_t ch49_evt_id; - volatile soc_etm_chn_task_id_reg_t ch49_task_id; + volatile struct { + soc_etm_chn_evt_id_reg_t eid; + soc_etm_chn_task_id_reg_t tid; + } channel[50]; volatile soc_etm_evt_st0_reg_t evt_st0; volatile soc_etm_evt_st0_clr_reg_t evt_st0_clr; volatile soc_etm_evt_st1_reg_t evt_st1; diff --git a/components/soc/esp32c5/ld/esp32c5.peripherals.ld b/components/soc/esp32c5/ld/esp32c5.peripherals.ld index 7d78fd392a..31097118a3 100644 --- a/components/soc/esp32c5/ld/esp32c5.peripherals.ld +++ b/components/soc/esp32c5/ld/esp32c5.peripherals.ld @@ -44,6 +44,7 @@ PROVIDE ( IO_MUX = 0x60090000 ); PROVIDE ( GPIO = 0x60091000 ); PROVIDE ( GPIO_EXT = 0x60091e00 ); PROVIDE ( SDM = 0x60091e00 ); +PROVIDE ( GPIO_ETM = 0x60091f18 ); PROVIDE ( MEM_MONITOR = 0x60092000 ); PROVIDE ( PAU = 0x60093000 ); PROVIDE ( HP_SYSTEM = 0x60095000 ); diff --git a/docs/docs_not_updated/esp32c5.txt b/docs/docs_not_updated/esp32c5.txt index 10d49479d1..132596763e 100644 --- a/docs/docs_not_updated/esp32c5.txt +++ b/docs/docs_not_updated/esp32c5.txt @@ -90,7 +90,6 @@ api-reference/peripherals/usb_host/usb_host_notes_ext_hub.rst api-reference/peripherals/usb_device.rst api-reference/peripherals/sdspi_host.rst api-reference/peripherals/spi_slave.rst -api-reference/peripherals/etm.rst api-reference/peripherals/gptimer.rst api-reference/peripherals/touch_element.rst api-reference/peripherals/lcd.rst diff --git a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md index 474d93d775..26ed2f38b7 100644 --- a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md +++ b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C6 | ESP32-H2 | ESP32-P4 | -| ----------------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | +| ----------------- | -------- | -------- | -------- | -------- | # HC-SR04 Example based on GPTimer Capture and ETM diff --git a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/pytest_gptimer_capture_example.py b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/pytest_gptimer_capture_example.py index 809c04f336..0c668e45bb 100644 --- a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/pytest_gptimer_capture_example.py +++ b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/pytest_gptimer_capture_example.py @@ -1,10 +1,10 @@ # SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: CC0-1.0 - import pytest from pytest_embedded import Dut +@pytest.mark.esp32c5 @pytest.mark.esp32c6 @pytest.mark.esp32h2 @pytest.mark.esp32p4