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fix(heap): fix memory caps defination in memory_layout

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fix the issue on esp32c3 where retention memory was exhausted
prematurely and preventing the CPU from powering down because
all of the last level of RAM is retention dma accessible on
esp32c3.
This commit is contained in:
wuzhenghui 2023-09-21 10:27:04 +08:00
parent 6b1f40b9bf
commit 2302bc4862
1 changed files with 26 additions and 18 deletions
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36
components/heap/port/esp32c3/memory_layout.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -28,32 +28,40 @@
/* Index of memory in `soc_memory_types[]` */
enum {
SOC_MEMORY_TYPE_DRAM = 0,
SOC_MEMORY_TYPE_STACK_DRAM = 1,
SOC_MEMORY_TYPE_DIRAM = 2,
SOC_MEMORY_TYPE_STACK_DIRAM = 3,
SOC_MEMORY_TYPE_RTCRAM = 4,
SOC_MEMORY_TYPE_DRAM_RETENTION = 1,
SOC_MEMORY_TYPE_DRAM_RETENTION_STACK = 2,
SOC_MEMORY_TYPE_DIRAM = 3,
SOC_MEMORY_TYPE_DIRAM_RETENTION = 4,
SOC_MEMORY_TYPE_DIRAM_RETENTION_STACK = 5,
SOC_MEMORY_TYPE_RTCRAM = 6,
SOC_MEMORY_TYPE_NUM,
};
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
// Type 0: DRAM
[SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
// Type 1: DRAM used for startup stacks
[SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
// Type 2: DRAM which has an alias on the I-port
// Type 1: DRAM and Retention DMA accessible
[SOC_MEMORY_TYPE_DRAM_RETENTION] = { "DRAM/RETENTION", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, false},
// Type 2: DRAM used for startup stacks
[SOC_MEMORY_TYPE_DRAM_RETENTION_STACK] = { "DRAM/RETENTION/STACK", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
// Type 3: DRAM which has an alias on the I-port
[SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
// Type 3: DIRAM used for startup stacks
[SOC_MEMORY_TYPE_STACK_DIRAM] = { "STACK/DIRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, true, true},
// Type 4: RTCRAM
// Type 4: DRAM which has an alias on the I-port and Retention DMA accessible
[SOC_MEMORY_TYPE_DIRAM_RETENTION] = { "DIRAM/RETENTION", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, true, false},
// Type 5: DIRAM used for startup stacks
[SOC_MEMORY_TYPE_DIRAM_RETENTION_STACK] = { "DIRAM/RETENTION/STACK", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, true, true},
// Type 6: RTCRAM
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false},
};
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM
#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DRAM
#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_DRAM_RETENTION_STACK
#define SOC_MEMORY_TYPE_RETENTION_DEFAULT SOC_MEMORY_TYPE_DRAM_RETENTION
#else
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM
#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DIRAM
#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_DIRAM_RETENTION_STACK
#define SOC_MEMORY_TYPE_RETENTION_DEFAULT SOC_MEMORY_TYPE_DIRAM_RETENTION
#endif
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
@ -74,7 +82,7 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
const soc_memory_region_t soc_memory_regions[] = {
{ 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1, can be used as trace memory
{ 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level2, can be used as trace memory
{ 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403C0000}, //D/IRAM level3, can be used as trace memory
{ 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_RETENTION_DEFAULT, 0x403C0000}, //D/IRAM level3, can be used as trace memory
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DEFAULT, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area)
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ 0x50000000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory