Merge branch 'bugfix/esp_eth_start_tx_buff_v4.3' into 'release/v4.3'

Fixed ESP32 EMAC driver `insufficient TX buffer size` (v4.3)

See merge request espressif/esp-idf!16665

components/esp_eth/src/esp_eth.c

@@ -262,7 +262,6 @@ esp_err_t esp_eth_start(esp_eth_handle_t hdl)
     esp_eth_driver_t *eth_driver = (esp_eth_driver_t *)hdl;
     ETH_CHECK(eth_driver, "ethernet driver handle can't be null", err, ESP_ERR_INVALID_ARG);
     esp_eth_phy_t *phy = eth_driver->phy;
-    esp_eth_mac_t *mac = eth_driver->mac;
     // check if driver has started
     esp_eth_fsm_t expected_fsm = ESP_ETH_FSM_STOP;
     if (!atomic_compare_exchange_strong(&eth_driver->fsm, &expected_fsm, ESP_ETH_FSM_START)) {
@@ -271,7 +270,6 @@ esp_err_t esp_eth_start(esp_eth_handle_t hdl)
         goto err;
     }
     ETH_CHECK(phy->negotiate(phy) == ESP_OK, "phy negotiation failed", err, ESP_FAIL);
-    ETH_CHECK(mac->start(mac) == ESP_OK, "start mac failed", err, ESP_FAIL);
     ETH_CHECK(esp_event_post(ETH_EVENT, ETHERNET_EVENT_START, &eth_driver, sizeof(esp_eth_driver_t *), 0) == ESP_OK,
               "send ETHERNET_EVENT_START event failed", err, ESP_FAIL);
     ETH_CHECK(phy->get_link(phy) == ESP_OK, "phy get link status failed", err, ESP_FAIL);
@@ -323,6 +321,13 @@ esp_err_t esp_eth_transmit(esp_eth_handle_t hdl, void *buf, size_t length)
 {
     esp_err_t ret = ESP_OK;
     esp_eth_driver_t *eth_driver = (esp_eth_driver_t *)hdl;
+
+    if (atomic_load(&eth_driver->fsm) != ESP_ETH_FSM_START) {
+        ret = ESP_ERR_INVALID_STATE;
+        ESP_LOGD(TAG, "Ethernet is not started");
+        goto err;
+    }
+
     ETH_CHECK(buf, "can't set buf to null", err, ESP_ERR_INVALID_ARG);
     ETH_CHECK(length, "buf length can't be zero", err, ESP_ERR_INVALID_ARG);
     ETH_CHECK(eth_driver, "ethernet driver handle can't be null", err, ESP_ERR_INVALID_ARG);

components/esp_eth/src/esp_eth_mac_esp32.c

@@ -47,7 +47,7 @@ static const char *TAG = "emac_esp32";
     } while (0)
 
 #define PHY_OPERATION_TIMEOUT_US (1000)
-
+#define MAC_STOP_TIMEOUT_US (250)
 #define FLOW_CONTROL_LOW_WATER_MARK (CONFIG_ETH_DMA_RX_BUFFER_NUM / 3)
 #define FLOW_CONTROL_HIGH_WATER_MARK (FLOW_CONTROL_LOW_WATER_MARK * 2)
 
@@ -77,6 +77,8 @@ typedef struct {
 
 static esp_err_t esp_emac_alloc_driver_obj(const eth_mac_config_t *config, emac_esp32_t **emac_out_hdl, void **out_descriptors);
 static void esp_emac_free_driver_obj(emac_esp32_t *emac, void *descriptors);
+static esp_err_t emac_esp32_start(esp_eth_mac_t *mac);
+static esp_err_t emac_esp32_stop(esp_eth_mac_t *mac);
 
 static esp_err_t emac_esp32_set_mediator(esp_eth_mac_t *mac, esp_eth_mediator_t *eth)
 {
@@ -163,11 +165,11 @@ static esp_err_t emac_esp32_set_link(esp_eth_mac_t *mac, eth_link_t link)
     switch (link) {
     case ETH_LINK_UP:
         MAC_CHECK(esp_intr_enable(emac->intr_hdl) == ESP_OK, "enable interrupt failed", err, ESP_FAIL);
-        emac_hal_start(&emac->hal);
+        emac_esp32_start(mac);
         break;
     case ETH_LINK_DOWN:
         MAC_CHECK(esp_intr_disable(emac->intr_hdl) == ESP_OK, "disable interrupt failed", err, ESP_FAIL);
-        emac_hal_stop(&emac->hal);
+        emac_esp32_stop(mac);
         break;
     default:
         MAC_CHECK(false, "unknown link status", err, ESP_ERR_INVALID_ARG);
@@ -388,6 +390,7 @@ static esp_err_t emac_esp32_deinit(esp_eth_mac_t *mac)
 static esp_err_t emac_esp32_start(esp_eth_mac_t *mac)
 {
     emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
+    emac_hal_reset_desc_chain(&emac->hal);
     emac_hal_start(&emac->hal);
     return ESP_OK;
 }
@@ -395,8 +398,16 @@ static esp_err_t emac_esp32_start(esp_eth_mac_t *mac)
 static esp_err_t emac_esp32_stop(esp_eth_mac_t *mac)
 {
     emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
-    emac_hal_stop(&emac->hal);
-    return ESP_OK;
+    esp_err_t ret = ESP_OK;
+    int32_t to = 0;
+    do {
+        if ((ret = emac_hal_stop(&emac->hal)) == ESP_OK) {
+            break;
+        }
+        to += 25;
+        esp_rom_delay_us(25);
+    } while (to < MAC_STOP_TIMEOUT_US);
+    return ret;
 }
 
 static esp_err_t emac_esp32_del(esp_eth_mac_t *mac)

components/hal/esp32/emac_hal.c

@@ -184,6 +184,8 @@ void emac_hal_reset_desc_chain(emac_hal_context_t *hal)
 
     /* init tx chain */
     for (int i = 0; i < CONFIG_ETH_DMA_TX_BUFFER_NUM; i++) {
+        /* Set Own bit of the Tx descriptor Status: CPU */
+        hal->tx_desc[i].TDES0.Own = 0;
         /* Set Second Address Chained bit */
         hal->tx_desc[i].TDES0.SecondAddressChained = 1;
         hal->tx_desc[i].TDES1.TransmitBuffer1Size = CONFIG_ETH_DMA_BUFFER_SIZE;
@@ -427,27 +429,37 @@ void emac_hal_start(emac_hal_context_t *hal)
     hal->dma_regs->dmastatus.val = 0xFFFFFFFF;
 }
 
-void emac_hal_stop(emac_hal_context_t *hal)
+esp_err_t emac_hal_stop(emac_hal_context_t *hal)
 {
     typeof(hal->dma_regs->dmaoperation_mode) opm = hal->dma_regs->dmaoperation_mode;
     typeof(hal->mac_regs->gmacconfig) cfg = hal->mac_regs->gmacconfig;
 
-    /* Flush Transmit FIFO */
-    opm.flush_tx_fifo = 1;
     /* Stop DMA transmission */
     opm.start_stop_transmission_command = 0;
-    /* Stop DMA reception */
-    opm.start_stop_rx = 0;
-    /* Disable receive state machine of the MAC for reception from the MII */
-    cfg.rx = 0;
+    hal->dma_regs->dmaoperation_mode = opm;
+    if (hal->mac_regs->emacdebug.mactfcs != 0x0) {
+        /* Previous transmit in progress */
+        return ESP_ERR_INVALID_STATE;
+    }
     /* Disable transmit state machine of the MAC for transmission on the MII */
     cfg.tx = 0;
-
-    hal->dma_regs->dmaoperation_mode = opm;
     hal->mac_regs->gmacconfig = cfg;
 
+    /* Disable receive state machine of the MAC for reception from the MII */
+    cfg.rx = 0;
+    hal->mac_regs->gmacconfig = cfg;
+    if (hal->mac_regs->emacdebug.mtlrfrcs != 0x0) {
+        /* Previous receive copy in progress */
+        return ESP_ERR_INVALID_STATE;
+    }
+    /* Stop DMA reception */
+    opm.start_stop_rx = 0;
+    hal->dma_regs->dmaoperation_mode = opm;
+
     /* Disable Ethernet MAC and DMA Interrupt */
     hal->dma_regs->dmain_en.val = 0x0;
+
+    return ESP_OK;
 }
 
 uint32_t emac_hal_get_tx_desc_owner(emac_hal_context_t *hal)

components/hal/esp32/include/hal/emac.h

@@ -1,16 +1,8 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 
@@ -381,9 +373,24 @@ uint32_t emac_hal_get_phy_data(emac_hal_context_t *hal);
 
 void emac_hal_set_address(emac_hal_context_t *hal, uint8_t *mac_addr);
 
+
+/**
+ * @brief Starts EMAC Transmission & Reception
+ *
+ * @param hal EMAC HAL context infostructure
+ */
 void emac_hal_start(emac_hal_context_t *hal);
 
-void emac_hal_stop(emac_hal_context_t *hal);
+/**
+ * @brief Stops EMAC Transmission & Reception
+ *
+ * @param hal EMAC HAL context infostructure
+ * @return
+ *     - ESP_OK: succeed
+  *    - ESP_ERR_INVALID_STATE: previous frame transmission/reception is not completed. When this error occurs,
+  *      wait and reapeat the EMAC stop again.
+ */
+esp_err_t emac_hal_stop(emac_hal_context_t *hal);
 
 uint32_t emac_hal_get_tx_desc_owner(emac_hal_context_t *hal);