diff --git a/components/esp32/Kconfig b/components/esp32/Kconfig
index f4fe83f0cd..f1d31fd199 100644
--- a/components/esp32/Kconfig
+++ b/components/esp32/Kconfig
@@ -521,7 +521,8 @@ config INT_WDT
 config INT_WDT_TIMEOUT_MS
     int "Interrupt watchdog timeout (ms)"
     depends on INT_WDT
-    default 300
+    default 300 if !SPIRAM_SUPPORT
+    default 800 if SPIRAM_SUPPORT
     range 10 10000
     help
         The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate.
diff --git a/components/esp32/int_wdt.c b/components/esp32/int_wdt.c
index 8179fca5d8..debd675c41 100644
--- a/components/esp32/int_wdt.c
+++ b/components/esp32/int_wdt.c
@@ -29,7 +29,7 @@
 #include "soc/timer_group_struct.h"
 #include "soc/timer_group_reg.h"
 #include "driver/timer.h"
-
+#include "driver/periph_ctrl.h"
 #include "esp_int_wdt.h"
 
 #if CONFIG_INT_WDT
@@ -71,6 +71,7 @@ static void IRAM_ATTR tick_hook(void) {
 
 
 void esp_int_wdt_init() {
+    periph_module_enable(PERIPH_TIMG1_MODULE);
     TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
     TIMERG1.wdt_config0.sys_reset_length=7;                 //3.2uS
     TIMERG1.wdt_config0.cpu_reset_length=7;                 //3.2uS
diff --git a/components/esp32/task_wdt.c b/components/esp32/task_wdt.c
index dc46e1c9b8..0e0b87c658 100644
--- a/components/esp32/task_wdt.c
+++ b/components/esp32/task_wdt.c
@@ -33,7 +33,7 @@
 #include "soc/timer_group_reg.h"
 #include "esp_log.h"
 #include "driver/timer.h"
-
+#include "driver/periph_ctrl.h"
 #include "esp_task_wdt.h"
 
 //Assertion macro where, if 'cond' is false, will exit the critical section and return 'ret'
@@ -183,6 +183,7 @@ esp_err_t esp_task_wdt_init(uint32_t timeout, bool panic)
         ESP_ERROR_CHECK(esp_intr_alloc(ETS_TG0_WDT_LEVEL_INTR_SOURCE, 0, task_wdt_isr, NULL, &twdt_config->intr_handle))
 
         //Configure hardware timer
+        periph_module_enable(PERIPH_TIMG0_MODULE);
         TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;               //Disable write protection
         TIMERG0.wdt_config0.sys_reset_length=7;                 //3.2uS
         TIMERG0.wdt_config0.cpu_reset_length=7;                 //3.2uS
diff --git a/components/esp32/test/test_int_wdt.c b/components/esp32/test/test_int_wdt.c
index 80a8462ff4..9bfde9cdca 100644
--- a/components/esp32/test/test_int_wdt.c
+++ b/components/esp32/test/test_int_wdt.c
@@ -13,7 +13,7 @@
 
 
 
-TEST_CASE("Int wdt test", "[esp32][ignore]")
+TEST_CASE("Int wdt test", "[esp32][reset=Interrupt wdt timeout on CPU0,SW_CPU_RESET]")
 {
     portENTER_CRITICAL_NESTED();
     while(1);