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remove(c5beta3): remove c5 beta3 system files

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This commit is contained in:
laokaiyao 2024-06-11 15:31:03 +08:00
parent 1d894680a8
commit 21f870ecd5
51 changed files with 31 additions and 3238 deletions
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6
components/bootloader/subproject/main/CMakeLists.txt
View File

@ -1,13 +1,7 @@
idf_component_register(SRCS "bootloader_start.c"
REQUIRES bootloader bootloader_support)
if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
set(target_folder "esp32c5/beta3")
elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
set(target_folder "esp32c5/mp")
else()
set(target_folder "${target}")
endif()
idf_build_get_property(target IDF_TARGET)
set(scripts "ld/${target_folder}/bootloader.ld")

310
components/bootloader/subproject/main/ld/esp32c5/beta3/bootloader.ld
View File

@ -1,310 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/** Simplified memory map for the bootloader.
* Make sure the bootloader can load into main memory without overwriting itself.
*
* TODO: [ESP32C5] IDF-9358 Check this file whether need update for MP ROM
* ESP32-C5 ROM static data usage is as follows:
* - 0x4086b2b8 - 0x4087cbc0: Shared buffers, used in UART/USB/SPI download mode only
* - 0x4087cbc0 - 0x4087ebc0: PRO CPU stack, can be reclaimed as heap after RTOS startup
* - 0x4087ebc0 - 0x40880000: ROM .bss and .data (not easily reclaimable)
*
* The 2nd stage bootloader can take space up to the end of ROM shared
* buffers area (0x4087cbc0).
*/
/* We consider 0x4087cbc0 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
* and work out iram_seg and iram_loader_seg addresses from there, backwards.
*/
/* These lengths can be adjusted, if necessary: */
bootloader_usable_dram_end = 0x4087cbc0;
bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
bootloader_dram_seg_len = 0x5000;
bootloader_iram_loader_seg_len = 0x7000;
bootloader_iram_seg_len = 0x2200;
/* Start of the lower region is determined by region size and the end of the higher region */
bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len;
bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
MEMORY
{
iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
}
/* The app may use RAM for static allocations up to the start of iram_loader_seg.
* If you have changed something above and this assert fails:
* 1. Check what the new value of bootloader_iram_loader_seg start is.
* 2. Update the value in this assert.
* 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32c5/memory.ld.in to the same value.
*/
ASSERT(bootloader_iram_loader_seg_start == 0x4086EBC0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
/* Default entry point: */
ENTRY(call_start_cpu0);
SECTIONS
{
.iram_loader.text :
{
. = ALIGN (16);
_loader_text_start = ABSOLUTE(.);
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
*liblog.a:(.literal .text .literal.* .text.*)
/* we use either libgcc or compiler-rt, so put similar entries for them here */
*libgcc.a:(.literal .text .literal.* .text.*)
*libclang_rt.builtins.a:(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
*libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
*libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
*libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
*libspi_flash.a:*.*(.literal .text .literal.* .text.*)
*libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
*libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
*libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
*libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
*libefuse.a:*.*(.literal .text .literal.* .text.*)
*(.fini.literal)
*(.fini)
*(.gnu.version)
_loader_text_end = ABSOLUTE(.);
} > iram_loader_seg
.iram.text :
{
. = ALIGN (16);
*(.entry.text)
*(.init.literal)
*(.init)
} > iram_seg
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
. = ALIGN (8);
_dram_start = ABSOLUTE(.);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
} > dram_seg
.dram0.bootdesc : ALIGN(0x10)
{
_data_start = ABSOLUTE(.);
*(.data_bootloader_desc .data_bootloader_desc.*) /* Should be the first. Bootloader version info. DO NOT PUT ANYTHING BEFORE IT! */
} > dram_seg
.dram0.data :
{
*(.dram1 .dram1.*) /* catch stray DRAM_ATTR */
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.gnu.linkonce.s2.*)
*(.jcr)
_data_end = ABSOLUTE(.);
} > dram_seg
.dram0.rodata :
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
*(.sdata2 .sdata2.* .srodata .srodata.*)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
*(.eh_frame_hdr)
*(.eh_frame)
. = (. + 3) & ~ 3;
/* C++ constructor and destructor tables, properly ordered: */
__init_array_start = ABSOLUTE(.);
KEEP (*crtbegin.*(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__init_array_end = ABSOLUTE(.);
KEEP (*crtbegin.*(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
_rodata_end = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
_dram_end = ABSOLUTE(.);
} > dram_seg
.iram.text :
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.iram .iram.*) /* catch stray IRAM_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
/** CPU will try to prefetch up to 16 bytes of
* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
* safe access to up to 16 bytes after the last real instruction, add
* dummy bytes to ensure this
*/
. += 16;
_text_end = ABSOLUTE(.);
_etext = .;
} > iram_seg
.riscv.attributes 0: { *(.riscv.attributes) }
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_pubtypes 0 : { *(.debug_pubtypes) }
/* DWARF 3 */
.debug_ranges 0 : { *(.debug_ranges) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* GNU DWARF 2 extensions */
.debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
.debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
/* DWARF 4 */
.debug_types 0 : { *(.debug_types) }
/* DWARF 5 */
.debug_addr 0 : { *(.debug_addr) }
.debug_line_str 0 : { *(.debug_line_str) }
.debug_loclists 0 : { *(.debug_loclists) }
.debug_macro 0 : { *(.debug_macro) }
.debug_names 0 : { *(.debug_names) }
.debug_rnglists 0 : { *(.debug_rnglists) }
.debug_str_offsets 0 : { *(.debug_str_offsets) }
.comment 0 : { *(.comment) }
.note.GNU-stack 0: { *(.note.GNU-stack) }
/**
* Discarding .rela.* sections results in the following mapping:
* .rela.text.* -> .text.*
* .rela.data.* -> .data.*
* And so forth...
*/
/DISCARD/ : { *(.rela.*) }
}
/**
* Appendix: Memory Usage of ROM bootloader
*
* 0x4086b2b8 ------------------> _dram0_0_start
* | |
* | |
* | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h
* | |
* | |
* 0x4087cbc0 ------------------> __stack_sentry
* | |
* | | 2. Startup pro cpu stack (freed when IDF app is running)
* | |
* 0x4087ebc0 ------------------> __stack (pro cpu)
* | |
* | |
* | | 3. Shared memory only used in startup code or nonos/early boot*
* | | (can be freed when IDF runs)
* | |
* | |
* 0x4087fb14 ------------------> _dram0_rtos_reserved_start
* | |
* | |
* | | 4. Shared memory used in startup code and when IDF runs
* | |
* | |
* 0x4087fefc ------------------> _dram0_rtos_reserved_end
* | |
* 0x4087ffb8 ------------------> _data_start_interface
* | |
* | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
* | |
* 0x40880000 ------------------> _data_end_interface
*/

0
components/bootloader/subproject/main/ld/esp32c5/mp/bootloader.ld → components/bootloader/subproject/main/ld/esp32c5/bootloader.ld
View File

0
components/bootloader/subproject/main/ld/esp32c5/beta3/bootloader.rom.ld → components/bootloader/subproject/main/ld/esp32c5/bootloader.rom.ld
View File

6
components/bootloader/subproject/main/ld/esp32c5/mp/bootloader.rom.ld
View File

@ -1,6 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* No definition for ESP32-C5 target */

12
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
View File

@ -14,11 +14,8 @@
#include "esp32c5/rom/efuse.h"
#include "soc/gpio_periph.h"
#include "soc/io_mux_reg.h"
// TODO: IDF-9197
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
#include "esp_rom_efuse.h"
#include "soc/efuse_reg.h"
#endif
#include "soc/spi_reg.h"
#include "soc/spi_mem_reg.h"
#include "soc/soc_caps.h"
@ -207,19 +204,10 @@ static void bootloader_spi_flash_resume(void)
esp_err_t bootloader_init_spi_flash(void)
{
// TODO: IDF-9197
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// On ESP32C5, MSPI source clock's default HS divider leads to 120MHz, which is unusable before calibration
// Therefore, before switching SOC_ROOT_CLK to HS, we need to set MSPI source clock HS divider to make it run at
// 80MHz after the switch. PLL = 480MHz, so divider is 6.
clk_ll_mspi_fast_set_hs_divider(6);
#elif CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
/* TODO: [ESP32C5] IDF-8649 temporary use xtal clock source,
need to change back SPLL(480M) and set divider to 6 to use the 80M MSPI，
and we need to check flash freq before restart as well */
clk_ll_mspi_fast_set_divider(1);
clk_ll_mspi_fast_set_src(MSPI_CLK_SRC_XTAL);
#endif
bootloader_init_flash_configure();
bootloader_spi_flash_resume();

9
components/bootloader_support/include/esp_app_format.h
View File

@ -8,9 +8,6 @@
#include <inttypes.h>
#include "esp_assert.h"
// TODO: IDF-9197
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
@ -28,11 +25,7 @@ typedef enum {
ESP_CHIP_ID_ESP32C6 = 0x000D, /*!< chip ID: ESP32-C6 */
ESP_CHIP_ID_ESP32H2 = 0x0010, /*!< chip ID: ESP32-H2 */
ESP_CHIP_ID_ESP32P4 = 0x0012, /*!< chip ID: ESP32-P4 */
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION // TODO: IDF-9197
ESP_CHIP_ID_ESP32C5 = 0x0011, /*!< chip ID: ESP32-C5 beta3 (MPW)*/
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
ESP_CHIP_ID_ESP32C5 = 0x0017, /*!< chip ID: ESP32-C5 MP */
#endif
ESP_CHIP_ID_ESP32C5 = 0x0017, /*!< chip ID: ESP32-C5 */
ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
} __attribute__((packed)) esp_chip_id_t;

5
components/bootloader_support/src/bootloader_random_esp32c5.c
View File

@ -3,7 +3,6 @@
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "soc/soc.h"
#include "soc/pcr_reg.h"
#include "soc/pmu_reg.h"
@ -12,12 +11,12 @@
void bootloader_random_enable(void)
{
// TODO: [ESP32C5] IDF-8626, IDF-9197
// TODO: [ESP32C5] IDF-8626
ESP_EARLY_LOGW("bootloader_random", "bootloader_random_enable() has not been implemented on C5 yet");
}
void bootloader_random_disable(void)
{
// TODO: [ESP32C5] IDF-8626, IDF-9197
// TODO: [ESP32C5] IDF-8626
ESP_EARLY_LOGW("bootloader_random", "bootloader_random_disable() has not been implemented on C5 yet");
}

4
components/bootloader_support/test_apps/rtc_custom_section/README.md
View File

@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

9
components/esp_hw_support/CMakeLists.txt
View File

@ -153,13 +153,7 @@ if(NOT BOOTLOADER_BUILD)
list(APPEND srcs "esp_clock_output.c")
endif()
if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
list(REMOVE_ITEM srcs
"sleep_gpio.c" # TODO: [ESP32C5] IDF-8638
"port/esp_clk_tree_common.c" # TODO: [ESP32C5] IDF-8638
)
endif()
if(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
if(CONFIG_IDF_TARGET_ESP32C5)
list(REMOVE_ITEM srcs
"sleep_modes.c" # TODO: [ESP32C5] IDF-8638
"sleep_modem.c" # TODO: [ESP32C5] IDF-8638
@ -168,6 +162,7 @@ if(NOT BOOTLOADER_BUILD)
"port/esp_clk_tree_common.c" # TODO: [ESP32C5] IDF-8638
)
endif()
if(CONFIG_IDF_TARGET_ESP32C61) # TODO: [ESP32C61] IDF-9245, IDF-9247, IDF-9248
list(REMOVE_ITEM srcs
"sleep_cpu.c"

8
components/esp_hw_support/include/esp_chip_info.h
View File

@ -27,13 +27,9 @@ typedef enum {
CHIP_ESP32C2 = 12, //!< ESP32-C2
CHIP_ESP32C6 = 13, //!< ESP32-C6
CHIP_ESP32H2 = 16, //!< ESP32-H2
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION // TODO: IDF-9197
CHIP_ESP32C5 = 17, //!< ESP32-C5 beta3 (MPW)
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
CHIP_ESP32C5 = 23, //!< ESP32-C5 MP
#endif
CHIP_ESP32P4 = 18, //!< ESP32-P4
CHIP_ESP32C61= 20, //!< ESP32-C61
CHIP_ESP32C5 = 23, //!< ESP32-C5
CHIP_POSIX_LINUX = 999, //!< The code is running on POSIX/Linux simulator
} esp_chip_model_t;
@ -66,7 +62,7 @@ void esp_chip_info(esp_chip_info_t* out_info);
* @brief Cache lock bug exists or not
*
* @return
* - ture : bug exists
* - true : bug exists
* - false : bug not exists
*/
bool soc_has_cache_lock_bug(void);

12
components/esp_hw_support/port/esp32c5/CMakeLists.txt
View File

@ -1,20 +1,8 @@
if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
set(srcs "rtc_clk_init.c"
"rtc_clk.c"
"rtc_time.c"
"pmu_init.c"
"pmu_sleep.c"
"pmu_param.c"
"chip_info.c"
)
endif()
if(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
set(srcs "rtc_clk_init.c"
"rtc_time.c"
"rtc_clk.c"
"chip_info.c"
)
endif()
if(NOT BOOTLOADER_BUILD)

4
components/esp_hw_support/port/esp32c5/Kconfig.rtc
View File

@ -1,8 +1,6 @@
choice RTC_CLK_SRC
prompt "RTC clock source"
# TODO: IDF-9197
default RTC_CLK_SRC_INT_RC if IDF_TARGET_ESP32C5_MP_VERSION
default RTC_CLK_SRC_INT_RC32K if IDF_TARGET_ESP32C5_BETA3_VERSION
default RTC_CLK_SRC_INT_RC
help
Choose which clock is used as RTC clock source.

4
components/esp_hw_support/port/esp32c5/clock_retention_init.c
View File

@ -12,11 +12,7 @@ static __attribute__((unused)) const char *TAG = "sleep_clock";
esp_err_t sleep_clock_system_retention_init(void *arg)
{
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
#define N_REGS_PCR() (((PCR_SRAM_POWER_CONF_1_REG - DR_REG_PCR_BASE) / 4) + 1)
#elif CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
#define N_REGS_PCR() (((PCR_PWDET_SAR_CLK_CONF_REG - DR_REG_PCR_BASE) / 4) + 1)
#endif
const static sleep_retention_entries_config_t pcr_regs_retention[] = {
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(0), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* pcr */

10
components/esp_hw_support/port/esp32c5/cpu_region_protect.c
View File

@ -5,7 +5,6 @@
*/
#include <stdint.h>
#include "sdkconfig.h"
#include "soc/soc.h"
#include "esp_cpu.h"
#include "esp_fault.h"
@ -24,14 +23,6 @@
#define CONDITIONAL_RWX RWX
#endif
// TODO: IDF-9197
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
void esp_cpu_configure_region_protection(void)
{
// TODO: [ESP32C5] IDF-8833
}
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
static void esp_cpu_configure_invalid_regions(void)
{
const unsigned PMA_NONE = PMA_L | PMA_EN;
@ -220,4 +211,3 @@ void esp_cpu_configure_region_protection(void)
PMP_ENTRY_SET(14, pmpaddr14, PMP_NAPOT | RW);
_Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region");
}
#endif // CONFIG_IDF_TARGET_ESP32C5_MP_VERSION

5
components/esp_hw_support/port/esp32c5/esp_clk_tree.c
View File

@ -38,11 +38,6 @@ uint32_t *freq_value)
case SOC_MOD_CLK_PLL_F240M:
clk_src_freq = CLK_LL_PLL_240M_FREQ_MHZ * MHZ;
break;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case SOC_MOD_CLK_RTC_FAST:
clk_src_freq = 20 * MHZ;
break;
#endif
case SOC_MOD_CLK_SPLL:
clk_src_freq = CLK_LL_PLL_480M_FREQ_MHZ * MHZ;
break;

2
components/esp_hw_support/port/esp32c5/include/soc/rtc.h
View File

@ -135,9 +135,7 @@ typedef enum {
RTC_CAL_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K, //!< Internal 32kHz RC oscillator, as one type of 32k clock
RTC_CAL_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32kHz XTAL, as one type of 32k clock
RTC_CAL_32K_OSC_SLOW = SOC_RTC_SLOW_CLK_SRC_OSC_SLOW, //!< External slow clock signal input by lp_pad_gpio0, as one type of 32k clock
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
RTC_CAL_RC_FAST //!< Internal 20MHz RC oscillator
#endif
} rtc_cal_sel_t;
/**

4
components/esp_hw_support/port/esp32c5/pmu_param.c
View File

@ -367,11 +367,7 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
# define PMU_SLOW_CLK_USE_EXT_XTAL (0)
#endif
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
#define PMU_LP_DEFAULT_XPD_RC32K (1)
#else
#define PMU_LP_DEFAULT_XPD_RC32K (0)
#endif
#define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \
.dig_power = { \

139
components/esp_hw_support/port/esp32c5/rtc_clk.c
View File

@ -9,7 +9,6 @@
#include <stddef.h>
#include <assert.h>
#include <stdlib.h>
#include "sdkconfig.h"
#include "esp32c5/rom/rtc.h"
#include "soc/rtc.h"
#include "soc/soc_caps.h"
@ -117,9 +116,7 @@ soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void)
uint32_t rtc_clk_slow_freq_get_hz(void)
{
switch (rtc_clk_slow_src_get()) {
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: return SOC_CLK_RC_SLOW_FREQ_APPROX;
#endif
case SOC_RTC_SLOW_CLK_SRC_XTAL32K: return SOC_CLK_XTAL32K_FREQ_APPROX;
case SOC_RTC_SLOW_CLK_SRC_RC32K: return SOC_CLK_RC32K_FREQ_APPROX;
case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: return SOC_CLK_OSC_SLOW_FREQ_APPROX;
@ -175,9 +172,6 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
clk_ll_bbpll_set_config(pll_freq, xtal_freq);
/* WAIT CALIBRATION DONE */
while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
esp_rom_delay_us(10); // wait for true stop // TODO: check this
#endif
/* BBPLL CALIBRATION STOP */
regi2c_ctrl_ll_bbpll_calibration_stop();
rtc_clk_enable_i2c_ana_master_clock(false);
@ -191,39 +185,17 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
*/
static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
/* Configure clk mspi fast to XTAL*/
clk_ll_mspi_fast_set_src(MSPI_CLK_SRC_XTAL);
clk_ll_mspi_fast_set_divider(1);
clk_ll_cpu_set_divider(div);
clk_ll_ahb_set_divider(div);
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
clk_ll_bus_update();
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
clk_ll_ahb_set_ls_divider(div);
clk_ll_cpu_set_ls_divider(div);
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
#endif
esp_rom_set_cpu_ticks_per_us(cpu_freq);
}
static void rtc_clk_cpu_freq_to_8m(void)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
/* Configure clk mspi fast to XTAL*/
clk_ll_mspi_fast_set_src(MSPI_CLK_SRC_XTAL);
clk_ll_mspi_fast_set_divider(1);
clk_ll_cpu_set_divider(1);
clk_ll_ahb_set_divider(1);
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
clk_ll_bus_update();
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
clk_ll_ahb_set_ls_divider(1);
clk_ll_cpu_set_ls_divider(1);
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
#endif
esp_rom_set_cpu_ticks_per_us(20);
}
@ -234,24 +206,9 @@ static void rtc_clk_cpu_freq_to_8m(void)
*/
static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
rtc_cpu_freq_config_t cfg;
rtc_clk_cpu_freq_mhz_to_config(cpu_freq_mhz, &cfg);
// Set AHB always be 40MHz
clk_ll_ahb_set_divider(cfg.source_freq_mhz / 40);
clk_ll_cpu_set_divider(cfg.div);
clk_ll_cpu_set_src(cfg.source);
clk_ll_bus_update();
esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
/* Configure clk mspi fast to 80m*/
clk_ll_mspi_fast_set_divider(6);
clk_ll_mspi_fast_set_src(MSPI_CLK_SRC_SPLL);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
clk_ll_cpu_set_hs_divider(CLK_LL_PLL_480M_FREQ_MHZ / cpu_freq_mhz);
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
#endif
}
bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config)
@ -262,16 +219,6 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
uint32_t real_freq_mhz;
uint32_t xtal_freq = (uint32_t)rtc_clk_xtal_freq_get();
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION && (CONFIG_XTAL_FREQ == 48)
// To maintain APB_MAX (40MHz) while lowering CPU frequency when using a 48MHz XTAL, have to let CPU frequnecy be
// 40MHz with PLL_F160M or PLL_F240M clock source. This is a special case, has to handle separately.
if (freq_mhz == 40) {
real_freq_mhz = freq_mhz;
source = SOC_CPU_CLK_SRC_PLL_F160M;
source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ;
divider = CLK_LL_PLL_160M_FREQ_MHZ / freq_mhz;
} else
#endif
if (freq_mhz <= xtal_freq && freq_mhz != 0) {
divider = xtal_freq / freq_mhz;
real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */
@ -282,18 +229,6 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
source_freq_mhz = xtal_freq;
source = SOC_CPU_CLK_SRC_XTAL;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
} else if (freq_mhz == 240) {
real_freq_mhz = freq_mhz;
source = SOC_CPU_CLK_SRC_PLL_F240M;
source_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ;
divider = CLK_LL_PLL_240M_FREQ_MHZ / freq_mhz;
} else if (freq_mhz == 160 || freq_mhz == 80) { // TODO: 80MHz can be get from PLL_F240M or PLL_F160M, which is better?
real_freq_mhz = freq_mhz;
source = SOC_CPU_CLK_SRC_PLL_F160M;
source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ;
divider = CLK_LL_PLL_160M_FREQ_MHZ / freq_mhz;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
} else if (freq_mhz == 80) {
real_freq_mhz = freq_mhz;
source = SOC_CPU_CLK_SRC_PLL;
@ -309,7 +244,6 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
source = SOC_CPU_CLK_SRC_PLL;
source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ;
divider = 3;
#endif
} else {
// unsupported frequency
return false;
@ -330,31 +264,6 @@ __attribute__((weak)) void rtc_clk_set_cpu_switch_to_pll(int event_id)
void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
{
soc_cpu_clk_src_t old_cpu_clk_src = clk_ll_cpu_get_src();
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
if (config->source == SOC_CPU_CLK_SRC_XTAL) {
/* Configure clk mspi fast to 80m*/
rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
if (((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F160M) || (old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F240M)) && !s_bbpll_digi_consumers_ref_count) {
// We don't turn off the bbpll if some consumers depend on bbpll
rtc_clk_bbpll_disable();
}
} else if ((config->source == SOC_CPU_CLK_SRC_PLL_F160M) || (config->source == SOC_CPU_CLK_SRC_PLL_F240M)) {
if ((old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL_F160M) && (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL_F240M)) {
// PLL_F160M and PLL_F240M both derived from S(BB)PLL (480MHz)
rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_START);
rtc_clk_bbpll_enable();
rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), CLK_LL_PLL_480M_FREQ_MHZ);
}
rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_STOP);
} else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
rtc_clk_cpu_freq_to_8m();
if (((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F160M) || (old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F240M)) && !s_bbpll_digi_consumers_ref_count) {
// We don't turn off the bbpll if some consumers depend on bbpll
rtc_clk_bbpll_disable();
}
}
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
if (config->source == SOC_CPU_CLK_SRC_XTAL) {
rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
if ((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL) && !s_bbpll_digi_consumers_ref_count) {
@ -376,7 +285,6 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
rtc_clk_bbpll_disable();
}
}
#endif
}
void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
@ -384,36 +292,18 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
uint32_t source_freq_mhz;
uint32_t freq_mhz;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
uint32_t div = clk_ll_cpu_get_divider(); // div = freq of SOC_ROOT_CLK / freq of CPU_CLK
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
uint32_t div = clk_ll_cpu_get_ls_divider(); // div = freq of SOC_ROOT_CLK / freq of CPU_CLK
uint32_t hs_div = clk_ll_cpu_get_hs_divider();
#else
uint32_t div = 0;
#endif
switch (source) {
case SOC_CPU_CLK_SRC_XTAL: {
source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
freq_mhz = source_freq_mhz / div;
break;
}
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case SOC_CPU_CLK_SRC_PLL_F160M: {
source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ;
freq_mhz = source_freq_mhz / div;
break;
}
case SOC_CPU_CLK_SRC_PLL_F240M: {
source_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ;
freq_mhz = source_freq_mhz / div;
break;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
case SOC_CPU_CLK_SRC_PLL: {
source_freq_mhz = clk_ll_bbpll_get_freq_mhz();
freq_mhz = source_freq_mhz / hs_div;
break;
#endif
}
case SOC_CPU_CLK_SRC_RC_FAST:
source_freq_mhz = 20;
@ -436,11 +326,7 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
if (config->source == SOC_CPU_CLK_SRC_XTAL) {
rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
} else if (
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
((config->source == SOC_CPU_CLK_SRC_PLL_F160M) || (config->source == SOC_CPU_CLK_SRC_PLL_F240M)) &&
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
config->source == SOC_CPU_CLK_SRC_PLL &&
#endif
s_cur_pll_freq == config->source_freq_mhz
) {
rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
@ -476,18 +362,12 @@ void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
if (xtal_freq_mhz == 0) {
ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 48MHz");
return SOC_XTAL_FREQ_48M;
}
return (soc_xtal_freq_t)xtal_freq_mhz;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
uint32_t xtal_freq_mhz = clk_ll_xtal_get_freq_mhz();
assert(xtal_freq_mhz == SOC_XTAL_FREQ_48M || xtal_freq_mhz == SOC_XTAL_FREQ_40M);
return (soc_xtal_freq_t)xtal_freq_mhz;
#endif
}
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
@ -503,24 +383,6 @@ static uint32_t rtc_clk_ahb_freq_get(void)
uint32_t soc_root_freq_mhz;
uint32_t divider;
switch (source) {
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case SOC_CPU_CLK_SRC_XTAL:
soc_root_freq_mhz = rtc_clk_xtal_freq_get();
divider = clk_ll_ahb_get_divider();
break;
case SOC_CPU_CLK_SRC_PLL_F160M:
soc_root_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ;
divider = clk_ll_ahb_get_divider();
break;
case SOC_CPU_CLK_SRC_PLL_F240M:
soc_root_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ;
divider = clk_ll_ahb_get_divider();
break;
case SOC_CPU_CLK_SRC_RC_FAST:
soc_root_freq_mhz = 20;
divider = clk_ll_ahb_get_divider();
break;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
case SOC_CPU_CLK_SRC_XTAL:
soc_root_freq_mhz = rtc_clk_xtal_freq_get();
divider = clk_ll_ahb_get_ls_divider();
@ -533,7 +395,6 @@ static uint32_t rtc_clk_ahb_freq_get(void)
soc_root_freq_mhz = 20;
divider = clk_ll_ahb_get_ls_divider();
break;
#endif
default:
// Unknown SOC_ROOT clock source
soc_root_freq_mhz = 0;

4
components/esp_hw_support/port/esp32c5/rtc_time.c
View File

@ -246,12 +246,8 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
return lp_timer_hal_get_cycle_count();
#else
ESP_EARLY_LOGW(TAG, "rtc_timer has not been implemented yet");
return 0;
#endif
}
void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more

8
components/esp_hw_support/sleep_modes.c
View File

@ -737,11 +737,7 @@ static IRAM_ATTR void sleep_low_power_clock_calibration(bool is_dslp)
if ((s_lightsleep_cnt % CONFIG_PM_LIGHTSLEEP_RTC_OSC_CAL_INTERVAL == 0) || is_dslp)
#endif
{
#if !CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
s_config.fast_clk_cal_period = rtc_clk_cal(RTC_CAL_RC_FAST, FAST_CLK_SRC_CAL_CYCLES);
#else
s_config.fast_clk_cal_period = 0x8000;
#endif
}
#endif
}
@ -1665,11 +1661,7 @@ bool esp_sleep_is_valid_wakeup_gpio(gpio_num_t gpio_num)
#if SOC_RTCIO_PIN_COUNT > 0
return RTC_GPIO_IS_VALID_GPIO(gpio_num);
#else
#if !CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION // TODO: IDF-9673
return GPIO_IS_DEEP_SLEEP_WAKEUP_VALID_GPIO(gpio_num);
#else
return true;
#endif
#endif
}

4
components/esp_hw_support/test_apps/esp_hw_support_unity_tests/README.md
View File

@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

136
components/esp_system/ld/esp32c5/beta3/memory.ld.in
View File

@ -1,136 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* ESP32-C5 Linker Script Memory Layout
* This file describes the memory layout (memory blocks) by virtual memory addresses.
* This linker script is passed through the C preprocessor to include configuration options.
* Please use preprocessor features sparingly!
* Restrict to simple macros with numeric values, and/or #if/#endif blocks.
*/
#include "sdkconfig.h"
#include "ld.common"
/**
* physical memory is mapped twice to the vritual address (IRAM and DRAM).
* `I_D_SRAM_OFFSET` is the offset between the two locations of the same physical memory
*/
#define SRAM_IRAM_START 0x40800000
#define SRAM_DRAM_START 0x40800000
#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START)
#define SRAM_DRAM_END 0x4086EBC0 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */
#define SRAM_IRAM_ORG (SRAM_IRAM_START)
#define SRAM_DRAM_ORG (SRAM_DRAM_START)
#define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
#define IDROM_SEG_SIZE (CONFIG_MMU_PAGE_SIZE << 8)
#endif
#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE
MEMORY
{
/**
* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
* of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
* are connected to the data port of the CPU and eg allow byte-wise access.
*/
/* IRAM for PRO CPU. */
iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* Flash mapped instruction data */
irom_seg (RX) : org = 0x41000020, len = IDROM_SEG_SIZE - 0x20
/**
* (0x20 offset above is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
* header. Setting this offset makes it simple to meet the flash cache MMU's
* constraint that (paddr % 64KB == vaddr % 64KB).)
*/
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/**
* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
* Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
*/
dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* Flash mapped constant data */
drom_seg (R) : org = 0x41000020, len = IDROM_SEG_SIZE - 0x20
/* (See irom_seg for meaning of 0x20 offset in the above.) */
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/**
* lp ram memory (RWX). Persists over deep sleep. // TODO: IDF-5667
*/
#if CONFIG_ULP_COPROC_ENABLED
lp_ram_seg(RW) : org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
len = 0x4000 - CONFIG_ULP_COPROC_RESERVE_MEM - RESERVE_RTC_MEM
#else
lp_ram_seg(RW) : org = 0x50000000, len = 0x4000 - RESERVE_RTC_MEM
#endif // CONFIG_ULP_COPROC_ENABLED
/* We reduced the size of lp_ram_seg by RESERVE_RTC_MEM value.
It reserves the amount of LP memory that we use for this memory segment.
This segment is intended for keeping:
- (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
- (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
The aim of this is to keep data that will not be moved around and have a fixed address.
*/
lp_reserved_seg(RW) : org = 0x50000000 + 0x4000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM
}
/* Heap ends at top of dram0_0_seg */
_heap_end = 0x40000000;
_data_seg_org = ORIGIN(rtc_data_seg);
/**
* The lines below define location alias for .rtc.data section
* C5 has no distinguished LP(RTC) fast and slow memory sections, instead, there is a unified LP_RAM section
* Thus, the following region segments are not configurable like on other targets
*/
REGION_ALIAS("rtc_iram_seg", lp_ram_seg );
REGION_ALIAS("rtc_data_seg", rtc_iram_seg );
REGION_ALIAS("rtc_slow_seg", rtc_iram_seg );
REGION_ALIAS("rtc_data_location", rtc_iram_seg );
REGION_ALIAS("rtc_reserved_seg", lp_reserved_seg );
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
REGION_ALIAS("default_code_seg", irom_seg);
#else
REGION_ALIAS("default_code_seg", iram0_0_seg);
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
REGION_ALIAS("default_rodata_seg", drom_seg);
#else
REGION_ALIAS("default_rodata_seg", dram0_0_seg);
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/**
* If rodata default segment is placed in `drom_seg`, then flash's first rodata section must
* also be first in the segment.
*/
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg),
".flash_rodata_dummy section must be placed at the beginning of the rodata segment.")
#endif
#if CONFIG_ESP_SYSTEM_USE_EH_FRAME
ASSERT ((__eh_frame_end > __eh_frame), "Error: eh_frame size is null!");
ASSERT ((__eh_frame_hdr_end > __eh_frame_hdr), "Error: eh_frame_hdr size is null!");
#endif

458
components/esp_system/ld/esp32c5/beta3/sections.ld.in
View File

@ -1,458 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "ld.common"
/* Default entry point */
ENTRY(call_start_cpu0);
SECTIONS
{
/**
* RTC fast memory holds RTC wake stub code,
* including from any source file named rtc_wake_stub*.c
*/
.rtc.text :
{
ALIGNED_SYMBOL(4, _rtc_fast_start)
ALIGNED_SYMBOL(4, _rtc_text_start)
*(.rtc.entry.text)
mapping[rtc_text]
*rtc_wake_stub*.*(.text .text.*)
*(.rtc_text_end_test)
_rtc_text_end = ABSOLUTE(.);
} > lp_ram_seg
/**
* This section located in RTC FAST Memory area.
* It holds data marked with RTC_FAST_ATTR attribute.
* See the file "esp_attr.h" for more information.
*/
.rtc.force_fast :
{
ALIGNED_SYMBOL(4, _rtc_force_fast_start)
mapping[rtc_force_fast]
*(.rtc.force_fast .rtc.force_fast.*)
ALIGNED_SYMBOL(4, _rtc_force_fast_end)
} > lp_ram_seg
/**
* RTC data section holds RTC wake stub
* data/rodata, including from any source file
* named rtc_wake_stub*.c and the data marked with
* RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
*/
.rtc.data :
{
_rtc_data_start = ABSOLUTE(.);
mapping[rtc_data]
*rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .srodata.*)
_rtc_data_end = ABSOLUTE(.);
} > lp_ram_seg
/* RTC bss, from any source file named rtc_wake_stub*.c */
.rtc.bss (NOLOAD) :
{
_rtc_bss_start = ABSOLUTE(.);
*rtc_wake_stub*.*(.bss .bss.* .sbss .sbss.*)
*rtc_wake_stub*.*(COMMON)
mapping[rtc_bss]
_rtc_bss_end = ABSOLUTE(.);
} > lp_ram_seg
/**
* This section holds data that should not be initialized at power up
* and will be retained during deep sleep.
* User data marked with RTC_NOINIT_ATTR will be placed
* into this section. See the file "esp_attr.h" for more information.
*/
.rtc_noinit (NOLOAD):
{
ALIGNED_SYMBOL(4, _rtc_noinit_start)
*(.rtc_noinit .rtc_noinit.*)
ALIGNED_SYMBOL(4, _rtc_noinit_end)
} > lp_ram_seg
/**
* This section located in RTC SLOW Memory area.
* It holds data marked with RTC_SLOW_ATTR attribute.
* See the file "esp_attr.h" for more information.
*/
.rtc.force_slow :
{
ALIGNED_SYMBOL(4, _rtc_force_slow_start)
*(.rtc.force_slow .rtc.force_slow.*)
ALIGNED_SYMBOL(4, _rtc_force_slow_end)
} > lp_ram_seg
/**
* This section holds RTC data that should have fixed addresses.
* The data are not initialized at power-up and are retained during deep
* sleep.
*/
.rtc_reserved (NOLOAD):
{
ALIGNED_SYMBOL(4, _rtc_reserved_start)
/**
* New data can only be added here to ensure existing data are not moved.
* Because data have adhered to the end of the segment and code is relied
* on it.
* >> put new data here <<
*/
*(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*)
KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*))
_rtc_reserved_end = ABSOLUTE(.);
} > rtc_reserved_seg
_rtc_reserved_length = _rtc_reserved_end - _rtc_reserved_start;
ASSERT((_rtc_reserved_length <= LENGTH(rtc_reserved_seg)),
"RTC reserved segment data does not fit.")
/* Get size of rtc slow data based on rtc_data_location alias */
_rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
? (_rtc_force_slow_end - _rtc_data_start)
: (_rtc_force_slow_end - _rtc_force_slow_start);
_rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
? (_rtc_force_fast_end - _rtc_fast_start)
: (_rtc_noinit_end - _rtc_fast_start);
ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)),
"RTC_SLOW segment data does not fit.")
ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)),
"RTC_FAST segment data does not fit.")
.iram0.text :
{
_iram_start = ABSOLUTE(.);
/* Vectors go to start of IRAM */
ASSERT(ABSOLUTE(.) % 0x100 == 0, "vector address must be 256 byte aligned");
KEEP(*(.exception_vectors_table.text));
KEEP(*(.exception_vectors.text));
ALIGNED_SYMBOL(4, _invalid_pc_placeholder)
/* Code marked as running out of IRAM */
_iram_text_start = ABSOLUTE(.);
mapping[iram0_text]
} > iram0_0_seg
/* Marks the end of IRAM code segment */
.iram0.text_end (NOLOAD) :
{
ALIGNED_SYMBOL(4, _iram_text_end)
} > iram0_0_seg
.iram0.data :
{
ALIGNED_SYMBOL(16, _iram_data_start)
mapping[iram0_data]
_iram_data_end = ABSOLUTE(.);
} > iram0_0_seg
.iram0.bss (NOLOAD) :
{
ALIGNED_SYMBOL(16, _iram_bss_start)
mapping[iram0_bss]
_iram_bss_end = ABSOLUTE(.);
ALIGNED_SYMBOL(16, _iram_end)
} > iram0_0_seg
/**
* This section is required to skip .iram0.text area because iram0_0_seg and
* dram0_0_seg reflect the same address space on different buses.
*/
.dram0.dummy (NOLOAD):
{
. = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
} > dram0_0_seg
.dram0.data :
{
_data_start = ABSOLUTE(.);
*(.gnu.linkonce.d.*)
*(.data1)
__global_pointer$ = . + 0x800;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.gnu.linkonce.s2.*)
*(.jcr)
mapping[dram0_data]
_data_end = ABSOLUTE(.);
} > dram0_0_seg
/**
* This section holds data that should not be initialized at power up.
* The section located in Internal SRAM memory region. The macro _NOINIT
* can be used as attribute to place data into this section.
* See the "esp_attr.h" file for more information.
*/
.noinit (NOLOAD):
{
ALIGNED_SYMBOL(4, _noinit_start)
*(.noinit .noinit.*)
ALIGNED_SYMBOL(4, _noinit_end)
} > dram0_0_seg
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
ALIGNED_SYMBOL(8, _bss_start)
/**
* ldgen places all bss-related data to mapping[dram0_bss]
* (See components/esp_system/app.lf).
*/
mapping[dram0_bss]
ALIGNED_SYMBOL(8, _bss_end)
} > dram0_0_seg
ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.")
.flash.text :
{
_stext = .;
/**
* Mark the start of flash.text.
* This can be used by the MMU driver to maintain the virtual address.
*/
_instruction_reserved_start = ABSOLUTE(.);
_text_start = ABSOLUTE(.);
mapping[flash_text]
*(.stub)
*(.gnu.linkonce.t.*)
*(.gnu.warning)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
/**
* CPU will try to prefetch up to 16 bytes of of instructions.
* This means that any configuration (e.g. MMU, PMS) must allow
* safe access to up to 16 bytes after the last real instruction, add
* dummy bytes to ensure this
*/
. += _esp_flash_mmap_prefetch_pad_size;
_text_end = ABSOLUTE(.);
/**
* Mark the flash.text end.
* This can be used for MMU driver to maintain virtual address.
*/
_instruction_reserved_end = ABSOLUTE(.);
_etext = .;
/**
* Similar to _iram_start, this symbol goes here so it is
* resolved by addr2line in preference to the first symbol in
* the flash.text segment.
*/
_flash_cache_start = ABSOLUTE(0);
} > default_code_seg
/**
* Dummy section represents the .flash.text section but in default_rodata_seg.
* Thus, it must have its alignment and (at least) its size.
*/
.flash_rodata_dummy (NOLOAD):
{
_flash_rodata_dummy_start = .;
. = ALIGN(ALIGNOF(.flash.text)) + SIZEOF(.flash.text);
/* Add alignment of MMU page size + 0x20 bytes for the mapping header. */
. = ALIGN(_esp_mmu_page_size) + 0x20;
} > default_rodata_seg
.flash.appdesc : ALIGN(0x10)
{
/**
* Mark flash.rodata start.
* This can be used for mmu driver to maintain virtual address
*/
_rodata_reserved_start = ABSOLUTE(.);
_rodata_start = ABSOLUTE(.);
/* !DO NOT PUT ANYTHING BEFORE THIS! */
/* Should be the first. App version info. */
*(.rodata_desc .rodata_desc.*)
/* Should be the second. Custom app version info. */
*(.rodata_custom_desc .rodata_custom_desc.*)
/**
* Create an empty gap within this section. Thanks to this, the end of this
* section will match .flash.rodata's begin address. Thus, both sections
* will be merged when creating the final bin image.
*/
. = ALIGN(ALIGNOF(.flash.rodata));
} > default_rodata_seg
ASSERT_SECTIONS_GAP(.flash.appdesc, .flash.rodata)
.flash.rodata : ALIGN(0x10)
{
_flash_rodata_start = ABSOLUTE(.);
mapping[flash_rodata]
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
*(.gnu.linkonce.r.*)
*(.rodata1)
*(.gcc_except_table .gcc_except_table.*)
*(.gnu.linkonce.e.*)
/**
* C++ constructor tables.
*
* Excluding crtbegin.o/crtend.o since IDF doesn't use the toolchain crt.
*
* RISC-V gcc is configured with --enable-initfini-array so it emits
* .init_array section instead. But the init_priority sections will be
* sorted for iteration in ascending order during startup.
* The rest of the init_array sections is sorted for iteration in descending
* order during startup, however. Hence a different section is generated for
* the init_priority functions which is iterated in ascending order during
* startup. The corresponding code can be found in startup.c.
*/
ALIGNED_SYMBOL(4, __init_priority_array_start)
KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))
__init_priority_array_end = ABSOLUTE(.);
ALIGNED_SYMBOL(4, __init_array_start)
KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))
__init_array_end = ABSOLUTE(.);
/* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */
ALIGNED_SYMBOL(4, soc_reserved_memory_region_start)
KEEP (*(.reserved_memory_address))
soc_reserved_memory_region_end = ABSOLUTE(.);
/* System init functions registered via ESP_SYSTEM_INIT_FN */
ALIGNED_SYMBOL(4, _esp_system_init_fn_array_start)
KEEP (*(SORT_BY_INIT_PRIORITY(.esp_system_init_fn.*)))
_esp_system_init_fn_array_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
. = ALIGN(ALIGNOF(.eh_frame_hdr));
} > default_rodata_seg
ASSERT_SECTIONS_GAP(.flash.rodata, .eh_frame_hdr)
.eh_frame_hdr :
{
#if CONFIG_COMPILER_CXX_EXCEPTIONS || CONFIG_ESP_SYSTEM_USE_EH_FRAME
ALIGNED_SYMBOL(4, __eh_frame_hdr)
KEEP (*(.eh_frame_hdr))
__eh_frame_hdr_end = ABSOLUTE(.);
#endif // CONFIG_COMPILER_CXX_EXCEPTIONS || CONFIG_ESP_SYSTEM_USE_EH_FRAME
. = ALIGN(ALIGNOF(.eh_frame));
} > default_rodata_seg
ASSERT_SECTIONS_GAP(.eh_frame_hdr, .eh_frame)
.eh_frame :
{
#if CONFIG_COMPILER_CXX_EXCEPTIONS || CONFIG_ESP_SYSTEM_USE_EH_FRAME
ALIGNED_SYMBOL(4, __eh_frame)
KEEP (*(.eh_frame))
/**
* As we are not linking with crtend.o, which includes the CIE terminator
* (see __FRAME_END__ in libgcc sources), it is manually provided here.
*/
LONG(0);
__eh_frame_end = ABSOLUTE(.);
#endif // CONFIG_COMPILER_CXX_EXCEPTIONS || CONFIG_ESP_SYSTEM_USE_EH_FRAME
. = ALIGN(ALIGNOF(.flash.tdata));
} > default_rodata_seg
ASSERT_SECTIONS_GAP(.eh_frame, .flash.tdata)
.flash.tdata :
{
_thread_local_data_start = ABSOLUTE(.);
*(.tdata .tdata.* .gnu.linkonce.td.*)
. = ALIGN(ALIGNOF(.flash.tbss));
_thread_local_data_end = ABSOLUTE(.);
} > default_rodata_seg
ASSERT_SECTIONS_GAP(.flash.tdata, .flash.tbss)
.flash.tbss (NOLOAD) :
{
_thread_local_bss_start = ABSOLUTE(.);
*(.tbss .tbss.* .gnu.linkonce.tb.*)
*(.tcommon .tcommon.*)
_thread_local_bss_end = ABSOLUTE(.);
} > default_rodata_seg
/**
* This section contains all the rodata that is not used
* at runtime, helping to avoid an increase in binary size.
*/
.flash.rodata_noload (NOLOAD) :
{
/**
* This symbol marks the end of flash.rodata. It can be utilized by the MMU
* driver to maintain the virtual address.
* NOLOAD rodata may not be included in this section.
*/
_rodata_reserved_end = ADDR(.flash.tbss);
mapping[rodata_noload]
} > default_rodata_seg
/* Marks the end of data, bss and possibly rodata */
.dram0.heap_start (NOLOAD) :
{
ALIGNED_SYMBOL(16, _heap_start)
} > dram0_0_seg
#include "elf_misc.ld.in"
}
ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
"IRAM0 segment data does not fit.")
ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),
"DRAM segment data does not fit.")

0
components/esp_system/ld/esp32c5/mp/memory.ld.in → components/esp_system/ld/esp32c5/memory.ld.in
View File

0
components/esp_system/ld/esp32c5/mp/sections.ld.in → components/esp_system/ld/esp32c5/sections.ld.in
View File

10
components/esp_system/ld/ld.cmake
View File

@ -19,13 +19,7 @@ string(REPLACE "\\n" "\n" TEXT "${PREPROCESSED_LINKER_SCRIPT}")
file(WRITE "${TARGET}" "${TEXT}")
]=])
if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
set(target_folder "esp32c5/beta3")
elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
set(target_folder "esp32c5/mp")
else()
set(target_folder "${target}")
endif()
function(preprocess_linker_file name_in name_out out_path)
set(script_in "${CMAKE_CURRENT_LIST_DIR}/${target_folder}/${name_in}")
@ -49,11 +43,11 @@ function(preprocess_linker_file name_in name_out out_path)
add_dependencies(${COMPONENT_LIB} "${name_out}")
endfunction()
# Generage memory.ld
# Generate memory.ld
preprocess_linker_file("memory.ld.in" "memory.ld" ld_out_path)
target_linker_script(${COMPONENT_LIB} INTERFACE "${ld_out_path}")
# Generage sections.ld.in and pass it through linker script generator
# Generate sections.ld.in and pass it through linker script generator
preprocess_linker_file("sections.ld.in" "sections.ld.in" ld_out_path)
target_linker_script(${COMPONENT_LIB} INTERFACE "${ld_out_path}"
PROCESS "${CMAKE_CURRENT_BINARY_DIR}/ld/sections.ld")

30
components/esp_system/port/soc/esp32c5/clk.c
View File

@ -30,9 +30,7 @@
#include "esp_private/esp_pmu.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
#include "ocode_init.h"
#endif
/* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
* Larger values increase startup delay. Smaller values may cause false positive
@ -49,20 +47,10 @@ static const char *TAG = "clk";
// TODO: [ESP32C5] IDF-8642
__attribute__((weak)) void esp_clk_init(void)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
#if !CONFIG_IDF_ENV_FPGA
#if SOC_PMU_SUPPORTED
pmu_init();
#endif
assert((rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_40M) || (rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_48M));
#if SOC_MODEM_CLOCK_SUPPORTED
modem_lpcon_ll_set_pwr_tick_target(&MODEM_LPCON, rtc_clk_xtal_freq_get() - 1);
#endif
rtc_clk_8m_enable(true);
rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
#else
#if !CONFIG_IDF_ENV_FPGA
pmu_init();
if (esp_rom_get_reset_reason(0) == RESET_REASON_CHIP_POWER_ON) {
esp_ocode_calib_init();
}
@ -72,7 +60,6 @@ __attribute__((weak)) void esp_clk_init(void)
rtc_clk_8m_enable(true);
rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
#endif
#endif
#ifdef CONFIG_BOOTLOADER_WDT_ENABLE
// WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.
@ -96,12 +83,8 @@ __attribute__((weak)) void esp_clk_init(void)
#elif defined(CONFIG_RTC_CLK_SRC_INT_RC32K)
select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_RC32K);
#else
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
abort();
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
select_rtc_slow_clk(SOC_RTC_SLOW_CLK_SRC_RC_SLOW);
#endif
#endif
#ifdef CONFIG_BOOTLOADER_WDT_ENABLE
// After changing a frequency WDT timeout needs to be set for new frequency.
@ -170,13 +153,8 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
if (retry_32k_xtal-- > 0) {
continue;
}
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
ESP_EARLY_LOGW(TAG, "32 kHz clock not found, switching to internal 32 kHz oscillator");
rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC32K;
#else
ESP_EARLY_LOGW(TAG, "32 kHz clock not found, switching to internal 150 kHz oscillator");
rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
#endif
}
}
} else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
@ -212,9 +190,7 @@ void rtc_clk_select_rtc_slow_clk(void)
__attribute__((weak)) void esp_perip_clk_init(void)
{
// TODO: [ESP32C5] IDF-8844
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// modem_clock_domain_pmu_state_icg_map_init();
#endif
/* During system initialization, the low-power clock source of the modem
* (WiFi, BLE or Coexist) follows the configuration of the slow clock source
* of the system. If the WiFi, BLE or Coexist module needs a higher
@ -322,11 +298,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Set WiFi light sleep clock source to RTC slow clock */
REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M);
#endif
SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
/* Enable RNG clock. */

28
components/esp_system/port/soc/esp32c5/system_internal.c
View File

@ -20,9 +20,6 @@
#include "esp_private/rtc_clk.h"
#include "soc/rtc_periph.h"
#include "soc/uart_reg.h"
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
#include "hal/clk_tree_ll.h"
#endif
#include "hal/wdt_hal.h"
#if SOC_MODEM_CLOCK_SUPPORTED
#include "hal/modem_syscon_ll.h"
@ -45,43 +42,22 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
modem_syscon_ll_reset_all(&MODEM_SYSCON);
modem_lpcon_ll_reset_all(&MODEM_LPCON);
#endif
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
// Set SPI Flash Freq to 40M
clk_ll_mspi_fast_set_src(MSPI_CLK_SRC_XTAL);
clk_ll_mspi_fast_set_divider(1);
// Set Peripheral clk rst
SET_PERI_REG_MASK(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
#endif
// Set Peripheral clk rst
SET_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
SET_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
SET_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
SET_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
SET_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
SET_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
SET_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
SET_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
// Clear Peripheral clk rst
CLEAR_PERI_REG_MASK(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
SET_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
SET_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
#endif
// Clear Peripheral clk rst
CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
CLEAR_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
CLEAR_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
CLEAR_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
CLEAR_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
CLEAR_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// CLEAR_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
#endif
CLEAR_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
CLEAR_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
}
@ -119,11 +95,7 @@ void IRAM_ATTR esp_restart_noos(void)
wdt_hal_write_protect_enable(&wdt1_context);
// Disable cache
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
Cache_Disable_ICache();
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
Cache_Disable_Cache();
#endif
// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
// Moved to module internal

9
components/esptool_py/project_include.cmake
View File

@ -8,15 +8,6 @@ idf_build_get_property(idf_path IDF_PATH)
set(chip_model ${target})
# TODO: [ESP32C5] IDF-9197 remove this 'if' block when esp32C5 beta3 is no longer supported
if(target STREQUAL "esp32c5")
if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
set(chip_model esp32c5beta3)
elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
set(chip_model esp32c5)
endif()
endif()
set(ESPTOOLPY ${python} "$ENV{ESPTOOL_WRAPPER}" "${CMAKE_CURRENT_LIST_DIR}/esptool/esptool.py" --chip ${chip_model})
set(ESPSECUREPY ${python} "${CMAKE_CURRENT_LIST_DIR}/esptool/espsecure.py")
set(ESPEFUSEPY ${python} "${CMAKE_CURRENT_LIST_DIR}/esptool/espefuse.py")

6
components/hal/CMakeLists.txt
View File

@ -7,12 +7,6 @@ set(includes "platform_port/include")
# because of the "include_next" directive used by the efuse_hal.h
list(APPEND includes "${target}/include")
if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
list(APPEND includes "${target}/beta3/include")
elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
list(APPEND includes "${target}/mp/include")
endif()
list(APPEND includes "include")
if(CONFIG_SOC_MPU_SUPPORTED)

610
components/hal/esp32c5/beta3/include/hal/gdma_beta3_ll.h
View File

@ -1,610 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stddef.h> /* Required for NULL constant */
#include <stdint.h>
#include <stdbool.h>
#include "soc/soc_caps.h"
#include "hal/gdma_types.h"
#include "soc/gdma_struct.h"
#include "soc/gdma_reg.h"
#include "soc/soc_etm_source.h"
#include "soc/retention_periph_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#define GDMA_CH_RETENTION_GET_MODULE_ID(group_id, pair_id) (SLEEP_RETENTION_MODULE_GDMA_CH0 << (SOC_GDMA_PAIRS_PER_GROUP_MAX * group_id) << pair_id)
#define GDMA_LL_GET_HW(id) (((id) == 0) ? (&GDMA) : NULL)
#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]
#define GDMA_LL_RX_EVENT_MASK (0x7F)
#define GDMA_LL_TX_EVENT_MASK (0x3F)
// any "dummy" peripheral ID can be used for M2M mode
#define GDMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFC32)
#define GDMA_LL_INVALID_PERIPH_ID (0x3F)
#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5)
#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<4)
#define GDMA_LL_EVENT_RX_FIFO_UDF (1<<6)
#define GDMA_LL_EVENT_RX_FIFO_OVF (1<<5)
#define GDMA_LL_EVENT_TX_TOTAL_EOF (1<<3)
#define GDMA_LL_EVENT_RX_DESC_EMPTY (1<<4)
#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<2)
#define GDMA_LL_EVENT_RX_DESC_ERROR (1<<3)
#define GDMA_LL_EVENT_TX_EOF (1<<1)
#define GDMA_LL_EVENT_TX_DONE (1<<0)
#define GDMA_LL_EVENT_RX_ERR_EOF (1<<2)
#define GDMA_LL_EVENT_RX_SUC_EOF (1<<1)
#define GDMA_LL_EVENT_RX_DONE (1<<0)
#define GDMA_LL_AHB_GROUP_START_ID 0 // AHB GDMA group ID starts from 0
#define GDMA_LL_AHB_NUM_GROUPS 1 // Number of AHB GDMA groups
#define GDMA_LL_AHB_PAIRS_PER_GROUP 3 // Number of GDMA pairs in each AHB group
#define GDMA_LL_TX_ETM_EVENT_TABLE(group, chan, event) \
(uint32_t[1][3][GDMA_ETM_EVENT_MAX]){{{ \
[GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH0, \
}, \
{ \
[GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH1, \
}, \
{ \
[GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH2, \
}}}[group][chan][event]
#define GDMA_LL_RX_ETM_EVENT_TABLE(group, chan, event) \
(uint32_t[1][3][GDMA_ETM_EVENT_MAX]){{{ \
[GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH0, \
}, \
{ \
[GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH1, \
}, \
{ \
[GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH2, \
}}}[group][chan][event]
#define GDMA_LL_TX_ETM_TASK_TABLE(group, chan, task) \
(uint32_t[1][3][GDMA_ETM_TASK_MAX]){{{ \
[GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH0, \
}, \
{ \
[GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH1, \
}, \
{ \
[GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH2, \
}}}[group][chan][task]
#define GDMA_LL_RX_ETM_TASK_TABLE(group, chan, task) \
(uint32_t[1][3][GDMA_ETM_TASK_MAX]){{{ \
[GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH0, \
}, \
{ \
[GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH1, \
}, \
{ \
[GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH2, \
}}}[group][chan][task]
// Workaround for C5-beta3 only, it can not vectorized channels into an array in gdma_struct.h
#define GDMA_LL_CHANNEL_GET_REG_ADDR(dev, ch) ((volatile gdma_chn_reg_t*[]){&dev->channel0, &dev->channel1, &dev->channel2}[(ch)])
#define GDMA_LL_AHB_DESC_ALIGNMENT 4
///////////////////////////////////// Common /////////////////////////////////////////
/**
* @brief Force enable register clock
*/
static inline void gdma_ll_force_enable_reg_clock(gdma_dev_t *dev, bool enable)
{
dev->misc_conf.clk_en = enable;
}
///////////////////////////////////// RX /////////////////////////////////////////
/**
* @brief Get DMA RX channel interrupt status word
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw)
{
if (raw) {
return dev->in_intr[channel].raw.val;
} else {
return dev->in_intr[channel].st.val;
}
}
/**
* @brief Enable DMA RX channel interrupt
*/
static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
{
if (enable) {
dev->in_intr[channel].ena.val |= mask;
} else {
dev->in_intr[channel].ena.val &= ~mask;
}
}
/**
* @brief Clear DMA RX channel interrupt
*/
__attribute__((always_inline))
static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
{
dev->in_intr[channel].clr.val = mask;
}
/**
* @brief Get DMA RX channel interrupt status register address
*/
static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel)
{
return (volatile void *)(&dev->in_intr[channel].st);
}
/**
* @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default
*/
static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_conf1.in_check_owner = enable;
}
/**
* @brief Enable DMA RX channel burst reading data, disabled by default
*/
static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_conf0.in_data_burst_en = enable;
}
/**
* @brief Enable DMA RX channel burst reading descriptor link, disabled by default
*/
static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_conf0.indscr_burst_en = enable;
}
/**
* @brief Reset DMA RX channel FSM and FIFO pointer
*/
__attribute__((always_inline))
static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_conf0.in_rst = 1;
ch->in.in_conf0.in_rst = 0;
}
/**
* @brief Check if DMA RX FIFO is full
* @param fifo_level only supports level 1
*/
static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->in.infifo_status.val & 0x01;
}
/**
* @brief Check if DMA RX FIFO is empty
* @param fifo_level only supports level 1
*/
static inline bool gdma_ll_rx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->in.infifo_status.val & 0x02;
}
/**
* @brief Get number of bytes in RX FIFO
* @param fifo_level only supports level 1
*/
static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->in.infifo_status.infifo_cnt;
}
/**
* @brief Pop data from DMA RX FIFO
*/
static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_pop.infifo_pop = 1;
return ch->in.in_pop.infifo_rdata;
}
/**
* @brief Set the descriptor link base address for RX channel
*/
__attribute__((always_inline))
static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_link.inlink_addr = addr;
}
/**
* @brief Start dealing with RX descriptors
*/
__attribute__((always_inline))
static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_link.inlink_start = 1;
}
/**
* @brief Stop dealing with RX descriptors
*/
__attribute__((always_inline))
static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_link.inlink_stop = 1;
}
/**
* @brief Restart a new inlink right after the last descriptor
*/
__attribute__((always_inline))
static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_link.inlink_restart = 1;
}
/**
* @brief Enable DMA RX to return the address of current descriptor when receives error
*/
static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_link.inlink_auto_ret = enable;
}
/**
* @brief Check if DMA RX descriptor FSM is in IDLE state
*/
static inline bool gdma_ll_rx_is_desc_fsm_idle(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->in.in_link.inlink_park;
}
/**
* @brief Get RX success EOF descriptor's address
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->in.in_suc_eof_des_addr.val;
}
/**
* @brief Get RX error EOF descriptor's address
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->in.in_err_eof_des_addr.val;
}
/**
* @brief Get the pre-fetched RX descriptor's address
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_rx_get_prefetched_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->in.in_dscr.val;
}
/**
* @brief Set priority for DMA RX channel
*/
static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_pri.rx_pri = prio;
}
/**
* @brief Connect DMA RX channel to a given peripheral
*/
static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_peri_sel.peri_in_sel = periph_id;
ch->in.in_conf0.mem_trans_en = (periph == GDMA_TRIG_PERIPH_M2M);
}
/**
* @brief Disconnect DMA RX channel from peripheral
*/
static inline void gdma_ll_rx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_peri_sel.peri_in_sel = GDMA_LL_INVALID_PERIPH_ID;
ch->in.in_conf0.mem_trans_en = false;
}
/**
* @brief Whether to enable the ETM subsystem for RX channel
*
* @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel.
*/
static inline void gdma_ll_rx_enable_etm_task(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->in.in_conf0.in_etm_en = enable;
}
///////////////////////////////////// TX /////////////////////////////////////////
/**
* @brief Get DMA TX channel interrupt status word
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw)
{
if (raw) {
return dev->out_intr[channel].raw.val;
} else {
return dev->out_intr[channel].st.val;
}
}
/**
* @brief Enable DMA TX channel interrupt
*/
static inline void gdma_ll_tx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
{
if (enable) {
dev->out_intr[channel].ena.val |= mask;
} else {
dev->out_intr[channel].ena.val &= ~mask;
}
}
/**
* @brief Clear DMA TX channel interrupt
*/
__attribute__((always_inline))
static inline void gdma_ll_tx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
{
dev->out_intr[channel].clr.val = mask;
}
/**
* @brief Get DMA TX channel interrupt status register address
*/
static inline volatile void *gdma_ll_tx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel)
{
return (volatile void *)(&dev->out_intr[channel].st);
}
/**
* @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default
*/
static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_conf1.out_check_owner = enable;
}
/**
* @brief Enable DMA TX channel burst sending data, disabled by default
*/
static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_conf0.out_data_burst_en = enable;
}
/**
* @brief Enable DMA TX channel burst reading descriptor link, disabled by default
*/
static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_conf0.outdscr_burst_en = enable;
}
/**
* @brief Set TX channel EOF mode
*/
static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, uint32_t mode)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_conf0.out_eof_mode = mode;
}
/**
* @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default
*/
static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_conf0.out_auto_wrback = enable;
}
/**
* @brief Reset DMA TX channel FSM and FIFO pointer
*/
__attribute__((always_inline))
static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_conf0.out_rst = 1;
ch->out.out_conf0.out_rst = 0;
}
/**
* @brief Check if DMA TX FIFO is full
* @param fifo_level only supports level 1
*/
static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->out.outfifo_status.val & 0x01;
}
/**
* @brief Check if DMA TX FIFO is empty
* @param fifo_level only supports level 1
*/
static inline bool gdma_ll_tx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->out.outfifo_status.val & 0x02;
}
/**
* @brief Get number of bytes in TX FIFO
* @param fifo_level only supports level 1
*/
static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->out.outfifo_status.outfifo_cnt;
}
/**
* @brief Push data into DMA TX FIFO
*/
static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint32_t data)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_push.outfifo_wdata = data;
ch->out.out_push.outfifo_push = 1;
}
/**
* @brief Set the descriptor link base address for TX channel
*/
__attribute__((always_inline))
static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_link.outlink_addr = addr;
}
/**
* @brief Start dealing with TX descriptors
*/
__attribute__((always_inline))
static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_link.outlink_start = 1;
}
/**
* @brief Stop dealing with TX descriptors
*/
__attribute__((always_inline))
static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_link.outlink_stop = 1;
}
/**
* @brief Restart a new outlink right after the last descriptor
*/
__attribute__((always_inline))
static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_link.outlink_restart = 1;
}
/**
* @brief Check if DMA TX descriptor FSM is in IDLE state
*/
static inline bool gdma_ll_tx_is_desc_fsm_idle(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->out.out_link.outlink_park;
}
/**
* @brief Get TX EOF descriptor's address
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->out.out_eof_des_addr.val;
}
/**
* @brief Get the pre-fetched TX descriptor's address
*/
__attribute__((always_inline))
static inline uint32_t gdma_ll_tx_get_prefetched_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
return ch->out.out_dscr.val;
}
/**
* @brief Set priority for DMA TX channel
*/
static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_pri.tx_pri = prio;
}
/**
* @brief Connect DMA TX channel to a given peripheral
*/
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
{
(void)periph;
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_peri_sel.peri_out_sel = periph_id;
}
/**
* @brief Disconnect DMA TX channel from peripheral
*/
static inline void gdma_ll_tx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_peri_sel.peri_out_sel = GDMA_LL_INVALID_PERIPH_ID;
}
/**
* @brief Whether to enable the ETM subsystem for TX channel
*
* @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel.
*/
static inline void gdma_ll_tx_enable_etm_task(gdma_dev_t *dev, uint32_t channel, bool enable)
{
volatile gdma_chn_reg_t *ch = (volatile gdma_chn_reg_t *)GDMA_LL_CHANNEL_GET_REG_ADDR(dev, channel);
ch->out.out_conf0.out_etm_en = enable;
}
#ifdef __cplusplus
}
#endif

19
components/hal/esp32c5/clk_tree_hal.c
View File

@ -21,15 +21,8 @@ uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
switch (cpu_clk_src) {
case SOC_CPU_CLK_SRC_XTAL:
return clk_hal_xtal_get_freq_mhz();
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case SOC_CPU_CLK_SRC_PLL_F160M:
return CLK_LL_PLL_160M_FREQ_MHZ;
case SOC_CPU_CLK_SRC_PLL_F240M:
return CLK_LL_PLL_240M_FREQ_MHZ;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
case SOC_CPU_CLK_SRC_PLL:
return clk_ll_bbpll_get_freq_mhz();
#endif
case SOC_CPU_CLK_SRC_RC_FAST:
return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ;
default:
@ -42,22 +35,16 @@ uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
uint32_t clk_hal_cpu_get_freq_hz(void)
{
soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
uint32_t divider = clk_ll_cpu_get_divider();
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
uint32_t divider = (source == SOC_CPU_CLK_SRC_PLL) ? clk_ll_cpu_get_hs_divider() : clk_ll_cpu_get_ls_divider();
#endif
return clk_hal_soc_root_get_freq_mhz(source) * MHZ / divider;
}
uint32_t clk_hal_ahb_get_freq_hz(void)
{
soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
uint32_t divider = clk_ll_ahb_get_divider();
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
uint32_t divider = (source == SOC_CPU_CLK_SRC_PLL) ? clk_ll_ahb_get_hs_divider() : clk_ll_ahb_get_ls_divider();
#endif
return clk_hal_soc_root_get_freq_mhz(source) * MHZ / divider;
}
@ -69,10 +56,8 @@ uint32_t clk_hal_apb_get_freq_hz(void)
uint32_t clk_hal_lp_slow_get_freq_hz(void)
{
switch (clk_ll_rtc_slow_get_src()) {
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
return SOC_CLK_RC_SLOW_FREQ_APPROX;
#endif
case SOC_RTC_SLOW_CLK_SRC_XTAL32K:
return SOC_CLK_XTAL32K_FREQ_APPROX;
case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW:

0
components/hal/esp32c5/mp/include/hal/ahb_dma_ll.h → components/hal/esp32c5/include/hal/ahb_dma_ll.h
View File

80
components/hal/esp32c5/include/hal/cache_ll.h
View File

@ -64,13 +64,8 @@ static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cach
__attribute__((always_inline))
static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
(void) type;
Cache_Disable_ICache();
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
(void) type;
Cache_Disable_Cache();
#endif
}
/**
@ -85,11 +80,7 @@ static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t typ
__attribute__((always_inline))
static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
Cache_Enable_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
Cache_Enable_Cache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
#endif
}
/**
@ -102,11 +93,7 @@ static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type
__attribute__((always_inline))
static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
Cache_Suspend_ICache();
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
Cache_Suspend_Cache();
#endif
}
/**
@ -121,11 +108,7 @@ static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t typ
__attribute__((always_inline))
static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
Cache_Resume_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
Cache_Resume_Cache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
#endif
}
/**
@ -155,11 +138,7 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t
__attribute__((always_inline))
static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
Cache_Freeze_Enable(CACHE_FREEZE_ACK_BUSY);
#endif
}
/**
@ -172,11 +151,7 @@ static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type
__attribute__((always_inline))
static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
Cache_Freeze_ICache_Disable();
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
Cache_Freeze_Disable();
#endif
}
/**
@ -191,15 +166,9 @@ static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t ty
__attribute__((always_inline))
static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
uint32_t size = 0;
size = Cache_Get_ICache_Line_Size();
return size;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
uint32_t size = 0;
size = Cache_Get_Line_Size(CACHE_MAP_FLASH_CACHE);
return size;
#endif
}
/**
@ -217,18 +186,6 @@ __attribute__((always_inline))
#endif
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1;
if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
//c5 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0`
mask = (cache_bus_mask_t)(mask | (CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0));
} else {
HAL_ASSERT(0); //Out of region
}
return mask;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
cache_bus_mask_t mask = (cache_bus_mask_t)0;
@ -241,7 +198,6 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
}
return mask;
#endif
}
/**
@ -255,17 +211,6 @@ __attribute__((always_inline))
#endif
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
@ -277,7 +222,6 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
uint32_t dbus_mask = 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
#endif
}
/**
@ -289,17 +233,6 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
__attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
@ -311,7 +244,6 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m
uint32_t dbus_mask = 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
#endif
}
/**
@ -327,17 +259,6 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m
__attribute__((always_inline))
static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
bool valid = false;
uint32_t vaddr_end = vaddr_start + len - 1;
valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
if (valid) {
*out_level = 1;
*out_id = 0;
}
return valid;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
bool valid = false;
uint32_t vaddr_end = vaddr_start + len - 1;
@ -350,7 +271,6 @@ static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32
}
return valid;
#endif
}
/*------------------------------------------------------------------------------

177
components/hal/esp32c5/include/hal/clk_tree_ll.h
View File

@ -7,7 +7,6 @@
#pragma once
#include <stdint.h>
#include "sdkconfig.h" // TODO: IDF-9197 remove
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#include "soc/pcr_struct.h"
@ -318,37 +317,6 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
uint8_t dr3;
uint8_t dchgp;
uint8_t dbias;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
uint8_t href = 3;
uint8_t lref = 1;
/* Configure 480M PLL */
switch (xtal_freq_mhz) {
case SOC_XTAL_FREQ_40M:
div_ref = 1;
div7_0 = 12;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dbias = 2;
break;
case SOC_XTAL_FREQ_48M:
div_ref = 1;
div7_0 = 10;
dr1 = 1;
dr3 = 1;
dchgp = 5;
dbias = 2;
break;
default:
div_ref = 1;
div7_0 = 12;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dbias = 2;
break;
}
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
uint8_t dcur;
/* Configure 480M PLL */
@ -364,36 +332,19 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
dbias = 2;
break;
}
#endif
uint8_t i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref);
uint8_t i2c_bbpll_div_7_0 = div7_0;
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
uint8_t i2c_bbpll_dcur = (1 << I2C_BBPLL_OC_DLREF_SEL_LSB ) | (3 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
#endif
REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1);
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, lref);
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, href);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
#endif
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias);
}
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
/**
* @brief To enable the change of soc_clk_sel, cpu_div_num, and ahb_div_num
*/
static inline __attribute__((always_inline)) void clk_ll_bus_update(void)
{
PCR.bus_clk_update.bus_clock_update = 1;
while (PCR.bus_clk_update.bus_clock_update);
}
#endif
/**
* @brief Select the clock source for CPU_CLK (SOC Clock Root)
*
@ -405,24 +356,12 @@ static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk
case SOC_CPU_CLK_SRC_XTAL:
PCR.sysclk_conf.soc_clk_sel = 0;
break;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case SOC_CPU_CLK_SRC_RC_FAST:
PCR.sysclk_conf.soc_clk_sel = 1;
break;
case SOC_CPU_CLK_SRC_PLL_F160M:
PCR.sysclk_conf.soc_clk_sel = 2;
break;
case SOC_CPU_CLK_SRC_PLL_F240M:
PCR.sysclk_conf.soc_clk_sel = 3;
break;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
case SOC_CPU_CLK_SRC_PLL:
PCR.sysclk_conf.soc_clk_sel = 1;
break;
case SOC_CPU_CLK_SRC_RC_FAST:
PCR.sysclk_conf.soc_clk_sel = 2;
break;
#endif
default:
// Unsupported SOC_CLK mux input sel
abort();
@ -441,73 +380,15 @@ static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_sr
case 0:
return SOC_CPU_CLK_SRC_XTAL;
case 1:
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
return SOC_CPU_CLK_SRC_RC_FAST;
case 2:
return SOC_CPU_CLK_SRC_PLL_F160M;
case 3:
return SOC_CPU_CLK_SRC_PLL_F240M;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
return SOC_CPU_CLK_SRC_PLL;
case 2:
return SOC_CPU_CLK_SRC_RC_FAST;
#endif
default:
// Invalid SOC_CLK_SEL value
return SOC_CPU_CLK_SRC_INVALID;
}
}
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
/**
* @brief Set CPU_CLK's divider
*
* @param divider Divider. (PCR_CPU_DIV_NUM + 1) = divider.
*/
static inline __attribute__((always_inline)) void clk_ll_cpu_set_divider(uint32_t divider)
{
// SOC_ROOT_CLK ---(1)---> HP_ROOT_CLK ---(2)---> CPU_CLK
// (2) configurable
// divider option: 1, 2, 4 (PCR_CPU_HS_DIV_NUM=0, 1, 3)
HAL_ASSERT(divider == 1 || divider == 2 || divider == 3 || divider == 4 || divider == 6);
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num, (divider) - 1);
}
/**
* @brief Get CPU_CLK's high-speed divider
*
* @return Divider. Divider = (PCR_HS_DIV_NUM + 1) * (PCR_CPU_HS_DIV_NUM + 1).
*/
static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(void)
{
uint32_t cpu_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num);
return (cpu_div + 1);
}
/**
* @brief Set AHB_CLK's low-speed divider (valid when SOC_ROOT clock source is XTAL/RC_FAST)
*
* @param divider Divider. (PCR_LS_DIV_NUM + 1) * (PCR_AHB_LS_DIV_NUM + 1) = divider.
*/
static inline __attribute__((always_inline)) void clk_ll_ahb_set_divider(uint32_t divider)
{
// SOC_ROOT_CLK ---(1)---> HP_ROOT_CLK ---(2)---> AHB_CLK
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num, divider - 1);
}
/**
* @brief Get AHB_CLK's low-speed divider
*
* @return Divider. Divider = (PCR_LS_DIV_NUM + 1) * (PCR_AHB_LS_DIV_NUM + 1).
*/
static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_divider(void)
{
uint32_t ahb_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num);
uint32_t hp_root_ls_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.sysclk_conf, ls_div_num);
return (hp_root_ls_div + 1) * (ahb_div + 1);
}
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
/**
* @brief Set CPU_CLK's high-speed divider (valid when SOC_ROOT clock source is PLL)
*
@ -633,7 +514,6 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_ls_divider(
uint32_t hp_root_ls_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.sysclk_conf, ls_div_num);
return (hp_root_ls_div + 1) * (ahb_ls_div + 1);
}
#endif
/**
* @brief Set APB_CLK divider. freq of APB_CLK = freq of AHB_CLK / divider
@ -658,41 +538,6 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi
return HAL_FORCE_READ_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num) + 1;
}
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
/**
* @brief Select the clock source for MSPI_FAST_CLK
*
* @param in_sel One of the clock sources in soc_periph_mspi_clk_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_mspi_fast_set_src(soc_periph_mspi_clk_src_t in_sel)
{
switch (in_sel) {
case MSPI_CLK_SRC_XTAL:
PCR.mspi_clk_conf.mspi_func_clk_sel = 0;
break;
case MSPI_CLK_SRC_RC_FAST:
PCR.mspi_clk_conf.mspi_func_clk_sel = 1;
break;
case MSPI_CLK_SRC_SPLL:
PCR.mspi_clk_conf.mspi_func_clk_sel = 2;
break;
default:
// Unsupported MSPI_FAST_CLK mux input sel
abort();
}
}
/**
* @brief Set MSPI_FAST_CLK's divider
*
* @param divider Divider.
*/
static inline __attribute__((always_inline)) void clk_ll_mspi_fast_set_divider(uint32_t divider)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.mspi_clk_conf, mspi_fast_div_num, divider - 1);
}
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
/**
* @brief Set MSPI_FAST_CLK's high-speed divider (valid when SOC_ROOT clock source is PLL)
*
@ -746,7 +591,6 @@ static inline __attribute__((always_inline)) void clk_ll_mspi_fast_set_ls_divide
}
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.mspi_clk_conf, mspi_fast_div_num, div_num);
}
#endif
/**
* @brief Select the calibration 32kHz clock source for timergroup0
@ -799,11 +643,9 @@ static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_32k_c
static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
{
switch (in_sel) {
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
LP_CLKRST.lp_clk_conf.slow_clk_sel = 0;
break;
#endif
case SOC_RTC_SLOW_CLK_SRC_XTAL32K:
LP_CLKRST.lp_clk_conf.slow_clk_sel = 1;
break;
@ -828,10 +670,8 @@ static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_s
{
uint32_t clk_sel = LP_CLKRST.lp_clk_conf.slow_clk_sel;
switch (clk_sel) {
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
case 0:
return SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
#endif
case 1:
return SOC_RTC_SLOW_CLK_SRC_XTAL32K;
case 2:
@ -857,11 +697,6 @@ static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rt
case SOC_RTC_FAST_CLK_SRC_XTAL_D2:
LP_CLKRST.lp_clk_conf.fast_clk_sel = 1;
break;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case SOC_RTC_FAST_CLK_SRC_XTAL:
LP_CLKRST.lp_clk_conf.fast_clk_sel = 2;
break;
#endif
default:
// Unsupported RTC_FAST_CLK mux input sel
abort();
@ -881,10 +716,6 @@ static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_f
return SOC_RTC_FAST_CLK_SRC_RC_FAST;
case 1:
return SOC_RTC_FAST_CLK_SRC_XTAL_D2;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case 2:
return SOC_RTC_FAST_CLK_SRC_XTAL;
#endif
default:
return SOC_RTC_FAST_CLK_SRC_INVALID;
}
@ -998,11 +829,7 @@ Set the frequency division factor of ref_tick
*/
static inline void clk_ll_rc_fast_tick_conf(void)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
PCR.ctrl_tick_conf.fosc_tick_num = REG_FOSC_TICK_NUM;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
PCR.ctrl_32k_conf.fosc_tick_num = REG_FOSC_TICK_NUM;
#endif
}

1
components/hal/esp32c5/include/hal/ecc_ll.h
View File

@ -7,7 +7,6 @@
#include <stdbool.h>
#include <string.h>
#include "sdkconfig.h" // TODO: IDF-9197 remove
#include "hal/assert.h"
#include "hal/ecc_types.h"
#include "soc/ecc_mult_reg.h"

12
components/hal/esp32c5/include/hal/ecdsa_ll.h
View File

@ -112,11 +112,7 @@ static inline void ecdsa_ll_enable_intr(ecdsa_ll_intr_type_t type)
{
switch (type) {
case ECDSA_INT_CALC_DONE:
#if !CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 1);
#else
REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_CALC_DONE_INT_ENA, 1);
#endif
break;
case ECDSA_INT_SHA_RELEASE:
REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 1);
@ -136,11 +132,7 @@ static inline void ecdsa_ll_disable_intr(ecdsa_ll_intr_type_t type)
{
switch (type) {
case ECDSA_INT_CALC_DONE:
#if !CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 0);
#else
REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_CALC_DONE_INT_ENA, 0);
#endif
break;
case ECDSA_INT_SHA_RELEASE:
REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 0);
@ -160,11 +152,7 @@ static inline void ecdsa_ll_clear_intr(ecdsa_ll_intr_type_t type)
{
switch (type) {
case ECDSA_INT_CALC_DONE:
#if !CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_CLR, 1);
#else
REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_CALC_DONE_INT_CLR, 1);
#endif
break;
case ECDSA_INT_SHA_RELEASE:
REG_SET_FIELD(ECDSA_INT_CLR_REG, ECDSA_SHA_RELEASE_INT_CLR, 1);

6
components/hal/esp32c5/include/hal/gdma_ll.h
View File

@ -5,15 +5,9 @@
*/
#pragma once
#include "sdkconfig.h"
#include "soc/pcr_struct.h"
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
#include "hal/gdma_beta3_ll.h"
#define GDMA_LL_AHB_RX_BURST_NEEDS_ALIGNMENT 1
#else
#include "hal/ahb_dma_ll.h"
#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
#endif
#ifdef __cplusplus
extern "C" {

20
components/hal/esp32c5/include/hal/gpio_ll.h
View File

@ -16,7 +16,6 @@
#include <stdlib.h>
#include <stdbool.h>
#include "sdkconfig.h" // TODO: IDF-9197 remove
#include "soc/soc.h"
#include "soc/gpio_periph.h"
#include "soc/gpio_struct.h"
@ -28,11 +27,7 @@
#include "soc/usb_serial_jtag_struct.h"
#include "hal/gpio_types.h"
#include "hal/assert.h"
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
#include "soc/lp_io_struct.h"
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
#include "soc/lp_gpio_struct.h"
#endif
#ifdef __cplusplus
extern "C" {
@ -485,17 +480,10 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign
*/
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
// Disable USB Serial JTAG if pins 25 or pins 26 needs to select an IOMUX function
if (pin_name == IO_MUX_GPIO25_REG || pin_name == IO_MUX_GPIO26_REG) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
}
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// Disable USB Serial JTAG if pins 13 or pins 14 needs to select an IOMUX function
if (pin_name == IO_MUX_GPIO13_REG || pin_name == IO_MUX_GPIO14_REG) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
}
#endif
PIN_FUNC_SELECT(pin_name, func);
}
@ -522,19 +510,11 @@ static inline void gpio_ll_set_pin_ctrl(uint32_t val, uint32_t bmap, uint32_t sh
__attribute__((always_inline))
static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
// Disable USB Serial JTAG if pins 25 or pins 26 needs to select an IOMUX function
if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
}
IO_MUX.gpio[gpio_num].mcu_sel = func;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// Disable USB Serial JTAG if pins 13 or pins 14 needs to select an IOMUX function
if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
}
IO_MUX.gpio[gpio_num].mcu_sel = func;
#endif
}
/**

38
components/hal/esp32c5/include/hal/lp_timer_ll.h
View File

@ -33,12 +33,7 @@ extern "C" {
*/
FORCE_INLINE_ATTR void lp_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].hi, main_timer_tar_high, (value >> 32) & 0xFFFF);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].lo, main_timer_tar_low, value & 0xFFFFFFFF);
#else
HAL_ASSERT(false && "lp_timer not supported yet");
#endif
}
/**
@ -52,11 +47,7 @@ FORCE_INLINE_ATTR void lp_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t
*/
FORCE_INLINE_ATTR void lp_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->target[timer_id].hi.main_timer_tar_en = en;
#else
HAL_ASSERT(false && "lp_timer not supported yet");
#endif
}
/**
@ -69,12 +60,8 @@ FORCE_INLINE_ATTR void lp_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_
*/
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t buffer_id)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[buffer_id].lo, main_timer_buf_low);
#else
HAL_ASSERT(false && "lp_timer not supported yet");
return 0;
#endif
}
/**
@ -87,12 +74,8 @@ FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_low(lp_timer_dev_t *dev
*/
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t buffer_id)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[buffer_id].hi, main_timer_buf_high);
#else
HAL_ASSERT(false && "lp_timer not supported yet");
return 0;
#endif
}
/**
@ -104,11 +87,7 @@ FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_high(lp_timer_dev_t *de
*/
FORCE_INLINE_ATTR void lp_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->update.main_timer_update = 1;
#else
HAL_ASSERT(false && "lp_timer not supported yet");
#endif
}
/**
@ -120,11 +99,7 @@ FORCE_INLINE_ATTR void lp_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
*/
FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->int_clr.soc_wakeup_int_clr = 1;
#else
HAL_ASSERT(false && "lp_timer not supported yet");
#endif
}
/**
@ -136,11 +111,7 @@ FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev)
*/
FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->int_clr.overflow_clr = 1;
#else
HAL_ASSERT(false && "lp_timer not supported yet");
#endif
}
/**
@ -152,11 +123,7 @@ FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *de
*/
FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_alarm_intr_status(lp_timer_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->lp_int_clr.main_timer_lp_int_clr = 1;
#else
HAL_ASSERT(false && "lp_timer not supported yet");
#endif
}
/**
@ -168,13 +135,8 @@ FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_alarm_intr_status(lp_timer_dev_t *de
*/
FORCE_INLINE_ATTR uint64_t lp_timer_ll_time_to_count(uint64_t time_in_us)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
uint32_t slow_clk_value = REG_READ(LP_AON_STORE1_REG);
return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value);
#else
HAL_ASSERT(false && "lp_timer not supported yet");
return 0;
#endif
}
#ifdef __cplusplus

276
components/hal/esp32c5/include/hal/modem_lpcon_ll.h
View File

@ -10,289 +10,13 @@
#include <stdlib.h>
#include <stdbool.h>
#include "sdkconfig.h" // TODO: [ESP32C5] IDF-8845 remove
#include "soc/soc.h"
#include "hal/assert.h"
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
#include "modem/modem_lpcon_struct.h"
#include "hal/modem_clock_types.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_test_clk(modem_lpcon_dev_t *hw, bool en)
{
hw->test_conf.clk_en = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_ble_rtc_timer_slow_osc(modem_lpcon_dev_t *hw, bool en)
{
hw->lp_timer_conf.clk_lp_timer_sel_osc_slow = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_ble_rtc_timer_fast_osc(modem_lpcon_dev_t *hw, bool en)
{
hw->lp_timer_conf.clk_lp_timer_sel_osc_fast = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_ble_rtc_timer_main_xtal(modem_lpcon_dev_t *hw, bool en)
{
hw->lp_timer_conf.clk_lp_timer_sel_xtal = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(modem_lpcon_dev_t *hw, bool en)
{
hw->lp_timer_conf.clk_lp_timer_sel_xtal32k = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_set_ble_rtc_timer_divisor_value(modem_lpcon_dev_t *hw, uint32_t value)
{
hw->lp_timer_conf.clk_lp_timer_div_num = value;
}
__attribute__((always_inline))
static inline uint32_t modem_lpcon_ll_get_ble_rtc_timer_divisor_value(modem_lpcon_dev_t *hw)
{
return hw->lp_timer_conf.clk_lp_timer_div_num;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_coex_lpclk_slow_osc(modem_lpcon_dev_t *hw, bool en)
{
hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_slow = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_coex_lpclk_fast_osc(modem_lpcon_dev_t *hw, bool en)
{
hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_fast = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_coex_lpclk_main_xtal(modem_lpcon_dev_t *hw, bool en)
{
hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_coex_lpclk_32k_xtal(modem_lpcon_dev_t *hw, bool en)
{
hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal32k = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_set_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw, uint32_t value)
{
hw->coex_lp_clk_conf.clk_coex_lp_div_num = value;
}
__attribute__((always_inline))
static inline uint32_t modem_lpcon_ll_get_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw)
{
return hw->coex_lp_clk_conf.clk_coex_lp_div_num;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_wifi_lpclk_slow_osc(modem_lpcon_dev_t *hw, bool en)
{
hw->wifi_lp_clk_conf.clk_wifipwr_lp_sel_osc_slow = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_wifi_lpclk_fast_osc(modem_lpcon_dev_t *hw, bool en)
{
hw->wifi_lp_clk_conf.clk_wifipwr_lp_sel_osc_fast = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_wifi_lpclk_main_xtal(modem_lpcon_dev_t *hw, bool en)
{
hw->wifi_lp_clk_conf.clk_wifipwr_lp_sel_xtal = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_wifi_lpclk_32k_xtal(modem_lpcon_dev_t *hw, bool en)
{
hw->wifi_lp_clk_conf.clk_wifipwr_lp_sel_xtal32k = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_set_wifi_lpclk_divisor_value(modem_lpcon_dev_t *hw, uint32_t value)
{
hw->wifi_lp_clk_conf.clk_wifipwr_lp_div_num = value;
}
__attribute__((always_inline))
static inline uint32_t modem_lpcon_ll_get_wifi_lpclk_divisor_value(modem_lpcon_dev_t *hw)
{
return hw->wifi_lp_clk_conf.clk_wifipwr_lp_div_num;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_i2c_master_160m_clock(modem_lpcon_dev_t *hw, bool en)
{
hw->i2c_mst_clk_conf.clk_i2c_mst_sel_160m = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_select_modem_32k_clock_source(modem_lpcon_dev_t *hw, uint32_t src)
{
hw->modem_32k_clk_conf.clk_modem_32k_sel = src;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_wifipwr_clock(modem_lpcon_dev_t *hw, bool en)
{
hw->clk_conf.clk_wifipwr_en = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_coex_clock(modem_lpcon_dev_t *hw, bool en)
{
hw->clk_conf.clk_coex_en = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_i2c_master_clock(modem_lpcon_dev_t *hw, bool en)
{
hw->clk_conf.clk_i2c_mst_en = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_ble_rtc_timer_clock(modem_lpcon_dev_t *hw, bool en)
{
hw->clk_conf.clk_lp_timer_en = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_wifipwr_force_clock(modem_lpcon_dev_t *hw, bool en)
{
hw->clk_conf_force_on.clk_wifipwr_fo = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_coex_force_clock(modem_lpcon_dev_t *hw, bool en)
{
hw->clk_conf_force_on.clk_coex_fo = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_i2c_master_force_clock(modem_lpcon_dev_t *hw, bool en)
{
hw->clk_conf_force_on.clk_i2c_mst_fo = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_ble_rtc_timer_force_clock(modem_lpcon_dev_t *hw, bool en)
{
hw->clk_conf_force_on.clk_lp_timer_fo = en;
}
__attribute__((always_inline))
static inline uint32_t modem_lpcon_ll_get_wifipwr_icg_bitmap(modem_lpcon_dev_t *hw)
{
return hw->clk_conf_power_st.clk_wifipwr_st_map;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_set_wifipwr_icg_bitmap(modem_lpcon_dev_t *hw, uint32_t bitmap)
{
hw->clk_conf_power_st.clk_wifipwr_st_map = bitmap;
}
__attribute__((always_inline))
static inline uint32_t modem_lpcon_ll_get_coex_icg_bitmap(modem_lpcon_dev_t *hw)
{
return hw->clk_conf_power_st.clk_coex_st_map;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_set_coex_icg_bitmap(modem_lpcon_dev_t *hw, uint32_t bitmap)
{
hw->clk_conf_power_st.clk_coex_st_map = bitmap;
}
__attribute__((always_inline))
static inline uint32_t modem_lpcon_ll_get_i2c_master_icg_bitmap(modem_lpcon_dev_t *hw)
{
return hw->clk_conf_power_st.clk_i2c_mst_st_map;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_set_i2c_master_icg_bitmap(modem_lpcon_dev_t *hw, uint32_t bitmap)
{
hw->clk_conf_power_st.clk_i2c_mst_st_map = bitmap;
}
__attribute__((always_inline))
static inline uint32_t modem_lpcon_ll_get_lp_apb_icg_bitmap(modem_lpcon_dev_t *hw)
{
return hw->clk_conf_power_st.clk_lp_apb_st_map;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_set_lp_apb_icg_bitmap(modem_lpcon_dev_t *hw, uint32_t bitmap)
{
hw->clk_conf_power_st.clk_lp_apb_st_map = bitmap;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_reset_wifipwr(modem_lpcon_dev_t *hw)
{
hw->rst_conf.rst_wifipwr = 1;
hw->rst_conf.rst_wifipwr = 0;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_reset_coex(modem_lpcon_dev_t *hw)
{
hw->rst_conf.rst_coex = 1;
hw->rst_conf.rst_coex = 0;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_reset_i2c_master(modem_lpcon_dev_t *hw)
{
hw->rst_conf.rst_i2c_mst = 1;
hw->rst_conf.rst_i2c_mst = 0;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_reset_ble_rtc_timer(modem_lpcon_dev_t *hw)
{
hw->rst_conf.rst_lp_timer = 1;
hw->rst_conf.rst_lp_timer = 0;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_reset_all(modem_lpcon_dev_t *hw)
{
hw->rst_conf.val = 0xf;
hw->rst_conf.val = 0;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_set_pwr_tick_target(modem_lpcon_dev_t *hw, uint32_t val)
{
hw->tick_conf.modem_pwr_tick_target = val;
}
__attribute__((always_inline))
static inline uint32_t modem_lpcon_ll_get_date(modem_lpcon_dev_t *hw)
{
return hw->date.val;
}
#endif
#ifdef __cplusplus
}

626
components/hal/esp32c5/include/hal/modem_syscon_ll.h
View File

@ -10,639 +10,13 @@
#include <stdlib.h>
#include <stdbool.h>
#include "sdkconfig.h" // TODO: [ESP32C5] IDF-8845 remove
#include "soc/soc.h"
#include "hal/assert.h"
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
#include "modem/modem_syscon_struct.h"
#include "hal/modem_clock_types.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_test_clk(modem_syscon_dev_t *hw, bool en)
{
hw->test_conf.clk_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_data_dump_mux_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf.clk_data_dump_mux = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_etm_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf.clk_etm_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_ieee802154_apb_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf.clk_zb_apb_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_ieee802154_mac_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf.clk_zbmac_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_modem_sec_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf.clk_modem_sec_en = en;
hw->clk_conf.clk_modem_sec_ecb_en = en;
hw->clk_conf.clk_modem_sec_ccm_en = en;
hw->clk_conf.clk_modem_sec_bah_en = en;
hw->clk_conf.clk_modem_sec_apb_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_ble_timer_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf.clk_ble_timer_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_data_dump_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf.clk_data_dump_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_etm_force_clock(modem_syscon_dev_t *hw)
{
hw->clk_conf_force_on.clk_etm_fo = 1;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_ieee802154_apb_clock_force(modem_syscon_dev_t *hw)
{
hw->clk_conf_force_on.clk_zbmac_apb_fo = 1;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_ieee802154_mac_clock_force(modem_syscon_dev_t *hw)
{
hw->clk_conf_force_on.clk_zbmac_fo = 1;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_modem_sec_force_clock(modem_syscon_dev_t *hw)
{
hw->clk_conf_force_on.clk_modem_sec_fo = 1;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_ble_timer_force_clock(modem_syscon_dev_t *hw)
{
hw->clk_conf_force_on.clk_ble_timer_fo = 1;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_data_dump_force_clock(modem_syscon_dev_t *hw)
{
hw->clk_conf_force_on.clk_data_dump_fo = 1;
}
__attribute__((always_inline))
static inline uint32_t modem_syscon_ll_get_ieee802154_icg_bitmap(modem_syscon_dev_t *hw)
{
return hw->clk_conf_power_st.clk_zb_st_map;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_set_ieee802154_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap)
{
hw->clk_conf_power_st.clk_zb_st_map = bitmap;
}
__attribute__((always_inline))
static inline uint32_t modem_syscon_ll_get_fe_icg_bitmap(modem_syscon_dev_t *hw)
{
return hw->clk_conf_power_st.clk_fe_st_map;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_set_fe_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap)
{
hw->clk_conf_power_st.clk_fe_st_map = bitmap;
}
__attribute__((always_inline))
static inline uint32_t modem_syscon_ll_get_bt_icg_bitmap(modem_syscon_dev_t *hw)
{
return hw->clk_conf_power_st.clk_bt_st_map;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_set_bt_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap)
{
hw->clk_conf_power_st.clk_bt_st_map = bitmap;
}
__attribute__((always_inline))
static inline uint32_t modem_syscon_ll_get_wifi_icg_bitmap(modem_syscon_dev_t *hw)
{
return hw->clk_conf_power_st.clk_wifi_st_map;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_set_wifi_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap)
{
hw->clk_conf_power_st.clk_wifi_st_map = bitmap;
}
__attribute__((always_inline))
static inline uint32_t modem_syscon_ll_get_modem_periph_icg_bitmap(modem_syscon_dev_t *hw)
{
return hw->clk_conf_power_st.clk_modem_peri_st_map;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_set_modem_periph_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap)
{
hw->clk_conf_power_st.clk_modem_peri_st_map = bitmap;
}
__attribute__((always_inline))
static inline uint32_t modem_syscon_ll_get_modem_apb_icg_bitmap(modem_syscon_dev_t *hw)
{
return hw->clk_conf_power_st.clk_modem_apb_st_map;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_set_modem_apb_icg_bitmap(modem_syscon_dev_t *hw, uint32_t bitmap)
{
hw->clk_conf_power_st.clk_modem_apb_st_map = bitmap;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_wifibb(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_wifibb = 1;
hw->modem_rst_conf.rst_wifibb = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_wifimac(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_wifimac = 1;
hw->modem_rst_conf.rst_wifimac = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_fe(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_fe = 1;
hw->modem_rst_conf.rst_fe = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_btmac_apb(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_btmac_apb = 1;
hw->modem_rst_conf.rst_btmac_apb = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_btmac(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_btmac = 1;
hw->modem_rst_conf.rst_btmac = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_btbb_apb(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_btbb_apb = 1;
hw->modem_rst_conf.rst_btbb_apb = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_btbb(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_btbb = 1;
hw->modem_rst_conf.rst_btbb = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_etm(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_etm = 1;
hw->modem_rst_conf.rst_etm = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_zbmac(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_zbmac = 1;
hw->modem_rst_conf.rst_zbmac = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_modem_sec(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_modem_ecb = 1;
hw->modem_rst_conf.rst_modem_ccm = 1;
hw->modem_rst_conf.rst_modem_bah = 1;
hw->modem_rst_conf.rst_modem_sec = 1;
hw->modem_rst_conf.rst_modem_ecb = 0;
hw->modem_rst_conf.rst_modem_ccm = 0;
hw->modem_rst_conf.rst_modem_bah = 0;
hw->modem_rst_conf.rst_modem_sec = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_ble_timer(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_ble_timer = 1;
hw->modem_rst_conf.rst_ble_timer = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_data_dump(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.rst_data_dump = 1;
hw->modem_rst_conf.rst_data_dump = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_reset_all(modem_syscon_dev_t *hw)
{
hw->modem_rst_conf.val = 0xffffffff;
hw->modem_rst_conf.val = 0;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, bool en, uint32_t mask)
{
if(en){
hw->clk_conf1.val = hw->clk_conf1.val | mask;
} else {
hw->clk_conf1.val = hw->clk_conf1.val & ~mask;
}
}
__attribute__((always_inline))
static inline void modem_syscon_ll_clk_wifibb_configure(modem_syscon_dev_t *hw, bool en)
{
/* Configure
clk_wifibb_22m / clk_wifibb_40m / clk_wifibb_44m / clk_wifibb_80m
clk_wifibb_40x / clk_wifibb_80x / clk_wifibb_40x1 / clk_wifibb_80x1
clk_wifibb_160x1
*/
modem_syscon_ll_clk_conf1_configure(hw, en, 0x1ff);
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifibb_22m_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_wifibb_22m_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifibb_40m_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_wifibb_40m_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifibb_44m_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_wifibb_44m_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifibb_80m_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_wifibb_80m_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifibb_40x_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_wifibb_40x_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifibb_80x_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_wifibb_80x_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifibb_40x1_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_wifibb_40x1_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifibb_80x1_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_wifibb_80x1_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifibb_160x1_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_wifibb_160x1_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifibb_480m_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1.clk_wifibb_480m_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifi_mac_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_wifimac_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifi_apb_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_wifi_apb_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_20m_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_fe_20m_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_40m_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_fe_40m_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_80m_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_fe_80m_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_160m_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_fe_160m_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_apb_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_fe_apb_en = en;
}
// The modem_syscon of esp32c5beta3 adds the enablement of the adc clock on the analog front end compared to esp32h2 and esp32c6.
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_adc_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_fe_adc_en = en;
}
// The modem_syscon of esp32c5beta3 adds the enablement of the dac clock on the analog front end compared to esp32h2 and esp32c6.
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_dac_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_fe_dac_en = en;
}
// The modem_syscon of esp32c5beta3 adds the enablement of the analog power detect clock on the analog front end compared to esp32h2 and esp32c6.
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_pwdet_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_fe_pwdet_adc_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_bt_apb_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_bt_apb_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_bt_mac_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_btmac_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_bt_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf1.clk_btbb_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_480m_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1.clk_fe_480m_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_anamode_40m_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1.clk_fe_anamode_40m_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_anamode_80m_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1.clk_fe_anamode_80m_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_anamode_160m_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1.clk_fe_anamode_160m_en = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifibb_22m_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1_force_on.clk_wifibb_22m_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifibb_40m_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1_force_on.clk_wifibb_40m_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifibb_44m_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1_force_on.clk_wifibb_44m_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifibb_80m_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1_force_on.clk_wifibb_80m_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifibb_40x_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1_force_on.clk_wifibb_40x_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifibb_80x_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1_force_on.clk_wifibb_80x_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifibb_40x1_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1_force_on.clk_wifibb_40x1_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifibb_80x1_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1_force_on.clk_wifibb_80x1_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifibb_160x1_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1_force_on.clk_wifibb_160x1_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifibb_480m_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifi_mac_force_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf_force_on.clk_wifimac_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_wifi_apb_force_clock(modem_syscon_dev_t *hw, bool en)
{
hw->clk_conf_force_on.clk_wifi_apb_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_20m_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1_force_on.clk_fe_20m_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_40m_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1_force_on.clk_fe_40m_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_80m_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1_force_on.clk_fe_80m_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_160m_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1_force_on.clk_fe_160m_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_cal_160m_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1_force_on.clk_fe_cal_160m_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_apb_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1_force_on.clk_fe_apb_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_bt_apb_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1_force_on.clk_bt_apb_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_bt_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1_force_on.clk_bt_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_480m_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1_force_on.clk_fe_480m_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_anamode_40m_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1_force_on.clk_fe_anamode_40m_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_anamode_80m_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1_force_on.clk_fe_anamode_80m_fo = en;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_anamode_160m_force_clock(modem_syscon_dev_t *hw, bool en)
{
HAL_ASSERT(0 && "not implemented yet");
// hw->clk_conf1_force_on.clk_fe_anamode_160m_fo = en;
}
__attribute__((always_inline))
static inline uint32_t modem_syscon_ll_get_date(modem_syscon_dev_t *hw)
{
return hw->date.val;
}
#endif
#ifdef __cplusplus
}

104
components/hal/esp32c5/include/hal/pau_ll.h
View File

@ -34,242 +34,138 @@ static inline void pau_ll_enable_bus_clock(bool enable)
static inline uint32_t pau_ll_get_regdma_backup_flow_error(pau_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
return dev->regdma_conf.flow_err;
#else
HAL_ASSERT(false && "pau not supported yet");
return 0;
#endif
}
static inline void pau_ll_select_regdma_entry_link(pau_dev_t *dev, int link)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->regdma_conf.link_sel = link;
#else
HAL_ASSERT(false && "pau not supported yet");
#endif
}
static inline void pau_ll_set_regdma_entry_link_backup_direction(pau_dev_t *dev, bool to_mem)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->regdma_conf.to_mem = to_mem ? 1 : 0;
#else
HAL_ASSERT(false && "pau not supported yet");
#endif
}
static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->regdma_conf.start = 1;
#else
HAL_ASSERT(false && "pau not supported yet");
#endif
}
static inline void pau_ll_set_regdma_entry_link_backup_start_disable(pau_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->regdma_conf.start = 0;
#else
HAL_ASSERT(false && "pau not supported yet");
#endif
}
static inline void pau_ll_set_regdma_select_wifimac_link(pau_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->regdma_conf.sel_mac = 1;
#else
HAL_ASSERT(false && "pau not supported yet");
#endif
}
static inline void pau_ll_set_regdma_deselect_wifimac_link(pau_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->regdma_conf.sel_mac = 0;
#else
HAL_ASSERT(false && "pau not supported yet");
#endif
}
static inline void pau_ll_set_regdma_wifimac_link_backup_direction(pau_dev_t *dev, bool to_mem)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->regdma_conf.to_mem_mac = to_mem ? 1 : 0;
#else
HAL_ASSERT(false && "pau not supported yet");
#endif
}
static inline void pau_ll_set_regdma_wifimac_link_backup_start_enable(pau_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->regdma_conf.start_mac = 1;
#else
HAL_ASSERT(false && "pau not supported yet");
#endif
}
static inline void pau_ll_set_regdma_wifimac_link_backup_start_disable(pau_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->regdma_conf.start_mac = 0;
#else
HAL_ASSERT(false && "pau not supported yet");
#endif
}
static inline void pau_ll_set_regdma_link0_addr(pau_dev_t *dev, void *link_addr)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->regdma_link_0_addr.val = (uint32_t)link_addr;
#else
HAL_ASSERT(false && "pau not supported yet");
#endif
}
static inline void pau_ll_set_regdma_link1_addr(pau_dev_t *dev, void *link_addr)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->regdma_link_1_addr.val = (uint32_t)link_addr;
#else
HAL_ASSERT(false && "pau not supported yet");
#endif
}
static inline void pau_ll_set_regdma_link2_addr(pau_dev_t *dev, void *link_addr)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->regdma_link_2_addr.val = (uint32_t)link_addr;
#else
HAL_ASSERT(false && "pau not supported yet");
#endif
}
static inline void pau_ll_set_regdma_link3_addr(pau_dev_t *dev, void *link_addr)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->regdma_link_3_addr.val = (uint32_t)link_addr;
#else
HAL_ASSERT(false && "pau not supported yet");
#endif
}
static inline void pau_ll_set_regdma_wifimac_link_addr(pau_dev_t *dev, void *link_addr)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->regdma_link_mac_addr.val = (uint32_t)link_addr;
#else
HAL_ASSERT(false && "pau not supported yet");
#endif
}
static inline uint32_t pau_ll_get_regdma_current_link_addr(pau_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
return dev->regdma_current_link_addr.val;
#else
HAL_ASSERT(false && "pau not supported yet");
return 0;
#endif
}
static inline uint32_t pau_ll_get_regdma_backup_addr(pau_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
return dev->regdma_backup_addr.val;
#else
HAL_ASSERT(false && "pau not supported yet");
return 0;
#endif
}
static inline uint32_t pau_ll_get_regdma_memory_addr(pau_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
return dev->regdma_mem_addr.val;
#else
HAL_ASSERT(false && "pau not supported yet");
return 0;
#endif
}
static inline uint32_t pau_ll_get_regdma_intr_raw_signal(pau_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
return dev->int_raw.val;
#else
HAL_ASSERT(false && "pau not supported yet");
return 0;
#endif
}
static inline uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
return dev->int_st.val;
#else
HAL_ASSERT(false && "pau not supported yet");
return 0;
#endif
}
static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->int_ena.done_int_ena = 1;
#else
HAL_ASSERT(false && "pau not supported yet");
#endif
}
static inline void pau_ll_set_regdma_backup_done_intr_disable(pau_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->int_ena.done_int_ena = 0;
#else
HAL_ASSERT(false && "pau not supported yet");
#endif
}
static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->int_ena.error_int_ena = 1;
#else
HAL_ASSERT(false && "pau not supported yet");
#endif
}
static inline void pau_ll_set_regdma_backup_error_intr_disable(pau_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->int_ena.error_int_ena = 0;
#else
HAL_ASSERT(false && "pau not supported yet");
#endif
}
static inline void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->int_clr.done_int_clr = 1;
#else
HAL_ASSERT(false && "pau not supported yet");
#endif
}
static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->int_clr.error_int_clr = 1;
#else
HAL_ASSERT(false && "pau not supported yet");
#endif
}
#ifdef __cplusplus

11
components/hal/esp32c5/include/hal/spi_flash_encrypted_ll.h
View File

@ -36,15 +36,9 @@ typedef enum
*/
static inline void spi_flash_encrypt_ll_enable(void)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
REG_SET_BIT(HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT |
HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT);
#else
REG_SET_BIT(HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT |
HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT);
#endif
}
/*
@ -52,13 +46,8 @@ static inline void spi_flash_encrypt_ll_enable(void)
*/
static inline void spi_flash_encrypt_ll_disable(void)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
REG_CLR_BIT(HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT);
#else
REG_CLR_BIT(HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT);
#endif
}
/**

9
components/hal/esp32c5/include/hal/spimem_flash_ll.h
View File

@ -626,17 +626,8 @@ static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_
*/
static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
// TODO: [ESP32C5] IDF-8649
// MAY CAN IMPROVE (ONLY rc_fast case is incorrect)!
// TODO: Default is PLL480M, this is hard-coded.
// In the future, we can get the CPU clock source by calling interface.
// HAL_ASSERT(HAL_FORCE_READ_U32_REG_FIELD(PCR.mspi_clk_conf, mspi_func_clk_sel) == 2);
return 40; // Use Xtal clock source
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// TODO: [ESP32C5] IDF-8649
return 80;
#endif
}
/**

1
components/hal/esp32c5/include/hal/uart_ll.h
View File

@ -9,7 +9,6 @@
#pragma once
#include "sdkconfig.h" // TODO: IDF-9197 remove
#include "esp_attr.h"
#include "hal/misc.h"
#include "hal/uart_types.h"

7
components/hal/include/hal/modem_clock_hal.h
View File

@ -19,13 +19,6 @@
extern "C" {
#endif
#if !CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
typedef struct {
modem_syscon_dev_t *syscon_dev;
modem_lpcon_dev_t *lpcon_dev;
} modem_clock_hal_context_t;
#endif
#if !CONFIG_IDF_TARGET_ESP32H2 //TODO: PM-92
void modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap);
uint32_t modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain);

6
components/heap/port/esp32c5/memory_layout.c
View File

@ -29,9 +29,7 @@
enum {
SOC_MEMORY_TYPE_RAM = 0,
SOC_MEMORY_TYPE_RTCRAM = 1,
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
SOC_MEMORY_TYPE_SPIRAM = 2,
#endif
SOC_MEMORY_TYPE_NUM,
};
@ -52,9 +50,7 @@ const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
/* Mem Type Name High Priority Matching Medium Priority Matching Low Priority Matching */
[SOC_MEMORY_TYPE_RAM] = { "RAM", { ESP32C5_MEM_COMMON_CAPS | MALLOC_CAP_DMA, 0, 0 }},
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, ESP32C5_MEM_COMMON_CAPS, 0 }},
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
[SOC_MEMORY_TYPE_SPIRAM] = { "SPIRAM", { MALLOC_CAP_SPIRAM | MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT}},
#endif
};
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
@ -73,7 +69,7 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
const soc_memory_region_t soc_memory_regions[] = {
#if CONFIG_SPIRAM && CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
#if CONFIG_SPIRAM
{ SOC_EXTRAM_DATA_LOW, (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW), SOC_MEMORY_TYPE_SPIRAM, 0, false}, //SPI SRAM, if available
#endif
{ SOC_DIRAM_DRAM_LOW, (APP_USABLE_DRAM_END - SOC_DIRAM_DRAM_LOW), SOC_MEMORY_TYPE_RAM, SOC_DIRAM_IRAM_LOW, false}, //D/IRAM, can be used as trace memory

2
components/riscv/include/esp_private/interrupt_clic.h
View File

@ -46,7 +46,7 @@ extern "C" {
#define MTVT_CSR 0x307
#if CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
#if CONFIG_IDF_TARGET_ESP32P4
/**
* The ESP32-P4 and the beta version of the ESP32-C5 implement a non-standard version of the CLIC:

4
examples/system/light_sleep/main/gpio_wakeup.c
View File

@ -15,10 +15,8 @@
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2 \
|| CONFIG_IDF_TARGET_ESP32C6
#define BOOT_BUTTON_NUM 9
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
#elif CONFIG_IDF_TARGET_ESP32C5
#define BOOT_BUTTON_NUM 28
#elif CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
#define BOOT_BUTTON_NUM 7
#elif CONFIG_IDF_TARGET_ESP32P4
#define BOOT_BUTTON_NUM 35
#else