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fix(gpio): correct usb dp gpio pullup disable function

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This commit is contained in:
gaoxu 2024-07-05 20:45:57 +08:00
parent 5ca9f2a49a
commit 21dd9d12fa
5 changed files with 55 additions and 51 deletions
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19
components/hal/esp32c5/include/hal/gpio_ll.h
View File

@ -89,6 +89,15 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
// The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
// Note that esp32C5 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
// TODO: read the specific efuse with efuse_ll.h
if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
USB_SERIAL_JTAG.conf0.pad_pull_override = 1;
USB_SERIAL_JTAG.conf0.dp_pullup = 0;
}
IO_MUX.gpio[gpio_num].fun_wpu = 0;
}
@ -112,15 +121,7 @@ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
// The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
// Note that esp32C5 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
// TODO: read the specific efuse with efuse_ll.h
if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
USB_SERIAL_JTAG.conf0.pad_pull_override = 1;
USB_SERIAL_JTAG.conf0.dp_pullup = 0;
}
IO_MUX.gpio[gpio_num].fun_wpd = 0;
}

18
components/hal/esp32c6/include/hal/gpio_ll.h
View File

@ -90,6 +90,15 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
// The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
// Note that esp32c6 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
// TODO: read the specific efuse with efuse_ll.h
if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
}
REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
}
@ -113,15 +122,6 @@ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
// The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
// Note that esp32c6 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
// TODO: read the specific efuse with efuse_ll.h
if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
}
REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
}

19
components/hal/esp32c61/include/hal/gpio_ll.h
View File

@ -88,6 +88,15 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
// The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
// Note that esp32C61 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
// TODO: read the specific efuse with efuse_ll.h
if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
USB_SERIAL_JTAG.conf0.exchg_pins_override = 1;
USB_SERIAL_JTAG.conf0.dp_pullup = 0;
}
IO_MUX.gpion[gpio_num].gpion_fun_wpu = 0;
}
@ -111,15 +120,7 @@ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
// The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
// Note that esp32C61 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
// TODO: read the specific efuse with efuse_ll.h
if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
USB_SERIAL_JTAG.conf0.exchg_pins_override = 1;
USB_SERIAL_JTAG.conf0.dp_pullup = 0;
}
IO_MUX.gpion[gpio_num].gpion_fun_wpd = 0;
}

19
components/hal/esp32h2/include/hal/gpio_ll.h
View File

@ -90,6 +90,15 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
{
// The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
// Note that esp32h2 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
// TODO: read the specific efuse with efuse_ll.h
if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
}
REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
}
@ -113,15 +122,7 @@ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
{
// The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
// Note that esp32h2 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
// TODO: read the specific efuse with efuse_ll.h
if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
}
REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
}

31
components/hal/esp32p4/include/hal/gpio_ll.h
View File

@ -95,6 +95,22 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
// The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
// Note that esp32p4 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
// TODO: read the specific efuse with efuse_ll.h
// One more noticeable point is P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) separately.
// We only consider the default connection here: PHY0 -> USJ, PHY1 -> USB_OTG
if (gpio_num == USB_USJ_INT_PHY_DP_GPIO_NUM) {
USB_SERIAL_JTAG.conf0.pad_pull_override = 1;
USB_SERIAL_JTAG.conf0.dp_pullup = 0;
} else if (gpio_num == USB_OTG_INT_PHY_DP_GPIO_NUM) {
USB_WRAP.otg_conf.pad_pull_override = 1;
USB_WRAP.otg_conf.dp_pullup = 0;
}
IO_MUX.gpio[gpio_num].fun_wpu = 0;
}
@ -118,21 +134,6 @@ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
// The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
// Note that esp32p4 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
// TODO: read the specific efuse with efuse_ll.h
// One more noticeable point is P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) separately.
// We only consider the default connection here: PHY0 -> USJ, PHY1 -> USB_OTG
if (gpio_num == USB_USJ_INT_PHY_DP_GPIO_NUM) {
USB_SERIAL_JTAG.conf0.pad_pull_override = 1;
USB_SERIAL_JTAG.conf0.dp_pullup = 0;
} else if (gpio_num == USB_OTG_INT_PHY_DP_GPIO_NUM) {
USB_WRAP.otg_conf.pad_pull_override = 1;
USB_WRAP.otg_conf.dp_pullup = 0;
}
IO_MUX.gpio[gpio_num].fun_wpd = 0;
}