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https://github.com/espressif/esp-idf.git
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fix(usb/host): Fix USB Low Speed devices connection on P4
P4 USB UTMI PHY was updated to specification v2.0
This commit is contained in:
Tomas Rezucha
parent
a82b8565b7
commit
21c6c62087
@ -16,12 +16,27 @@
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extern "C" {
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#endif
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/* ---------------------------- USB PHY Control ---------------------------- */
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/**
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* @brief Configure Low-Speed mode
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*
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* @param[in] hw Beginning address of the peripheral registers
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* @param[in] parallel Parallel or serial LS mode
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* @return FORCE_INLINE_ATTR
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*/
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FORCE_INLINE_ATTR void usb_utmi_ll_configure_ls(usb_utmi_dev_t *hw, bool parallel)
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{
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hw->fc_06.ls_par_en = parallel;
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hw->fc_06.ls_kpalv_en = 1;
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}
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/* ----------------------------- RCC Functions ----------------------------- */
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/**
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* @brief Enable the bus clock for the USB UTMI PHY and USB_DWC_HS controller
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*
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* @param clk_en True to enable, false to disable
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* @param[in] clk_en True to enable, false to disable
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*/
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FORCE_INLINE_ATTR void usb_utmi_ll_enable_bus_clock(bool clk_en)
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{
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@ -39,8 +54,11 @@ FORCE_INLINE_ATTR void usb_utmi_ll_enable_bus_clock(bool clk_en)
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*/
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FORCE_INLINE_ATTR void usb_utmi_ll_reset_register(void)
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{
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//@todo call this function somewhere
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// Reset the USB_UTMI and USB_DWC_HS
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LP_AON_CLKRST.hp_usb_clkrst_ctrl1.rst_en_usb_otg20 = 1;
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LP_AON_CLKRST.hp_usb_clkrst_ctrl1.rst_en_usb_otg20_phy = 1;
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LP_AON_CLKRST.hp_usb_clkrst_ctrl1.rst_en_usb_otg20_phy = 0;
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LP_AON_CLKRST.hp_usb_clkrst_ctrl1.rst_en_usb_otg20 = 0;
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}
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@ -12,6 +12,11 @@
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extern "C" {
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#endif
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/**
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* Following register description is taken from
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* U2OPHYT40LL USB 2.0 OTG PHY specification v2.0
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*/
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typedef union {
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struct {
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/** clk_gate_rx : R/W; bitpos: [0]; default 2'b0;
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@ -93,38 +98,130 @@ typedef union {
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* PLL adjustment signal
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*/
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uint32_t adj_pll:4;
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/** adj_osc : R/W; bitpos: [4]; default: 2'b00
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* PLL adjustment signal
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/** adj_osc : R/W; bitpos: [4]; default: 3'b000
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* TX Clock phase adjust signal
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*/
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uint32_t adj_osc:2;
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uint32_t reserved_6:26;
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uint32_t adj_txclk_phase:3;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} usb_utmi_fc_03_reg_t;
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typedef union {
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struct {
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/** reserved_out5 : R/W; bitpos: [0]; default: 8'b0
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* RESERVED_OUT5
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/** test_sel : R/W; bitpos: [0]; default: 8'b0
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* The PHY has test_sel register here, which normally drives DTO (Digital Test Output) signal.
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* In our implementation output of this register is left floating and DTO is driven from Probe module.
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* Thus writing to this register has no effect and is renamed to 'reserved'
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*/
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uint32_t reserved_out5:8;
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uint32_t reserved:8;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} usb_utmi_fc_04_reg_t;
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typedef union {
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struct {
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/** rxgap_fix_en : R/W; bitpos: [0]; default: 1'b1
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* RXGAP fix enable
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*/
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uint32_t rxgap_fix_en:1;
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/** counter_sel : R/W; bitpos: [1]; default: 1'b0
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* SIE_input sample enable
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*/
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uint32_t counter_sel:1;
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/** clk_sel : R/W; bitpos: [2]; default: 1'b0
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* CLK60_30 source select
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*/
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uint32_t clk_sel:1;
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/** phy_mode_sel : R/W; bitpos: [3]; default: 1'b0
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* PHY MODE select
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*/
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uint32_t phy_mode_sel:1;
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/** uni_bidi_i : R/W; bitpos: [4]; default: 1'b0
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* UNI_BIDI signal
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*/
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uint32_t uni_bidi_i:1;
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/** short_5v : R/W; bitpos: [5]; default: 1'b0
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* SHORT_5V signal
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*/
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uint32_t short_5v:1;
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/** short_5v_enable : R/W; bitpos: [6]; default: 1'b1
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* SHORT_5V_ENABLE signal
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*/
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uint32_t short_5v_enable:1;
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/** usable_en : R/W; bitpos: [7]; default: 1'b1
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* compare_begin delay time select
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*/
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uint32_t usable_en:1;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} usb_utmi_fc_05_reg_t;
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typedef union {
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struct {
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/** ls_par_en : R/W; bitpos: [0]; default: 1'b0
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* LS mode with parallel enable
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*/
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uint32_t ls_par_en:1;
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/** det_fseop_en : R/W; bitpos: [1]; default: 1'b0
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* FS EOP detect enable
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*/
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uint32_t det_fseop_en:1;
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/** pre_hphy_lsie : R/W; bitpos: [2]; default: 1'b0
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* Dis_preamble enable
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*/
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uint32_t pre_hphy_lsie:1;
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/** ls_kpalv_en : R/W; bitpos: [3]; default: 1'b0
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* LS mode keep alive enable
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*/
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uint32_t ls_kpalv_en:1;
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/** hs_tx2rx_dly_cnt_sel : R/W; bitpos: [4]; default: 3'b100
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* PHY High-SPeed bus turn-around time select
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*/
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uint32_t hs_tx2rx_dly_cnt_sel:3;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} usb_utmi_fc_06_reg_t;
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typedef union {
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struct {
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/** cnt_num : R/W; bitpos: [1:0]; default: 2'b00
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* 3 ms counter select
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* 00: 392us (Default)
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* 01: 682us
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* 10: 1.36ms
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* 11: 2.72ms
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*/
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uint32_t cnt_num:2;
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/** clk480_sel : R/W; bitpos: [2]; default: 1'b0
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* CLK_480 output time select
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* 0: CLK_480 is valid after a delay time when PLL is locked
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* 1: CLK_480 is valid immediately after PLL is locked
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*/
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uint32_t clk480_sel:1;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} usb_utmi_fc_07_reg_t;
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typedef struct usb_utmi_dev_t {
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volatile usb_utmi_fc_00_reg_t fc_00;
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volatile usb_utmi_fc_01_reg_t fc_01;
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volatile usb_utmi_fc_02_reg_t fc_02;
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volatile usb_utmi_fc_03_reg_t fc_03;
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usb_utmi_fc_04_reg_t fc_04;
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volatile usb_utmi_fc_04_reg_t fc_04;
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volatile usb_utmi_fc_05_reg_t fc_05;
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volatile usb_utmi_fc_06_reg_t fc_06;
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volatile usb_utmi_fc_07_reg_t fc_07;
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} usb_utmi_dev_t;
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extern usb_utmi_dev_t USB_UTMI;
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#ifndef __cplusplus
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_Static_assert(sizeof(usb_utmi_dev_t) == 0x14, "Invalid size of usb_utmi_dev_t structure");
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_Static_assert(sizeof(usb_utmi_dev_t) == 0x20, "Invalid size of usb_utmi_dev_t structure");
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#endif
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#ifdef __cplusplus
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@ -4,13 +4,11 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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// This is only a dummy USB PHY file for successful linking of ESP32-P4 target
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// The internal HS PHY is enabled by default, therefore it needs no configuration
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// TODO: Refactor during the IDF-9198
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#include "sdkconfig.h"
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#include "soc/usb_dwc_cfg.h"
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#include "hal/usb_wrap_hal.h"
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#include "hal/usb_utmi_ll.h"
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// TODO: Remove this file when proper support of P4 PHYs is implemented IDF-7323
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#include "esp_private/usb_phy.h"
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@ -25,6 +23,7 @@ esp_err_t usb_new_phy(const usb_phy_config_t *config, usb_phy_handle_t *handle_r
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For correct detection of the device detaching, internal signal should be set to 1 by the software.
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*/
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usb_wrap_ll_enable_precise_detection();
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usb_utmi_ll_configure_ls(&USB_UTMI, true);
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#endif // CONFIG_IDF_TARGET_ESP32P4
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#endif // (OTG_HSPHY_INTERFACE != 0)
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return ESP_OK;
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