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Merge branch 'fix/bus_clear_error' into 'master'

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fix(i2c): Fix possible error state in clear the bus

Closes IDFGH-12655

See merge request espressif/esp-idf!33174
This commit is contained in:
C.S.M 2024-09-09 11:51:17 +08:00
commit 2014e5ae10
12 changed files with 190 additions and 54 deletions
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5
components/driver/i2c/i2c.c
View File

@ -684,7 +684,10 @@ static esp_err_t i2c_master_clear_bus(i2c_port_t i2c_num)
gpio_set_level(sda_io, 1); // STOP, SDA low -> high while SCL is HIGH
i2c_set_pin(i2c_num, sda_io, scl_io, 1, 1, I2C_MODE_MASTER);
#else
i2c_ll_master_clr_bus(i2c_context[i2c_num].hal.dev, I2C_CLR_BUS_SCL_NUM);
i2c_ll_master_clr_bus(i2c_context[i2c_num].hal.dev, I2C_CLR_BUS_SCL_NUM, true);
while (i2c_ll_master_is_bus_clear_done(i2c_context[i2c_num].hal.dev)) {
}
i2c_ll_update(i2c_context[i2c_num].hal.dev);
#endif
return ESP_OK;
}

30
components/esp_driver_i2c/i2c_master.c
View File

@ -46,6 +46,8 @@ static const char *TAG = "i2c.master";
#define I2C_FIFO_LEN(port_num) (SOC_I2C_FIFO_LEN)
#endif
#define I2C_CLR_BUS_TIMEOUT_MS (50) // 50ms is sufficient for clearing the bus
// Use the platform to same master bus handle
typedef struct i2c_master_bus_platform_t i2c_master_bus_platform_t;
@ -57,6 +59,7 @@ static i2c_master_bus_platform_t s_platform;
static esp_err_t s_i2c_master_clear_bus(i2c_bus_handle_t handle)
{
esp_err_t ret = ESP_OK;
#if !SOC_I2C_SUPPORT_HW_CLR_BUS
const int scl_half_period = 5; // use standard 100kHz data rate
int i = 0;
@ -83,9 +86,23 @@ static esp_err_t s_i2c_master_clear_bus(i2c_bus_handle_t handle)
i2c_common_set_pins(handle);
#else
i2c_hal_context_t *hal = &handle->hal;
i2c_ll_master_clr_bus(hal->dev, I2C_LL_RESET_SLV_SCL_PULSE_NUM_DEFAULT);
i2c_ll_master_clr_bus(hal->dev, I2C_LL_RESET_SLV_SCL_PULSE_NUM_DEFAULT, true);
// If the i2c master clear bus state machine got disturbed when its work, it would go into error state.
// The solution here is to use freertos tick counter to set time threshold. If its not return on time,
// return invalid state and turn off the state machine for avoiding its always wrong.
TickType_t start_tick = xTaskGetTickCount();
const TickType_t timeout_ticks = pdMS_TO_TICKS(I2C_CLR_BUS_TIMEOUT_MS);
while (i2c_ll_master_is_bus_clear_done(hal->dev)) {
if ((xTaskGetTickCount() - start_tick) > timeout_ticks) {
ESP_LOGE(TAG, "clear bus failed.");
i2c_ll_master_clr_bus(hal->dev, 0, false);
ret = ESP_ERR_INVALID_STATE;
break;
}
}
i2c_ll_update(hal->dev);
#endif
return ESP_OK;
return ret;
}
/**
@ -97,6 +114,7 @@ static esp_err_t s_i2c_master_clear_bus(i2c_bus_handle_t handle)
*/
static esp_err_t s_i2c_hw_fsm_reset(i2c_master_bus_handle_t i2c_master)
{
esp_err_t ret = ESP_OK;
i2c_hal_context_t *hal = &i2c_master->base->hal;
#if !SOC_I2C_SUPPORT_HW_FSM_RST
i2c_hal_timing_config_t timing_config;
@ -106,7 +124,7 @@ static esp_err_t s_i2c_hw_fsm_reset(i2c_master_bus_handle_t i2c_master)
i2c_ll_master_get_filter(hal->dev, &filter_cfg);
//to reset the I2C hw module, we need re-enable the hw
s_i2c_master_clear_bus(i2c_master->base);
ret = s_i2c_master_clear_bus(i2c_master->base);
I2C_RCC_ATOMIC() {
i2c_ll_reset_register(i2c_master->base->port_num);
}
@ -118,9 +136,9 @@ static esp_err_t s_i2c_hw_fsm_reset(i2c_master_bus_handle_t i2c_master)
i2c_ll_master_set_filter(hal->dev, filter_cfg);
#else
i2c_ll_master_fsm_rst(hal->dev);
s_i2c_master_clear_bus(i2c_master->base);
ret = s_i2c_master_clear_bus(i2c_master->base);
#endif
return ESP_OK;
return ret;
}
static void s_i2c_err_log_print(i2c_master_event_t event, bool bypass_nack_log)
@ -572,7 +590,7 @@ static esp_err_t s_i2c_transaction_start(i2c_master_dev_handle_t i2c_dev, int xf
// Sometimes when the FSM get stuck, the ACK_ERR interrupt will occur endlessly until we reset the FSM and clear bus.
esp_err_t ret = ESP_OK;
if (i2c_master->status == I2C_STATUS_TIMEOUT || i2c_ll_is_bus_busy(hal->dev)) {
s_i2c_hw_fsm_reset(i2c_master);
ESP_RETURN_ON_ERROR(s_i2c_hw_fsm_reset(i2c_master), TAG, "reset hardware failed");
}
if (i2c_master->base->pm_lock) {

24
components/hal/esp32/include/hal/i2c_ll.h
View File

@ -106,7 +106,7 @@ static inline void i2c_ll_master_set_bus_timing(i2c_dev_t *hw, i2c_hal_clk_confi
/* SCL period. According to the TRM, we should always subtract 1 to SCL low period */
HAL_ASSERT(bus_cfg->scl_low > 0);
hw->scl_low_period.period = bus_cfg->scl_low - 1;
/* Still according to the TRM, if filter is not enbled, we have to subtract 7,
/* Still according to the TRM, if filter is not enabled, we have to subtract 7,
* if SCL filter is enabled, we have to subtract:
* 8 if SCL filter is between 0 and 2 (included)
* 6 + SCL threshold if SCL filter is between 3 and 7 (included)
@ -547,7 +547,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
*
* @param hw Beginning address of the peripheral registers
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen
* @param len Amount of data needs to be written
*
* @return None.
*/
@ -612,7 +612,7 @@ static inline void i2c_ll_master_get_filter(i2c_dev_t *hw, uint8_t *filter_conf)
}
/**
* @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
* @brief Reset I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
*
* @param hw Beginning address of the peripheral registers
*
@ -633,11 +633,23 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
*
* @return None
*/
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses)
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses, bool enable)
{
;//ESP32 do not support
}
/**
* @brief Get the clear bus state
*
* @param hw Beginning address of the peripheral registers
*
* @return true: the clear bus not finish, otherwise, false.
*/
static inline bool i2c_ll_master_is_bus_clear_done(i2c_dev_t *hw)
{
return true;
}
/**
* @brief Set I2C source clock
*
@ -875,7 +887,7 @@ static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, in
* @brief Configure I2C SCL timing
*
* @param hw Beginning address of the peripheral registers
* @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
* @param high_period The I2C SCL high period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* @param wait_high_period The I2C SCL wait rising edge period.
*
@ -1058,7 +1070,7 @@ static inline uint32_t i2c_ll_get_hw_version(i2c_dev_t *hw)
* @brief Configure I2C SCL timing
*
* @param hw Beginning address of the peripheral registers
* @param hight_period The I2C SCL hight period (in APB cycle)
* @param hight_period The I2C SCL high period (in APB cycle)
* @param low_period The I2C SCL low period (in APB cycle)
*
* @return None.

21
components/hal/esp32c2/include/hal/i2c_ll.h
View File

@ -667,18 +667,29 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
*
* @param hw Beginning address of the peripheral registers
* @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out.
* @param enable True to start the state machine, otherwise, false
*
* @return None
*/
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses)
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses, bool enable)
{
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1;
hw->scl_sp_conf.scl_rst_slv_en = enable;
hw->ctr.conf_upgate = 1;
// hardware will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value.
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->ctr.conf_upgate = 1;
// and we should set conf_upgate bit to synchronize register value after this function.
}
/**
* @brief Get the clear bus state
*
* @param hw Beginning address of the peripheral registers
*
* @return true: the clear bus not finish, otherwise, false.
*/
static inline bool i2c_ll_master_is_bus_clear_done(i2c_dev_t *hw)
{
return hw->scl_sp_conf.scl_rst_slv_en;
}
/**

21
components/hal/esp32c3/include/hal/i2c_ll.h
View File

@ -790,18 +790,29 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
*
* @param hw Beginning address of the peripheral registers
* @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out.
* @param enable True to start the state machine, otherwise, false
*
* @return None
*/
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses)
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses, bool enable)
{
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1;
hw->scl_sp_conf.scl_rst_slv_en = enable;
hw->ctr.conf_upgate = 1;
// hardware will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value.
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->ctr.conf_upgate = 1;
// and we should set conf_upgate bit to synchronize register value after this function.
}
/**
* @brief Get the clear bus state
*
* @param hw Beginning address of the peripheral registers
*
* @return true: the clear bus not finish, otherwise, false.
*/
static inline bool i2c_ll_master_is_bus_clear_done(i2c_dev_t *hw)
{
return hw->scl_sp_conf.scl_rst_slv_en;
}
/**

21
components/hal/esp32c5/include/hal/i2c_ll.h
View File

@ -747,18 +747,29 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
*
* @param hw Beginning address of the peripheral registers
* @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out.
* @param enable True to start the state machine, otherwise, false
*
* @return None
*/
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses)
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses, bool enable)
{
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1;
hw->scl_sp_conf.scl_rst_slv_en = enable;
hw->ctr.conf_upgate = 1;
// hardware will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value.
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->ctr.conf_upgate = 1;
// and we should set conf_upgate bit to synchronize register value after this function.
}
/**
* @brief Get the clear bus state
*
* @param hw Beginning address of the peripheral registers
*
* @return true: the clear bus not finish, otherwise, false.
*/
static inline bool i2c_ll_master_is_bus_clear_done(i2c_dev_t *hw)
{
return hw->scl_sp_conf.scl_rst_slv_en;
}
/**

21
components/hal/esp32c6/include/hal/i2c_ll.h
View File

@ -754,18 +754,29 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
*
* @param hw Beginning address of the peripheral registers
* @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out.
* @param enable True to start the state machine, otherwise, false
*
* @return None
*/
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses)
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses, bool enable)
{
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1;
hw->scl_sp_conf.scl_rst_slv_en = enable;
hw->ctr.conf_upgate = 1;
// hardware will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value.
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->ctr.conf_upgate = 1;
// and we should set conf_upgate bit to synchronize register value after this function.
}
/**
* @brief Get the clear bus state
*
* @param hw Beginning address of the peripheral registers
*
* @return true: the clear bus not finish, otherwise, false.
*/
static inline bool i2c_ll_master_is_bus_clear_done(i2c_dev_t *hw)
{
return hw->scl_sp_conf.scl_rst_slv_en;
}
/**

21
components/hal/esp32c61/include/hal/i2c_ll.h
View File

@ -741,18 +741,29 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
*
* @param hw Beginning address of the peripheral registers
* @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out.
* @param enable True to start the state machine, otherwise, false
*
* @return None
*/
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses)
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses, bool enable)
{
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1;
hw->scl_sp_conf.scl_rst_slv_en = enable;
hw->ctr.conf_upgate = 1;
// hardware will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value.
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->ctr.conf_upgate = 1;
// and we should set conf_upgate bit to synchronize register value after this function.
}
/**
* @brief Get the clear bus state
*
* @param hw Beginning address of the peripheral registers
*
* @return true: the clear bus not finish, otherwise, false.
*/
static inline bool i2c_ll_master_is_bus_clear_done(i2c_dev_t *hw)
{
return hw->scl_sp_conf.scl_rst_slv_en;
}
/**

21
components/hal/esp32h2/include/hal/i2c_ll.h
View File

@ -740,18 +740,29 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
*
* @param hw Beginning address of the peripheral registers
* @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out.
* @param enable True to start the state machine, otherwise, false
*
* @return None
*/
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses)
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses, bool enable)
{
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1;
hw->scl_sp_conf.scl_rst_slv_en = enable;
hw->ctr.conf_upgate = 1;
// hardware will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value.
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->ctr.conf_upgate = 1;
// and we should set conf_upgate bit to synchronize register value after this function.
}
/**
* @brief Get the clear bus state
*
* @param hw Beginning address of the peripheral registers
*
* @return true: the clear bus not finish, otherwise, false.
*/
static inline bool i2c_ll_master_is_bus_clear_done(i2c_dev_t *hw)
{
return hw->scl_sp_conf.scl_rst_slv_en;
}
/**

21
components/hal/esp32p4/include/hal/i2c_ll.h
View File

@ -742,18 +742,29 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
*
* @param hw Beginning address of the peripheral registers
* @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out.
* @param enable True to start the state machine, otherwise, false
*
* @return None
*/
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses)
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses, bool enable)
{
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1;
hw->scl_sp_conf.scl_rst_slv_en = enable;
hw->ctr.conf_upgate = 1;
// hardware will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value.
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->ctr.conf_upgate = 1;
// and we should set conf_upgate bit to synchronize register value after this function.
}
/**
* @brief Get the clear bus state
*
* @param hw Beginning address of the peripheral registers
*
* @return true: the clear bus not finish, otherwise, false.
*/
static inline bool i2c_ll_master_is_bus_clear_done(i2c_dev_t *hw)
{
return hw->scl_sp_conf.scl_rst_slv_en;
}
/**

23
components/hal/esp32s2/include/hal/i2c_ll.h
View File

@ -573,7 +573,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
*
* @param hw Beginning address of the peripheral registers
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen
* @param len Amount of data needs to be written
*
* @return None.
*/
@ -658,16 +658,29 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
*
* @param hw Beginning address of the peripheral registers
* @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out.
* @param enable True to start the state machine, otherwise, false
*
* @return None
*/
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses)
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses, bool enable)
{
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 0;
hw->scl_sp_conf.scl_rst_slv_en = 1;
}
/**
* @brief Get the clear bus state
*
* @param hw Beginning address of the peripheral registers
*
* @return true: the clear bus not finish, otherwise, false.
*/
static inline bool i2c_ll_master_is_bus_clear_done(i2c_dev_t *hw)
{
return true; // not supported on esp32s2
}
/**
* @brief Set I2C source clock
*
@ -717,7 +730,7 @@ static inline void i2c_ll_master_init(i2c_dev_t *hw)
* Otherwise it is not needed.
*
* @param hw Beginning address of the peripheral registers
* @param internal_od_ena Set true to enble internal open-drain, otherwise, set it false.
* @param internal_od_ena Set true to enable internal open-drain, otherwise, set it false.
*
* @return None
*/
@ -908,7 +921,7 @@ typedef enum {
* @brief Configure I2C SCL timing
*
* @param hw Beginning address of the peripheral registers
* @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
* @param high_period The I2C SCL high period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* @param wait_high_period The I2C SCL wait rising edge period.
*
@ -1096,7 +1109,7 @@ static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw)
* @brief Configure I2C SCL timing
*
* @param hw Beginning address of the peripheral registers
* @param hight_period The I2C SCL hight period (in APB cycle, hight_period > 2)
* @param hight_period The I2C SCL high period (in APB cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in APB cycle, low_period > 1)
*
* @return None.

15
components/hal/esp32s3/include/hal/i2c_ll.h
View File

@ -797,16 +797,29 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
*
* @param hw Beginning address of the peripheral registers
* @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out.
* @param enable True to start the state machine, otherwise, false
*
* @return None
*/
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses)
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses, bool enable)
{
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1;
hw->ctr.conf_upgate = 1;
}
/**
* @brief Get the clear bus state
*
* @param hw Beginning address of the peripheral registers
*
* @return true: the clear bus not finish, otherwise, false.
*/
static inline bool i2c_ll_master_is_bus_clear_done(i2c_dev_t *hw)
{
return true; // not supported on esp32s3
}
/**
* @brief Set I2C source clock
*