mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
feat(gdma): support hardware crc calculation
On ESP32-P4, the GDMA peripherals support CRC calculating.
This commit is contained in:
morris
parent
a5748580d6
commit
200eb866dc
@ -257,7 +257,7 @@ esp_err_t gdma_connect(gdma_channel_handle_t dma_chan, gdma_trigger_t trig_perip
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gdma_group_t *group = pair->group;
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gdma_hal_context_t *hal = &group->hal;
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bool periph_conflict = false;
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//
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if (trig_periph.bus_id != SOC_GDMA_BUS_ANY) {
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ESP_RETURN_ON_FALSE(trig_periph.bus_id == group->bus_id, ESP_ERR_INVALID_ARG, TAG,
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"peripheral and DMA system bus mismatch");
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@ -404,6 +404,57 @@ esp_err_t gdma_set_priority(gdma_channel_handle_t dma_chan, uint32_t priority)
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return ESP_OK;
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}
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#if SOC_GDMA_SUPPORT_CRC
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esp_err_t gdma_config_crc_calculator(gdma_channel_handle_t dma_chan, const gdma_crc_calculator_config_t *config)
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{
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ESP_RETURN_ON_FALSE(dma_chan && config, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
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gdma_pair_t *pair = dma_chan->pair;
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gdma_group_t *group = pair->group;
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gdma_hal_context_t *hal = &group->hal;
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switch (group->bus_id) {
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#if SOC_AHB_GDMA_SUPPORTED
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case SOC_GDMA_BUS_AHB:
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ESP_RETURN_ON_FALSE(config->crc_bit_width <= GDMA_LL_AHB_MAX_CRC_BIT_WIDTH, ESP_ERR_INVALID_ARG, TAG, "invalid crc bit width");
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break;
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#endif // SOC_AHB_GDMA_SUPPORTED
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#if SOC_AXI_GDMA_SUPPORTED
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case SOC_GDMA_BUS_AXI:
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ESP_RETURN_ON_FALSE(config->crc_bit_width <= GDMA_LL_AXI_MAX_CRC_BIT_WIDTH, ESP_ERR_INVALID_ARG, TAG, "invalid crc bit width");
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break;
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#endif // SOC_AXI_GDMA_SUPPORTED
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default:
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ESP_LOGE(TAG, "invalid bus id: %d", group->bus_id);
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return ESP_ERR_INVALID_ARG;
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}
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// clear the previous CRC result
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gdma_hal_clear_crc(hal, pair->pair_id, dma_chan->direction);
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// set polynomial and initial value
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gdma_hal_crc_config_t hal_config = {
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.crc_bit_width = config->crc_bit_width,
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.poly_hex = config->poly_hex,
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.init_value = config->init_value,
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.reverse_data_mask = config->reverse_data_mask,
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};
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gdma_hal_set_crc_poly(hal, pair->pair_id, dma_chan->direction, &hal_config);
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return ESP_OK;
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}
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esp_err_t gdma_crc_get_result(gdma_channel_handle_t dma_chan, uint32_t *result)
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{
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ESP_RETURN_ON_FALSE(dma_chan && result, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
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gdma_pair_t *pair = dma_chan->pair;
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gdma_group_t *group = pair->group;
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gdma_hal_context_t *hal = &group->hal;
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*result = gdma_hal_get_crc_result(hal, pair->pair_id, dma_chan->direction);
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return ESP_OK;
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}
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#endif // SOC_GDMA_SUPPORT_CRC
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esp_err_t gdma_register_tx_event_callbacks(gdma_channel_handle_t dma_chan, gdma_tx_event_callbacks_t *cbs, void *user_data)
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{
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ESP_RETURN_ON_FALSE(dma_chan && cbs && dma_chan->direction == GDMA_CHANNEL_DIRECTION_TX, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
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@ -354,6 +354,7 @@ esp_err_t gdma_append(gdma_channel_handle_t dma_chan);
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*/
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esp_err_t gdma_reset(gdma_channel_handle_t dma_chan);
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#if SOC_GDMA_SUPPORT_ETM
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/**
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* @brief GDMA ETM event configuration
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*/
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@ -400,6 +401,7 @@ typedef struct {
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* - ESP_FAIL: Get ETM task failed because of other error
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*/
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esp_err_t gdma_new_etm_task(gdma_channel_handle_t dma_chan, const gdma_etm_task_config_t *config, esp_etm_task_handle_t *out_task);
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#endif // SOC_GDMA_SUPPORT_ETM
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/**
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* @brief Get the mask of free M2M trigger IDs
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@ -417,6 +419,47 @@ esp_err_t gdma_new_etm_task(gdma_channel_handle_t dma_chan, const gdma_etm_task_
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*/
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esp_err_t gdma_get_free_m2m_trig_id_mask(gdma_channel_handle_t dma_chan, uint32_t *mask);
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#if SOC_GDMA_SUPPORT_CRC
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/**
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* @brief CRC Calculator configuration
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*/
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typedef struct {
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uint32_t init_value; /*!< CRC initial value */
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uint32_t crc_bit_width; /*!< CRC bit width */
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uint32_t poly_hex; /*!< Polynomial Formula, in hex */
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bool reverse_data_mask; /*!< Reverse data mask, used when you want to reverse the input data (a.k.a, refin) */
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} gdma_crc_calculator_config_t;
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/**
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* @brief Configure CRC Calculator
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*
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* @note This function must be called before `gdma_start`.
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* @note The CRC Calculator will reset itself automatically if the DMA stops and starts again.
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*
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* @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel`
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* @param[in] config CRC Calculator configuration
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* @return
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* - ESP_OK: Configure CRC Calculator successfully
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* - ESP_ERR_INVALID_ARG: Configure CRC Calculator failed because of invalid argument
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* - ESP_FAIL: Configure CRC Calculator failed because of other error
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*/
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esp_err_t gdma_config_crc_calculator(gdma_channel_handle_t dma_chan, const gdma_crc_calculator_config_t *config);
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/**
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* @brief Get CRC Calculator result
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*
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* @note You need to call this function before a new DMA transaction starts, otherwise the CRC results may be overridden.
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*
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* @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel`
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* @param[out] result Returned CRC result
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* @return
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* - ESP_OK: Get CRC result successfully
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* - ESP_ERR_INVALID_ARG: Get CRC result failed because of invalid argument
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* - ESP_FAIL: Get CRC result failed because of other error
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*/
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esp_err_t gdma_crc_get_result(gdma_channel_handle_t dma_chan, uint32_t *result);
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#endif // SOC_GDMA_SUPPORT_CRC
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#ifdef __cplusplus
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}
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#endif
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@ -4,6 +4,7 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include <inttypes.h>
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#include "sdkconfig.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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@ -299,3 +300,117 @@ TEST_CASE("GDMA M2M Mode", "[GDMA]")
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TEST_ESP_OK(gdma_del_channel(rx_chan));
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#endif // SOC_AXI_GDMA_SUPPORTED
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}
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#if SOC_GDMA_SUPPORT_CRC
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typedef struct {
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uint32_t init_value;
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uint32_t crc_bit_width;
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uint32_t poly_hex;
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bool reverse_data_mask;
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uint32_t expected_result;
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} test_crc_case_t;
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static test_crc_case_t crc_test_cases[] = {
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// CRC8, x^8+x^2+x+1
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[0] = {
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.crc_bit_width = 8,
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.init_value = 0x00,
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.poly_hex = 0x07,
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.expected_result = 0xC6,
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},
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[1] = {
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.crc_bit_width = 8,
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.init_value = 0x00,
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.poly_hex = 0x07,
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.reverse_data_mask = true, // refin = true
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.expected_result = 0xDE,
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},
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// CRC16, x^16+x^12+x^5+1
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[2] = {
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.crc_bit_width = 16,
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.init_value = 0xFFFF,
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.poly_hex = 0x1021,
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.expected_result = 0x5289,
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},
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// CRC32, x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
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[3] = {
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.crc_bit_width = 32,
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.init_value = 0xFFFFFFFF,
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.poly_hex = 0x04C11DB7,
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.expected_result = 0x63B3E283,
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}
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};
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// CRC online: https://www.lddgo.net/en/encrypt/crc
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static void test_gdma_crc_calculation(gdma_channel_handle_t tx_chan, int test_num_crc_algorithm)
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{
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uint32_t crc_result = 0;
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const char *test_input_string = "Share::Connect::Innovate";
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size_t input_data_size = strlen(test_input_string);
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printf("Calculate CRC value for string: \"%s\"\r\n", test_input_string);
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gdma_trigger_t m2m_trigger = GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0);
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// get a free DMA trigger ID
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uint32_t free_m2m_id_mask = 0;
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gdma_get_free_m2m_trig_id_mask(tx_chan, &free_m2m_id_mask);
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m2m_trigger.instance_id = __builtin_ctz(free_m2m_id_mask);
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TEST_ESP_OK(gdma_connect(tx_chan, m2m_trigger));
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uint8_t *src_buf = heap_caps_aligned_calloc(64, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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TEST_ASSERT_NOT_NULL(src_buf);
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dma_descriptor_align8_t *tx_descs = (dma_descriptor_align8_t *) src_buf;
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uint8_t *src_data = src_buf + 64;
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memcpy(src_data, test_input_string, input_data_size);
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tx_descs->buffer = src_data;
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tx_descs->dw0.size = 256 - 64;
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tx_descs->dw0.length = input_data_size;
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tx_descs->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
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tx_descs->dw0.suc_eof = 1;
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tx_descs->next = NULL;
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#if CONFIG_IDF_TARGET_ESP32P4
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// do write-back for the buffer because it's in the cache
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Cache_WriteBack_Addr(CACHE_MAP_L1_DCACHE, (uint32_t)src_buf, 256);
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#endif
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for (int i = 0; i < test_num_crc_algorithm; i++) {
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gdma_crc_calculator_config_t crc_config = {
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.crc_bit_width = crc_test_cases[i].crc_bit_width,
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.init_value = crc_test_cases[i].init_value,
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.poly_hex = crc_test_cases[i].poly_hex,
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.reverse_data_mask = crc_test_cases[i].reverse_data_mask,
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};
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TEST_ESP_OK(gdma_config_crc_calculator(tx_chan, &crc_config));
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TEST_ESP_OK(gdma_reset(tx_chan));
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TEST_ESP_OK(gdma_start(tx_chan, (intptr_t)tx_descs));
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// simply wait for the transfer done
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vTaskDelay(pdMS_TO_TICKS(100));
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TEST_ESP_OK(gdma_crc_get_result(tx_chan, &crc_result));
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printf("CRC Result: 0x%"PRIx32"\r\n", crc_result);
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TEST_ASSERT_EQUAL(crc_test_cases[i].expected_result, crc_result);
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}
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free(src_buf);
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}
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TEST_CASE("GDMA CRC Calculation", "[GDMA]")
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{
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gdma_channel_handle_t tx_chan = NULL;
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gdma_channel_alloc_config_t tx_chan_alloc_config = {
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.direction = GDMA_CHANNEL_DIRECTION_TX,
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};
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#if SOC_AHB_GDMA_SUPPORTED
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printf("Test CRC calculation for AHB GDMA\r\n");
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TEST_ESP_OK(gdma_new_ahb_channel(&tx_chan_alloc_config, &tx_chan));
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test_gdma_crc_calculation(tx_chan, 4);
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TEST_ESP_OK(gdma_del_channel(tx_chan));
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#endif // SOC_AHB_GDMA_SUPPORTED
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#if SOC_AXI_GDMA_SUPPORTED
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printf("Test CRC calculation for AXI GDMA\r\n");
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TEST_ESP_OK(gdma_new_axi_channel(&tx_chan_alloc_config, &tx_chan));
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test_gdma_crc_calculation(tx_chan, 3);
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TEST_ESP_OK(gdma_del_channel(tx_chan));
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#endif // SOC_AXI_GDMA_SUPPORTED
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}
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#endif // SOC_GDMA_SUPPORT_CRC
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@ -91,6 +91,10 @@ if(NOT BOOTLOADER_BUILD)
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list(APPEND srcs "gdma_hal_top.c")
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endif()
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if(CONFIG_SOC_GDMA_SUPPORT_CRC)
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list(APPEND srcs "gdma_hal_crc_gen.c")
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endif()
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if(CONFIG_SOC_AHB_GDMA_VERSION EQUAL 1)
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list(APPEND srcs "gdma_hal_ahb_v1.c")
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endif()
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@ -8,6 +8,8 @@
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#include <stddef.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "hal/assert.h"
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#include "hal/misc.h"
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#include "hal/gdma_types.h"
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#include "hal/gdma_ll.h"
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#include "soc/ahb_dma_struct.h"
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@ -500,6 +502,128 @@ static inline void ahb_dma_ll_tx_enable_etm_task(ahb_dma_dev_t *dev, uint32_t ch
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dev->channel[channel].out.out_conf0.out_etm_en_chn = enable;
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}
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///////////////////////////////////// CRC-TX /////////////////////////////////////////
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/**
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* @brief Clear the CRC result for the TX channel
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*/
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static inline void ahb_dma_ll_tx_crc_clear(ahb_dma_dev_t *dev, uint32_t channel)
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{
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dev->out_crc[channel].crc_clear.out_crc_clear_chn_reg = 1;
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dev->out_crc[channel].crc_clear.out_crc_clear_chn_reg = 0;
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}
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/**
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* @brief Set CRC width for TX channel
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*/
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static inline void ahb_dma_ll_tx_crc_set_width(ahb_dma_dev_t *dev, uint32_t channel, uint32_t width)
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{
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HAL_ASSERT(width <= 32);
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dev->out_crc[channel].crc_width.tx_crc_width_chn = (width - 1) / 8;
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}
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/**
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* @brief Set CRC initial value for TX channel
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*/
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static inline void ahb_dma_ll_tx_crc_set_init_value(ahb_dma_dev_t *dev, uint32_t channel, uint32_t value)
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{
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dev->out_crc[channel].crc_init_data.out_crc_init_data_chn = value;
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}
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/**
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* @brief Get CRC result for TX channel
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*/
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static inline uint32_t ahb_dma_ll_tx_crc_get_result(ahb_dma_dev_t *dev, uint32_t channel)
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{
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return dev->out_crc[channel].crc_final_result.out_crc_final_result_chn;
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}
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/**
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* @brief Latch the CRC configuration to the hardware, TX channel
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*/
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static inline void ahb_dma_ll_tx_crc_latch_config(ahb_dma_dev_t *dev, uint32_t channel)
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{
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dev->out_crc[channel].crc_width.tx_crc_latch_flag_chn = 1;
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dev->out_crc[channel].crc_width.tx_crc_latch_flag_chn = 0;
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}
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/**
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* @brief Set the lfsr and data mask that used by the Parallel CRC calculation formula for a given CRC bit, TX channel
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*/
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static inline void ahb_dma_ll_tx_crc_set_lfsr_data_mask(ahb_dma_dev_t *dev, uint32_t channel, uint32_t crc_bit,
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uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask)
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{
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dev->out_crc[channel].crc_en_addr.tx_crc_en_addr_chn = crc_bit;
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dev->out_crc[channel].crc_en_wr_data.tx_crc_en_wr_data_chn = lfsr_mask;
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dev->out_crc[channel].crc_data_en_addr.tx_crc_data_en_addr_chn = crc_bit;
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if (reverse_data_mask) {
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// "& 0xff" because the hardware only support 8-bit data
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data_mask = _bitwise_reverse(data_mask & 0xFF);
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}
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HAL_FORCE_MODIFY_U32_REG_FIELD(dev->out_crc[channel].crc_data_en_wr_data, tx_crc_data_en_wr_data_chn, data_mask);
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}
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///////////////////////////////////// CRC-RX /////////////////////////////////////////
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/**
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* @brief Clear the CRC result for the RX channel
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*/
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static inline void ahb_dma_ll_rx_crc_clear(ahb_dma_dev_t *dev, uint32_t channel)
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{
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dev->in_crc[channel].crc_clear.in_crc_clear_chn_reg = 1;
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dev->in_crc[channel].crc_clear.in_crc_clear_chn_reg = 0;
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}
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/**
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* @brief Set CRC width for RX channel
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*/
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static inline void ahb_dma_ll_rx_crc_set_width(ahb_dma_dev_t *dev, uint32_t channel, uint32_t width)
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{
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HAL_ASSERT(width <= 32);
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dev->in_crc[channel].crc_width.rx_crc_width_chn = (width - 1) / 8;
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}
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/**
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* @brief Set CRC initial value for RX channel
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*/
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static inline void ahb_dma_ll_rx_crc_set_init_value(ahb_dma_dev_t *dev, uint32_t channel, uint32_t value)
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{
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dev->in_crc[channel].crc_init_data.in_crc_init_data_chn = value;
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}
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/**
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* @brief Get CRC result for RX channel
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*/
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static inline uint32_t ahb_dma_ll_rx_crc_get_result(ahb_dma_dev_t *dev, uint32_t channel)
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{
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return dev->in_crc[channel].crc_final_result.in_crc_final_result_chn;
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}
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/**
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||||
* @brief Latch the CRC configuration to the hardware, RX channel
|
||||
*/
|
||||
static inline void ahb_dma_ll_rx_crc_latch_config(ahb_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->in_crc[channel].crc_width.rx_crc_latch_flag_chn = 1;
|
||||
dev->in_crc[channel].crc_width.rx_crc_latch_flag_chn = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the lfsr and data mask that used by the Parallel CRC calculation formula for a given CRC bit, RX channel
|
||||
*/
|
||||
static inline void ahb_dma_ll_rx_crc_set_lfsr_data_mask(ahb_dma_dev_t *dev, uint32_t channel, uint32_t crc_bit,
|
||||
uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask)
|
||||
{
|
||||
dev->in_crc[channel].crc_en_addr.rx_crc_en_addr_chn = crc_bit;
|
||||
dev->in_crc[channel].crc_en_wr_data.rx_crc_en_wr_data_chn = lfsr_mask;
|
||||
dev->in_crc[channel].crc_data_en_addr.rx_crc_data_en_addr_chn = crc_bit;
|
||||
if (reverse_data_mask) {
|
||||
// "& 0xff" because the hardware only support 8-bit data
|
||||
data_mask = _bitwise_reverse(data_mask & 0xFF);
|
||||
}
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->in_crc[channel].crc_data_en_wr_data, rx_crc_data_en_wr_data_chn, data_mask);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -8,6 +8,8 @@
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "hal/assert.h"
|
||||
#include "hal/misc.h"
|
||||
#include "hal/gdma_types.h"
|
||||
#include "hal/gdma_ll.h"
|
||||
#include "soc/axi_dma_struct.h"
|
||||
@ -446,6 +448,128 @@ static inline void axi_dma_ll_tx_enable_etm_task(axi_dma_dev_t *dev, uint32_t ch
|
||||
dev->out[channel].conf.out_conf0.out_etm_en_chn = enable;
|
||||
}
|
||||
|
||||
///////////////////////////////////// CRC-TX /////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Clear the CRC result for the TX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_crc_clear(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->out[channel].crc.out_crc_clear.out_crc_clear_chn_reg = 1;
|
||||
dev->out[channel].crc.out_crc_clear.out_crc_clear_chn_reg = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC width for TX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_crc_set_width(axi_dma_dev_t *dev, uint32_t channel, uint32_t width)
|
||||
{
|
||||
HAL_ASSERT(width <= 16);
|
||||
dev->out[channel].crc.tx_crc_width.tx_crc_width_chn = (width - 1) / 8;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC initial value for TX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_crc_set_init_value(axi_dma_dev_t *dev, uint32_t channel, uint32_t value)
|
||||
{
|
||||
dev->out[channel].crc.out_crc_init_data.out_crc_init_data_chn = value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC result for TX channel
|
||||
*/
|
||||
static inline uint32_t axi_dma_ll_tx_crc_get_result(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->out[channel].crc.out_crc_final_result.out_crc_final_result_chn;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Latch the CRC configuration to the hardware, TX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_crc_latch_config(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->out[channel].crc.tx_crc_width.tx_crc_latch_flag_chn = 1;
|
||||
dev->out[channel].crc.tx_crc_width.tx_crc_latch_flag_chn = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the lfsr and data mask that used by the Parallel CRC calculation formula for a given CRC bit, TX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_tx_crc_set_lfsr_data_mask(axi_dma_dev_t *dev, uint32_t channel, uint32_t crc_bit,
|
||||
uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask)
|
||||
{
|
||||
dev->out[channel].crc.tx_crc_en_addr.tx_crc_en_addr_chn = crc_bit;
|
||||
dev->out[channel].crc.tx_crc_en_wr_data.tx_crc_en_wr_data_chn = lfsr_mask;
|
||||
dev->out[channel].crc.tx_crc_data_en_addr.tx_crc_data_en_addr_chn = crc_bit;
|
||||
if (reverse_data_mask) {
|
||||
// "& 0xff" because the hardware only support 8-bit data
|
||||
data_mask = _bitwise_reverse(data_mask & 0xFF);
|
||||
}
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->out[channel].crc.tx_crc_data_en_wr_data, tx_crc_data_en_wr_data_chn, data_mask);
|
||||
}
|
||||
|
||||
///////////////////////////////////// CRC-RX /////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Clear the CRC result for the RX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_crc_clear(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->in[channel].crc.in_crc_clear.in_crc_clear_chn_reg = 1;
|
||||
dev->in[channel].crc.in_crc_clear.in_crc_clear_chn_reg = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC width for RX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_crc_set_width(axi_dma_dev_t *dev, uint32_t channel, uint32_t width)
|
||||
{
|
||||
HAL_ASSERT(width <= 16);
|
||||
dev->in[channel].crc.rx_crc_width.rx_crc_width_chn = (width - 1) / 8;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set CRC initial value for RX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_crc_set_init_value(axi_dma_dev_t *dev, uint32_t channel, uint32_t value)
|
||||
{
|
||||
dev->in[channel].crc.in_crc_init_data.in_crc_init_data_chn = value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC result for RX channel
|
||||
*/
|
||||
static inline uint32_t axi_dma_ll_rx_crc_get_result(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->in[channel].crc.in_crc_final_result.in_crc_final_result_chn;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Latch the CRC configuration to the hardware, RX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_crc_latch_config(axi_dma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->in[channel].crc.rx_crc_width.rx_crc_latch_flag_chn = 1;
|
||||
dev->in[channel].crc.rx_crc_width.rx_crc_latch_flag_chn = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the lfsr and data mask that used by the Parallel CRC calculation formula for a given CRC bit, RX channel
|
||||
*/
|
||||
static inline void axi_dma_ll_rx_crc_set_lfsr_data_mask(axi_dma_dev_t *dev, uint32_t channel, uint32_t crc_bit,
|
||||
uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask)
|
||||
{
|
||||
dev->in[channel].crc.rx_crc_en_addr.rx_crc_en_addr_chn = crc_bit;
|
||||
dev->in[channel].crc.rx_crc_en_wr_data.rx_crc_en_wr_data_chn = lfsr_mask;
|
||||
dev->in[channel].crc.rx_crc_data_en_addr.rx_crc_data_en_addr_chn = crc_bit;
|
||||
if (reverse_data_mask) {
|
||||
// "& 0xff" because the hardware only support 8-bit data
|
||||
data_mask = _bitwise_reverse(data_mask & 0xFF);
|
||||
}
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->in[channel].crc.rx_crc_data_en_wr_data, rx_crc_data_en_wr_data_chn, data_mask);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -10,6 +10,8 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
@ -40,6 +42,19 @@ extern "C" {
|
||||
#define GDMA_LL_AXI_NUM_GROUPS 1 // Number of AXI GDMA groups
|
||||
#define GDMA_LL_AXI_PAIRS_PER_GROUP 3 // Number of GDMA pairs in each AXI group
|
||||
|
||||
#define GDMA_LL_PARALLEL_CRC_DATA_WIDTH 8 // Parallel CRC data width is fixed to 8bits
|
||||
#define GDMA_LL_AHB_MAX_CRC_BIT_WIDTH 32 // Max CRC bit width supported by AHB GDMA
|
||||
#define GDMA_LL_AXI_MAX_CRC_BIT_WIDTH 16 // Max CRC bit width supported by AXI GDMA
|
||||
|
||||
__attribute__((always_inline))
|
||||
static inline uint8_t _bitwise_reverse(uint8_t n)
|
||||
{
|
||||
n = ((n & 0xf0) >> 4) | ((n & 0x0f) << 4);
|
||||
n = ((n & 0xcc) >> 2) | ((n & 0x33) << 2);
|
||||
n = ((n & 0xaa) >> 1) | ((n & 0x55) << 1);
|
||||
return n;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -150,9 +150,66 @@ uint32_t gdma_ahb_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gd
|
||||
}
|
||||
}
|
||||
|
||||
#if SOC_GDMA_SUPPORT_CRC
|
||||
void gdma_ahb_hal_clear_crc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
ahb_dma_ll_rx_crc_clear(hal->ahb_dma_dev, chan_id);
|
||||
} else {
|
||||
ahb_dma_ll_tx_crc_clear(hal->ahb_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_ahb_hal_set_crc_poly(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, const gdma_hal_crc_config_t *config)
|
||||
{
|
||||
uint32_t init_value = config->init_value;
|
||||
uint32_t crc_bit_width = config->crc_bit_width;
|
||||
uint32_t poly_hex = config->poly_hex;
|
||||
// bit matrix for parallel CRC
|
||||
uint32_t lfsr_matrix[crc_bit_width];
|
||||
uint32_t data_matrix[GDMA_LL_PARALLEL_CRC_DATA_WIDTH];
|
||||
uint32_t lfsr_mask = 0;
|
||||
uint32_t data_mask = 0;
|
||||
// build the parallel CRC matrix first, later we will extract the control mask from it
|
||||
gdma_hal_build_parallel_crc_matrix(crc_bit_width, poly_hex, GDMA_LL_PARALLEL_CRC_DATA_WIDTH,
|
||||
lfsr_matrix, data_matrix);
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
ahb_dma_ll_rx_crc_set_init_value(hal->ahb_dma_dev, chan_id, init_value);
|
||||
ahb_dma_ll_rx_crc_set_width(hal->ahb_dma_dev, chan_id, crc_bit_width);
|
||||
for (uint32_t i = 0; i < crc_bit_width; i++) {
|
||||
// extract the control mask from the matrix, for each CRC bit
|
||||
data_mask = gdma_hal_get_data_mask_from_matrix(data_matrix, GDMA_LL_PARALLEL_CRC_DATA_WIDTH, i);
|
||||
lfsr_mask = gdma_hal_get_lfsr_mask_from_matrix(lfsr_matrix, crc_bit_width, i);
|
||||
ahb_dma_ll_rx_crc_set_lfsr_data_mask(hal->ahb_dma_dev, chan_id, i, lfsr_mask, data_mask, config->reverse_data_mask);
|
||||
ahb_dma_ll_rx_crc_latch_config(hal->ahb_dma_dev, chan_id);
|
||||
}
|
||||
} else {
|
||||
ahb_dma_ll_tx_crc_set_init_value(hal->ahb_dma_dev, chan_id, init_value);
|
||||
ahb_dma_ll_tx_crc_set_width(hal->ahb_dma_dev, chan_id, crc_bit_width);
|
||||
for (uint32_t i = 0; i < crc_bit_width; i++) {
|
||||
// extract the control mask from the matrix, for each CRC bit
|
||||
data_mask = gdma_hal_get_data_mask_from_matrix(data_matrix, GDMA_LL_PARALLEL_CRC_DATA_WIDTH, i);
|
||||
lfsr_mask = gdma_hal_get_lfsr_mask_from_matrix(lfsr_matrix, crc_bit_width, i);
|
||||
ahb_dma_ll_tx_crc_set_lfsr_data_mask(hal->ahb_dma_dev, chan_id, i, lfsr_mask, data_mask, config->reverse_data_mask);
|
||||
ahb_dma_ll_tx_crc_latch_config(hal->ahb_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t gdma_ahb_hal_get_crc_result(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
return ahb_dma_ll_rx_crc_get_result(hal->ahb_dma_dev, chan_id);
|
||||
} else {
|
||||
return ahb_dma_ll_tx_crc_get_result(hal->ahb_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
#endif // SOC_GDMA_SUPPORT_CRC
|
||||
|
||||
void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
|
||||
{
|
||||
hal->ahb_dma_dev = AHB_DMA_LL_GET_HW(config->group_id - GDMA_LL_AHB_GROUP_START_ID);
|
||||
hal->priv_data = &gdma_ahb_hal_priv_data;
|
||||
hal->start_with_desc = gdma_ahb_hal_start_with_desc;
|
||||
hal->stop = gdma_ahb_hal_stop;
|
||||
hal->append = gdma_ahb_hal_append;
|
||||
@ -167,5 +224,9 @@ void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
|
||||
hal->read_intr_status = gdma_ahb_hal_read_intr_status;
|
||||
hal->get_intr_status_reg = gdma_ahb_hal_get_intr_status_reg;
|
||||
hal->get_eof_desc_addr = gdma_ahb_hal_get_eof_desc_addr;
|
||||
hal->priv_data = &gdma_ahb_hal_priv_data;
|
||||
#if SOC_GDMA_SUPPORT_CRC
|
||||
hal->clear_crc = gdma_ahb_hal_clear_crc;
|
||||
hal->set_crc_poly = gdma_ahb_hal_set_crc_poly;
|
||||
hal->get_crc_result = gdma_ahb_hal_get_crc_result;
|
||||
#endif // SOC_GDMA_SUPPORT_CRC
|
||||
}
|
||||
|
||||
@ -150,9 +150,66 @@ uint32_t gdma_axi_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gd
|
||||
}
|
||||
}
|
||||
|
||||
#if SOC_GDMA_SUPPORT_CRC
|
||||
void gdma_axi_hal_clear_crc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
axi_dma_ll_rx_crc_clear(hal->axi_dma_dev, chan_id);
|
||||
} else {
|
||||
axi_dma_ll_tx_crc_clear(hal->axi_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
|
||||
void gdma_axi_hal_set_crc_poly(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, const gdma_hal_crc_config_t *config)
|
||||
{
|
||||
uint32_t init_value = config->init_value;
|
||||
uint32_t crc_bit_width = config->crc_bit_width;
|
||||
uint32_t poly_hex = config->poly_hex;
|
||||
// bit matrix for parallel CRC
|
||||
uint32_t lfsr_matrix[crc_bit_width];
|
||||
uint32_t data_matrix[GDMA_LL_PARALLEL_CRC_DATA_WIDTH];
|
||||
uint32_t lfsr_mask = 0;
|
||||
uint32_t data_mask = 0;
|
||||
// build the parallel CRC matrix first, later we will extract the control mask from it
|
||||
gdma_hal_build_parallel_crc_matrix(crc_bit_width, poly_hex, GDMA_LL_PARALLEL_CRC_DATA_WIDTH,
|
||||
lfsr_matrix, data_matrix);
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
axi_dma_ll_rx_crc_set_init_value(hal->axi_dma_dev, chan_id, init_value);
|
||||
axi_dma_ll_rx_crc_set_width(hal->axi_dma_dev, chan_id, crc_bit_width);
|
||||
for (uint32_t i = 0; i < crc_bit_width; i++) {
|
||||
// extract the control mask from the matrix, for each CRC bit
|
||||
data_mask = gdma_hal_get_data_mask_from_matrix(data_matrix, GDMA_LL_PARALLEL_CRC_DATA_WIDTH, i);
|
||||
lfsr_mask = gdma_hal_get_lfsr_mask_from_matrix(lfsr_matrix, crc_bit_width, i);
|
||||
axi_dma_ll_rx_crc_set_lfsr_data_mask(hal->axi_dma_dev, chan_id, i, lfsr_mask, data_mask, config->reverse_data_mask);
|
||||
axi_dma_ll_rx_crc_latch_config(hal->axi_dma_dev, chan_id);
|
||||
}
|
||||
} else {
|
||||
axi_dma_ll_tx_crc_set_init_value(hal->axi_dma_dev, chan_id, init_value);
|
||||
axi_dma_ll_tx_crc_set_width(hal->axi_dma_dev, chan_id, crc_bit_width);
|
||||
for (uint32_t i = 0; i < crc_bit_width; i++) {
|
||||
// extract the control mask from the matrix, for each CRC bit
|
||||
data_mask = gdma_hal_get_data_mask_from_matrix(data_matrix, GDMA_LL_PARALLEL_CRC_DATA_WIDTH, i);
|
||||
lfsr_mask = gdma_hal_get_lfsr_mask_from_matrix(lfsr_matrix, crc_bit_width, i);
|
||||
axi_dma_ll_tx_crc_set_lfsr_data_mask(hal->axi_dma_dev, chan_id, i, lfsr_mask, data_mask, config->reverse_data_mask);
|
||||
axi_dma_ll_tx_crc_latch_config(hal->axi_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t gdma_axi_hal_get_crc_result(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
|
||||
{
|
||||
if (dir == GDMA_CHANNEL_DIRECTION_RX) {
|
||||
return axi_dma_ll_rx_crc_get_result(hal->axi_dma_dev, chan_id);
|
||||
} else {
|
||||
return axi_dma_ll_tx_crc_get_result(hal->axi_dma_dev, chan_id);
|
||||
}
|
||||
}
|
||||
#endif // SOC_GDMA_SUPPORT_CRC
|
||||
|
||||
void gdma_axi_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
|
||||
{
|
||||
hal->axi_dma_dev = AXI_DMA_LL_GET_HW(config->group_id - GDMA_LL_AXI_GROUP_START_ID);
|
||||
hal->priv_data = &gdma_axi_hal_priv_data;
|
||||
hal->start_with_desc = gdma_axi_hal_start_with_desc;
|
||||
hal->stop = gdma_axi_hal_stop;
|
||||
hal->append = gdma_axi_hal_append;
|
||||
@ -167,5 +224,9 @@ void gdma_axi_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
|
||||
hal->read_intr_status = gdma_axi_hal_read_intr_status;
|
||||
hal->get_intr_status_reg = gdma_axi_hal_get_intr_status_reg;
|
||||
hal->get_eof_desc_addr = gdma_axi_hal_get_eof_desc_addr;
|
||||
hal->priv_data = &gdma_axi_hal_priv_data;
|
||||
#if SOC_GDMA_SUPPORT_CRC
|
||||
hal->clear_crc = gdma_axi_hal_clear_crc;
|
||||
hal->set_crc_poly = gdma_axi_hal_set_crc_poly;
|
||||
hal->get_crc_result = gdma_axi_hal_get_crc_result;
|
||||
#endif // SOC_GDMA_SUPPORT_CRC
|
||||
}
|
||||
|
||||
87
components/hal/gdma_hal_crc_gen.c
Normal file
87
components/hal/gdma_hal_crc_gen.c
Normal file
@ -0,0 +1,87 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
//
|
||||
// Serially shift {data_in,lfsr_cur} N times to get {lfsr_next}
|
||||
//
|
||||
static uint32_t lfsr_serial_shift_crc(uint32_t data_in, uint32_t lfsr_cur,
|
||||
size_t crc_width, uint32_t crc_poly_hex,
|
||||
size_t num_bits_to_shift)
|
||||
{
|
||||
uint32_t lfsr_next = lfsr_cur;
|
||||
|
||||
for (int j = 0; j < num_bits_to_shift; j++) {
|
||||
uint32_t lfsr_upper_bit = lfsr_next >> (crc_width - 1);
|
||||
|
||||
// shift the entire LFSR
|
||||
for (int i = crc_width - 1; i > 0; i--) {
|
||||
lfsr_next &= ~(1 << i);
|
||||
if (crc_poly_hex & (1 << i)) {
|
||||
// lfsr_next[i] = lfsr_next[i - 1] ^ lfsr_upper_bit ^ data_in[j];
|
||||
lfsr_next |= (((lfsr_next >> (i - 1)) ^ lfsr_upper_bit ^ (data_in >> j)) & 0x01) << i;
|
||||
} else {
|
||||
// lfsr_next[i] = lfsr_next[i - 1];
|
||||
lfsr_next |= (lfsr_next & (1 << (i - 1))) << 1;
|
||||
}
|
||||
}
|
||||
// lfsr_next[0] = lfsr_upper_bit ^ data_in[j];
|
||||
lfsr_next &= ~0x01;
|
||||
lfsr_next |= (lfsr_upper_bit ^ (data_in >> j)) & 0x01;
|
||||
}
|
||||
|
||||
return lfsr_next;
|
||||
}
|
||||
|
||||
void gdma_hal_build_parallel_crc_matrix(int crc_width, uint32_t crc_poly_hex, int data_width,
|
||||
uint32_t *lfsr_transform_matrix, uint32_t *data_transform_matrix)
|
||||
{
|
||||
int N = crc_width;
|
||||
int M = data_width;
|
||||
uint32_t lfsr_cur = 0; // N-bit LFSR
|
||||
uint32_t lfsr_next = 0; // N-bit LFSR
|
||||
uint32_t data_in = 0; // M-bit data
|
||||
|
||||
// LFSR-2-LFSR matrix[NxN], data_in=0
|
||||
for (int n1 = 0; n1 < N; n1++) {
|
||||
lfsr_cur = 1 << n1;
|
||||
lfsr_next = lfsr_serial_shift_crc(data_in, lfsr_cur,
|
||||
crc_width, crc_poly_hex,
|
||||
data_width);
|
||||
lfsr_transform_matrix[n1] = lfsr_next;
|
||||
}
|
||||
|
||||
// Data-2-LFSR matrix[MxN], lfsr_cur=0
|
||||
lfsr_cur = 0;
|
||||
for (int m1 = 0; m1 < M; m1++) {
|
||||
data_in = 1 << m1;
|
||||
lfsr_next = lfsr_serial_shift_crc(data_in, lfsr_cur,
|
||||
crc_width, crc_poly_hex,
|
||||
data_width);
|
||||
// Invert CRC data bits
|
||||
data_transform_matrix[M - m1 - 1] = lfsr_next;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t gdma_hal_get_data_mask_from_matrix(uint32_t *data_transform_matrix, int data_width, int crc_bit)
|
||||
{
|
||||
uint32_t data_mask = 0;
|
||||
for (int j = 0; j < data_width; j++) {
|
||||
data_mask |= (data_transform_matrix[j] & (1 << crc_bit)) ? (1 << j) : 0;
|
||||
}
|
||||
return data_mask;
|
||||
}
|
||||
|
||||
uint32_t gdma_hal_get_lfsr_mask_from_matrix(uint32_t *lfsr_transform_matrix, int crc_width, int crc_bit)
|
||||
{
|
||||
uint32_t lfsr_mask = 0;
|
||||
for (int j = 0; j < crc_width; j++) {
|
||||
lfsr_mask |= (lfsr_transform_matrix[j] & (1 << crc_bit)) ? (1 << j) : 0;
|
||||
}
|
||||
return lfsr_mask;
|
||||
}
|
||||
@ -89,3 +89,20 @@ uint32_t gdma_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gdma_c
|
||||
{
|
||||
return hal->get_eof_desc_addr(hal, chan_id, dir, is_success);
|
||||
}
|
||||
|
||||
#if SOC_GDMA_SUPPORT_CRC
|
||||
void gdma_hal_clear_crc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
|
||||
{
|
||||
hal->clear_crc(hal, chan_id, dir);
|
||||
}
|
||||
|
||||
void gdma_hal_set_crc_poly(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, const gdma_hal_crc_config_t *config)
|
||||
{
|
||||
hal->set_crc_poly(hal, chan_id, dir, config);
|
||||
}
|
||||
|
||||
uint32_t gdma_hal_get_crc_result(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
|
||||
{
|
||||
return hal->get_crc_result(hal, chan_id, dir);
|
||||
}
|
||||
#endif // SOC_GDMA_SUPPORT_CRC
|
||||
|
||||
@ -36,6 +36,13 @@ typedef struct {
|
||||
int group_id; /*!< GDMA group ID */
|
||||
} gdma_hal_config_t;
|
||||
|
||||
typedef struct {
|
||||
uint32_t init_value; /*!< CRC initial value */
|
||||
uint32_t crc_bit_width; /*!< CRC bit width */
|
||||
uint32_t poly_hex; /*!< Polynomial Formula, in hex */
|
||||
bool reverse_data_mask; /*!< Reverse data mask */
|
||||
} gdma_hal_crc_config_t;
|
||||
|
||||
/**
|
||||
* @brief GDMA HAL private data
|
||||
*/
|
||||
@ -80,6 +87,11 @@ struct gdma_hal_context_t {
|
||||
void (*clear_intr)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask); /// Clear the channel interrupt
|
||||
uint32_t (*read_intr_status)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); /// Read the channel interrupt status
|
||||
uint32_t (*get_eof_desc_addr)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool is_success); /// Get the address of the descriptor with success/error EOF flag set
|
||||
#if SOC_GDMA_SUPPORT_CRC
|
||||
void (*clear_crc)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); /// Clear the CRC interim results
|
||||
void (*set_crc_poly)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, const gdma_hal_crc_config_t *config); /// Set the CRC polynomial
|
||||
uint32_t (*get_crc_result)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); /// Get the CRC result
|
||||
#endif // SOC_GDMA_SUPPORT_CRC
|
||||
};
|
||||
|
||||
void gdma_hal_deinit(gdma_hal_context_t *hal);
|
||||
@ -114,6 +126,21 @@ uint32_t gdma_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_ch
|
||||
|
||||
uint32_t gdma_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool is_success);
|
||||
|
||||
#if SOC_GDMA_SUPPORT_CRC
|
||||
void gdma_hal_build_parallel_crc_matrix(int crc_width, uint32_t crc_poly_hex, int data_width,
|
||||
uint32_t *lfsr_transform_matrix, uint32_t *data_transform_matrix);
|
||||
|
||||
uint32_t gdma_hal_get_data_mask_from_matrix(uint32_t *data_transform_matrix, int data_width, int crc_bit);
|
||||
|
||||
uint32_t gdma_hal_get_lfsr_mask_from_matrix(uint32_t *lfsr_transform_matrix, int crc_width, int crc_bit);
|
||||
|
||||
void gdma_hal_clear_crc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
|
||||
|
||||
void gdma_hal_set_crc_poly(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, const gdma_hal_crc_config_t *config);
|
||||
|
||||
uint32_t gdma_hal_get_crc_result(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir);
|
||||
#endif // SOC_GDMA_SUPPORT_CRC
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -247,6 +247,10 @@ config SOC_AHB_GDMA_VERSION
|
||||
int
|
||||
default 2
|
||||
|
||||
config SOC_GDMA_SUPPORT_CRC
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_GDMA_NUM_GROUPS_MAX
|
||||
int
|
||||
default 2
|
||||
|
||||
@ -3124,7 +3124,7 @@ extern "C" {
|
||||
#define AHB_DMA_OUT_CRC_INIT_DATA_CH0_S 0
|
||||
|
||||
/** AHB_DMA_TX_CRC_WIDTH_CH0_REG register
|
||||
* This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width
|
||||
* This register is used to config tx ch0 crc result width,2'b00 mean crc_width
|
||||
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
|
||||
* 24<crc_width<=32
|
||||
*/
|
||||
@ -3136,13 +3136,13 @@ extern "C" {
|
||||
#define AHB_DMA_TX_CRC_WIDTH_CH0_M (AHB_DMA_TX_CRC_WIDTH_CH0_V << AHB_DMA_TX_CRC_WIDTH_CH0_S)
|
||||
#define AHB_DMA_TX_CRC_WIDTH_CH0_V 0x00000003U
|
||||
#define AHB_DMA_TX_CRC_WIDTH_CH0_S 0
|
||||
/** AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0 : R/W; bitpos: [2]; default: 0;
|
||||
/** AHB_DMA_TX_CRC_LATCH_FLAG_CH0 : R/W; bitpos: [2]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0 (BIT(2))
|
||||
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0_M (AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0_V << AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0_S)
|
||||
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0_V 0x00000001U
|
||||
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0_S 2
|
||||
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH0 (BIT(2))
|
||||
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH0_M (AHB_DMA_TX_CRC_LATCH_FLAG_CH0_V << AHB_DMA_TX_CRC_LATCH_FLAG_CH0_S)
|
||||
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH0_V 0x00000001U
|
||||
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH0_S 2
|
||||
|
||||
/** AHB_DMA_OUT_CRC_CLEAR_CH0_REG register
|
||||
* This register is used to clear ch0 crc result
|
||||
@ -3253,7 +3253,7 @@ extern "C" {
|
||||
#define AHB_DMA_OUT_CRC_INIT_DATA_CH1_S 0
|
||||
|
||||
/** AHB_DMA_TX_CRC_WIDTH_CH1_REG register
|
||||
* This register is used to confiig tx ch1 crc result width,2'b00 mean crc_width
|
||||
* This register is used to config tx ch1 crc result width,2'b00 mean crc_width
|
||||
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
|
||||
* 24<crc_width<=32
|
||||
*/
|
||||
@ -3265,13 +3265,13 @@ extern "C" {
|
||||
#define AHB_DMA_TX_CRC_WIDTH_CH1_M (AHB_DMA_TX_CRC_WIDTH_CH1_V << AHB_DMA_TX_CRC_WIDTH_CH1_S)
|
||||
#define AHB_DMA_TX_CRC_WIDTH_CH1_V 0x00000003U
|
||||
#define AHB_DMA_TX_CRC_WIDTH_CH1_S 0
|
||||
/** AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1 : R/W; bitpos: [2]; default: 0;
|
||||
/** AHB_DMA_TX_CRC_LATCH_FLAG_CH1 : R/W; bitpos: [2]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1 (BIT(2))
|
||||
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1_M (AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1_V << AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1_S)
|
||||
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1_V 0x00000001U
|
||||
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1_S 2
|
||||
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH1 (BIT(2))
|
||||
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH1_M (AHB_DMA_TX_CRC_LATCH_FLAG_CH1_V << AHB_DMA_TX_CRC_LATCH_FLAG_CH1_S)
|
||||
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH1_V 0x00000001U
|
||||
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH1_S 2
|
||||
|
||||
/** AHB_DMA_OUT_CRC_CLEAR_CH1_REG register
|
||||
* This register is used to clear ch1 crc result
|
||||
@ -3382,7 +3382,7 @@ extern "C" {
|
||||
#define AHB_DMA_OUT_CRC_INIT_DATA_CH2_S 0
|
||||
|
||||
/** AHB_DMA_TX_CRC_WIDTH_CH2_REG register
|
||||
* This register is used to confiig tx ch2 crc result width,2'b00 mean crc_width
|
||||
* This register is used to config tx ch2 crc result width,2'b00 mean crc_width
|
||||
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
|
||||
* 24<crc_width<=32
|
||||
*/
|
||||
@ -3394,13 +3394,13 @@ extern "C" {
|
||||
#define AHB_DMA_TX_CRC_WIDTH_CH2_M (AHB_DMA_TX_CRC_WIDTH_CH2_V << AHB_DMA_TX_CRC_WIDTH_CH2_S)
|
||||
#define AHB_DMA_TX_CRC_WIDTH_CH2_V 0x00000003U
|
||||
#define AHB_DMA_TX_CRC_WIDTH_CH2_S 0
|
||||
/** AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2 : R/W; bitpos: [2]; default: 0;
|
||||
/** AHB_DMA_TX_CRC_LATCH_FLAG_CH2 : R/W; bitpos: [2]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2 (BIT(2))
|
||||
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2_M (AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2_V << AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2_S)
|
||||
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2_V 0x00000001U
|
||||
#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2_S 2
|
||||
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH2 (BIT(2))
|
||||
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH2_M (AHB_DMA_TX_CRC_LATCH_FLAG_CH2_V << AHB_DMA_TX_CRC_LATCH_FLAG_CH2_S)
|
||||
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH2_V 0x00000001U
|
||||
#define AHB_DMA_TX_CRC_LATCH_FLAG_CH2_S 2
|
||||
|
||||
/** AHB_DMA_OUT_CRC_CLEAR_CH2_REG register
|
||||
* This register is used to clear ch2 crc result
|
||||
@ -3511,7 +3511,7 @@ extern "C" {
|
||||
#define AHB_DMA_IN_CRC_INIT_DATA_CH0_S 0
|
||||
|
||||
/** AHB_DMA_RX_CRC_WIDTH_CH0_REG register
|
||||
* This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width
|
||||
* This register is used to config rx ch0 crc result width,2'b00 mean crc_width
|
||||
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
|
||||
* 24<crc_width<=32
|
||||
*/
|
||||
@ -3523,13 +3523,13 @@ extern "C" {
|
||||
#define AHB_DMA_RX_CRC_WIDTH_CH0_M (AHB_DMA_RX_CRC_WIDTH_CH0_V << AHB_DMA_RX_CRC_WIDTH_CH0_S)
|
||||
#define AHB_DMA_RX_CRC_WIDTH_CH0_V 0x00000003U
|
||||
#define AHB_DMA_RX_CRC_WIDTH_CH0_S 0
|
||||
/** AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0 : R/W; bitpos: [2]; default: 0;
|
||||
/** AHB_DMA_RX_CRC_LATCH_FLAG_CH0 : R/W; bitpos: [2]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0 (BIT(2))
|
||||
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0_M (AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0_V << AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0_S)
|
||||
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0_V 0x00000001U
|
||||
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0_S 2
|
||||
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH0 (BIT(2))
|
||||
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH0_M (AHB_DMA_RX_CRC_LATCH_FLAG_CH0_V << AHB_DMA_RX_CRC_LATCH_FLAG_CH0_S)
|
||||
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH0_V 0x00000001U
|
||||
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH0_S 2
|
||||
|
||||
/** AHB_DMA_IN_CRC_CLEAR_CH0_REG register
|
||||
* This register is used to clear ch0 crc result
|
||||
@ -3640,7 +3640,7 @@ extern "C" {
|
||||
#define AHB_DMA_IN_CRC_INIT_DATA_CH1_S 0
|
||||
|
||||
/** AHB_DMA_RX_CRC_WIDTH_CH1_REG register
|
||||
* This register is used to confiig rx ch1 crc result width,2'b00 mean crc_width
|
||||
* This register is used to config rx ch1 crc result width,2'b00 mean crc_width
|
||||
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
|
||||
* 24<crc_width<=32
|
||||
*/
|
||||
@ -3652,13 +3652,13 @@ extern "C" {
|
||||
#define AHB_DMA_RX_CRC_WIDTH_CH1_M (AHB_DMA_RX_CRC_WIDTH_CH1_V << AHB_DMA_RX_CRC_WIDTH_CH1_S)
|
||||
#define AHB_DMA_RX_CRC_WIDTH_CH1_V 0x00000003U
|
||||
#define AHB_DMA_RX_CRC_WIDTH_CH1_S 0
|
||||
/** AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1 : R/W; bitpos: [2]; default: 0;
|
||||
/** AHB_DMA_RX_CRC_LATCH_FLAG_CH1 : R/W; bitpos: [2]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1 (BIT(2))
|
||||
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1_M (AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1_V << AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1_S)
|
||||
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1_V 0x00000001U
|
||||
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1_S 2
|
||||
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH1 (BIT(2))
|
||||
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH1_M (AHB_DMA_RX_CRC_LATCH_FLAG_CH1_V << AHB_DMA_RX_CRC_LATCH_FLAG_CH1_S)
|
||||
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH1_V 0x00000001U
|
||||
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH1_S 2
|
||||
|
||||
/** AHB_DMA_IN_CRC_CLEAR_CH1_REG register
|
||||
* This register is used to clear ch1 crc result
|
||||
@ -3769,7 +3769,7 @@ extern "C" {
|
||||
#define AHB_DMA_IN_CRC_INIT_DATA_CH2_S 0
|
||||
|
||||
/** AHB_DMA_RX_CRC_WIDTH_CH2_REG register
|
||||
* This register is used to confiig rx ch2 crc result width,2'b00 mean crc_width
|
||||
* This register is used to config rx ch2 crc result width,2'b00 mean crc_width
|
||||
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
|
||||
* 24<crc_width<=32
|
||||
*/
|
||||
@ -3781,13 +3781,13 @@ extern "C" {
|
||||
#define AHB_DMA_RX_CRC_WIDTH_CH2_M (AHB_DMA_RX_CRC_WIDTH_CH2_V << AHB_DMA_RX_CRC_WIDTH_CH2_S)
|
||||
#define AHB_DMA_RX_CRC_WIDTH_CH2_V 0x00000003U
|
||||
#define AHB_DMA_RX_CRC_WIDTH_CH2_S 0
|
||||
/** AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2 : R/W; bitpos: [2]; default: 0;
|
||||
/** AHB_DMA_RX_CRC_LATCH_FLAG_CH2 : R/W; bitpos: [2]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2 (BIT(2))
|
||||
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2_M (AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2_V << AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2_S)
|
||||
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2_V 0x00000001U
|
||||
#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2_S 2
|
||||
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH2 (BIT(2))
|
||||
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH2_M (AHB_DMA_RX_CRC_LATCH_FLAG_CH2_V << AHB_DMA_RX_CRC_LATCH_FLAG_CH2_S)
|
||||
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH2_V 0x00000001U
|
||||
#define AHB_DMA_RX_CRC_LATCH_FLAG_CH2_S 2
|
||||
|
||||
/** AHB_DMA_IN_CRC_CLEAR_CH2_REG register
|
||||
* This register is used to clear ch2 crc result
|
||||
|
||||
@ -583,7 +583,7 @@ typedef union {
|
||||
} ahb_dma_out_crc_init_data_chn_reg_t;
|
||||
|
||||
/** Type of tx_crc_width_chn register
|
||||
* This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width
|
||||
* This register is used to config tx ch0 crc result width,2'b00 mean crc_width
|
||||
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
|
||||
* 24<crc_width<=32
|
||||
*/
|
||||
@ -593,10 +593,10 @@ typedef union {
|
||||
* reserved
|
||||
*/
|
||||
uint32_t tx_crc_width_chn: 2;
|
||||
/** tx_crc_lautch_flga_chn : R/W; bitpos: [2]; default: 0;
|
||||
/** tx_crc_latch_flag_chn : R/W; bitpos: [2]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t tx_crc_lautch_flga_chn: 1;
|
||||
uint32_t tx_crc_latch_flag_chn: 1;
|
||||
uint32_t reserved_3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
@ -724,7 +724,7 @@ typedef union {
|
||||
} ahb_dma_in_crc_init_data_chn_reg_t;
|
||||
|
||||
/** Type of rx_crc_width_chn register
|
||||
* This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width
|
||||
* This register is used to config rx ch0 crc result width,2'b00 mean crc_width
|
||||
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
|
||||
* 24<crc_width<=32
|
||||
*/
|
||||
@ -734,10 +734,10 @@ typedef union {
|
||||
* reserved
|
||||
*/
|
||||
uint32_t rx_crc_width_chn: 2;
|
||||
/** rx_crc_lautch_flga_chn : R/W; bitpos: [2]; default: 0;
|
||||
/** rx_crc_latch_flag_chn : R/W; bitpos: [2]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t rx_crc_lautch_flga_chn: 1;
|
||||
uint32_t rx_crc_latch_flag_chn: 1;
|
||||
uint32_t reserved_3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
@ -1350,7 +1350,7 @@ typedef struct {
|
||||
ahb_dma_in_crc_init_data_chn_reg_t crc_init_data;
|
||||
ahb_dma_rx_crc_width_chn_reg_t crc_width;
|
||||
ahb_dma_in_crc_clear_chn_reg_t crc_clear;
|
||||
ahb_dma_in_crc_final_result_chn_reg_t crc_final;
|
||||
ahb_dma_in_crc_final_result_chn_reg_t crc_final_result;
|
||||
ahb_dma_rx_crc_en_wr_data_chn_reg_t crc_en_wr_data;
|
||||
ahb_dma_rx_crc_en_addr_chn_reg_t crc_en_addr;
|
||||
ahb_dma_rx_crc_data_en_wr_data_chn_reg_t crc_data_en_wr_data;
|
||||
@ -1369,7 +1369,7 @@ typedef struct {
|
||||
ahb_dma_tx_crc_data_en_wr_data_chn_reg_t crc_data_en_wr_data;
|
||||
ahb_dma_tx_crc_data_en_addr_chn_reg_t crc_data_en_addr;
|
||||
ahb_dma_tx_ch_arb_weigh_chn_reg_t ch_arb_weigh;
|
||||
ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t arb_weigh_opt_dir;
|
||||
ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t arb_weigh_opt;
|
||||
} ahb_dma_out_crc_chn_reg_t;
|
||||
|
||||
typedef struct {
|
||||
|
||||
@ -803,7 +803,7 @@ extern "C" {
|
||||
#define AXI_DMA_IN_CRC_INIT_DATA_CH0_S 0
|
||||
|
||||
/** AXI_DMA_RX_CRC_WIDTH_CH0_REG register
|
||||
* This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width
|
||||
* This register is used to config rx ch0 crc result width,2'b00 mean crc_width
|
||||
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
|
||||
* 24<crc_width<=32
|
||||
*/
|
||||
@ -815,13 +815,13 @@ extern "C" {
|
||||
#define AXI_DMA_RX_CRC_WIDTH_CH0_M (AXI_DMA_RX_CRC_WIDTH_CH0_V << AXI_DMA_RX_CRC_WIDTH_CH0_S)
|
||||
#define AXI_DMA_RX_CRC_WIDTH_CH0_V 0x00000003U
|
||||
#define AXI_DMA_RX_CRC_WIDTH_CH0_S 0
|
||||
/** AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0 : R/W; bitpos: [2]; default: 0;
|
||||
/** AXI_DMA_RX_CRC_LATCH_FLAG_CH0 : R/W; bitpos: [2]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0 (BIT(2))
|
||||
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_M (AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_V << AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_S)
|
||||
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_V 0x00000001U
|
||||
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_S 2
|
||||
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH0 (BIT(2))
|
||||
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH0_M (AXI_DMA_RX_CRC_LATCH_FLAG_CH0_V << AXI_DMA_RX_CRC_LATCH_FLAG_CH0_S)
|
||||
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH0_V 0x00000001U
|
||||
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH0_S 2
|
||||
|
||||
/** AXI_DMA_IN_CRC_CLEAR_CH0_REG register
|
||||
* This register is used to clear ch0 crc result
|
||||
@ -1687,7 +1687,7 @@ extern "C" {
|
||||
#define AXI_DMA_IN_CRC_INIT_DATA_CH1_S 0
|
||||
|
||||
/** AXI_DMA_RX_CRC_WIDTH_CH1_REG register
|
||||
* This register is used to confiig rx ch1 crc result width,2'b00 mean crc_width
|
||||
* This register is used to config rx ch1 crc result width,2'b00 mean crc_width
|
||||
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
|
||||
* 24<crc_width<=32
|
||||
*/
|
||||
@ -1699,13 +1699,13 @@ extern "C" {
|
||||
#define AXI_DMA_RX_CRC_WIDTH_CH1_M (AXI_DMA_RX_CRC_WIDTH_CH1_V << AXI_DMA_RX_CRC_WIDTH_CH1_S)
|
||||
#define AXI_DMA_RX_CRC_WIDTH_CH1_V 0x00000003U
|
||||
#define AXI_DMA_RX_CRC_WIDTH_CH1_S 0
|
||||
/** AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1 : R/W; bitpos: [2]; default: 0;
|
||||
/** AXI_DMA_RX_CRC_LATCH_FLAG_CH1 : R/W; bitpos: [2]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1 (BIT(2))
|
||||
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_M (AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_V << AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_S)
|
||||
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_V 0x00000001U
|
||||
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_S 2
|
||||
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH1 (BIT(2))
|
||||
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH1_M (AXI_DMA_RX_CRC_LATCH_FLAG_CH1_V << AXI_DMA_RX_CRC_LATCH_FLAG_CH1_S)
|
||||
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH1_V 0x00000001U
|
||||
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH1_S 2
|
||||
|
||||
/** AXI_DMA_IN_CRC_CLEAR_CH1_REG register
|
||||
* This register is used to clear ch1 crc result
|
||||
@ -2571,7 +2571,7 @@ extern "C" {
|
||||
#define AXI_DMA_IN_CRC_INIT_DATA_CH2_S 0
|
||||
|
||||
/** AXI_DMA_RX_CRC_WIDTH_CH2_REG register
|
||||
* This register is used to confiig rx ch2 crc result width,2'b00 mean crc_width
|
||||
* This register is used to config rx ch2 crc result width,2'b00 mean crc_width
|
||||
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
|
||||
* 24<crc_width<=32
|
||||
*/
|
||||
@ -2583,13 +2583,13 @@ extern "C" {
|
||||
#define AXI_DMA_RX_CRC_WIDTH_CH2_M (AXI_DMA_RX_CRC_WIDTH_CH2_V << AXI_DMA_RX_CRC_WIDTH_CH2_S)
|
||||
#define AXI_DMA_RX_CRC_WIDTH_CH2_V 0x00000003U
|
||||
#define AXI_DMA_RX_CRC_WIDTH_CH2_S 0
|
||||
/** AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2 : R/W; bitpos: [2]; default: 0;
|
||||
/** AXI_DMA_RX_CRC_LATCH_FLAG_CH2 : R/W; bitpos: [2]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2 (BIT(2))
|
||||
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_M (AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_V << AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_S)
|
||||
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_V 0x00000001U
|
||||
#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_S 2
|
||||
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH2 (BIT(2))
|
||||
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH2_M (AXI_DMA_RX_CRC_LATCH_FLAG_CH2_V << AXI_DMA_RX_CRC_LATCH_FLAG_CH2_S)
|
||||
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH2_V 0x00000001U
|
||||
#define AXI_DMA_RX_CRC_LATCH_FLAG_CH2_S 2
|
||||
|
||||
/** AXI_DMA_IN_CRC_CLEAR_CH2_REG register
|
||||
* This register is used to clear ch2 crc result
|
||||
@ -3417,7 +3417,7 @@ extern "C" {
|
||||
#define AXI_DMA_OUT_CRC_INIT_DATA_CH0_S 0
|
||||
|
||||
/** AXI_DMA_TX_CRC_WIDTH_CH0_REG register
|
||||
* This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width
|
||||
* This register is used to config tx ch0 crc result width,2'b00 mean crc_width
|
||||
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
|
||||
* 24<crc_width<=32
|
||||
*/
|
||||
@ -3429,13 +3429,13 @@ extern "C" {
|
||||
#define AXI_DMA_TX_CRC_WIDTH_CH0_M (AXI_DMA_TX_CRC_WIDTH_CH0_V << AXI_DMA_TX_CRC_WIDTH_CH0_S)
|
||||
#define AXI_DMA_TX_CRC_WIDTH_CH0_V 0x00000003U
|
||||
#define AXI_DMA_TX_CRC_WIDTH_CH0_S 0
|
||||
/** AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0 : R/W; bitpos: [2]; default: 0;
|
||||
/** AXI_DMA_TX_CRC_LATCH_FLAG_CH0 : R/W; bitpos: [2]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0 (BIT(2))
|
||||
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_M (AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_V << AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_S)
|
||||
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_V 0x00000001U
|
||||
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_S 2
|
||||
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH0 (BIT(2))
|
||||
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH0_M (AXI_DMA_TX_CRC_LATCH_FLAG_CH0_V << AXI_DMA_TX_CRC_LATCH_FLAG_CH0_S)
|
||||
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH0_V 0x00000001U
|
||||
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH0_S 2
|
||||
|
||||
/** AXI_DMA_OUT_CRC_CLEAR_CH0_REG register
|
||||
* This register is used to clear ch0 crc result
|
||||
@ -4263,7 +4263,7 @@ extern "C" {
|
||||
#define AXI_DMA_OUT_CRC_INIT_DATA_CH1_S 0
|
||||
|
||||
/** AXI_DMA_TX_CRC_WIDTH_CH1_REG register
|
||||
* This register is used to confiig tx ch1 crc result width,2'b00 mean crc_width
|
||||
* This register is used to config tx ch1 crc result width,2'b00 mean crc_width
|
||||
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
|
||||
* 24<crc_width<=32
|
||||
*/
|
||||
@ -4275,13 +4275,13 @@ extern "C" {
|
||||
#define AXI_DMA_TX_CRC_WIDTH_CH1_M (AXI_DMA_TX_CRC_WIDTH_CH1_V << AXI_DMA_TX_CRC_WIDTH_CH1_S)
|
||||
#define AXI_DMA_TX_CRC_WIDTH_CH1_V 0x00000003U
|
||||
#define AXI_DMA_TX_CRC_WIDTH_CH1_S 0
|
||||
/** AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1 : R/W; bitpos: [2]; default: 0;
|
||||
/** AXI_DMA_TX_CRC_LATCH_FLAG_CH1 : R/W; bitpos: [2]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1 (BIT(2))
|
||||
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_M (AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_V << AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_S)
|
||||
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_V 0x00000001U
|
||||
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_S 2
|
||||
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH1 (BIT(2))
|
||||
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH1_M (AXI_DMA_TX_CRC_LATCH_FLAG_CH1_V << AXI_DMA_TX_CRC_LATCH_FLAG_CH1_S)
|
||||
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH1_V 0x00000001U
|
||||
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH1_S 2
|
||||
|
||||
/** AXI_DMA_OUT_CRC_CLEAR_CH1_REG register
|
||||
* This register is used to clear ch1 crc result
|
||||
@ -5109,7 +5109,7 @@ extern "C" {
|
||||
#define AXI_DMA_OUT_CRC_INIT_DATA_CH2_S 0
|
||||
|
||||
/** AXI_DMA_TX_CRC_WIDTH_CH2_REG register
|
||||
* This register is used to confiig tx ch2 crc result width,2'b00 mean crc_width
|
||||
* This register is used to config tx ch2 crc result width,2'b00 mean crc_width
|
||||
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
|
||||
* 24<crc_width<=32
|
||||
*/
|
||||
@ -5121,13 +5121,13 @@ extern "C" {
|
||||
#define AXI_DMA_TX_CRC_WIDTH_CH2_M (AXI_DMA_TX_CRC_WIDTH_CH2_V << AXI_DMA_TX_CRC_WIDTH_CH2_S)
|
||||
#define AXI_DMA_TX_CRC_WIDTH_CH2_V 0x00000003U
|
||||
#define AXI_DMA_TX_CRC_WIDTH_CH2_S 0
|
||||
/** AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2 : R/W; bitpos: [2]; default: 0;
|
||||
/** AXI_DMA_TX_CRC_LATCH_FLAG_CH2 : R/W; bitpos: [2]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2 (BIT(2))
|
||||
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_M (AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_V << AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_S)
|
||||
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_V 0x00000001U
|
||||
#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_S 2
|
||||
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH2 (BIT(2))
|
||||
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH2_M (AXI_DMA_TX_CRC_LATCH_FLAG_CH2_V << AXI_DMA_TX_CRC_LATCH_FLAG_CH2_S)
|
||||
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH2_V 0x00000001U
|
||||
#define AXI_DMA_TX_CRC_LATCH_FLAG_CH2_S 2
|
||||
|
||||
/** AXI_DMA_OUT_CRC_CLEAR_CH2_REG register
|
||||
* This register is used to clear ch2 crc result
|
||||
|
||||
@ -604,7 +604,7 @@ typedef union {
|
||||
} axi_dma_in_crc_init_data_chn_reg_t;
|
||||
|
||||
/** Type of rx_crc_width_chn register
|
||||
* This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width
|
||||
* This register is used to config rx ch0 crc result width,2'b00 mean crc_width
|
||||
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
|
||||
* 24<crc_width<=32
|
||||
*/
|
||||
@ -614,10 +614,10 @@ typedef union {
|
||||
* reserved
|
||||
*/
|
||||
uint32_t rx_crc_width_chn: 2;
|
||||
/** rx_crc_lautch_flga_chn : R/W; bitpos: [2]; default: 0;
|
||||
/** rx_crc_latch_flag_chn : R/W; bitpos: [2]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t rx_crc_lautch_flga_chn: 1;
|
||||
uint32_t rx_crc_latch_flag_chn: 1;
|
||||
uint32_t reserved_3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
@ -1275,7 +1275,7 @@ typedef union {
|
||||
} axi_dma_out_crc_init_data_chn_reg_t;
|
||||
|
||||
/** Type of tx_crc_width_chn register
|
||||
* This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width
|
||||
* This register is used to config tx ch0 crc result width,2'b00 mean crc_width
|
||||
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
|
||||
* 24<crc_width<=32
|
||||
*/
|
||||
@ -1285,10 +1285,10 @@ typedef union {
|
||||
* reserved
|
||||
*/
|
||||
uint32_t tx_crc_width_chn: 2;
|
||||
/** tx_crc_lautch_flga_chn : R/W; bitpos: [2]; default: 0;
|
||||
/** tx_crc_latch_flag_chn : R/W; bitpos: [2]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t tx_crc_lautch_flga_chn: 1;
|
||||
uint32_t tx_crc_latch_flag_chn: 1;
|
||||
uint32_t reserved_3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
|
||||
@ -160,6 +160,7 @@
|
||||
|
||||
/*-------------------------- GDMA CAPS -------------------------------------*/
|
||||
#define SOC_AHB_GDMA_VERSION 2
|
||||
#define SOC_GDMA_SUPPORT_CRC 1
|
||||
#define SOC_GDMA_NUM_GROUPS_MAX 2
|
||||
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
|
||||
#define SOC_AXI_GDMA_SUPPORT_PSRAM 1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user