From 200241b9aa92554bfb7925069f49512c556e11a4 Mon Sep 17 00:00:00 2001 From: Guillaume Souchere Date: Mon, 16 Sep 2024 14:44:57 +0200 Subject: [PATCH] feat(heap): Add support for esp32c61 --- components/heap/port/esp32c61/memory_layout.c | 21 ++++++++----- components/soc/esp32c61/include/soc/soc.h | 31 ++++++++++--------- 2 files changed, 29 insertions(+), 23 deletions(-) diff --git a/components/heap/port/esp32c61/memory_layout.c b/components/heap/port/esp32c61/memory_layout.c index 31fe2689ea..14ba9eae6b 100644 --- a/components/heap/port/esp32c61/memory_layout.c +++ b/components/heap/port/esp32c61/memory_layout.c @@ -28,7 +28,7 @@ /* Index of memory in `soc_memory_types[]` */ enum { SOC_MEMORY_TYPE_RAM = 0, - SOC_MEMORY_TYPE_RTCRAM = 1, + SOC_MEMORY_TYPE_SPIRAM = 1, SOC_MEMORY_TYPE_NUM, }; @@ -48,7 +48,7 @@ enum { const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = { /* Mem Type Name High Priority Matching Medium Priority Matching Low Priority Matching */ [SOC_MEMORY_TYPE_RAM] = { "RAM", { ESP32C6_MEM_COMMON_CAPS | MALLOC_CAP_DMA, 0, 0 }}, - [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, ESP32C6_MEM_COMMON_CAPS, 0 }}, + [SOC_MEMORY_TYPE_SPIRAM] = { "SPIRAM", { MALLOC_CAP_SPIRAM, ESP32C6_MEM_COMMON_CAPS, 0 }}, }; const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); @@ -64,19 +64,20 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor /** * Register the shared buffer area of the last memory block into the heap during heap initialization */ -#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) +#define APP_USABLE_DIRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) const soc_memory_region_t soc_memory_regions[] = { - { 0x40800000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40800000, false}, //D/IRAM level0, can be used as trace memory - { 0x40820000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40820000, false}, //D/IRAM level1, can be used as trace memory - { 0x40840000, (APP_USABLE_DRAM_END-0x40840000), SOC_MEMORY_TYPE_RAM, 0x40840000, false}, //D/IRAM level2, can be used as trace memory - { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM level3, can be used as trace memory (ROM reserved area) +#ifdef CONFIG_SPIRAM + { SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, SOC_MEMORY_TYPE_SPIRAM, 0, false}, //SPI SRAM, if available +#endif + { SOC_DIRAM_DRAM_LOW, (APP_USABLE_DIRAM_END - SOC_DIRAM_DRAM_LOW), SOC_MEMORY_TYPE_RAM, SOC_DIRAM_IRAM_LOW, false}, //D/IRAM, can be used as trace memory + { APP_USABLE_DIRAM_END, (SOC_DIRAM_DRAM_HIGH - APP_USABLE_DIRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DIRAM_END, true}, //D/IRAM, can be used as trace memory (ROM reserved area) }; const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t); -extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end; +extern int _data_start, _heap_start, _iram_start, _iram_end; /** * Reserved memory regions. @@ -84,6 +85,10 @@ extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end * */ +#ifdef CONFIG_SPIRAM +SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, extram_region); +#endif + // Static data region. DRAM used by data+bss and possibly rodata SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data); diff --git a/components/soc/esp32c61/include/soc/soc.h b/components/soc/esp32c61/include/soc/soc.h index 09740fe84a..cd1b6e7537 100644 --- a/components/soc/esp32c61/include/soc/soc.h +++ b/components/soc/esp32c61/include/soc/soc.h @@ -146,20 +146,21 @@ * should be defined statically! */ -#define SOC_IROM_LOW 0x42000000 -#define SOC_IROM_HIGH 0x44000000 -#define SOC_EXTRAM_DATA_LOW 0x42000000 -#define SOC_EXTRAM_DATA_HIGH 0x44000000 -#define SOC_DROM_LOW SOC_IROM_LOW -#define SOC_DROM_HIGH SOC_IROM_HIGH -#define SOC_IROM_MASK_LOW 0x40000000 -#define SOC_IROM_MASK_HIGH 0x40040000 -#define SOC_DROM_MASK_LOW 0x40000000 -#define SOC_DROM_MASK_HIGH 0x40040000 -#define SOC_IRAM_LOW 0x40800000 -#define SOC_IRAM_HIGH 0x40850000 -#define SOC_DRAM_LOW 0x40800000 -#define SOC_DRAM_HIGH 0x40850000 +#define SOC_IROM_LOW 0x42000000 +#define SOC_IROM_HIGH 0x44000000 +#define SOC_EXTRAM_DATA_LOW 0x42000000 +#define SOC_EXTRAM_DATA_HIGH 0x44000000 +#define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) +#define SOC_DROM_LOW SOC_IROM_LOW +#define SOC_DROM_HIGH SOC_IROM_HIGH +#define SOC_IROM_MASK_LOW 0x40000000 +#define SOC_IROM_MASK_HIGH 0x40040000 +#define SOC_DROM_MASK_LOW 0x40000000 +#define SOC_DROM_MASK_HIGH 0x40040000 +#define SOC_IRAM_LOW 0x40800000 +#define SOC_IRAM_HIGH 0x40850000 +#define SOC_DRAM_LOW 0x40800000 +#define SOC_DRAM_HIGH 0x40850000 //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. #define SOC_DIRAM_IRAM_LOW 0x40800000 @@ -196,7 +197,7 @@ #define SOC_CPU_SUBSYSTEM_HIGH 0x30000000 // Start (highest address) of ROM boot stack, only relevant during early boot -#define SOC_ROM_STACK_START 0x4084c9f0 +#define SOC_ROM_STACK_START 0x4084ea70 #define SOC_ROM_STACK_SIZE 0x2000 //On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.