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https://github.com/espressif/esp-idf.git
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Merge branch 'feat/c3_driver_api_cleanup' into 'master'
driver: cleanup i2c, i2s on C3 Closes IDF-2759 and IDF-2760 See merge request espressif/esp-idf!12329
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1f29036ead
@ -33,9 +33,39 @@ extern "C" {
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#define I2C_APB_CLK_FREQ APB_CLK_FREQ /*!< I2C source clock is APB clock, 80MHz */
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#define I2C_NUM_0 (0) /*!< I2C port 0 */
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#define I2C_NUM_1 (1) /*!< I2C port 1 */
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#define I2C_NUM_MAX (SOC_I2C_NUM) /*!< I2C port max */
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#define I2C_NUM_0 (0) /*!< I2C port 0 */
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#if SOC_I2C_NUM >= 2
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#define I2C_NUM_1 (1) /*!< I2C port 1 */
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#endif
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// I2C clk flags for users to use, can be expanded in the future.
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#define I2C_SCLK_SRC_FLAG_FOR_NOMAL (0) /*!< Any one clock source that is available for the specified frequency may be choosen*/
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#define I2C_SCLK_SRC_FLAG_AWARE_DFS (1 << 0) /*!< For REF tick clock, it won't change with APB.*/
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#define I2C_SCLK_SRC_FLAG_LIGHT_SLEEP (1 << 1) /*!< For light sleep mode.*/
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/**
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* @brief I2C initialization parameters
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*/
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typedef struct{
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i2c_mode_t mode; /*!< I2C mode */
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int sda_io_num; /*!< GPIO number for I2C sda signal */
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int scl_io_num; /*!< GPIO number for I2C scl signal */
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bool sda_pullup_en; /*!< Internal GPIO pull mode for I2C sda signal*/
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bool scl_pullup_en; /*!< Internal GPIO pull mode for I2C scl signal*/
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union {
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struct {
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uint32_t clk_speed; /*!< I2C clock frequency for master mode, (no higher than 1MHz for now) */
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} master; /*!< I2C master config */
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struct {
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uint8_t addr_10bit_en; /*!< I2C 10bit address mode enable for slave mode */
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uint16_t slave_addr; /*!< I2C address for slave mode */
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} slave; /*!< I2C slave config */
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};
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uint32_t clk_flags; /*!< Bitwise of ``I2C_SCLK_SRC_FLAG_**FOR_DFS**`` for clk source choice*/
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} i2c_config_t;
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typedef void *i2c_cmd_handle_t; /*!< I2C command handle */
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@ -25,6 +25,7 @@
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#include "hal/i2s_types.h"
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#include "driver/periph_ctrl.h"
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#include "esp_intr_alloc.h"
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#if SOC_I2S_SUPPORTS_ADC_DAC
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#include "driver/adc.h"
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#endif
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@ -82,21 +83,6 @@ esp_err_t i2s_set_pin(i2s_port_t i2s_num, const i2s_pin_config_t *pin);
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esp_err_t i2s_set_pdm_rx_down_sample(i2s_port_t i2s_num, i2s_pdm_dsr_t dsr);
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#endif
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/**
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* @brief Set I2S dac mode, I2S built-in DAC is disabled by default
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*
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* @param dac_mode DAC mode configurations - see i2s_dac_mode_t
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*
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* @note Built-in DAC functions are only supported on I2S0 for current ESP32 chip.
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* If either of the built-in DAC channel are enabled, the other one can not
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* be used as RTC DAC function at the same time.
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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*/
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esp_err_t i2s_set_dac_mode(i2s_dac_mode_t dac_mode);
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/**
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* @brief Install and start I2S driver.
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*
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@ -331,7 +317,23 @@ esp_err_t i2s_adc_enable(i2s_port_t i2s_num);
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* - ESP_ERR_INVALID_STATE Driver state error
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*/
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esp_err_t i2s_adc_disable(i2s_port_t i2s_num);
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#endif
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/**
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* @brief Set I2S dac mode, I2S built-in DAC is disabled by default
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*
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* @param dac_mode DAC mode configurations - see i2s_dac_mode_t
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*
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* @note Built-in DAC functions are only supported on I2S0 for current ESP32 chip.
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* If either of the built-in DAC channel are enabled, the other one can not
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* be used as RTC DAC function at the same time.
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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*/
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esp_err_t i2s_set_dac_mode(i2s_dac_mode_t dac_mode);
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#endif //SOC_I2S_SUPPORTS_ADC_DAC
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#ifdef __cplusplus
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}
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@ -79,36 +79,9 @@ typedef enum {
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I2C_SCLK_MAX,
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} i2c_sclk_t;
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// I2C clk flags for users to use, can be expanded in the future.
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#define I2C_SCLK_SRC_FLAG_FOR_NOMAL (0) /*!< Any one clock source that is available for the specified frequency may be choosen*/
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#define I2C_SCLK_SRC_FLAG_AWARE_DFS (1 << 0) /*!< For REF tick clock, it won't change with APB.*/
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#define I2C_SCLK_SRC_FLAG_LIGHT_SLEEP (1 << 1) /*!< For light sleep mode.*/
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/// Use the highest speed that is available for the clock source picked by clk_flags
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#define I2C_CLK_FREQ_MAX (-1)
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/**
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* @brief I2C initialization parameters
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*/
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typedef struct{
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i2c_mode_t mode; /*!< I2C mode */
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int sda_io_num; /*!< GPIO number for I2C sda signal */
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int scl_io_num; /*!< GPIO number for I2C scl signal */
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bool sda_pullup_en; /*!< Internal GPIO pull mode for I2C sda signal*/
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bool scl_pullup_en; /*!< Internal GPIO pull mode for I2C scl signal*/
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union {
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struct {
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uint32_t clk_speed; /*!< I2C clock frequency for master mode, (no higher than 1MHz for now) */
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} master; /*!< I2C master config */
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struct {
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uint8_t addr_10bit_en; /*!< I2C 10bit address mode enable for slave mode */
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uint16_t slave_addr; /*!< I2C address for slave mode */
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} slave; /*!< I2C slave config */
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};
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uint32_t clk_flags; /*!< Bitwise of ``I2C_SCLK_SRC_FLAG_**FOR_DFS**`` for clk source choice*/
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} i2c_config_t;
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#if CONFIG_IDF_TARGET_ESP32
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typedef enum{
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I2C_CMD_RESTART = 0, /*!<I2C restart command */
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@ -115,7 +115,6 @@ typedef enum {
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I2S_CLK_APLL, /*!< Clock from APLL*/
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} i2s_clock_src_t;
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/**
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* @brief I2S configuration parameters for i2s_param_config function
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*
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@ -145,6 +144,7 @@ typedef enum {
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I2S_EVENT_MAX, /*!< I2S event max index*/
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} i2s_event_type_t;
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#if SOC_I2S_SUPPORTS_ADC_DAC
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/**
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* @brief I2S DAC mode for i2s_set_dac_mode.
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*
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@ -157,6 +157,7 @@ typedef enum {
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I2S_DAC_CHANNEL_BOTH_EN = 0x3, /*!< Enable both of the I2S built-in DAC channels.*/
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I2S_DAC_CHANNEL_MAX = 0x4, /*!< I2S built-in DAC mode max index*/
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} i2s_dac_mode_t;
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#endif //SOC_I2S_SUPPORTS_ADC_DAC
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/**
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* @brief Event structure used in I2S event queue
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