alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

Waits for all previously fetched WSR and XSR instructions to be performed before interpreting the register fields of the next

Browse Source 
instruction

delete logs about livelock
This commit is contained in:
baohongde 2020-07-31 21:07:34 +08:00 committed by maojianxin
parent 73153d9bf6
commit 1f152b5146
3 changed files with 3 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
components/bt/hli_vectors.S
View File

@ -64,6 +64,7 @@ xt_highint4:
addmi a0, a0, (1<<14)
addmi a0, a0, (1<<14)
wsr a0, INTENABLE
rsync
1:
#endif
@ -98,6 +99,7 @@ xt_highint4:
movi a2, ~(1<<16)
and a0, a2, a0
wsr a0, INTENABLE
rsync
#endif
/* disable exception mode, window overflow */

5
components/esp32/cpu_start.c
View File

@ -253,11 +253,6 @@ void IRAM_ATTR call_start_cpu0()
fail initializing it properly. */
heap_caps_init();
for (int i = 0; i < 64; i++) {
ets_printf(((i+1)%8) ? DRAM_STR("%08x ") : DRAM_STR("%08x\n"), *(((volatile uint32_t *)SOC_RTC_DATA_LOW) + i));
*(((volatile uint32_t *)SOC_RTC_DATA_LOW) + i) = 0;
}
ESP_EARLY_LOGI(TAG, "Pro cpu start user code");
start_cpu0();
}

20
components/esp32/dport_panic_highint_hdl.S
View File

@ -206,7 +206,7 @@ xt_highint5:
nop
.endr
/* Disable Normally Mode */
/* Enable Normally Mode */
movi a2, ERI_ADDR(APB_ITCTRL)
rer a0, a2
movi a2, ~0x1
@ -289,24 +289,6 @@ xt_highint5:
.align 4
.handle_livelock_int:
movi a0, SOC_RTC_DATA_LOW
movi a5, _l5_intr_livelock_sync
l32i a5, a5, 0
s32i a5, a0, 0
memw
movi a5, _l5_intr_livelock_sync
l32i a5, a5, 4
s32i a5, a0, 4
memw
movi a5, _l5_intr_livelock_app
l32i a5, a5, 0
s32i a5, a0, 8
memw
movi a5, _l5_intr_livelock_counter
l32i a5, a5, 0
s32i a5, a0, 12
memw
getcoreid a5
/* Save A2, A3, A4 so we can use those registers */