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Merge branch 'feature/reinitialize_icg_map_in_modem_module_enable_v5.2' into 'release/v5.2'

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fix(esp_hw_support): re-initialize icg map in modem_clock_module_enable (backport v5.2)

See merge request espressif/esp-idf!27765
This commit is contained in:
Jiang Jiang Jian 2023-12-11 10:56:45 +08:00
commit 1ef5c02c37
7 changed files with 45 additions and 55 deletions
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9
components/esp_hw_support/include/esp_private/esp_modem_clock.h
View File

@ -70,15 +70,6 @@ void modem_clock_module_disable(periph_module_t module);
*/
void modem_clock_module_mac_reset(periph_module_t module);
/**
* @brief Initialize the clock gating control signal of each clock domain of the modem
*
* This is a global modem clock gating signal initialization interface, which is
* only configured during system initialization, and each modem module cannot
* use this interface.
*/
void modem_clock_domain_pmu_state_icg_map_init(void);
#if SOC_PMU_SUPPORTED
/**
* @brief Enable modem clock domain clock gate to gate it's output

64
components/esp_hw_support/modem_clock.c
View File

@ -157,36 +157,6 @@ modem_clock_context_t * __attribute__((weak)) IRAM_ATTR MODEM_CLOCK_instance(voi
}
#if SOC_PM_SUPPORT_PMU_MODEM_STATE
static void IRAM_ATTR modem_clock_domain_power_state_icg_map_init(modem_clock_context_t *ctx)
{
#define ICG_NOGATING_SLEEP (BIT(PMU_HP_ICG_MODEM_CODE_SLEEP))
#define ICG_NOGATING_MODEM (BIT(PMU_HP_ICG_MODEM_CODE_MODEM))
#define ICG_NOGATING_ACTIVE (BIT(PMU_HP_ICG_MODEM_CODE_ACTIVE))
/* the ICG code's bit 0, 1 and 2 indicates the ICG state
* of pmu SLEEP, MODEM and ACTIVE mode respectively */
const uint32_t code[MODEM_CLOCK_DOMAIN_MAX] = {
[MODEM_CLOCK_DOMAIN_MODEM_APB] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
[MODEM_CLOCK_DOMAIN_MODEM_PERIPH] = ICG_NOGATING_ACTIVE,
[MODEM_CLOCK_DOMAIN_WIFI] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
[MODEM_CLOCK_DOMAIN_BT] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
[MODEM_CLOCK_DOMAIN_MODEM_PRIVATE_FE] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
[MODEM_CLOCK_DOMAIN_IEEE802154] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
[MODEM_CLOCK_DOMAIN_LP_APB] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
[MODEM_CLOCK_DOMAIN_I2C_MASTER] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
[MODEM_CLOCK_DOMAIN_COEX] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
[MODEM_CLOCK_DOMAIN_WIFIPWR] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
};
for (modem_clock_domain_t domain = MODEM_CLOCK_DOMAIN_MODEM_APB; domain < MODEM_CLOCK_DOMAIN_MAX; domain++) {
modem_clock_hal_set_clock_domain_icg_bitmap(ctx->hal, domain, code[domain]);
}
}
void modem_clock_domain_pmu_state_icg_map_init(void)
{
modem_clock_domain_power_state_icg_map_init(MODEM_CLOCK_instance());
}
esp_err_t modem_clock_domain_clk_gate_enable(modem_clock_domain_t domain, pmu_hp_icg_modem_mode_t mode)
{
if (domain >= MODEM_CLOCK_DOMAIN_MAX || domain < MODEM_CLOCK_DOMAIN_MODEM_APB) {
@ -319,9 +289,43 @@ static IRAM_ATTR uint32_t modem_clock_get_module_deps(periph_module_t module)
return deps;
}
#if SOC_PM_SUPPORT_PMU_MODEM_STATE
/* the ICG code's bit 0, 1 and 2 indicates the ICG state
* of pmu SLEEP, MODEM and ACTIVE mode respectively */
#define ICG_NOGATING_SLEEP (BIT(PMU_HP_ICG_MODEM_CODE_SLEEP))
#define ICG_NOGATING_MODEM (BIT(PMU_HP_ICG_MODEM_CODE_MODEM))
#define ICG_NOGATING_ACTIVE (BIT(PMU_HP_ICG_MODEM_CODE_ACTIVE))
static const DRAM_ATTR uint32_t initial_gating_mode[MODEM_CLOCK_DOMAIN_MAX] = {
[MODEM_CLOCK_DOMAIN_MODEM_APB] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
[MODEM_CLOCK_DOMAIN_MODEM_PERIPH] = ICG_NOGATING_ACTIVE,
[MODEM_CLOCK_DOMAIN_WIFI] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
[MODEM_CLOCK_DOMAIN_BT] = ICG_NOGATING_ACTIVE,
[MODEM_CLOCK_DOMAIN_MODEM_FE] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
[MODEM_CLOCK_DOMAIN_IEEE802154] = ICG_NOGATING_ACTIVE,
[MODEM_CLOCK_DOMAIN_LP_APB] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
[MODEM_CLOCK_DOMAIN_I2C_MASTER] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
[MODEM_CLOCK_DOMAIN_COEX] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
[MODEM_CLOCK_DOMAIN_WIFIPWR] = ICG_NOGATING_ACTIVE | ICG_NOGATING_MODEM,
};
static IRAM_ATTR void modem_clock_module_icg_map_init_all(void)
{
portENTER_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock);
for (int domain = 0; domain < MODEM_CLOCK_DOMAIN_MAX; domain++) {
uint32_t code = modem_clock_hal_get_clock_domain_icg_bitmap(MODEM_CLOCK_instance()->hal, domain);
modem_clock_hal_set_clock_domain_icg_bitmap(MODEM_CLOCK_instance()->hal, domain, initial_gating_mode[domain] | code);
}
portEXIT_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock);
}
#endif // SOC_PM_SUPPORT_PMU_MODEM_STATE
void IRAM_ATTR modem_clock_module_enable(periph_module_t module)
{
assert(IS_MODEM_MODULE(module));
#if SOC_PM_SUPPORT_PMU_MODEM_STATE
modem_clock_module_icg_map_init_all();
#endif
uint32_t deps = modem_clock_get_module_deps(module);
modem_clock_device_enable(MODEM_CLOCK_instance(), deps);
}

2
components/esp_system/port/soc/esp32c6/clk.c
View File

@ -178,8 +178,6 @@ void rtc_clk_select_rtc_slow_clk(void)
*/
__attribute__((weak)) void esp_perip_clk_init(void)
{
modem_clock_domain_pmu_state_icg_map_init();
/* During system initialization, the low-power clock source of the modem
* (WiFi, BLE or Coexist) follows the configuration of the slow clock source
* of the system. If the WiFi, BLE or Coexist module needs a higher

2
components/esp_system/port/soc/esp32p4/clk.c
View File

@ -174,8 +174,6 @@ void rtc_clk_select_rtc_slow_clk(void)
*/
__attribute__((weak)) void esp_perip_clk_init(void)
{
modem_clock_domain_pmu_state_icg_map_init();
ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet");
#if 0 // TODO: IDF-5658
uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;

16
components/hal/esp32c6/modem_clock_hal.c
View File

@ -36,7 +36,7 @@ void IRAM_ATTR modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_conte
case MODEM_CLOCK_DOMAIN_BT:
modem_syscon_ll_set_bt_icg_bitmap(hal->syscon_dev, bitmap);
break;
case MODEM_CLOCK_DOMAIN_MODEM_PRIVATE_FE:
case MODEM_CLOCK_DOMAIN_MODEM_FE:
modem_syscon_ll_set_fe_icg_bitmap(hal->syscon_dev, bitmap);
break;
case MODEM_CLOCK_DOMAIN_IEEE802154:
@ -55,11 +55,11 @@ void IRAM_ATTR modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_conte
modem_lpcon_ll_set_wifipwr_icg_bitmap(hal->lpcon_dev, bitmap);
break;
default:
break;
HAL_ASSERT(0);
}
}
uint32_t modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain)
uint32_t IRAM_ATTR modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain)
{
HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX);
uint32_t bitmap = 0;
@ -77,7 +77,7 @@ uint32_t modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t *
case MODEM_CLOCK_DOMAIN_BT:
bitmap = modem_syscon_ll_get_bt_icg_bitmap(hal->syscon_dev);
break;
case MODEM_CLOCK_DOMAIN_MODEM_PRIVATE_FE:
case MODEM_CLOCK_DOMAIN_MODEM_FE:
bitmap = modem_syscon_ll_get_fe_icg_bitmap(hal->syscon_dev);
break;
case MODEM_CLOCK_DOMAIN_IEEE802154:
@ -96,7 +96,7 @@ uint32_t modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t *
bitmap = modem_lpcon_ll_get_wifipwr_icg_bitmap(hal->lpcon_dev);
break;
default:
break;
HAL_ASSERT(0);
}
return bitmap;
}
@ -163,7 +163,7 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE);
break;
default:
break;
HAL_ASSERT(0);
}
}
@ -203,7 +203,7 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE);
break;
default:
break;
HAL_ASSERT(0);
}
}
@ -243,7 +243,7 @@ void modem_clock_hal_select_wifi_lpclk_source(modem_clock_hal_context_t *hal, mo
modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE);
break;
default:
break;
HAL_ASSERT(0);
}
}

4
components/hal/esp32h2/modem_clock_hal.c
View File

@ -79,7 +79,7 @@ void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
break;
default:
break;
HAL_ASSERT(0);
}
}
@ -119,6 +119,6 @@ void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, mo
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
break;
default:
break;
HAL_ASSERT(0);
}
}

3
components/hal/include/hal/modem_clock_types.h
View File

@ -15,8 +15,7 @@ typedef enum {
MODEM_CLOCK_DOMAIN_MODEM_PERIPH,
MODEM_CLOCK_DOMAIN_WIFI,
MODEM_CLOCK_DOMAIN_BT,
MODEM_CLOCK_DOMAIN_MODEM_ADC_COMMON_FE,
MODEM_CLOCK_DOMAIN_MODEM_PRIVATE_FE,
MODEM_CLOCK_DOMAIN_MODEM_FE,
MODEM_CLOCK_DOMAIN_IEEE802154,
MODEM_CLOCK_DOMAIN_LP_APB,
MODEM_CLOCK_DOMAIN_I2C_MASTER,