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Merge branch 'bugfix/lp_active_slow_clock_domain_default_power_down_v5.1' into 'release/v5.1'
backport v5.1: In the LP ACTIVE state, the slow clock power domain is by default in a powered-off state See merge request espressif/esp-idf!26601
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commit
1ed40720d6
@ -361,14 +361,20 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
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/** LP system default parameter */
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#if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
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# define PMU_SLOW_CLK_USE_EXT_XTAL (1)
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#else
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# define PMU_SLOW_CLK_USE_EXT_XTAL (0)
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#endif
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#define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \
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.dig_power = { \
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.mem_dslp = 0, \
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.peri_pd_en = 0, \
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}, \
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.clk_power = { \
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.xpd_xtal32k = 1, \
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.xpd_rc32k = 1, \
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.xpd_xtal32k = PMU_SLOW_CLK_USE_EXT_XTAL, \
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.xpd_rc32k = 0, \
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.xpd_fosc = 1, \
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.pd_osc = 0 \
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} \
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@ -285,8 +285,8 @@ typedef struct {
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.mem_dslp = 0 \
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}, \
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.clk_power = { \
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.xpd_xtal32k = 1, \
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.xpd_rc32k = 1, \
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.xpd_xtal32k = ((pd_flags) & PMU_SLEEP_PD_XTAL32K) ? 0 : 1, \
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.xpd_rc32k = ((pd_flags) & PMU_SLEEP_PD_RC32K) ? 0 : 1, \
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.xpd_fosc = 1 \
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} \
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}, \
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@ -359,13 +359,19 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
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/** LP system default parameter */
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#if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
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# define PMU_SLOW_CLK_USE_EXT_XTAL (1)
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#else
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# define PMU_SLOW_CLK_USE_EXT_XTAL (0)
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#endif
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#define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \
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.dig_power = { \
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.mem_dslp = 0, \
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.peri_pd_en = 0, \
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}, \
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.clk_power = { \
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.xpd_xtal32k = 0, \
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.xpd_xtal32k = PMU_SLOW_CLK_USE_EXT_XTAL, \
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.xpd_rc32k = 0, \
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.xpd_fosc = 1, \
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.pd_osc = 0 \
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@ -280,8 +280,8 @@ typedef struct {
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.mem_dslp = 0 \
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}, \
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.clk_power = { \
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.xpd_xtal32k = 1, \
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.xpd_rc32k = 1, \
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.xpd_xtal32k = ((pd_flags) & PMU_SLEEP_PD_XTAL32K) ? 0 : 1, \
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.xpd_rc32k = ((pd_flags) & PMU_SLEEP_PD_RC32K) ? 0 : 1, \
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.xpd_fosc = 1 \
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} \
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}, \
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