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synced 2024-09-19 14:26:01 -04:00
esp_mm: fix dependency to esp_psram
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fda9746bb8
commit
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36
components/esp_mm/cache_esp32.c
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36
components/esp_mm/cache_esp32.c
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@ -0,0 +1,36 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <sys/param.h>
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#include <inttypes.h>
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#include "sdkconfig.h"
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#include "rom/cache.h"
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#include "esp_private/esp_cache_esp32_private.h"
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static cache_driver_t s_cache_drv = {
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Cache_Flush,
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NULL,
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};
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void cache_register_writeback(cache_driver_t *func)
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{
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s_cache_drv.cache_writeback_psram = func->cache_writeback_psram;
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}
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void cache_sync(void)
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{
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if (s_cache_drv.cache_writeback_psram) {
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s_cache_drv.cache_writeback_psram();
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}
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s_cache_drv.cache_flush(0);
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#if !CONFIG_FREERTOS_UNICORE
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s_cache_drv.cache_flush(1);
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#endif // !CONFIG_FREERTOS_UNICORE
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}
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@ -23,14 +23,8 @@
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#include "hal/mmu_hal.h"
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#include "hal/mmu_ll.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/cache.h"
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#endif
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#include "esp_private/cache_utils.h"
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#if CONFIG_SPIRAM
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#include "esp_private/esp_psram_extram.h"
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#endif
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#include "esp_private/esp_cache_esp32_private.h"
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#include "esp_private/esp_mmu_map_private.h"
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#include "ext_mem_layout.h"
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#include "esp_mmu_map.h"
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@ -333,29 +327,15 @@ esp_err_t esp_mmu_map_reserve_block_with_caps(size_t size, mmu_mem_caps_t caps,
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}
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#if CONFIG_IDF_TARGET_ESP32
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/**
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* On ESP32, due to hardware limitation, we don't have an
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* easy way to sync between cache and external memory wrt
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* certain range. So we do a full sync here
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*/
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static void IRAM_ATTR NOINLINE_ATTR s_cache_sync(void)
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{
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#if CONFIG_SPIRAM
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esp_psram_extram_writeback_cache();
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#endif //#if CONFIG_SPIRAM
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Cache_Flush(0);
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#if !CONFIG_FREERTOS_UNICORE
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Cache_Flush(1);
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#endif // !CONFIG_FREERTOS_UNICORE
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}
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#endif //#if CONFIG_IDF_TARGET_ESP32
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static void IRAM_ATTR NOINLINE_ATTR s_do_cache_invalidate(uint32_t vaddr_start, uint32_t size)
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{
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#if CONFIG_IDF_TARGET_ESP32
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s_cache_sync();
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/**
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* On ESP32, due to hardware limitation, we don't have an
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* easy way to sync between cache and external memory wrt
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* certain range. So we do a full sync here
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*/
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cache_sync();
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#else //Other chips
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cache_hal_invalidate_addr(vaddr_start, size);
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#endif // CONFIG_IDF_TARGET_ESP32
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@ -0,0 +1,59 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdlib.h>
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#include <stdint.h>
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#include "esp_err.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Private header for cache drivers, where cache functionality requires other components
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*
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* @note Now only esp32, can be applied to other similar chips
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*/
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typedef struct cache_driver_s cache_driver_t;
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/**
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* @brief Cache driver
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*/
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struct cache_driver_s {
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/**
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* @brief Cache flush
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*
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* @param[in] cpu_no CPU id
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*/
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void (*cache_flush)(int cpu_no);
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/**
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* @brief Cache writeback to psram
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*/
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void (*cache_writeback_psram)(void);
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};
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/**
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* @brief Register cache writeback
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*
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* @param[in] func Cache driver
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*/
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void cache_register_writeback(cache_driver_t *func);
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/**
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* @brief Cache sync
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*
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* @note This API only do cache sync, but doesn't guarantee concurrent access to cache
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* @note Do not use in your application
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*/
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void cache_sync(void);
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#ifdef __cplusplus
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}
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#endif
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@ -2,7 +2,8 @@
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archive: libesp_mm.a
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entries:
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esp_cache (noflash)
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if APP_BUILD_TYPE_PURE_RAM_APP = n:
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esp_cache (noflash)
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if IDF_TARGET_ESP32S3 = y:
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cache_esp32 (noflash)
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if IDF_TARGET_ESP32 = y:
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cache_esp32 (noflash)
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@ -32,6 +32,7 @@
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/himem.h"
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#include "esp32/rom/cache.h"
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#include "esp_private/esp_cache_esp32_private.h"
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#endif
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@ -293,6 +294,15 @@ esp_err_t esp_psram_init(void)
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s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].size -= esp_himem_reserved_area_size() - 1;
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#endif
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//will be removed, TODO: IDF-6944
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#if CONFIG_IDF_TARGET_ESP32
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cache_driver_t drv = {
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NULL,
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esp_psram_extram_writeback_cache,
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};
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cache_register_writeback(&drv);
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#endif
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return ESP_OK;
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}
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