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Merge branch 'bugfix/c5_mpi_ecc_power_mode' into 'master'

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fix(hal): correct mpi/ecc peripheral power up sequence for ESP32-C5

See merge request espressif/esp-idf!31621
This commit is contained in:
Mahavir Jain 2024-06-24 13:47:07 +08:00
commit 1ec218260f
12 changed files with 69 additions and 2 deletions
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3
components/hal/esp32c2/include/hal/ecc_ll.h
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@ -49,6 +49,9 @@ static inline void ecc_ll_reset_register(void)
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define ecc_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; ecc_ll_reset_register(__VA_ARGS__)
static inline void ecc_ll_power_up(void) {}
static inline void ecc_ll_power_down(void) {}
static inline void ecc_ll_enable_interrupt(void)
{
REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 1);

15
components/hal/esp32c5/include/hal/ecc_ll.h
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@ -11,6 +11,7 @@
#include "hal/ecc_types.h"
#include "soc/ecc_mult_reg.h"
#include "soc/pcr_struct.h"
#include "soc/pcr_reg.h"
#ifdef __cplusplus
extern "C" {
@ -46,6 +47,20 @@ static inline void ecc_ll_reset_register(void)
PCR.ecdsa_conf.ecdsa_rst_en = 0;
}
static inline void ecc_ll_power_up(void)
{
/* Power up the ECC peripheral (default state is power-down) */
REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD);
REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD);
}
static inline void ecc_ll_power_down(void)
{
/* Power down the ECC peripheral */
REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PU);
REG_SET_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD);
}
static inline void ecc_ll_enable_interrupt(void)
{
REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 1);

4
components/hal/esp32c5/include/hal/mpi_ll.h
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@ -51,11 +51,15 @@ static inline size_t mpi_ll_calculate_hardware_words(size_t words)
static inline void mpi_ll_clear_power_control_bit(void)
{
/* Power up the MPI peripheral (default is power-down state) */
REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_PD);
REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_FORCE_PD);
}
static inline void mpi_ll_set_power_control_bit(void)
{
/* Power down the MPI peripheral */
REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_FORCE_PU);
REG_SET_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_PD);
}

15
components/hal/esp32c6/include/hal/ecc_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -11,6 +11,7 @@
#include "hal/ecc_types.h"
#include "soc/ecc_mult_reg.h"
#include "soc/pcr_struct.h"
#include "soc/pcr_reg.h"
#ifdef __cplusplus
extern "C" {
@ -41,6 +42,18 @@ static inline void ecc_ll_reset_register(void)
PCR.ecc_conf.ecc_rst_en = 0;
}
static inline void ecc_ll_power_up(void)
{
REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD);
REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD);
}
static inline void ecc_ll_power_down(void)
{
REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PU);
REG_SET_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD);
}
static inline void ecc_ll_enable_interrupt(void)
{
REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 1);

4
components/hal/esp32c6/include/hal/mpi_ll.h
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@ -49,11 +49,15 @@ static inline size_t mpi_ll_calculate_hardware_words(size_t words)
static inline void mpi_ll_clear_power_control_bit(void)
{
/* Power up the MPI peripheral */
REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_PD);
REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_FORCE_PD);
}
static inline void mpi_ll_set_power_control_bit(void)
{
/* Power down the MPI peripheral */
REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_FORCE_PU);
REG_SET_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_PD);
}

15
components/hal/esp32h2/include/hal/ecc_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -11,6 +11,7 @@
#include "hal/ecc_types.h"
#include "soc/ecc_mult_reg.h"
#include "soc/pcr_struct.h"
#include "soc/pcr_reg.h"
#ifdef __cplusplus
extern "C" {
@ -47,6 +48,18 @@ static inline void ecc_ll_reset_register(void)
PCR.ecdsa_conf.ecdsa_rst_en = 0;
}
static inline void ecc_ll_power_up(void)
{
REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD);
REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD);
}
static inline void ecc_ll_power_down(void)
{
REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PU);
REG_SET_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD);
}
static inline void ecc_ll_enable_interrupt(void)
{
REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 1);

4
components/hal/esp32h2/include/hal/mpi_ll.h
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@ -50,11 +50,15 @@ static inline size_t mpi_ll_calculate_hardware_words(size_t words)
static inline void mpi_ll_clear_power_control_bit(void)
{
/* Power up the MPI peripheral */
REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_PD);
REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_FORCE_PD);
}
static inline void mpi_ll_set_power_control_bit(void)
{
/* Power down the MPI peripheral */
REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_FORCE_PU);
REG_SET_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_PD);
}

3
components/hal/esp32p4/include/hal/ecc_ll.h
View File

@ -56,6 +56,9 @@ static inline void ecc_ll_reset_register(void)
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define ecc_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; ecc_ll_reset_register(__VA_ARGS__)
static inline void ecc_ll_power_up(void) {}
static inline void ecc_ll_power_down(void) {}
static inline void ecc_ll_enable_interrupt(void)
{
REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 1);

2
components/hal/test_apps/crypto/main/ecc/test_ecc.c
View File

@ -46,6 +46,7 @@ static void ecc_enable_and_reset(void)
{
ECC_RCC_ATOMIC() {
ecc_ll_enable_bus_clock(true);
ecc_ll_power_up();
ecc_ll_reset_register();
}
}
@ -54,6 +55,7 @@ static void ecc_disable(void)
{
ECC_RCC_ATOMIC() {
ecc_ll_enable_bus_clock(false);
ecc_ll_power_down();
}
}

2
components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c
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@ -34,6 +34,7 @@ static void ecdsa_enable_and_reset(void)
ECC_RCC_ATOMIC() {
ecc_ll_enable_bus_clock(true);
ecc_ll_power_up();
ecc_ll_reset_register();
}
@ -55,6 +56,7 @@ static void ecdsa_disable(void)
ECC_RCC_ATOMIC() {
ecc_ll_enable_bus_clock(false);
ecc_ll_power_down();
}
ECDSA_RCC_ATOMIC() {

2
components/mbedtls/port/ecc/esp_ecc.c
View File

@ -19,6 +19,7 @@ static void esp_ecc_acquire_hardware(void)
ECC_RCC_ATOMIC() {
ecc_ll_enable_bus_clock(true);
ecc_ll_power_up();
ecc_ll_reset_register();
}
}
@ -27,6 +28,7 @@ static void esp_ecc_release_hardware(void)
{
ECC_RCC_ATOMIC() {
ecc_ll_enable_bus_clock(false);
ecc_ll_power_down();
}
esp_crypto_ecc_lock_release();

2
components/mbedtls/port/ecdsa/ecdsa_alt.c
View File

@ -35,6 +35,7 @@ static void esp_ecdsa_acquire_hardware(void)
ECC_RCC_ATOMIC() {
ecc_ll_enable_bus_clock(true);
ecc_ll_power_up();
ecc_ll_reset_register();
}
@ -57,6 +58,7 @@ static void esp_ecdsa_release_hardware(void)
ECC_RCC_ATOMIC() {
ecc_ll_enable_bus_clock(false);
ecc_ll_power_down();
}
#ifdef SOC_ECDSA_USES_MPI