diff --git a/components/esp_system/include/esp_private/crosscore_int.h b/components/esp_system/include/esp_private/crosscore_int.h
index ea2737513c..1325c2a055 100644
--- a/components/esp_system/include/esp_private/crosscore_int.h
+++ b/components/esp_system/include/esp_private/crosscore_int.h
@@ -75,7 +75,7 @@ void esp_crosscore_int_send_print_backtrace(int core_id);
 void esp_crosscore_int_send_twdt_abort(int core_id);
 
 #endif // CONFIG_ESP_TASK_WDT_EN
-#endif // !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C2
+#endif // !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6
 
 #ifdef __cplusplus
 }
diff --git a/components/esp_system/port/soc/esp32c6/system_internal.c b/components/esp_system/port/soc/esp32c6/system_internal.c
index 274460853e..0522220e77 100644
--- a/components/esp_system/port/soc/esp32c6/system_internal.c
+++ b/components/esp_system/port/soc/esp32c6/system_internal.c
@@ -11,8 +11,7 @@
 #include "esp_attr.h"
 #include "esp_log.h"
 #include "esp_rom_sys.h"
-#include "riscv/riscv_interrupts.h"
-#include "riscv/interrupt.h"
+#include "riscv/rv_utils.h"
 #include "esp_rom_uart.h"
 #include "soc/gpio_reg.h"
 #include "esp_cpu.h"
@@ -33,7 +32,7 @@
 void IRAM_ATTR esp_restart_noos(void)
 {
     // Disable interrupts
-    riscv_global_interrupts_disable();
+    rv_utils_intr_global_disable();
     // Enable RTC watchdog for 1 second
     wdt_hal_context_t rtc_wdt_ctx;
     wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
diff --git a/components/riscv/include/riscv/rv_utils.h b/components/riscv/include/riscv/rv_utils.h
index 335ed00b41..cff0fa2786 100644
--- a/components/riscv/include/riscv/rv_utils.h
+++ b/components/riscv/include/riscv/rv_utils.h
@@ -195,7 +195,9 @@ FORCE_INLINE_ATTR void rv_utils_dbgr_break(void)
 
 FORCE_INLINE_ATTR bool rv_utils_compare_and_set(volatile uint32_t *addr, uint32_t compare_value, uint32_t new_value)
 {
-    // Single core target has no atomic CAS instruction. We can achieve atomicity by disabling interrupts
+    // ESP32C6 starts to support atomic CAS instructions, but it is still a single core target, no need to implement
+    // through lr and sc instructions for now
+    // For an RV target has no atomic CAS instruction, we can achieve atomicity by disabling interrupts
     unsigned old_mstatus;
     old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
     // Compare and set
diff --git a/components/soc/esp32c6/include/soc/soc.h b/components/soc/esp32c6/include/soc/soc.h
index 641ddce136..230ce59ec0 100644
--- a/components/soc/esp32c6/include/soc/soc.h
+++ b/components/soc/esp32c6/include/soc/soc.h
@@ -241,3 +241,6 @@
 
 //Interrupt medium level, used for INT WDT for example
 #define SOC_INTERRUPT_LEVEL_MEDIUM              4
+
+// Interrupt number for the Interrupt watchdog
+#define ETS_INT_WDT_INUM                         (ETS_T1_WDT_INUM)