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Merge branch 'refactor/rename_hal_usb_phy_to_fsls' into 'master'

Browse Source 
USB HAL: Change name of usb_phy HAL files to usb_fsls_phy

See merge request espressif/esp-idf!28158
This commit is contained in:
Darian 2023-12-29 11:42:11 +08:00
commit 1da17fce18
14 changed files with 118 additions and 118 deletions
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6
components/bootloader_support/src/bootloader_console.c
View File

@ -19,7 +19,7 @@
#include "esp32s2/rom/usb/usb_common.h"
#endif
#if SOC_USB_SERIAL_JTAG_SUPPORTED
#include "hal/usb_phy_ll.h"
#include "hal/usb_fsls_phy_ll.h"
#endif
#include "esp_rom_gpio.h"
#include "esp_rom_uart.h"
@ -106,8 +106,8 @@ void bootloader_console_init(void)
esp_rom_uart_set_as_console(ESP_ROM_USB_OTG_NUM);
esp_rom_install_channel_putc(1, bootloader_console_write_char_usb);
#if SOC_USB_SERIAL_JTAG_SUPPORTED
usb_phy_ll_usb_wrap_pad_enable(&USB_WRAP, true);
usb_phy_ll_int_otg_enable(&USB_WRAP);
usb_fsls_phy_ll_usb_wrap_pad_enable(&USB_WRAP, true);
usb_fsls_phy_ll_int_otg_enable(&USB_WRAP);
#endif
}
#endif //CONFIG_ESP_CONSOLE_USB_CDC

4
components/driver/usb_serial_jtag/usb_serial_jtag.c
View File

@ -9,7 +9,7 @@
#include <stdatomic.h>
#include "esp_log.h"
#include "hal/usb_serial_jtag_ll.h"
#include "hal/usb_phy_ll.h"
#include "hal/usb_fsls_phy_ll.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "freertos/ringbuf.h"
@ -186,7 +186,7 @@ esp_err_t usb_serial_jtag_driver_install(usb_serial_jtag_driver_config_t *usb_se
atomic_store(&p_usb_serial_jtag_obj->fifo_status, FIFO_IDLE);
// Configure PHY
usb_phy_ll_int_jtag_enable(&USB_SERIAL_JTAG);
usb_fsls_phy_ll_int_jtag_enable(&USB_SERIAL_JTAG);
usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY|
USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT);

2
components/hal/CMakeLists.txt
View File

@ -246,7 +246,7 @@ if(NOT BOOTLOADER_BUILD)
list(APPEND srcs
"usb_hal.c"
"usb_dwc_hal.c"
"usb_phy_hal.c")
"usb_fsls_phy_hal.c")
endif()
if(${target} STREQUAL "esp32")

2
components/hal/esp32c3/include/hal/usb_phy_ll.h → components/hal/esp32c3/include/hal/usb_fsls_phy_ll.h
View File

@ -17,7 +17,7 @@ extern "C" {
*
* @param hw Start address of the USB Serial_JTAG registers
*/
static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
{
// USB_Serial_JTAG use internal PHY
hw->conf0.phy_sel = 0;

2
components/hal/esp32c6/include/hal/usb_phy_ll.h → components/hal/esp32c6/include/hal/usb_fsls_phy_ll.h
View File

@ -17,7 +17,7 @@ extern "C" {
*
* @param hw Start address of the USB Serial_JTAG registers
*/
static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
{
// USB_Serial_JTAG use internal PHY
hw->conf0.phy_sel = 0;

2
components/hal/esp32h2/include/hal/usb_phy_ll.h → components/hal/esp32h2/include/hal/usb_fsls_phy_ll.h
View File

@ -17,7 +17,7 @@ extern "C" {
*
* @param hw Start address of the USB Serial_JTAG registers
*/
static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
{
// USB_Serial_JTAG use internal PHY
hw->conf0.phy_sel = 0;

18
components/hal/esp32s2/include/hal/usb_phy_ll.h → components/hal/esp32s2/include/hal/usb_fsls_phy_ll.h
View File

@ -21,7 +21,7 @@ extern "C" {
*
* @param hw Start address of the USB Wrap registers
*/
static inline void usb_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
static inline void usb_fsls_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
{
hw->otg_conf.phy_sel = 0;
}
@ -31,7 +31,7 @@ static inline void usb_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
*
* @param hw Start address of the USB Wrap registers
*/
static inline void usb_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw)
static inline void usb_fsls_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw)
{
//Enable external PHY
hw->otg_conf.phy_sel = 1;
@ -46,7 +46,7 @@ static inline void usb_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw)
* @param dm_pu D- pullup load
* @param dm_pd D- pulldown load
*/
static inline void usb_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
static inline void usb_fsls_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
{
usb_wrap_otg_conf_reg_t conf;
conf.val = hw->otg_conf.val;
@ -63,7 +63,7 @@ static inline void usb_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool
* @param hw Start address of the USB Wrap registers
* @param pad_en Enable the PHY control to D+/D- pad
*/
static inline void usb_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_en)
static inline void usb_fsls_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_en)
{
hw->otg_conf.pad_enable = pad_en;
}
@ -74,7 +74,7 @@ static inline void usb_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_e
* @param hw Start address of the USB Wrap registers
* @param en Whether to enable the internal PHY's test mode
*/
static inline void usb_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en)
static inline void usb_fsls_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en)
{
if (en) {
// Clear USB_WRAP_TEST_CONF_REG
@ -92,25 +92,25 @@ static inline void usb_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en)
* Enable the bus clock for USB Wrap module
* @param clk_en True if enable the clock of USB Wrap module
*/
FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_enable_bus_clock(bool clk_en)
FORCE_INLINE_ATTR void usb_fsls_phy_ll_usb_wrap_enable_bus_clock(bool clk_en)
{
REG_SET_FIELD(DPORT_PERIP_CLK_EN0_REG, DPORT_USB_CLK_EN, clk_en);
}
// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way
#define usb_phy_ll_usb_wrap_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_phy_ll_usb_wrap_enable_bus_clock(__VA_ARGS__)
#define usb_fsls_phy_ll_usb_wrap_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_fsls_phy_ll_usb_wrap_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the USB Wrap module
*/
FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_reset_register(void)
FORCE_INLINE_ATTR void usb_fsls_phy_ll_usb_wrap_reset_register(void)
{
REG_SET_FIELD(DPORT_PERIP_RST_EN0_REG, DPORT_USB_RST, 1);
REG_SET_FIELD(DPORT_PERIP_RST_EN0_REG, DPORT_USB_RST, 0);
}
// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way
#define usb_phy_ll_usb_wrap_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_phy_ll_usb_wrap_reset_register(__VA_ARGS__)
#define usb_fsls_phy_ll_usb_wrap_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_fsls_phy_ll_usb_wrap_reset_register(__VA_ARGS__)
#ifdef __cplusplus
}

22
components/hal/esp32s3/include/hal/usb_phy_ll.h → components/hal/esp32s3/include/hal/usb_fsls_phy_ll.h
View File

@ -23,7 +23,7 @@ extern "C" {
*
* @param hw Start address of the USB Wrap registers
*/
static inline void usb_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
static inline void usb_fsls_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
{
// USB_OTG use internal PHY
hw->otg_conf.phy_sel = 0;
@ -38,7 +38,7 @@ static inline void usb_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
*
* @param hw Start address of the USB Wrap registers
*/
static inline void usb_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw)
static inline void usb_fsls_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw)
{
// USB_OTG use external PHY
hw->otg_conf.phy_sel = 1;
@ -53,7 +53,7 @@ static inline void usb_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw)
*
* @param hw Start address of the USB Serial_JTAG registers
*/
static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
{
// USB_Serial_JTAG use internal PHY
hw->conf0.phy_sel = 0;
@ -74,7 +74,7 @@ static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
*
* @param hw Start address of the USB Serial_JTAG registers
*/
static inline void usb_phy_ll_ext_jtag_enable(usb_serial_jtag_dev_t *hw)
static inline void usb_fsls_phy_ll_ext_jtag_enable(usb_serial_jtag_dev_t *hw)
{
// USB_Serial_JTAG use external PHY
hw->conf0.phy_sel = 1;
@ -93,7 +93,7 @@ static inline void usb_phy_ll_ext_jtag_enable(usb_serial_jtag_dev_t *hw)
* @param dm_pu D- pullup load
* @param dm_pd D- pulldown load
*/
static inline void usb_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
static inline void usb_fsls_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
{
usb_wrap_otg_conf_reg_t conf;
conf.val = hw->otg_conf.val;
@ -112,7 +112,7 @@ static inline void usb_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool
* @param hw Start address of the USB Wrap registers
* @param pad_en Enable the PHY control to D+/D- pad
*/
static inline void usb_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_en)
static inline void usb_fsls_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_en)
{
hw->otg_conf.pad_enable = pad_en;
}
@ -123,7 +123,7 @@ static inline void usb_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_e
* @param hw Start address of the USB Wrap registers
* @param en Whether to enable the internal PHY's test mode
*/
static inline void usb_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en)
static inline void usb_fsls_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en)
{
if (en) {
// Clear USB_WRAP_TEST_CONF_REG
@ -141,25 +141,25 @@ static inline void usb_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en)
* Enable the bus clock for USB Wrap module
* @param clk_en True if enable the clock of USB Wrap module
*/
FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_enable_bus_clock(bool clk_en)
FORCE_INLINE_ATTR void usb_fsls_phy_ll_usb_wrap_enable_bus_clock(bool clk_en)
{
SYSTEM.perip_clk_en0.usb_clk_en = clk_en;
}
// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way
#define usb_phy_ll_usb_wrap_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_phy_ll_usb_wrap_enable_bus_clock(__VA_ARGS__)
#define usb_fsls_phy_ll_usb_wrap_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_fsls_phy_ll_usb_wrap_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the USB Wrap module
*/
FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_reset_register(void)
FORCE_INLINE_ATTR void usb_fsls_phy_ll_usb_wrap_reset_register(void)
{
SYSTEM.perip_rst_en0.usb_rst = 1;
SYSTEM.perip_rst_en0.usb_rst = 0;
}
// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way
#define usb_phy_ll_usb_wrap_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_phy_ll_usb_wrap_reset_register(__VA_ARGS__)
#define usb_fsls_phy_ll_usb_wrap_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_fsls_phy_ll_usb_wrap_reset_register(__VA_ARGS__)
#ifdef __cplusplus
}

16
components/hal/include/hal/usb_phy_hal.h → components/hal/include/hal/usb_fsls_phy_hal.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -31,7 +31,7 @@ typedef struct {
#if SOC_USB_SERIAL_JTAG_SUPPORTED
usb_serial_jtag_dev_t *jtag_dev; /**< Pointer to base address of USB Serial JTAG registers */
#endif
} usb_phy_hal_context_t;
} usb_fsls_phy_hal_context_t;
/**
@ -39,7 +39,7 @@ typedef struct {
*
* @param hal Context of the HAL layer
*/
void usb_phy_hal_init(usb_phy_hal_context_t *hal);
void usb_fsls_phy_hal_init(usb_fsls_phy_hal_context_t *hal);
/**
* @brief Configure internal/external PHY for USB_OTG
@ -47,7 +47,7 @@ void usb_phy_hal_init(usb_phy_hal_context_t *hal);
* @param hal Context of the HAL layer
* @param phy_target USB PHY target
*/
void usb_phy_hal_otg_conf(usb_phy_hal_context_t *hal, usb_phy_target_t phy_target);
void usb_fsls_phy_hal_otg_conf(usb_fsls_phy_hal_context_t *hal, usb_phy_target_t phy_target);
#if SOC_USB_SERIAL_JTAG_SUPPORTED
/**
@ -56,7 +56,7 @@ void usb_phy_hal_otg_conf(usb_phy_hal_context_t *hal, usb_phy_target_t phy_targe
* @param hal Context of the HAL layer
* @param phy_target USB PHY target
*/
void usb_phy_hal_jtag_conf(usb_phy_hal_context_t *hal, usb_phy_target_t phy_target);
void usb_fsls_phy_hal_jtag_conf(usb_fsls_phy_hal_context_t *hal, usb_phy_target_t phy_target);
#endif
/**
@ -64,7 +64,7 @@ void usb_phy_hal_jtag_conf(usb_phy_hal_context_t *hal, usb_phy_target_t phy_targ
*
* @param hal Context of the HAL layer
*/
void usb_phy_hal_int_load_conf_host(usb_phy_hal_context_t *hal);
void usb_fsls_phy_hal_int_load_conf_host(usb_fsls_phy_hal_context_t *hal);
/**
* @brief Configure pullup/pulldown loads for the D+/D- as a device
@ -72,7 +72,7 @@ void usb_phy_hal_int_load_conf_host(usb_phy_hal_context_t *hal);
* @param hal Context of the HAL layer
* @param speed USB speed
*/
void usb_phy_hal_int_load_conf_dev(usb_phy_hal_context_t *hal, usb_phy_speed_t speed);
void usb_fsls_phy_hal_int_load_conf_dev(usb_fsls_phy_hal_context_t *hal, usb_phy_speed_t speed);
/**
* @brief Enable/Disable test mode for internal PHY to mimick host-device disconnection
@ -80,7 +80,7 @@ void usb_phy_hal_int_load_conf_dev(usb_phy_hal_context_t *hal, usb_phy_speed_t s
* @param hal Context of the HAL layer
* @param disconn Whether to disconnect
*/
void usb_phy_hal_int_mimick_disconn(usb_phy_hal_context_t *hal, bool disconn);
void usb_fsls_phy_hal_int_mimick_disconn(usb_fsls_phy_hal_context_t *hal, bool disconn);
#endif

64
components/hal/usb_fsls_phy_hal.c Normal file
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@ -0,0 +1,64 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/usb_fsls_phy_ll.h"
#include "hal/usb_fsls_phy_hal.h"
void usb_fsls_phy_hal_init(usb_fsls_phy_hal_context_t *hal)
{
hal->wrap_dev = &USB_WRAP;
#if SOC_USB_SERIAL_JTAG_SUPPORTED
hal->jtag_dev = &USB_SERIAL_JTAG;
#endif
}
void usb_fsls_phy_hal_otg_conf(usb_fsls_phy_hal_context_t *hal, usb_phy_target_t phy_target)
{
if (phy_target == USB_PHY_TARGET_EXT) {
usb_fsls_phy_ll_ext_otg_enable(hal->wrap_dev);
} else if (phy_target == USB_PHY_TARGET_INT) {
usb_fsls_phy_ll_usb_wrap_pad_enable(hal->wrap_dev, true);
usb_fsls_phy_ll_int_otg_enable(hal->wrap_dev);
}
}
#if SOC_USB_SERIAL_JTAG_SUPPORTED
void usb_fsls_phy_hal_jtag_conf(usb_fsls_phy_hal_context_t *hal, usb_phy_target_t phy_target)
{
if (phy_target == USB_PHY_TARGET_EXT) {
usb_fsls_phy_ll_ext_jtag_enable(hal->jtag_dev);
} else if (phy_target == USB_PHY_TARGET_INT) {
usb_fsls_phy_ll_int_jtag_enable(hal->jtag_dev);
}
}
#endif
void usb_fsls_phy_hal_int_load_conf_host(usb_fsls_phy_hal_context_t *hal)
{
// HOST - upstream: dp_pd = 1, dm_pd = 1
usb_fsls_phy_ll_int_load_conf(hal->wrap_dev, false, true, false, true);
}
void usb_fsls_phy_hal_int_load_conf_dev(usb_fsls_phy_hal_context_t *hal, usb_phy_speed_t speed)
{
// DEVICE - downstream
if (speed == USB_PHY_SPEED_LOW) {
// LS: dm_pu = 1
usb_fsls_phy_ll_int_load_conf(hal->wrap_dev, false, false, true, false);
} else {
// FS: dp_pu = 1
usb_fsls_phy_ll_int_load_conf(hal->wrap_dev, true, false, false, false);
}
}
void usb_fsls_phy_hal_int_mimick_disconn(usb_fsls_phy_hal_context_t *hal, bool disconn)
{
/*
We mimick a disconnect by enabling the internal PHY's test mode, then forcing the output_enable to HIGH. This will:
A HIGH output_enable will cause the received VP and VM to be zero, thus mimicking a disconnection.
*/
usb_fsls_phy_ll_int_enable_test_mode(hal->wrap_dev, disconn);
}

64
components/hal/usb_phy_hal.c
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@ -1,64 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/usb_phy_ll.h"
#include "hal/usb_phy_hal.h"
void usb_phy_hal_init(usb_phy_hal_context_t *hal)
{
hal->wrap_dev = &USB_WRAP;
#if SOC_USB_SERIAL_JTAG_SUPPORTED
hal->jtag_dev = &USB_SERIAL_JTAG;
#endif
}
void usb_phy_hal_otg_conf(usb_phy_hal_context_t *hal, usb_phy_target_t phy_target)
{
if (phy_target == USB_PHY_TARGET_EXT) {
usb_phy_ll_ext_otg_enable(hal->wrap_dev);
} else if (phy_target == USB_PHY_TARGET_INT) {
usb_phy_ll_usb_wrap_pad_enable(hal->wrap_dev, true);
usb_phy_ll_int_otg_enable(hal->wrap_dev);
}
}
#if SOC_USB_SERIAL_JTAG_SUPPORTED
void usb_phy_hal_jtag_conf(usb_phy_hal_context_t *hal, usb_phy_target_t phy_target)
{
if (phy_target == USB_PHY_TARGET_EXT) {
usb_phy_ll_ext_jtag_enable(hal->jtag_dev);
} else if (phy_target == USB_PHY_TARGET_INT) {
usb_phy_ll_int_jtag_enable(hal->jtag_dev);
}
}
#endif
void usb_phy_hal_int_load_conf_host(usb_phy_hal_context_t *hal)
{
// HOST - upstream: dp_pd = 1, dm_pd = 1
usb_phy_ll_int_load_conf(hal->wrap_dev, false, true, false, true);
}
void usb_phy_hal_int_load_conf_dev(usb_phy_hal_context_t *hal, usb_phy_speed_t speed)
{
// DEVICE - downstream
if (speed == USB_PHY_SPEED_LOW) {
// LS: dm_pu = 1
usb_phy_ll_int_load_conf(hal->wrap_dev, false, false, true, false);
} else {
// FS: dp_pu = 1
usb_phy_ll_int_load_conf(hal->wrap_dev, true, false, false, false);
}
}
void usb_phy_hal_int_mimick_disconn(usb_phy_hal_context_t *hal, bool disconn)
{
/*
We mimick a disconnect by enabling the internal PHY's test mode, then forcing the output_enable to HIGH. This will:
A HIGH output_enable will cause the received VP and VM to be zero, thus mimicking a disconnection.
*/
usb_phy_ll_int_enable_test_mode(hal->wrap_dev, disconn);
}

2
components/soc/esp32s2/include/soc/usb_wrap_struct.h
View File

@ -153,7 +153,7 @@ typedef union {
* USB D- rx value in test.
*/
uint32_t test_rx_dm:1;
uint32_t reserved:25;
uint32_t reserved_7:25;
};
uint32_t val;
} usb_wrap_test_conf_reg_t;

2
components/soc/esp32s3/include/soc/usb_wrap_struct.h
View File

@ -154,7 +154,7 @@ typedef union {
* USB D- rx value in test.
*/
uint32_t test_rx_dm:1;
uint32_t reserved7:25;
uint32_t reserved_7:25;
};
uint32_t val;
} usb_wrap_test_conf_reg_t;

30
components/usb/usb_phy.c
View File

@ -12,8 +12,8 @@
#include "esp_private/periph_ctrl.h"
#include "esp_private/usb_phy.h"
#include "soc/usb_otg_periph.h"
#include "hal/usb_phy_hal.h"
#include "hal/usb_phy_ll.h"
#include "hal/usb_fsls_phy_hal.h"
#include "hal/usb_fsls_phy_ll.h"
#include "esp_rom_gpio.h"
#include "driver/gpio.h"
#include "hal/gpio_ll.h"
@ -39,7 +39,7 @@ struct phy_context_t {
usb_otg_mode_t otg_mode; /**< USB OTG mode */
usb_phy_speed_t otg_speed; /**< USB speed */
usb_phy_ext_io_conf_t *iopins; /**< external PHY I/O pins */
usb_phy_hal_context_t hal_context; /**< USB_PHY hal context */
usb_fsls_phy_hal_context_t hal_context; /**< USB_PHY hal context */
};
typedef struct {
@ -126,7 +126,7 @@ esp_err_t usb_phy_otg_set_mode(usb_phy_handle_t handle, usb_otg_mode_t mode)
esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_VBUSVALID_IN_IDX, false); // receiving a valid Vbus from host
esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_AVALID_IN_IDX, false); // HIGH to force USB host mode
if (handle->target == USB_PHY_TARGET_INT) {
usb_phy_hal_int_load_conf_host(&(handle->hal_context));
usb_fsls_phy_hal_int_load_conf_host(&(handle->hal_context));
}
} else if (mode == USB_OTG_MODE_DEVICE) {
esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_IDDIG_IN_IDX, false); // connected connector is mini-B side
@ -147,7 +147,7 @@ esp_err_t usb_phy_otg_dev_set_speed(usb_phy_handle_t handle, usb_phy_speed_t spe
USBPHY_TAG, "set speed not supported");
handle->otg_speed = speed;
usb_phy_hal_int_load_conf_dev(&(handle->hal_context), speed);
usb_fsls_phy_hal_int_load_conf_dev(&(handle->hal_context), speed);
return ESP_OK;
}
@ -163,7 +163,7 @@ esp_err_t usb_phy_action(usb_phy_handle_t handle, usb_phy_action_t action)
switch (action) {
case USB_PHY_ACTION_HOST_ALLOW_CONN:
if (handle->target == USB_PHY_TARGET_INT) {
usb_phy_hal_int_mimick_disconn(&(handle->hal_context), false);
usb_fsls_phy_hal_int_mimick_disconn(&(handle->hal_context), false);
} else {
if (!handle->iopins) {
ret = ESP_FAIL;
@ -180,7 +180,7 @@ esp_err_t usb_phy_action(usb_phy_handle_t handle, usb_phy_action_t action)
case USB_PHY_ACTION_HOST_FORCE_DISCONN:
if (handle->target == USB_PHY_TARGET_INT) {
usb_phy_hal_int_mimick_disconn(&(handle->hal_context), true);
usb_fsls_phy_hal_int_mimick_disconn(&(handle->hal_context), true);
} else {
/*
Disable connections on the external PHY by connecting the VP and VM signals to the constant LOW signal.
@ -223,8 +223,8 @@ static esp_err_t usb_phy_install(void)
// Enable USB peripheral and reset the register
portEXIT_CRITICAL(&phy_spinlock);
USB_WRAP_RCC_ATOMIC() {
usb_phy_ll_usb_wrap_enable_bus_clock(true);
usb_phy_ll_usb_wrap_reset_register();
usb_fsls_phy_ll_usb_wrap_enable_bus_clock(true);
usb_fsls_phy_ll_usb_wrap_reset_register();
}
return ESP_OK;
@ -263,13 +263,13 @@ esp_err_t usb_new_phy(const usb_phy_config_t *config, usb_phy_handle_t *handle_r
phy_context->controller = config->controller;
phy_context->status = USB_PHY_STATUS_IN_USE;
usb_phy_hal_init(&(phy_context->hal_context));
usb_fsls_phy_hal_init(&(phy_context->hal_context));
if (config->controller == USB_PHY_CTRL_OTG) {
usb_phy_hal_otg_conf(&(phy_context->hal_context), config->target == USB_PHY_TARGET_EXT);
usb_fsls_phy_hal_otg_conf(&(phy_context->hal_context), config->target == USB_PHY_TARGET_EXT);
}
#if SOC_USB_SERIAL_JTAG_SUPPORTED
else if (config->controller == USB_PHY_CTRL_SERIAL_JTAG) {
usb_phy_hal_jtag_conf(&(phy_context->hal_context), config->target == USB_PHY_TARGET_EXT);
usb_fsls_phy_hal_jtag_conf(&(phy_context->hal_context), config->target == USB_PHY_TARGET_EXT);
phy_context->otg_mode = USB_OTG_MODE_DEVICE;
phy_context->otg_speed = USB_PHY_SPEED_FULL;
}
@ -317,7 +317,7 @@ static void phy_uninstall(void)
p_phy_ctrl_obj = NULL;
USB_WRAP_RCC_ATOMIC() {
// Disable USB peripheral without reset the module
usb_phy_ll_usb_wrap_enable_bus_clock(false);
usb_fsls_phy_ll_usb_wrap_enable_bus_clock(false);
}
}
portEXIT_CRITICAL(&phy_spinlock);
@ -334,8 +334,8 @@ esp_err_t usb_del_phy(usb_phy_handle_t handle)
p_phy_ctrl_obj->external_phy = NULL;
} else {
// Clear pullup and pulldown loads on D+ / D-, and disable the pads
usb_phy_ll_int_load_conf(handle->hal_context.wrap_dev, false, false, false, false);
usb_phy_ll_usb_wrap_pad_enable(handle->hal_context.wrap_dev, false);
usb_fsls_phy_ll_int_load_conf(handle->hal_context.wrap_dev, false, false, false, false);
usb_fsls_phy_ll_usb_wrap_pad_enable(handle->hal_context.wrap_dev, false);
p_phy_ctrl_obj->internal_phy = NULL;
}
portEXIT_CRITICAL(&phy_spinlock);