mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
esp32c6: add bootloader support
This commit is contained in:
wuzhenghui
Song Ruo Jing
parent
a9f15d1556
commit
1c820b0a6d
200
components/bootloader/subproject/main/ld/esp32c6/bootloader.ld
Normal file
200
components/bootloader/subproject/main/ld/esp32c6/bootloader.ld
Normal file
@ -0,0 +1,200 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** Simplified memory map for the bootloader.
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* Make sure the bootloader can load into main memory without overwriting itself.
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* We put 2nd bootloader in the high address space (before ROM stack/data/bss).
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* See memory usage for ROM bootloader at the end of this file.
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*/
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MEMORY
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{
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iram_seg (RWX) : org = 0x4086E000, len = 0x2000
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iram_loader_seg (RWX) : org = 0x40870000, len = 0x6000
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dram_seg (RW) : org = 0x40876000, len = 0x4000
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}
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/* Default entry point: */
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ENTRY(call_start_cpu0);
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SECTIONS
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{
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.iram_loader.text :
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{
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. = ALIGN (16);
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_loader_text_start = ABSOLUTE(.);
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*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
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*liblog.a:(.literal .text .literal.* .text.*)
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*libgcc.a:(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
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*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
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*libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
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*libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
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*libspi_flash.a:*.*(.literal .text .literal.* .text.*)
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*libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
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*libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
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*libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
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*libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
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*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
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*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
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*libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
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*libefuse.a:*.*(.literal .text .literal.* .text.*)
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*(.fini.literal)
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*(.fini)
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*(.gnu.version)
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_loader_text_end = ABSOLUTE(.);
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} > iram_loader_seg
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.iram.text :
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{
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. = ALIGN (16);
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*(.entry.text)
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*(.init.literal)
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*(.init)
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} > iram_seg
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/* Shared RAM */
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.dram0.bss (NOLOAD) :
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{
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. = ALIGN (8);
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_dram_start = ABSOLUTE(.);
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_bss_start = ABSOLUTE(.);
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*(.dynsbss)
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*(.sbss)
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*(.sbss.*)
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*(.gnu.linkonce.sb.*)
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*(.scommon)
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*(.sbss2)
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*(.sbss2.*)
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*(.gnu.linkonce.sb2.*)
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*(.dynbss)
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*(.bss)
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*(.bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN (8);
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_bss_end = ABSOLUTE(.);
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} > dram_seg
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.dram0.data :
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{
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_data_start = ABSOLUTE(.);
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*(.data)
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*(.data.*)
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*(.gnu.linkonce.d.*)
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*(.data1)
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*(.sdata)
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*(.sdata.*)
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*(.gnu.linkonce.s.*)
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*(.gnu.linkonce.s2.*)
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*(.jcr)
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_data_end = ABSOLUTE(.);
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} > dram_seg
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.dram0.rodata :
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{
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_rodata_start = ABSOLUTE(.);
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*(.rodata)
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*(.rodata.*)
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*(.gnu.linkonce.r.*)
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*(.rodata1)
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*(.sdata2 .sdata2.* .srodata .srodata.*)
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__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
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*(.xt_except_table)
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*(.gcc_except_table)
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*(.gnu.linkonce.e.*)
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*(.gnu.version_r)
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*(.eh_frame)
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. = (. + 3) & ~ 3;
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/* C++ constructor and destructor tables, properly ordered: */
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__init_array_start = ABSOLUTE(.);
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KEEP (*crtbegin.*(.ctors))
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KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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__init_array_end = ABSOLUTE(.);
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KEEP (*crtbegin.*(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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/* C++ exception handlers table: */
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__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
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*(.xt_except_desc)
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*(.gnu.linkonce.h.*)
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__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
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*(.xt_except_desc_end)
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*(.dynamic)
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*(.gnu.version_d)
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_rodata_end = ABSOLUTE(.);
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/* Literals are also RO data. */
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_lit4_start = ABSOLUTE(.);
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*(*.lit4)
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*(.lit4.*)
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*(.gnu.linkonce.lit4.*)
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_lit4_end = ABSOLUTE(.);
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. = ALIGN(4);
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_dram_end = ABSOLUTE(.);
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} > dram_seg
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.iram.text :
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{
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_stext = .;
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_text_start = ABSOLUTE(.);
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*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.iram .iram.*) /* catch stray IRAM_ATTR */
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*(.fini.literal)
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*(.fini)
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*(.gnu.version)
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/** CPU will try to prefetch up to 16 bytes of
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* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
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* safe access to up to 16 bytes after the last real instruction, add
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* dummy bytes to ensure this
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*/
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. += 16;
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_text_end = ABSOLUTE(.);
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_etext = .;
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} > iram_seg
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}
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/**
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* Appendix: Memory Usage of ROM bootloader
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*
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* +--------+--------------+------+ 0x3FCC_AE00
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* | ^ |
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* | | |
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* | | data/bss |
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* | | |
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* | v |
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* +------------------------------+ 0x3FCD_C710
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* | ^ |
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* | | |
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* | | stack |
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* | | |
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* | v |
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* +------------------------------+ 0x3FCD_E710
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*/
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@ -0,0 +1,6 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* No definition for ESP32-C6 target */
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@ -128,9 +128,9 @@ static const char *TAG = "bootloader_flash";
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50th block for bootloader_flash_read
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*/
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#define MMU_BLOCK0_VADDR SOC_DROM_LOW
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#define MMU_SIZE (0x320000)
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#define MMU_BLOCK50_VADDR (MMU_BLOCK0_VADDR + MMU_SIZE)
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#define FLASH_READ_VADDR MMU_BLOCK50_VADDR
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#define MMAP_MMU_SIZE (0x320000)
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#define MMU_BLOCK50_VADDR (MMU_BLOCK0_VADDR + MMAP_MMU_SIZE)
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#define FLASH_READ_VADDR MMU_BLOCK50_VADDR
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#else // !CONFIG_IDF_TARGET_ESP32
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@ -139,15 +139,15 @@ static const char *TAG = "bootloader_flash";
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*/
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#define MMU_BLOCK0_VADDR SOC_DROM_LOW
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#ifdef SOC_MMU_PAGE_SIZE_CONFIGURABLE
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#define MMU_SIZE (DRAM0_CACHE_ADDRESS_HIGH(SPI_FLASH_MMU_PAGE_SIZE) - DRAM0_CACHE_ADDRESS_LOW - SPI_FLASH_MMU_PAGE_SIZE) // This mmu size means that the mmu size to be mapped
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#define MMAP_MMU_SIZE (DRAM0_CACHE_ADDRESS_HIGH(SPI_FLASH_MMU_PAGE_SIZE) - DRAM0_CACHE_ADDRESS_LOW - SPI_FLASH_MMU_PAGE_SIZE) // This mmu size means that the mmu size to be mapped
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#else
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#define MMU_SIZE (DRAM0_CACHE_ADDRESS_HIGH - DRAM0_CACHE_ADDRESS_LOW - SPI_FLASH_MMU_PAGE_SIZE) // This mmu size means that the mmu size to be mapped
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#define MMAP_MMU_SIZE (DRAM0_CACHE_ADDRESS_HIGH - DRAM0_CACHE_ADDRESS_LOW - SPI_FLASH_MMU_PAGE_SIZE) // This mmu size means that the mmu size to be mapped
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#endif
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#define MMU_BLOCK63_VADDR (MMU_BLOCK0_VADDR + MMU_SIZE)
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#define MMU_BLOCK63_VADDR (MMU_BLOCK0_VADDR + MMAP_MMU_SIZE)
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#define FLASH_READ_VADDR MMU_BLOCK63_VADDR
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#endif
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#define MMU_FREE_PAGES (MMU_SIZE / FLASH_BLOCK_SIZE)
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#define MMU_FREE_PAGES (MMAP_MMU_SIZE / CONFIG_MMU_PAGE_SIZE)
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static bool mapped;
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@ -169,7 +169,7 @@ const void *bootloader_mmap(uint32_t src_paddr, uint32_t size)
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ESP_EARLY_LOGE(TAG, "tried to bootloader_mmap twice");
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return NULL; /* can't map twice */
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}
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if (size > MMU_SIZE) {
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if (size > MMAP_MMU_SIZE) {
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ESP_EARLY_LOGE(TAG, "bootloader_mmap excess size %x", size);
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return NULL;
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}
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@ -769,10 +769,8 @@ esp_err_t IRAM_ATTR bootloader_flash_reset_chip(void)
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bootloader_execute_flash_command(0x05, 0, 0, 0);
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#if CONFIG_IDF_TARGET_ESP32
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if (SPI1.ext2.st != 0)
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#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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if (SPIMEM1.fsm.st != 0)
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#else
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if (SPIMEM1.fsm.spi0_mst_st != 0)
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if (!spimem_flash_ll_host_idle(&SPIMEM1))
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#endif
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{
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return ESP_FAIL;
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@ -0,0 +1,69 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdbool.h>
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#include <assert.h>
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#include "string.h"
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#include "sdkconfig.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "esp32c6/rom/gpio.h"
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#include "esp32c6/rom/spi_flash.h"
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#include "esp32c6/rom/efuse.h"
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#include "soc/gpio_periph.h"
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#include "soc/efuse_reg.h"
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#include "soc/spi_reg.h"
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#include "soc/spi_mem_reg.h"
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#include "soc/soc_caps.h"
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#include "flash_qio_mode.h"
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#include "bootloader_flash_config.h"
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#include "bootloader_common.h"
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void bootloader_flash_update_id()
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{
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esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
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chip->device_id = bootloader_read_flash_id();
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}
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void IRAM_ATTR bootloader_flash_cs_timing_config()
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{
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SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
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SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
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SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
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}
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void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
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{
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uint32_t spi_clk_div = 0;
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switch (pfhdr->spi_speed) {
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case ESP_IMAGE_SPI_SPEED_DIV_1:
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spi_clk_div = 1;
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break;
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case ESP_IMAGE_SPI_SPEED_DIV_2:
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spi_clk_div = 2;
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break;
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case ESP_IMAGE_SPI_SPEED_DIV_3:
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spi_clk_div = 3;
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break;
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case ESP_IMAGE_SPI_SPEED_DIV_4:
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spi_clk_div = 4;
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break;
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default:
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break;
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}
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esp_rom_spiflash_config_clk(spi_clk_div, 0);
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}
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void IRAM_ATTR bootloader_flash_set_dummy_out(void)
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{
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REG_SET_BIT(SPI_MEM_CTRL_REG(0), /*SPI_MEM_FDUMMY_OUT |*/ SPI_MEM_D_POL | SPI_MEM_Q_POL); // TODO: IDF-5631 ESP32C6 not have SPI_MEM_FDUMMY_OUT
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REG_SET_BIT(SPI_MEM_CTRL_REG(1), /*SPI_MEM_FDUMMY_OUT |*/ SPI_MEM_D_POL | SPI_MEM_Q_POL); // TODO: idf-5631 ESP32C6 not have SPI_MEM_FDUMMY_OUT
|
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}
|
||||
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void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t *pfhdr)
|
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{
|
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bootloader_configure_spi_pins(1);
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bootloader_flash_set_dummy_out();
|
||||
}
|
||||
@ -106,8 +106,8 @@ static void s_flash_set_qio_pins(void)
|
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const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
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int wp_pin = bootloader_flash_get_wp_pin();
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esp_rom_spiflash_select_qio_pins(wp_pin, spiconfig);
|
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#elif CONFIG_IDF_TARGET_ESP32C2
|
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// ESP32C2 doesn't support configure mspi pins. So the second
|
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#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5649 Add a soc_caps
|
||||
// ESP32C2/ESP32C6 doesn't support configure mspi pins. So the second
|
||||
// parameter is set to 0, means that chip uses default SPI pins
|
||||
// and wp_gpio_num parameter(the first parameter) is ignored.
|
||||
esp_rom_spiflash_select_qio_pins(0, 0);
|
||||
|
||||
@ -22,6 +22,7 @@ typedef enum {
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
|
||||
ESP_CHIP_ID_ESP32H2 = 0x000A, /*!< chip ID: ESP32-H2 Beta1 */
|
||||
#endif
|
||||
ESP_CHIP_ID_ESP32C6 = 0x000D, /*!< chip ID: ESP32-C6 */
|
||||
ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
|
||||
} __attribute__((packed)) esp_chip_id_t;
|
||||
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||||
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||||
@ -21,6 +21,8 @@
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||||
#include "esp32h2/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2
|
||||
#include "esp32c2/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#include "esp32c6/rom/secure_boot.h"
|
||||
#endif
|
||||
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#if !CONFIG_IDF_TARGET_ESP32 || CONFIG_ESP32_REV_MIN_3
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@ -7,7 +7,16 @@
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||||
#include "soc/soc.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
|
||||
#if !CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5645
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#else
|
||||
#include "soc/lp_wdt_reg.h"
|
||||
#include "soc/lp_timer_reg.h"
|
||||
#include "soc/lp_analog_peri_reg.h"
|
||||
#include "soc/pmu_reg.h"
|
||||
#endif
|
||||
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||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "hal/clk_tree_ll.h"
|
||||
#endif
|
||||
@ -65,6 +74,24 @@ __attribute__((weak)) void bootloader_clock_configure(void)
|
||||
}
|
||||
#endif // CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
|
||||
|
||||
// TODO: IDF-5645
|
||||
#if CONFIG_IDF_TARGET_ESP32C6
|
||||
// CLR ENA
|
||||
CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_SUPER_WDT_INT_ENA); /* SWD */
|
||||
CLEAR_PERI_REG_MASK(LP_TIMER_LP_INT_ENA_REG, LP_TIMER_MAIN_TIMER_LP_INT_ENA); /* MAIN_TIMER */
|
||||
CLEAR_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_ENA_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA); /* BROWN_OUT */
|
||||
CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_LP_WDT_INT_ENA); /* WDT */
|
||||
CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_WAKEUP_INT_ENA); /* SLP_REJECT */
|
||||
CLEAR_PERI_REG_MASK(PMU_SOC_SLEEP_REJECT_INT_ENA, PMU_SOC_SLEEP_REJECT_INT_ENA); /* SLP_WAKEUP */
|
||||
// SET CLR
|
||||
SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_SUPER_WDT_INT_CLR); /* SWD */
|
||||
SET_PERI_REG_MASK(LP_TIMER_LP_INT_CLR_REG, LP_TIMER_MAIN_TIMER_LP_INT_CLR); /* MAIN_TIMER */
|
||||
SET_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR); /* BROWN_OUT */
|
||||
SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_LP_WDT_INT_CLR); /* WDT */
|
||||
SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_WAKEUP_INT_CLR); /* SLP_REJECT */
|
||||
SET_PERI_REG_MASK(PMU_SOC_SLEEP_REJECT_INT_CLR, PMU_SOC_SLEEP_REJECT_INT_CLR); /* SLP_WAKEUP */
|
||||
#else
|
||||
REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
|
||||
REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -28,6 +28,9 @@
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2
|
||||
#include "esp32c2/rom/ets_sys.h"
|
||||
#include "esp32c2/rom/uart.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#include "esp32c6/rom/ets_sys.h"
|
||||
#include "esp32c6/rom/uart.h"
|
||||
#endif
|
||||
#include "esp_rom_gpio.h"
|
||||
#include "esp_rom_uart.h"
|
||||
|
||||
@ -30,6 +30,9 @@ int bootloader_clock_get_rated_freq_mhz(void)
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
return 96;
|
||||
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
return 160;
|
||||
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
return 240;
|
||||
|
||||
|
||||
@ -58,27 +58,31 @@ void bootloader_config_wdt(void)
|
||||
* protect the remainder of the bootloader process.
|
||||
*/
|
||||
//Disable RWDT flashboot protection.
|
||||
wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
|
||||
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
|
||||
wdt_hal_set_flashboot_en(&rtc_wdt_ctx, false);
|
||||
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5653
|
||||
wdt_hal_context_t rwdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT};
|
||||
#else
|
||||
wdt_hal_context_t rwdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
|
||||
#endif
|
||||
wdt_hal_write_protect_disable(&rwdt_ctx);
|
||||
wdt_hal_set_flashboot_en(&rwdt_ctx, false);
|
||||
wdt_hal_write_protect_enable(&rwdt_ctx);
|
||||
|
||||
#ifdef CONFIG_BOOTLOADER_WDT_ENABLE
|
||||
//Initialize and start RWDT to protect the for bootloader if configured to do so
|
||||
ESP_LOGD(TAG, "Enabling RTCWDT(%d ms)", CONFIG_BOOTLOADER_WDT_TIME_MS);
|
||||
wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
|
||||
wdt_hal_init(&rwdt_ctx, WDT_RWDT, 0, false);
|
||||
uint32_t stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000);
|
||||
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
|
||||
wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
|
||||
wdt_hal_enable(&rtc_wdt_ctx);
|
||||
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
|
||||
wdt_hal_write_protect_disable(&rwdt_ctx);
|
||||
wdt_hal_config_stage(&rwdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
|
||||
wdt_hal_enable(&rwdt_ctx);
|
||||
wdt_hal_write_protect_enable(&rwdt_ctx);
|
||||
#endif
|
||||
|
||||
//Disable MWDT0 flashboot protection. But only after we've enabled the RWDT first so that there's not gap in WDT protection.
|
||||
wdt_hal_context_t wdt_ctx = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
|
||||
wdt_hal_write_protect_disable(&wdt_ctx);
|
||||
wdt_hal_set_flashboot_en(&wdt_ctx, false);
|
||||
wdt_hal_write_protect_enable(&wdt_ctx);
|
||||
wdt_hal_context_t mwdt_ctx = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
|
||||
wdt_hal_write_protect_disable(&mwdt_ctx);
|
||||
wdt_hal_set_flashboot_en(&mwdt_ctx, false);
|
||||
wdt_hal_write_protect_enable(&mwdt_ctx);
|
||||
}
|
||||
|
||||
void bootloader_enable_random(void)
|
||||
|
||||
@ -12,8 +12,21 @@
|
||||
#include "bootloader_mem.h"
|
||||
#include "esp_cpu.h"
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32C6
|
||||
#include "soc/hp_apm_reg.h"
|
||||
#include "soc/lp_apm_reg.h"
|
||||
#include "soc/lp_apm0_reg.h"
|
||||
#endif
|
||||
|
||||
void bootloader_init_mem(void)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C6
|
||||
// disable apm filter // TODO: IDF-5909
|
||||
REG_WRITE(LP_APM_FUNC_CTRL_REG, 0);
|
||||
REG_WRITE(LP_APM0_FUNC_CTRL_REG, 0);
|
||||
REG_WRITE(HP_APM_FUNC_CTRL_REG, 0);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE
|
||||
// protect memory region
|
||||
esp_cpu_configure_region_protection();
|
||||
|
||||
@ -0,0 +1,22 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include "sdkconfig.h"
|
||||
#include "bootloader_random.h"
|
||||
#include "esp_log.h"
|
||||
|
||||
static const char *TAG = "bootloader_random";
|
||||
|
||||
void bootloader_random_enable(void)
|
||||
{
|
||||
// TODO: IDF-5352
|
||||
ESP_EARLY_LOGW(TAG, "bootloader_random_enable() has not been implemented yet");
|
||||
}
|
||||
|
||||
void bootloader_random_disable(void)
|
||||
{
|
||||
// TODO: IDF-5352
|
||||
ESP_EARLY_LOGW(TAG, "bootloader_random_enable() has not been implemented yet");
|
||||
}
|
||||
@ -41,6 +41,13 @@
|
||||
#include "esp32c2/rom/uart.h"
|
||||
#include "esp32c2/rom/gpio.h"
|
||||
#include "esp32c2/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#include "esp32c6/rom/efuse.h"
|
||||
#include "esp32c6/rom/crc.h"
|
||||
#include "esp32c6/rom/rtc.h"
|
||||
#include "esp32c6/rom/uart.h"
|
||||
#include "esp32c6/rom/gpio.h"
|
||||
#include "esp32c6/rom/secure_boot.h"
|
||||
|
||||
#else // CONFIG_IDF_TARGET_*
|
||||
#error "Unsupported IDF_TARGET"
|
||||
|
||||
344
components/bootloader_support/src/esp32c6/bootloader_esp32c6.c
Normal file
344
components/bootloader_support/src/esp32c6/bootloader_esp32c6.c
Normal file
@ -0,0 +1,344 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <stdint.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_attr.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp_image_format.h"
|
||||
#include "flash_qio_mode.h"
|
||||
#include "esp_rom_gpio.h"
|
||||
#include "esp_rom_efuse.h"
|
||||
#include "esp_rom_uart.h"
|
||||
#include "esp_rom_sys.h"
|
||||
#include "esp_rom_spiflash.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
#include "soc/io_mux_reg.h"
|
||||
#include "soc/assist_debug_reg.h"
|
||||
#include "esp_cpu.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/spi_periph.h"
|
||||
#include "soc/extmem_reg.h"
|
||||
#include "soc/io_mux_reg.h"
|
||||
#include "soc/pcr_reg.h"
|
||||
#include "esp32c6/rom/efuse.h"
|
||||
#include "esp32c6/rom/ets_sys.h"
|
||||
#include "bootloader_common.h"
|
||||
#include "bootloader_init.h"
|
||||
#include "bootloader_clock.h"
|
||||
#include "bootloader_flash_config.h"
|
||||
#include "bootloader_mem.h"
|
||||
#include "esp_private/regi2c_ctrl.h"
|
||||
#include "soc/regi2c_lp_bias.h"
|
||||
#include "soc/regi2c_bias.h"
|
||||
#include "bootloader_console.h"
|
||||
#include "bootloader_flash_priv.h"
|
||||
#include "bootloader_soc.h"
|
||||
#include "esp_efuse.h"
|
||||
#include "hal/mmu_hal.h"
|
||||
#include "hal/cache_hal.h"
|
||||
#include "soc/lp_wdt_reg.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
|
||||
static const char *TAG = "boot.esp32c6";
|
||||
|
||||
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
// TODO: IDF-5649
|
||||
const uint32_t spiconfig = 0;
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
||||
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
||||
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
||||
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
||||
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
|
||||
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
|
||||
if (spiconfig == 0) {
|
||||
|
||||
}
|
||||
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
||||
esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
|
||||
if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
|
||||
esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
|
||||
}
|
||||
if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
|
||||
esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
|
||||
}
|
||||
}
|
||||
|
||||
static void update_flash_config(const esp_image_header_t *bootloader_hdr)
|
||||
{
|
||||
uint32_t size;
|
||||
switch (bootloader_hdr->spi_size) {
|
||||
case ESP_IMAGE_FLASH_SIZE_1MB:
|
||||
size = 1;
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_2MB:
|
||||
size = 2;
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_4MB:
|
||||
size = 4;
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_8MB:
|
||||
size = 8;
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_16MB:
|
||||
size = 16;
|
||||
break;
|
||||
default:
|
||||
size = 2;
|
||||
}
|
||||
cache_hal_disable(CACHE_TYPE_ALL);
|
||||
// Set flash chip size
|
||||
esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode
|
||||
cache_hal_enable(CACHE_TYPE_ALL);
|
||||
}
|
||||
|
||||
static void print_flash_info(const esp_image_header_t *bootloader_hdr)
|
||||
{
|
||||
ESP_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
|
||||
ESP_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
|
||||
ESP_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
|
||||
ESP_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
|
||||
ESP_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
|
||||
|
||||
const char *str;
|
||||
switch (bootloader_hdr->spi_speed) {
|
||||
case ESP_IMAGE_SPI_SPEED_DIV_2:
|
||||
str = "40MHz";
|
||||
break;
|
||||
case ESP_IMAGE_SPI_SPEED_DIV_3:
|
||||
str = "26.7MHz";
|
||||
break;
|
||||
case ESP_IMAGE_SPI_SPEED_DIV_4:
|
||||
str = "20MHz";
|
||||
break;
|
||||
case ESP_IMAGE_SPI_SPEED_DIV_1:
|
||||
str = "80MHz";
|
||||
break;
|
||||
default:
|
||||
str = "20MHz";
|
||||
break;
|
||||
}
|
||||
ESP_LOGI(TAG, "SPI Speed : %s", str);
|
||||
|
||||
/* SPI mode could have been set to QIO during boot already,
|
||||
so test the SPI registers not the flash header */
|
||||
uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
|
||||
if (spi_ctrl & SPI_MEM_FREAD_QIO) {
|
||||
str = "QIO";
|
||||
} else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {
|
||||
str = "QOUT";
|
||||
} else if (spi_ctrl & SPI_MEM_FREAD_DIO) {
|
||||
str = "DIO";
|
||||
} else if (spi_ctrl & SPI_MEM_FREAD_DUAL) {
|
||||
str = "DOUT";
|
||||
} else if (spi_ctrl & SPI_MEM_FASTRD_MODE) {
|
||||
str = "FAST READ";
|
||||
} else {
|
||||
str = "SLOW READ";
|
||||
}
|
||||
ESP_LOGI(TAG, "SPI Mode : %s", str);
|
||||
|
||||
switch (bootloader_hdr->spi_size) {
|
||||
case ESP_IMAGE_FLASH_SIZE_1MB:
|
||||
str = "1MB";
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_2MB:
|
||||
str = "2MB";
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_4MB:
|
||||
str = "4MB";
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_8MB:
|
||||
str = "8MB";
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_16MB:
|
||||
str = "16MB";
|
||||
break;
|
||||
default:
|
||||
str = "2MB";
|
||||
break;
|
||||
}
|
||||
ESP_LOGI(TAG, "SPI Flash Size : %s", str);
|
||||
}
|
||||
|
||||
static void IRAM_ATTR bootloader_init_flash_configure(void)
|
||||
{
|
||||
bootloader_flash_dummy_config(&bootloader_image_hdr);
|
||||
bootloader_flash_cs_timing_config();
|
||||
}
|
||||
|
||||
static void bootloader_spi_flash_resume(void)
|
||||
{
|
||||
bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0);
|
||||
esp_rom_spiflash_wait_idle(&g_rom_flashchip);
|
||||
}
|
||||
|
||||
static esp_err_t bootloader_init_spi_flash(void)
|
||||
{
|
||||
bootloader_init_flash_configure();
|
||||
// TODO: IDF-5649
|
||||
// #ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
|
||||
// const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
||||
// if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
|
||||
// ESP_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig");
|
||||
// return ESP_FAIL;
|
||||
// }
|
||||
// #endif
|
||||
|
||||
bootloader_spi_flash_resume();
|
||||
bootloader_flash_unlock();
|
||||
|
||||
#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
|
||||
bootloader_enable_qio_mode();
|
||||
#endif
|
||||
|
||||
print_flash_info(&bootloader_image_hdr);
|
||||
update_flash_config(&bootloader_image_hdr);
|
||||
//ensure the flash is write-protected
|
||||
bootloader_enable_wp();
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
static void wdt_reset_cpu0_info_enable(void)
|
||||
{
|
||||
REG_SET_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_CLK_EN);
|
||||
REG_CLR_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_RST_EN);
|
||||
REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN);
|
||||
}
|
||||
|
||||
static void wdt_reset_info_dump(int cpu)
|
||||
{
|
||||
(void) cpu;
|
||||
// saved PC was already printed by the ROM bootloader.
|
||||
// nothing to do here.
|
||||
}
|
||||
|
||||
static void bootloader_check_wdt_reset(void)
|
||||
{
|
||||
int wdt_rst = 0;
|
||||
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
|
||||
if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 ||
|
||||
rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) {
|
||||
ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
|
||||
wdt_rst = 1;
|
||||
}
|
||||
if (wdt_rst) {
|
||||
// if reset by WDT dump info from trace port
|
||||
wdt_reset_info_dump(0);
|
||||
}
|
||||
wdt_reset_cpu0_info_enable();
|
||||
}
|
||||
|
||||
static void bootloader_super_wdt_auto_feed(void)
|
||||
{
|
||||
REG_WRITE(LP_WDT_WPROTECT_REG, RTC_CNTL_SWD_WKEY_VALUE);
|
||||
REG_SET_BIT(LP_WDT_SWD_CONFIG_REG, LP_WDT_SWD_AUTO_FEED_EN);
|
||||
REG_WRITE(LP_WDT_WPROTECT_REG, 0);
|
||||
}
|
||||
|
||||
static inline void bootloader_hardware_init(void)
|
||||
{
|
||||
// TODO: IDF-5990 copied from C3, need update
|
||||
// This check is always included in the bootloader so it can
|
||||
// print the minimum revision error message later in the boot
|
||||
if (efuse_hal_get_minor_chip_version() < 3) {
|
||||
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 1);
|
||||
REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 12);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void bootloader_ana_reset_config(void)
|
||||
{
|
||||
// TODO: IDF-5990 copied from C3, need update
|
||||
/*
|
||||
esp32c6 has removed super wdt!
|
||||
For origin chip & ECO1: only support swt reset;
|
||||
For ECO2: fix brownout reset bug, support swt & brownout reset;
|
||||
For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
|
||||
*/
|
||||
uint8_t chip_version = efuse_hal_get_minor_chip_version();
|
||||
switch (chip_version) {
|
||||
case 0:
|
||||
case 1:
|
||||
//Disable BOR and GLITCH reset
|
||||
bootloader_ana_bod_reset_config(false);
|
||||
bootloader_ana_clock_glitch_reset_config(false);
|
||||
break;
|
||||
case 2:
|
||||
//Enable BOR reset. Disable GLITCH reset
|
||||
bootloader_ana_bod_reset_config(true);
|
||||
bootloader_ana_clock_glitch_reset_config(false);
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
//Enable BOR, and GLITCH reset
|
||||
bootloader_ana_bod_reset_config(true);
|
||||
bootloader_ana_clock_glitch_reset_config(true);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
esp_err_t bootloader_init(void)
|
||||
{
|
||||
esp_err_t ret = ESP_OK;
|
||||
|
||||
bootloader_hardware_init();
|
||||
bootloader_ana_reset_config();
|
||||
bootloader_super_wdt_auto_feed();
|
||||
// protect memory region
|
||||
bootloader_init_mem();
|
||||
/* check that static RAM is after the stack */
|
||||
assert(&_bss_start <= &_bss_end);
|
||||
assert(&_data_start <= &_data_end);
|
||||
// clear bss section
|
||||
bootloader_clear_bss_section();
|
||||
// init eFuse virtual mode (read eFuses to RAM)
|
||||
#ifdef CONFIG_EFUSE_VIRTUAL
|
||||
ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!");
|
||||
#ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
|
||||
esp_efuse_init_virtual_mode_in_ram();
|
||||
#endif
|
||||
#endif
|
||||
//init cache hal
|
||||
cache_hal_init();
|
||||
//reset mmu
|
||||
mmu_hal_init();
|
||||
// config clock
|
||||
bootloader_clock_configure();
|
||||
// initialize console, from now on, we can use esp_log
|
||||
bootloader_console_init();
|
||||
/* print 2nd bootloader banner */
|
||||
bootloader_print_banner();
|
||||
// update flash ID
|
||||
bootloader_flash_update_id();
|
||||
// Check and run XMC startup flow
|
||||
if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
|
||||
ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!");
|
||||
goto err;
|
||||
}
|
||||
// read bootloader header
|
||||
if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
|
||||
goto err;
|
||||
}
|
||||
// read chip revision and check if it's compatible to bootloader
|
||||
if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
|
||||
goto err;
|
||||
}
|
||||
// initialize spi flash
|
||||
if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
|
||||
goto err;
|
||||
}
|
||||
// check whether a WDT reset happend
|
||||
bootloader_check_wdt_reset();
|
||||
// config WDT
|
||||
bootloader_config_wdt();
|
||||
// enable RNG early entropy source
|
||||
bootloader_enable_random();
|
||||
err:
|
||||
return ret;
|
||||
}
|
||||
40
components/bootloader_support/src/esp32c6/bootloader_sha.c
Normal file
40
components/bootloader_support/src/esp32c6/bootloader_sha.c
Normal file
@ -0,0 +1,40 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include "bootloader_sha.h"
|
||||
#include <stdbool.h>
|
||||
#include <string.h>
|
||||
#include <assert.h>
|
||||
#include <sys/param.h>
|
||||
|
||||
#include "esp32c6/rom/sha.h"
|
||||
|
||||
static SHA_CTX ctx;
|
||||
|
||||
bootloader_sha256_handle_t bootloader_sha256_start()
|
||||
{
|
||||
// Enable SHA hardware
|
||||
ets_sha_enable();
|
||||
ets_sha_init(&ctx, SHA2_256);
|
||||
return &ctx; // Meaningless non-NULL value
|
||||
}
|
||||
|
||||
void bootloader_sha256_data(bootloader_sha256_handle_t handle, const void *data, size_t data_len)
|
||||
{
|
||||
assert(handle != NULL);
|
||||
assert(data_len % 4 == 0);
|
||||
ets_sha_update(&ctx, data, data_len, false);
|
||||
}
|
||||
|
||||
void bootloader_sha256_finish(bootloader_sha256_handle_t handle, uint8_t *digest)
|
||||
{
|
||||
assert(handle != NULL);
|
||||
|
||||
if (digest == NULL) {
|
||||
bzero(&ctx, sizeof(ctx));
|
||||
return;
|
||||
}
|
||||
ets_sha_finish(&ctx, digest);
|
||||
}
|
||||
28
components/bootloader_support/src/esp32c6/bootloader_soc.c
Normal file
28
components/bootloader_support/src/esp32c6/bootloader_soc.c
Normal file
@ -0,0 +1,28 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/lp_analog_peri_reg.h"
|
||||
|
||||
void bootloader_ana_bod_reset_config(bool enable)
|
||||
{
|
||||
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_BOR_RST);
|
||||
if (enable) {
|
||||
REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
|
||||
} else {
|
||||
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_BOD_MODE1_CNTL_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE1_RESET_ENA);
|
||||
}
|
||||
}
|
||||
|
||||
void bootloader_ana_clock_glitch_reset_config(bool enable)
|
||||
{
|
||||
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST);
|
||||
if (enable) {
|
||||
REG_SET_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
|
||||
} else {
|
||||
REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_CK_GLITCH_CNTL_REG, LP_ANALOG_PERI_LP_ANA_CK_GLITCH_RESET_ENA);
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,50 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <strings.h>
|
||||
#include "esp_flash_encrypt.h"
|
||||
#include "esp_secure_boot.h"
|
||||
#include "esp_efuse.h"
|
||||
#include "esp_efuse_table.h"
|
||||
#include "esp_log.h"
|
||||
#include "sdkconfig.h"
|
||||
|
||||
static __attribute__((unused)) const char *TAG = "flash_encrypt";
|
||||
|
||||
esp_err_t esp_flash_encryption_enable_secure_features(void)
|
||||
{
|
||||
#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC
|
||||
ESP_LOGI(TAG, "Disable UART bootloader encryption...");
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
|
||||
#else
|
||||
ESP_LOGW(TAG, "Not disabling UART bootloader encryption");
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE
|
||||
ESP_LOGI(TAG, "Disable UART bootloader cache...");
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
|
||||
#else
|
||||
ESP_LOGW(TAG, "Not disabling UART bootloader cache - SECURITY COMPROMISED");
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
|
||||
ESP_LOGI(TAG, "Disable JTAG...");
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG);
|
||||
#else
|
||||
ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
|
||||
#endif
|
||||
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
|
||||
|
||||
#if defined(CONFIG_SECURE_BOOT_V2_ENABLED) && !defined(CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS)
|
||||
// This bit is set when enabling Secure Boot V2, but we can't enable it until this later point in the first boot
|
||||
// otherwise the Flash Encryption key cannot be read protected
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS);
|
||||
#endif
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
@ -0,0 +1,70 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <strings.h>
|
||||
#include "esp_flash_encrypt.h"
|
||||
#include "esp_secure_boot.h"
|
||||
#include "esp_efuse.h"
|
||||
#include "esp_efuse_table.h"
|
||||
#include "esp_log.h"
|
||||
#include "sdkconfig.h"
|
||||
|
||||
static __attribute__((unused)) const char *TAG = "secure_boot";
|
||||
|
||||
esp_err_t esp_secure_boot_enable_secure_features(void)
|
||||
{
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
|
||||
|
||||
#ifdef CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE
|
||||
ESP_LOGI(TAG, "Enabling Security download mode...");
|
||||
esp_err_t err = esp_efuse_enable_rom_secure_download_mode();
|
||||
if (err != ESP_OK) {
|
||||
ESP_LOGE(TAG, "Could not enable Security download mode...");
|
||||
return err;
|
||||
}
|
||||
#elif CONFIG_SECURE_DISABLE_ROM_DL_MODE
|
||||
ESP_LOGI(TAG, "Disable ROM Download mode...");
|
||||
esp_err_t err = esp_efuse_disable_rom_download_mode();
|
||||
if (err != ESP_OK) {
|
||||
ESP_LOGE(TAG, "Could not disable ROM Download mode...");
|
||||
return err;
|
||||
}
|
||||
#else
|
||||
ESP_LOGW(TAG, "UART ROM Download mode kept enabled - SECURITY COMPROMISED");
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
|
||||
ESP_LOGI(TAG, "Disable hardware & software JTAG...");
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG);
|
||||
esp_efuse_write_field_cnt(ESP_EFUSE_SOFT_DIS_JTAG, ESP_EFUSE_SOFT_DIS_JTAG[0]->bit_count);
|
||||
#else
|
||||
ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT_ENABLE_AGGRESSIVE_KEY_REVOKE
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE);
|
||||
#endif
|
||||
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_EN);
|
||||
|
||||
#ifndef CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS
|
||||
bool rd_dis_now = true;
|
||||
#ifdef CONFIG_SECURE_FLASH_ENC_ENABLED
|
||||
/* If flash encryption is not enabled yet then don't read-disable efuses yet, do it later in the boot
|
||||
when Flash Encryption is being enabled */
|
||||
rd_dis_now = esp_flash_encryption_enabled();
|
||||
#endif
|
||||
if (rd_dis_now) {
|
||||
ESP_LOGI(TAG, "Prevent read disabling of additional efuses...");
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS);
|
||||
}
|
||||
#else
|
||||
ESP_LOGW(TAG, "Allowing read disabling of additional efuses - SECURITY COMPROMISED");
|
||||
#endif
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
@ -34,6 +34,9 @@
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2
|
||||
#include "esp32c2/rom/rtc.h"
|
||||
#include "esp32c2/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#include "esp32c6/rom/rtc.h"
|
||||
#include "esp32c6/rom/secure_boot.h"
|
||||
#endif
|
||||
|
||||
#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
|
||||
|
||||
@ -142,7 +142,7 @@ esp_flash_enc_mode_t esp_get_flash_encryption_mode(void)
|
||||
if (dis_dl_enc && dis_dl_icache && dis_dl_dcache) {
|
||||
mode = ESP_FLASH_ENC_MODE_RELEASE;
|
||||
}
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6
|
||||
bool dis_dl_enc = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
|
||||
bool dis_dl_icache = esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
|
||||
if (dis_dl_enc && dis_dl_icache) {
|
||||
@ -191,7 +191,7 @@ void esp_flash_encryption_set_release_mode(void)
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_DCACHE);
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
|
||||
#ifdef CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED
|
||||
|
||||
@ -429,7 +429,11 @@ esp_err_t esp_flash_encrypt_region(uint32_t src_addr, size_t data_length)
|
||||
return ESP_FAIL;
|
||||
}
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5653
|
||||
wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT};
|
||||
#else
|
||||
wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
|
||||
#endif
|
||||
for (size_t i = 0; i < data_length; i += FLASH_SECTOR_SIZE) {
|
||||
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
|
||||
wdt_hal_feed(&rtc_wdt_ctx);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user