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global: bring up esp32s2(not beta)

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This commit is contained in:
morris 2019-12-26 15:25:24 +08:00
parent a85b207d68
commit 1c2cc5430e
128 changed files with 17102 additions and 9733 deletions
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4
Kconfig
View File

@ -28,12 +28,12 @@ mainmenu "Espressif IoT Development Framework Configuration"
bool
default "y" if IDF_TARGET="esp32s2beta"
select FREERTOS_UNICORE
select IDF_ENV_FPGA
config IDF_FIRMWARE_CHIP_ID
hex
default 0x0000 if IDF_TARGET_ESP32
# note: S2 beta uses Chip ID 0 still, S2 will use 0x0002
default 0x0000 if IDF_TARGET_ESP32S2BETA
default 0x0002 if IDF_TARGET_ESP32S2BETA
default 0xFFFF
menu "SDK tool configuration"

2
components/bootloader/subproject/main/ld/esp32/bootloader.ld
View File

@ -11,8 +11,6 @@ Linker file used to link the bootloader.
MEMORY
{
/* I/O */
dport0_seg (RW) : org = 0x3FF00000, len = 0x10
/* IRAM POOL1, used for APP CPU cache. Bootloader runs from here during the final stage of loading the app because APP CPU is still held in reset, the main app enables APP CPU cache */
iram_loader_seg (RWX) : org = 0x40078000, len = 0x8000 /* 32KB, APP CPU cache */
/* 63kB, IRAM. We skip the first 1k to prevent the entry point being

19
components/bootloader/subproject/main/ld/esp32s2beta/bootloader.ld
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@ -1,22 +1,13 @@
/*
Linker file used to link the bootloader.
/* Simplified memory map for the bootloader.
* Make sure the bootloader can load into main memory without overwriting itself.
*/
/* Simplified memory map for the bootloader
The main purpose is to make sure the bootloader can load into main memory
without overwriting itself.
*/
MEMORY
{
/* I/O */
dport0_seg (RW) : org = 0x3FF00000, len = 0x10
iram_loader_seg (RWX) : org = 0x40062000, len = 0x4000 /* 16KB, IRAM */
iram_seg (RWX) : org = 0x40066000, len = 0x4000 /* 16KB, IRAM */
/* 8k at the end of DRAM, before ROM data & stack */
dram_seg (RW) : org = 0x3FFFA000, len = 0x2000
iram_loader_seg (RWX) : org = 0x40060000, len = 0x4000 /* 16KB, SRAM Block_18 */
iram_seg (RWX) : org = 0x40064000, len = 0x4000 /* 16KB, SRAM Block_19 */
dram_seg (RW) : org = 0x3FFF8000, len = 0x4000 /* 16KB, SRAM Block_20 */
}
/* Default entry point: */

17
components/bootloader/subproject/main/ld/esp32s2beta/bootloader.rom.ld
View File

@ -1,14 +1,13 @@
/*
* ESP32S2 ROM address table
* Generated for ROM with MD5sum: f054d40c5f6b9207d3827460a6f5748c
* Generated for ROM with MD5sum: 0a2c7ec5109c17884606d23b47045796
*/
PROVIDE ( ets_update_cpu_frequency = 0x4000d954 );
PROVIDE (ets_update_cpu_frequency = 0x4000d8a4);
/* ToDo: Following address may need modification */
PROVIDE ( MD5Final = 0x400056e8 );
PROVIDE ( MD5Init = 0x40005648 );
PROVIDE ( MD5Update = 0x40005668 );
PROVIDE (MD5Final = 0x4000530c);
PROVIDE (MD5Init = 0x4000526c);
PROVIDE (MD5Update = 0x4000528c);
/* bootloader will use following functions from xtensa hal library */
xthal_get_ccount = 0x40015cbc;
xthal_get_ccompare = 0x40015ce8;
xthal_set_ccompare = 0x40015cc4;
xthal_get_ccount = 0x4001aa90;
xthal_get_ccompare = 0x4001aabc;
xthal_set_ccompare = 0x4001aa98;

14
components/bootloader_support/src/bootloader_clock.c
View File

@ -16,15 +16,26 @@
#include "soc/rtc.h"
#include "soc/dport_reg.h"
#include "soc/efuse_periph.h"
#include "soc/rtc_cntl_reg.h"
#ifdef CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/uart.h"
#include "esp32/rom/rtc.h"
#else
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#include "esp32s2beta/rom/uart.h"
#include "esp32s2beta/rom/rtc.h"
#endif
#if CONFIG_IDF_ENV_FPGA
void bootloader_clock_configure(void)
{
uart_tx_wait_idle(0);
REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, 0);
rtc_cpu_freq_t cpu_freq = ets_get_apb_freq();
ets_update_cpu_frequency(cpu_freq / 1000000);
REG_WRITE(RTC_CNTL_STORE5_REG, (cpu_freq >> 12) | ((cpu_freq >> 12) << 16));
}
#else // CONFIG_IDF_ENV_FPGA
void bootloader_clock_configure(void)
{
// ROM bootloader may have put a lot of text into UART0 FIFO.
@ -72,6 +83,7 @@ void bootloader_clock_configure(void)
}
#endif
}
#endif // CONFIG_IDF_ENV_FPGA
#ifdef BOOTLOADER_BUILD

15
components/bootloader_support/src/bootloader_flash.c
View File

@ -92,13 +92,14 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
#else
/* Bootloader version, uses ROM functions only */
#include <soc/dport_reg.h>
#include "soc/dport_reg.h"
#if CONFIG_IDF_TARGET_ESP32
#include <esp32/rom/spi_flash.h>
#include <esp32/rom/cache.h>
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/cache.h"
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#include <esp32s2beta/rom/spi_flash.h>
#include <esp32s2beta/rom/cache.h>
#include "esp32s2beta/rom/spi_flash.h"
#include "esp32s2beta/rom/cache.h"
#include "soc/cache_memory.h"
#endif
static const char *TAG = "bootloader_flash";
@ -161,7 +162,7 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size)
#if CONFIG_IDF_TARGET_ESP32
int e = cache_flash_mmu_set(0, 0, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
int e = Cache_Ibus_MMU_Set(DPORT_MMU_ACCESS_FLASH, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count, 0);
int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count, 0);
#endif
if (e != 0) {
ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e);
@ -255,7 +256,7 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
#if CONFIG_IDF_TARGET_ESP32
int e = cache_flash_mmu_set(0, 0, FLASH_READ_VADDR, map_at, 64, 1);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
int e = Cache_Ibus_MMU_Set(DPORT_MMU_ACCESS_FLASH, FLASH_READ_VADDR, map_at, 64, 1, 0);
int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0);
#endif
if (e != 0) {
ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e);

39
components/bootloader_support/src/bootloader_random.c
View File

@ -11,6 +11,7 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "sdkconfig.h"
#include "bootloader_random.h"
#include "soc/cpu.h"
#include "soc/wdev_reg.h"
@ -20,6 +21,10 @@
#include "soc/dport_reg.h"
#include "soc/i2s_periph.h"
#include "esp_log.h"
#include "soc/io_mux_reg.h"
#if CONFIG_IDF_TARGET_ESP32S2BETA
#include "soc/apb_saradc_reg.h"
#endif
#ifndef BOOTLOADER_BUILD
#include "esp_system.h"
@ -84,9 +89,9 @@ void bootloader_random_enable(void)
Note: I2S requires the PLL to be running, so the call to rtc_set_cpu_freq(CPU_80M)
in early bootloader startup must have been made.
*/
#if CONFIG_IDF_TARGET_ESP32
SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 2, RTC_CNTL_DTEST_RTC_S);
SET_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC);
#if CONFIG_IDF_TARGET_ESP32
SET_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST);
#ifdef BOOTLOADER_BUILD
@ -97,6 +102,12 @@ void bootloader_random_enable(void)
CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP);
CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_START_TOP);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
/* Disable IO1 digital function for random function. */
PIN_INPUT_DISABLE(PERIPHS_IO_MUX_GPIO1_U);
PIN_PULLDWN_DIS(PERIPHS_IO_MUX_GPIO1_U);
PIN_PULLUP_DIS(PERIPHS_IO_MUX_GPIO1_U);
WRITE_PERI_REG(APB_SARADC_SAR1_PATT_TAB1_REG, 0xFFFFFFFF);
SET_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL1_REG, SENS_SAR2_EN_TEST);
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_FORCE_START_TOP);
@ -107,36 +118,42 @@ void bootloader_random_enable(void)
//--[7:4] channel_sel: 10-->en_test
//--[3:2] bit_width : 3-->12bit
//--[1:0] atten : 1-->3dB attenuation
#if CONFIG_IDF_TARGET_ESP32
WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD);
WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD);
WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD);
WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB4_REG, 0xADADADAD);
#if CONFIG_IDF_TARGET_ESP32
SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S);
SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE);
SET_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD);
WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD);
WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD);
WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB4_REG, 0xADADADAD);
SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S);
SET_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE);
#endif
#if CONFIG_IDF_TARGET_ESP32
SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX);
#endif
SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_CLK_DIV, 4, SYSCON_SARADC_SAR_CLK_DIV_S);
SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_RSTB_WAIT, 8, SYSCON_SARADC_RSTB_WAIT_S); /* was 1 */
#if CONFIG_IDF_TARGET_ESP32
SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 10, SYSCON_SARADC_START_WAIT_S);
#endif
SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_WORK_MODE, 0, SYSCON_SARADC_WORK_MODE_S);
SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_SEL);
CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_SAR_SEL);
SET_PERI_REG_BITS(I2S_SAMPLE_RATE_CONF_REG(0), I2S_RX_BCK_DIV_NUM, 20, I2S_RX_BCK_DIV_NUM_S);
SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_TO_I2S);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
SET_PERI_REG_BITS(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_DIV, 4, APB_SARADC_SAR_CLK_DIV_S);
SET_PERI_REG_BITS(APB_SARADC_FSM_REG, APB_SARADC_RSTB_WAIT, 8, APB_SARADC_RSTB_WAIT_S); /* was 1 */
SET_PERI_REG_BITS(APB_SARADC_CTRL_REG, APB_SARADC_WORK_MODE, 0, APB_SARADC_WORK_MODE_S);
SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_SEL);
CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_DATA_SAR_SEL);
SET_PERI_REG_BITS(I2S_SAMPLE_RATE_CONF_REG(0), I2S_RX_BCK_DIV_NUM, 20, I2S_RX_BCK_DIV_NUM_S);
SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_DATA_TO_I2S);
#endif
CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_CAMERA_EN);
SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_LCD_EN);
SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE);
@ -179,7 +196,7 @@ void bootloader_random_disable(void)
SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL1_REG, SENS_SAR2_EN_TEST);
CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S);
CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_SEL | APB_SARADC_DATA_TO_I2S);
SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
#endif
@ -195,7 +212,9 @@ void bootloader_random_disable(void)
periph_module_reset(PERIPH_I2S0_MODULE);
#endif
#if CONFIG_IDF_TARGET_ESP32
/* Disable pull supply voltage to SAR ADC */
CLEAR_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC);
SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 0, RTC_CNTL_DTEST_RTC_S);
#endif
}

36
components/bootloader_support/src/bootloader_utility.c
View File

@ -39,6 +39,8 @@
#include "esp32s2beta/rom/uart.h"
#include "esp32s2beta/rom/gpio.h"
#include "esp32s2beta/rom/secure_boot.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#else
#error "Unsupported IDF_TARGET"
#endif
@ -687,10 +689,15 @@ static void set_cache_and_start_app(
/* Clear the MMU entries that are already set up,
so the new app only has the mappings it creates.
*/
#if CONFIG_IDF_TARGET_ESP32
for (int i = 0; i < DPORT_FLASH_MMU_TABLE_SIZE; i++) {
DPORT_PRO_FLASH_MMU_TABLE[i] = DPORT_FLASH_MMU_TABLE_INVALID_VAL;
}
#elif CONFIG_IDF_TARGET_ESP32S2BETA
for (int i = 0; i < FLASH_MMU_TABLE_SIZE; i++) {
FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL;
}
#endif
uint32_t drom_load_addr_aligned = drom_load_addr & MMU_FLASH_MASK;
uint32_t drom_page_count = bootloader_cache_pages_to_map(drom_size, drom_load_addr);
ESP_LOGV(TAG, "d mmu set paddr=%08x vaddr=%08x size=%d n=%d",
@ -698,8 +705,7 @@ static void set_cache_and_start_app(
#if CONFIG_IDF_TARGET_ESP32
rc = cache_flash_mmu_set(0, 0, drom_load_addr_aligned, drom_addr & MMU_FLASH_MASK, 64, drom_page_count);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
rc = Cache_Ibus_MMU_Set(DPORT_MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000,
64, drom_page_count, 0);
rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count, 0);
#endif
ESP_LOGV(TAG, "rc=%d", rc);
#if CONFIG_IDF_TARGET_ESP32
@ -712,27 +718,17 @@ static void set_cache_and_start_app(
irom_addr & MMU_FLASH_MASK, irom_load_addr_aligned, irom_size, irom_page_count);
#if CONFIG_IDF_TARGET_ESP32
rc = cache_flash_mmu_set(0, 0, irom_load_addr_aligned, irom_addr & MMU_FLASH_MASK, 64, irom_page_count);
ESP_LOGV(TAG, "rc=%d", rc);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
uint32_t iram1_used = 0, irom0_used = 0;
uint32_t iram1_used = 0;
if (irom_load_addr + irom_size > IRAM1_ADDRESS_LOW) {
iram1_used = 1;
}
if (irom_load_addr + irom_size > IROM0_ADDRESS_LOW) {
irom0_used = 1;
if (iram1_used) {
rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, IRAM0_ADDRESS_LOW, 0, 64, 64, 1);
rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, IRAM1_ADDRESS_LOW, 0, 64, 64, 1);
REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_IRAM1);
}
if (iram1_used || irom0_used) {
rc = Cache_Ibus_MMU_Set(DPORT_MMU_ACCESS_FLASH, IRAM0_ADDRESS_LOW, 0, 64, 64, 1);
rc = Cache_Ibus_MMU_Set(DPORT_MMU_ACCESS_FLASH, IRAM1_ADDRESS_LOW, 0, 64, 64, 1);
REG_SET_BIT(DPORT_CACHE_SOURCE_1_REG, DPORT_PRO_CACHE_I_SOURCE_PRO_IRAM1);
REG_CLR_BIT(DPORT_PRO_ICACHE_CTRL1_REG, DPORT_PRO_ICACHE_MASK_IRAM1);
if (irom0_used) {
rc = Cache_Ibus_MMU_Set(DPORT_MMU_ACCESS_FLASH, IROM0_ADDRESS_LOW, 0, 64, 64, 1);
REG_SET_BIT(DPORT_CACHE_SOURCE_1_REG, DPORT_PRO_CACHE_I_SOURCE_PRO_IROM0);
REG_CLR_BIT(DPORT_PRO_ICACHE_CTRL1_REG, DPORT_PRO_ICACHE_MASK_IROM0);
}
}
rc = Cache_Ibus_MMU_Set(DPORT_MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0);
rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0);
#endif
ESP_LOGV(TAG, "rc=%d", rc);
#if CONFIG_IDF_TARGET_ESP32
@ -747,7 +743,7 @@ static void set_cache_and_start_app(
(DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 |
DPORT_APP_CACHE_MASK_DRAM1 );
#elif CONFIG_IDF_TARGET_ESP32S2BETA
DPORT_REG_CLR_BIT( DPORT_PRO_ICACHE_CTRL1_REG, (DPORT_PRO_ICACHE_MASK_IRAM0) | (DPORT_PRO_ICACHE_MASK_IRAM1 & 0) | (DPORT_PRO_ICACHE_MASK_IROM0 & 0) | DPORT_PRO_ICACHE_MASK_DROM0 );
REG_CLR_BIT( EXTMEM_PRO_ICACHE_CTRL1_REG, (EXTMEM_PRO_ICACHE_MASK_IRAM0) | (EXTMEM_PRO_ICACHE_MASK_IRAM1 & 0) | EXTMEM_PRO_ICACHE_MASK_DROM0 );
#endif
#if CONFIG_IDF_TARGET_ESP32
Cache_Read_Enable(0);

5
components/bootloader_support/src/esp32s2beta/bootloader_esp32s2beta.c
View File

@ -37,6 +37,7 @@
#include "soc/assist_debug_reg.h"
#include "soc/cpu.h"
#include "soc/dport_reg.h"
#include "soc/extmem_reg.h"
#include "soc/rtc.h"
#include "soc/spi_periph.h"
@ -97,7 +98,7 @@ static void bootloader_reset_mmu(void)
/* normal ROM boot exits with DROM0 cache unmasked,
but serial bootloader exits with it masked. */
DPORT_REG_CLR_BIT(DPORT_PRO_ICACHE_CTRL1_REG, DPORT_PRO_ICACHE_MASK_DROM0);
REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_DROM0);
}
static void update_flash_config(const esp_image_header_t *bootloader_hdr)
@ -235,7 +236,7 @@ static void bootloader_init_uart_console(void)
#else // CONFIG_ESP_CONSOLE_UART_NONE
const int uart_num = CONFIG_ESP_CONSOLE_UART_NUM;
uartAttach();
uartAttach(NULL);
ets_install_uart_printf();
// Wait for UART FIFO to be empty.

18
components/bootloader_support/src/esp_image_format.c
View File

@ -24,11 +24,11 @@
#include "bootloader_util.h"
#include "bootloader_common.h"
#if CONFIG_IDF_TARGET_ESP32
#include <esp32/rom/rtc.h>
#include <esp32/rom/secure_boot.h>
#include "esp32/rom/rtc.h"
#include "esp32/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#include <esp32s2beta/rom/rtc.h>
#include <esp32s2beta/rom/secure_boot.h>
#include "esp32s2beta/rom/rtc.h"
#include "esp32s2beta/rom/secure_boot.h"
#endif
/* Checking signatures as part of verifying images is necessary:
@ -107,7 +107,7 @@ static esp_err_t image_load(esp_image_load_mode_t mode, const esp_partition_pos_
bool do_verify = (mode == ESP_IMAGE_LOAD) || (mode == ESP_IMAGE_VERIFY) || (mode == ESP_IMAGE_VERIFY_SILENT);
#else
bool do_load = false; // Can't load the image in app mode
bool do_verify = true; // In app mode is avalible only verify mode
bool do_verify = true; // In app mode is available only verify mode
#endif
bool silent = (mode == ESP_IMAGE_VERIFY_SILENT);
esp_err_t err = ESP_OK;
@ -198,13 +198,13 @@ static esp_err_t image_load(esp_image_load_mode_t mode, const esp_partition_pos_
}
/* For secure boot on ESP32, we don't calculate SHA or verify signautre on bootloaders.
For ESP32S2, we do verify signature on botoloaders which includes the SHA calculation.
For ESP32S2, we do verify signature on bootloader which includes the SHA calculation.
(For non-secure boot, we don't verify any SHA-256 hash appended to the bootloader because
esptool.py may have rewritten the header - rely on esptool.py having verified the bootloader at flashing time, instead.)
*/
bool verify_sha;
#if defined(CONFIG_SECURE_BOOT_ENABLED) && defined(CONFIG_IDF_TARGET_ESP32S2BETA)
#if CONFIG_SECURE_BOOT_ENABLED && CONFIG_IDF_TARGET_ESP32S2BETA
verify_sha = true;
#else // ESP32, or ESP32S2 without secure boot enabled
verify_sha = (data->start_addr != ESP_BOOTLOADER_OFFSET);
@ -378,7 +378,7 @@ static esp_err_t process_segment(int index, uint32_t flash_addr, esp_image_segme
#ifdef BOOTLOADER_BUILD
/* Before loading segment, check it doesn't clobber bootloader RAM. */
if (do_load) {
if (do_load && data_len > 0) {
const intptr_t load_end = load_addr + data_len;
if (load_end < (intptr_t) SOC_DRAM_HIGH) {
/* Writing to DRAM */
@ -638,7 +638,7 @@ static esp_err_t verify_secure_boot_signature(bootloader_sha256_handle_t sha_han
bootloader_munmap(simple_hash);
}
#ifdef CONFIG_IDF_TARGET_ESP32S2BETA
#if CONFIG_IDF_TARGET_ESP32S2BETA
// Pad to 4096 byte sector boundary
if (end % FLASH_SECTOR_SIZE != 0) {
uint32_t pad_len = FLASH_SECTOR_SIZE - (end % FLASH_SECTOR_SIZE);

8
components/driver/periph_ctrl.c
View File

@ -11,14 +11,14 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <esp_types.h>
#include "esp_types.h"
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "freertos/xtensa_api.h"
#include "soc/dport_reg.h"
#include "soc/syscon_reg.h"
#include "driver/periph_ctrl.h"
#include "sdkconfig.h"
static portMUX_TYPE periph_spinlock = portMUX_INITIALIZER_UNLOCKED;
@ -116,8 +116,6 @@ static uint32_t get_clk_en_mask(periph_module_t periph)
return DPORT_SPI2_DMA_CLK_EN;
case PERIPH_SPI3_DMA_MODULE:
return DPORT_SPI3_DMA_CLK_EN;
case PERIPH_SPI_SHARED_DMA_MODULE:
return DPORT_SPI_SHARED_DMA_CLK_EN;
#endif
case PERIPH_SDMMC_MODULE:
return DPORT_WIFI_CLK_SDIO_HOST_EN;
@ -220,8 +218,6 @@ static uint32_t get_rst_en_mask(periph_module_t periph, bool enable)
return DPORT_SPI2_DMA_RST;
case PERIPH_SPI3_DMA_MODULE:
return DPORT_SPI3_DMA_RST;
case PERIPH_SPI_SHARED_DMA_MODULE:
return DPORT_SPI_SHARED_DMA_RST;
#endif
case PERIPH_SDMMC_MODULE:
return DPORT_SDIO_HOST_RST;

10
components/driver/spi_common.c
View File

@ -105,7 +105,7 @@ int spicommon_irqdma_source_for_host(spi_host_device_t host)
static inline uint32_t get_dma_periph(int dma_chan)
{
#ifdef CONFIG_IDF_TARGET_ESP32S2BETA
#if CONFIG_IDF_TARGET_ESP32S2BETA
if (dma_chan == 1) {
return PERIPH_SPI2_DMA_MODULE;
} else if (dma_chan==2) {
@ -116,7 +116,7 @@ static inline uint32_t get_dma_periph(int dma_chan)
abort();
return -1;
}
#elif defined(CONFIG_IDF_TARGET_ESP32)
#elif CONFIG_IDF_TARGET_ESP32
return PERIPH_SPI_DMA_MODULE;
#endif
}
@ -357,12 +357,8 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
}
//Select DMA channel.
#ifdef CONFIG_IDF_TARGET_ESP32
#if CONFIG_IDF_TARGET_ESP32
DPORT_SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, 3, dma_chan, (host * 2));
#elif defined(CONFIG_IDF_TARGET_ESP32S2BETA)
if (dma_chan==VSPI_HOST) {
DPORT_SET_PERI_REG_MASK(DPORT_SPI_DMA_CHAN_SEL_REG, DPORT_SPI_SHARED_DMA_SEL_M);
}
#endif
if (flags_o) *flags_o = temp_flag;

14
components/driver/test/include/test/test_common_spi.h
View File

@ -109,6 +109,7 @@
#define PSET_NAME_LEN 30 ///< length of each param set name
//test low frequency, high frequency until freq limit for worst case (both GPIO)
#if APB_CLK_FREQ==80*1000*1000
#define TEST_FREQ_DEFAULT(){ \
1*1000*1000, \
SPI_MASTER_FREQ_8M , \
@ -123,6 +124,19 @@
SPI_MASTER_FREQ_80M, \
0,\
}
#endif
#if APB_CLK_FREQ==40*1000*1000
#define TEST_FREQ_DEFAULT(){ \
1*1000*1000, \
SPI_MASTER_FREQ_8M , \
SPI_MASTER_FREQ_10M, \
SPI_MASTER_FREQ_13M, \
SPI_MASTER_FREQ_20M, \
SPI_MASTER_FREQ_40M, \
0,\
}
#endif
//default bus config for tests
#define SPI_BUS_TEST_DEFAULT_CONFIG() {\

14
components/driver/test/test_spi_param.c
View File

@ -299,11 +299,17 @@ TEST_SPI_LOCAL(TIMING, timing_pgroup)
#define FREQ_LIMIT_MODE SPI_MASTER_FREQ_16M
static int test_freq_mode_local[]={
1*1000*1000,
#if APB_CLK_FREQ==80*1000*1000
SPI_MASTER_FREQ_9M, //maximum freq MISO stable before next latch edge
#endif
SPI_MASTER_FREQ_13M,
#if APB_CLK_FREQ==80*1000*1000
SPI_MASTER_FREQ_16M,
#endif
SPI_MASTER_FREQ_20M,
#if APB_CLK_FREQ==80*1000*1000
SPI_MASTER_FREQ_26M,
#endif
SPI_MASTER_FREQ_40M,
0,
};
@ -345,6 +351,7 @@ static spitest_param_set_t mode_pgroup[] = {
.slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX,
.slave_tv_ns = TV_INT_CONNECT,
},
#if APB_CLK_FREQ==80*1000*1000
{ .pset_name = "Mode 1",
.freq_list = test_freq_mode_local,
.freq_limit = SPI_MASTER_FREQ_26M,
@ -355,6 +362,7 @@ static spitest_param_set_t mode_pgroup[] = {
.slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX,
.slave_tv_ns = TV_INT_CONNECT,
},
#endif
{ .pset_name = "Mode 2",
.freq_list = test_freq_mode_local,
.master_limit = SPI_MASTER_FREQ_13M,
@ -364,6 +372,7 @@ static spitest_param_set_t mode_pgroup[] = {
.slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX,
.slave_tv_ns = TV_INT_CONNECT,
},
#if APB_CLK_FREQ==80*1000*1000
{ .pset_name = "Mode 3",
.freq_list = test_freq_mode_local,
.freq_limit = SPI_MASTER_FREQ_26M,
@ -374,6 +383,7 @@ static spitest_param_set_t mode_pgroup[] = {
.slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX,
.slave_tv_ns = TV_INT_CONNECT,
},
#endif
{ .pset_name = "Mode 0, DMA",
.freq_list = test_freq_mode_local,
.master_limit = SPI_MASTER_FREQ_13M,
@ -385,6 +395,7 @@ static spitest_param_set_t mode_pgroup[] = {
.slave_tv_ns = TV_INT_CONNECT,
.length_aligned = true,
},
#if APB_CLK_FREQ==80*1000*1000
{ .pset_name = "Mode 1, DMA",
.freq_list = test_freq_mode_local,
.freq_limit = SPI_MASTER_FREQ_26M,
@ -397,6 +408,7 @@ static spitest_param_set_t mode_pgroup[] = {
.slave_tv_ns = TV_INT_CONNECT,
.length_aligned = true,
},
#endif
{ .pset_name = "Mode 2, DMA",
.freq_list = test_freq_mode_local,
.master_limit = SPI_MASTER_FREQ_13M,
@ -408,6 +420,7 @@ static spitest_param_set_t mode_pgroup[] = {
.slave_tv_ns = TV_INT_CONNECT,
.length_aligned = true,
},
#if APB_CLK_FREQ==80*1000*1000
{ .pset_name = "Mode 3, DMA",
.freq_list = test_freq_mode_local,
.freq_limit = SPI_MASTER_FREQ_26M,
@ -420,6 +433,7 @@ static spitest_param_set_t mode_pgroup[] = {
.slave_tv_ns = TV_INT_CONNECT,
.length_aligned = true,
},
#endif
/////////////////////////// MISO ////////////////////////////////////
{ .pset_name = "MISO, Mode 0",
.freq_list = test_freq_mode_local,

8
components/efuse/src/esp32s2beta/esp_efuse_utility.c
View File

@ -30,8 +30,8 @@ extern uint32_t virt_blocks[COUNT_EFUSE_BLOCKS][COUNT_EFUSE_REG_PER_BLOCK];
/*Range addresses to read blocks*/
const esp_efuse_range_addr_t range_read_addr_blocks[] = {
{EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT
{EFUSE_RD_MAC_SPI_8M_0_REG, EFUSE_RD_MAC_SPI_8M_5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M
{EFUSE_RD_SYS_DATA0_REG, EFUSE_RD_SYS_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA
{EFUSE_RD_MAC_SPI_SYS_0_REG, EFUSE_RD_MAC_SPI_SYS_5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M
{EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA
{EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA
{EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0
{EFUSE_RD_KEY1_DATA0_REG, EFUSE_RD_KEY1_DATA7_REG}, // range address of EFUSE_BLK5 KEY1
@ -39,7 +39,7 @@ const esp_efuse_range_addr_t range_read_addr_blocks[] = {
{EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3
{EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4
{EFUSE_RD_KEY5_DATA0_REG, EFUSE_RD_KEY5_DATA7_REG}, // range address of EFUSE_BLK9 KEY5
{EFUSE_RD_KEY6_DATA0_REG, EFUSE_RD_KEY6_DATA7_REG} // range address of EFUSE_BLK10 KEY6
{EFUSE_RD_SYS_PART2_DATA0_REG, EFUSE_RD_SYS_PART2_DATA7_REG} // range address of EFUSE_BLK10 KEY6
};
static uint32_t write_mass_blocks[COUNT_EFUSE_BLOCKS][COUNT_EFUSE_REG_PER_BLOCK] = { 0 };
@ -153,7 +153,7 @@ void esp_efuse_utility_burn_efuses(void)
// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values.
// This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme.
// The RS coding scheme does not require data changes for the encoded data. esp32s2beta has special registers for this.
// The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this.
// They will be filled during the burn operation.
esp_err_t esp_efuse_utility_apply_new_coding_scheme()
{

6
components/esp32s2beta/Kconfig
View File

@ -27,10 +27,13 @@ menu "ESP32S2-specific"
choice ESP32S2_DEFAULT_CPU_FREQ_MHZ
prompt "CPU frequency"
default ESP32S2_DEFAULT_CPU_FREQ_160
default ESP32S2_DEFAULT_CPU_FREQ_160 if !IDF_ENV_FPGA
default ESP32S2_DEFAULT_CPU_FREQ_FPGA if IDF_ENV_FPGA
help
CPU frequency to be set on application startup.
config ESP32S2_DEFAULT_CPU_FREQ_FPGA
bool "FPGA"
config ESP32S2_DEFAULT_CPU_FREQ_80
bool "80 MHz"
config ESP32S2_DEFAULT_CPU_FREQ_160
@ -41,6 +44,7 @@ menu "ESP32S2-specific"
config ESP32S2_DEFAULT_CPU_FREQ_MHZ
int
default 40 if IDF_ENV_FPGA
default 80 if ESP32S2_DEFAULT_CPU_FREQ_80
default 160 if ESP32S2_DEFAULT_CPU_FREQ_160
default 240 if ESP32S2_DEFAULT_CPU_FREQ_240

31
components/esp32s2beta/cache_err_int.c
View File

@ -27,6 +27,7 @@
#include "esp_err.h"
#include "esp_intr_alloc.h"
#include "esp_attr.h"
#include "soc/extmem_reg.h"
#include "soc/dport_reg.h"
#include "soc/periph_defs.h"
#include "sdkconfig.h"
@ -52,17 +53,25 @@ void esp_cache_err_int_init(void)
// interrupt is connected to PRO CPU and invalid access happens on the APP
// CPU.
DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_IA_INT_EN_REG,
DPORT_MMU_ENTRY_FAULT_INT_ENA |
DPORT_DCACHE_REJECT_INT_ENA |
DPORT_DCACHE_WRITE_FLASH_INT_ENA |
DPORT_DC_PRELOAD_SIZE_FAULT_INT_ENA |
DPORT_DC_SYNC_SIZE_FAULT_INT_ENA |
DPORT_ICACHE_REJECT_INT_ENA |
DPORT_IC_PRELOAD_SIZE_FAULT_INT_ENA |
DPORT_IC_SYNC_SIZE_FAULT_INT_ENA |
DPORT_CACHE_DBG_INT_CLR |
DPORT_CACHE_DBG_EN);
DPORT_SET_PERI_REG_MASK(EXTMEM_CACHE_DBG_INT_CLR_REG,
EXTMEM_MMU_ENTRY_FAULT_INT_CLR |
EXTMEM_DCACHE_REJECT_INT_CLR |
EXTMEM_DCACHE_WRITE_FLASH_INT_CLR |
EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR |
EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR |
EXTMEM_ICACHE_REJECT_INT_CLR |
EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR |
EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR);
DPORT_SET_PERI_REG_MASK(EXTMEM_CACHE_DBG_INT_ENA_REG,
EXTMEM_MMU_ENTRY_FAULT_INT_ENA |
EXTMEM_DCACHE_REJECT_INT_ENA |
EXTMEM_DCACHE_WRITE_FLASH_INT_ENA |
EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA |
EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA |
EXTMEM_ICACHE_REJECT_INT_ENA |
EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA |
EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA |
EXTMEM_CACHE_DBG_EN);
ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
}

20
components/esp32s2beta/clk.c
View File

@ -48,7 +48,6 @@ static void select_rtc_slow_clk(rtc_slow_freq_t slow_clk);
// g_ticks_us defined in ROMs for PRO CPU
extern uint32_t g_ticks_per_us_pro;
static const char *TAG = "clk";
@ -207,13 +206,13 @@ void esp_perip_clk_init(void)
/* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset.
*/
if ((rst_reas[0] >= TG0WDT_CPU_RESET && rst_reas[0] <= TG0WDT_CPU_RESET && rst_reas[0] != RTCWDT_BROWN_OUT_RESET)
) {
if (rst_reas[0] >= TG0WDT_CPU_RESET &&
rst_reas[0] <= TG0WDT_CPU_RESET &&
rst_reas[0] != RTCWDT_BROWN_OUT_RESET) {
common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERI_CLK_EN_REG);
wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG);
}
else {
} else {
common_perip_clk = DPORT_WDG_CLK_EN |
DPORT_I2S0_CLK_EN |
#if CONFIG_ESP_CONSOLE_UART_NUM != 0
@ -240,11 +239,10 @@ void esp_perip_clk_init(void)
DPORT_SPI3_DMA_CLK_EN |
DPORT_PWM2_CLK_EN |
DPORT_PWM3_CLK_EN;
common_perip_clk1 = DPORT_SPI_SHARED_DMA_CLK_EN;
hwcrypto_perip_clk = DPORT_PERI_EN_AES |
DPORT_PERI_EN_SHA |
DPORT_PERI_EN_RSA |
DPORT_PERI_EN_SECUREBOOT;
common_perip_clk1 = 0;
hwcrypto_perip_clk = DPORT_CRYPTO_AES_CLK_EN |
DPORT_CRYPTO_SHA_CLK_EN |
DPORT_CRYPTO_RSA_CLK_EN;
wifi_bt_sdio_clk = DPORT_WIFI_CLK_WIFI_EN |
DPORT_WIFI_CLK_BT_EN_M |
DPORT_WIFI_CLK_UNUSED_BIT5 |
@ -274,7 +272,7 @@ void esp_perip_clk_init(void)
DPORT_I2S1_CLK_EN |
DPORT_SPI2_DMA_CLK_EN |
DPORT_SPI3_DMA_CLK_EN;
common_perip_clk1 = DPORT_SPI_SHARED_DMA_CLK_EN;
common_perip_clk1 = 0;
/* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
* the current is not reduced when disable I2S clock.

8
components/esp32s2beta/cpu_start.c
View File

@ -93,7 +93,9 @@ extern volatile int port_xSchedulerRunning[2];
static const char *TAG = "cpu_start";
struct object { long placeholder[ 10 ]; };
struct object {
long placeholder[ 10 ];
};
void __register_frame_info (const void *begin, struct object *ob);
extern char __eh_frame[];
@ -259,8 +261,12 @@ void start_cpu0_default(void)
trax_enable(TRAX_ENA_PRO);
trax_start_trace(TRAX_DOWNCOUNT_WORDS);
#endif
#if !CONFIG_IDF_ENV_FPGA // ToDo: remove it once we get a real chip
esp_clk_init();
esp_perip_clk_init();
#else
ets_update_cpu_frequency(CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ);
#endif
intr_matrix_clear();
#ifndef CONFIG_ESP_CONSOLE_UART_NONE

27
components/esp32s2beta/ld/esp32s2beta.ld
View File

@ -1,18 +1,11 @@
/* ESP32S2Beta Linker Script Memory Layout
/* ESP32S2 Linker Script Memory Layout
This file describes the memory layout (memory blocks) as virtual
memory addresses.
This file describes the memory layout (memory blocks) by virtual memory addresses.
esp32.common.ld contains output sections to link compiler output
into these memory blocks.
This linker script is passed through the C preprocessor to include configuration options.
***
This linker script is passed through the C preprocessor to include
configuration options.
Please use preprocessor features sparingly! Restrict
to simple macros with numeric values, and/or #if/#endif blocks.
Please use preprocessor features sparingly!
Restrict to simple macros with numeric values, and/or #if/#endif blocks.
*/
#include "sdkconfig.h"
@ -33,7 +26,7 @@
#define RAM_IRAM_START 0x40020000
#define RAM_DRAM_START 0x3FFB0000
#define DATA_RAM_END 0x3FFF2000 /* start address of bootloader */
#define DATA_RAM_END 0x3FFF0000 /* start address of bootloader */
#define IRAM_ORG (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
+ CONFIG_ESP32S2_DATA_CACHE_SIZE)
@ -55,7 +48,7 @@ MEMORY
/* Even though the segment name is iram, it is actually mapped to flash
*/
iram0_2_seg (RX) : org = 0x40080020, len = 0xb80000-0x20
iram0_2_seg (RX) : org = 0x40080020, len = 0x380000-0x20
/*
(0x20 offset above is a convenience for the app binary image generation.
@ -66,11 +59,7 @@ MEMORY
*/
/* Shared data RAM, excluding memory reserved for bootloader and ROM bss/data/stack.
Enabling Bluetooth & Trace Memory features in menuconfig will decrease
the amount of RAM available.
*/
/* Shared data RAM, excluding memory reserved for bootloader and ROM bss/data/stack. */
dram0_0_seg (RW) : org = DRAM_ORG, len = DRAM_SIZE
/* Flash mapped constant data */

7
components/esp32s2beta/ld/esp32s2beta.peripherals.ld
View File

@ -13,16 +13,17 @@ PROVIDE ( I2C0 = 0x3f413000 );
PROVIDE ( UHCI0 = 0x3f414000 );
PROVIDE ( HOST = 0x3f415000 );
PROVIDE ( RMT = 0x3f416000 );
PROVIDE ( RMTMEM = 0x3f416400 );
PROVIDE ( RMTMEM = 0x3f416800 );
PROVIDE ( PCNT = 0x3f417000 );
PROVIDE ( SLC = 0x3f418000 );
PROVIDE ( LEDC = 0x3f419000 );
PROVIDE ( MCP = 0x3f4c3000 );
PROVIDE ( TIMERG0 = 0x3f41F000 );
PROVIDE ( TIMERG1 = 0x3f420000 );
PROVIDE ( GPSPI2 = 0x3f424000 );
PROVIDE ( GPSPI3 = 0x3f425000 );
PROVIDE ( SYSCON = 0x3f426000 );
PROVIDE ( I2C1 = 0x3f427000 );
PROVIDE ( GPSPI4 = 0x3f437000 );
PROVIDE ( CAN = 0x3f42B000 );
PROVIDE ( APB_SARADC = 0x3f440000 );
PROVIDE ( ToBeCleanedUpBelow = 0x00000000 );

56
components/esp32s2beta/panic.c
View File

@ -25,6 +25,8 @@
#include "soc/uart_reg.h"
#include "soc/io_mux_reg.h"
#include "soc/dport_reg.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/timer_group_struct.h"
#include "soc/timer_group_reg.h"
@ -214,35 +216,34 @@ static inline void printCacheError(void)
{
uint32_t vaddr = 0, size = 0;
uint32_t status[2];
status[0] = REG_READ(DPORT_CACHE_DBG_STATUS0_REG);
status[1] = REG_READ(DPORT_CACHE_DBG_STATUS1_REG);
status[0] = REG_READ(EXTMEM_CACHE_DBG_STATUS0_REG);
status[1] = REG_READ(EXTMEM_CACHE_DBG_STATUS1_REG);
for (int i = 0; i < 32; i++) {
switch (status[0] & BIT(i))
{
case DPORT_IC_SYNC_SIZE_FAULT_ST:
vaddr = REG_READ(DPORT_PRO_ICACHE_MEM_SYNC0_REG);
size = REG_READ(DPORT_PRO_ICACHE_MEM_SYNC1_REG);
switch (status[0] & BIT(i)) {
case EXTMEM_IC_SYNC_SIZE_FAULT_ST:
vaddr = REG_READ(EXTMEM_PRO_ICACHE_MEM_SYNC0_REG);
size = REG_READ(EXTMEM_PRO_ICACHE_MEM_SYNC1_REG);
panicPutStr("Icache sync parameter configuration error, the error address and size is 0x");
panicPutHex(vaddr);
panicPutStr("(0x");
panicPutHex(size);
panicPutStr(")\r\n");
break;
case DPORT_IC_PRELOAD_SIZE_FAULT_ST:
vaddr = REG_READ(DPORT_PRO_ICACHE_PRELOAD_ADDR_REG);
size = REG_READ(DPORT_PRO_ICACHE_PRELOAD_SIZE_REG);
case EXTMEM_IC_PRELOAD_SIZE_FAULT_ST:
vaddr = REG_READ(EXTMEM_PRO_ICACHE_PRELOAD_ADDR_REG);
size = REG_READ(EXTMEM_PRO_ICACHE_PRELOAD_SIZE_REG);
panicPutStr("Icache preload parameter configuration error, the error address and size is 0x");
panicPutHex(vaddr);
panicPutStr("(0x");
panicPutHex(size);
panicPutStr(")\r\n");
break;
case DPORT_ICACHE_REJECT_ST:
vaddr = REG_READ(DPORT_PRO_ICACHE_REJECT_VADDR_REG);
case EXTMEM_ICACHE_REJECT_ST:
vaddr = REG_READ(EXTMEM_PRO_ICACHE_REJECT_VADDR_REG);
panicPutStr("Icache reject error occurred while accessing the address 0x");
panicPutHex(vaddr);
if (REG_READ(DPORT_PRO_CACHE_MMU_ERROR_CONTENT_REG) & DPORT_MMU_INVALID) {
if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) {
panicPutStr(" (invalid mmu entry)");
}
panicPutStr("\r\n");
@ -250,45 +251,44 @@ static inline void printCacheError(void)
default:
break;
}
switch (status[1] & BIT(i))
{
case DPORT_DC_SYNC_SIZE_FAULT_ST:
vaddr = REG_READ(DPORT_PRO_DCACHE_MEM_SYNC0_REG);
size = REG_READ(DPORT_PRO_DCACHE_MEM_SYNC1_REG);
switch (status[1] & BIT(i)) {
case EXTMEM_DC_SYNC_SIZE_FAULT_ST:
vaddr = REG_READ(EXTMEM_PRO_DCACHE_MEM_SYNC0_REG);
size = REG_READ(EXTMEM_PRO_DCACHE_MEM_SYNC1_REG);
panicPutStr("Dcache sync parameter configuration error, the error address and size is 0x");
panicPutHex(vaddr);
panicPutStr("(0x");
panicPutHex(size);
panicPutStr(")\r\n");
break;
case DPORT_DC_PRELOAD_SIZE_FAULT_ST:
vaddr = REG_READ(DPORT_PRO_DCACHE_PRELOAD_ADDR_REG);
size = REG_READ(DPORT_PRO_DCACHE_PRELOAD_SIZE_REG);
case EXTMEM_DC_PRELOAD_SIZE_FAULT_ST:
vaddr = REG_READ(EXTMEM_PRO_DCACHE_PRELOAD_ADDR_REG);
size = REG_READ(EXTMEM_PRO_DCACHE_PRELOAD_SIZE_REG);
panicPutStr("Dcache preload parameter configuration error, the error address and size is 0x");
panicPutHex(vaddr);
panicPutStr("(0x");
panicPutHex(size);
panicPutStr(")\r\n");
break;
case DPORT_DCACHE_WRITE_FLASH_ST:
case EXTMEM_DCACHE_WRITE_FLASH_ST:
panicPutStr("Write back error occurred while dcache tries to write back to flash\r\n");
break;
case DPORT_DCACHE_REJECT_ST:
vaddr = REG_READ(DPORT_PRO_DCACHE_REJECT_VADDR_REG);
case EXTMEM_DCACHE_REJECT_ST:
vaddr = REG_READ(EXTMEM_PRO_DCACHE_REJECT_VADDR_REG);
panicPutStr("Dcache reject error occurred while accessing the address 0x");
panicPutHex(vaddr);
if (REG_READ(DPORT_PRO_CACHE_MMU_ERROR_CONTENT_REG) & DPORT_MMU_INVALID) {
if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) {
panicPutStr(" (invalid mmu entry)");
}
panicPutStr("\r\n");
break;
case DPORT_MMU_ENTRY_FAULT_ST:
vaddr = REG_READ(DPORT_PRO_CACHE_MMU_ERROR_VADDR_REG);
case EXTMEM_MMU_ENTRY_FAULT_ST:
vaddr = REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_REG);
panicPutStr("MMU entry fault error occurred while accessing the address 0x");
panicPutHex(vaddr);
if (REG_READ(DPORT_PRO_CACHE_MMU_ERROR_CONTENT_REG) & DPORT_MMU_INVALID) {
if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) {
panicPutStr(" (invalid mmu entry)");
}
panicPutStr("\r\n");

3
components/esp32s2beta/reset_reason.c
View File

@ -57,9 +57,6 @@ static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_re
case RTCWDT_BROWN_OUT_RESET:
return ESP_RST_BROWNOUT;
case SDIO_RESET:
return ESP_RST_SDIO;
case INTRUSION_RESET: /* unused */
default:
return ESP_RST_UNKNOWN;

6
components/esp32s2beta/sleep_modes.c
View File

@ -30,6 +30,7 @@
#include "soc/rtc.h"
#include "soc/spi_periph.h"
#include "soc/dport_reg.h"
#include "soc/extmem_reg.h"
#include "soc/rtc_wdt.h"
#include "soc/soc_memory_layout.h"
#include "soc/uart_caps.h"
@ -128,8 +129,7 @@ void esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub)
void RTC_IRAM_ATTR esp_default_wake_deep_sleep(void) {
/* Clear MMU for CPU 0 */
_DPORT_REG_SET_BIT(DPORT_PRO_CACHE_IA_INT_EN_REG, DPORT_PRO_CACHE_INT_CLR);
_DPORT_REG_SET_BIT(DPORT_PRO_CACHE_IA_INT_EN_REG, DPORT_PRO_CACHE_DBG_EN);
REG_SET_BIT(EXTMEM_CACHE_DBG_INT_ENA_REG, EXTMEM_CACHE_DBG_EN);
}
void __attribute__((weak, alias("esp_default_wake_deep_sleep"))) esp_wake_deep_sleep(void);
@ -196,7 +196,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
s_config.sleep_duration > 0) {
timer_wakeup_prepare();
}
uint32_t result = rtc_sleep_start(s_config.wakeup_triggers, 0, 0);
uint32_t result = rtc_sleep_start(s_config.wakeup_triggers, 0);
// Restore CPU frequency
rtc_clk_cpu_freq_set(cpu_freq);

9
components/esp32s2beta/spiram.c
View File

@ -34,16 +34,7 @@ we add more types of external RAM memory, this can be made into a more intellige
#include "soc/dport_reg.h"
#include "esp32s2beta/rom/cache.h"
#if CONFIG_FREERTOS_UNICORE
#define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
#else
#warning "spiram.c: TODO: no even/odd mode for ESP32S2 PSRAM?"
#if 0
#define PSRAM_MODE PSRAM_VADDR_MODE_EVENODD
#else
#define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH
#endif
#endif
#if CONFIG_SPIRAM

26
components/esp32s2beta/system_api_esp32s2beta.c
View File

@ -13,12 +13,12 @@
// limitations under the License.
#include <string.h>
#include "sdkconfig.h"
#include "esp_system.h"
#include "esp_private/system_internal.h"
#include "esp_attr.h"
#include "esp_wifi.h"
#include "esp_log.h"
#include "sdkconfig.h"
#include "esp32s2beta/rom/cache.h"
#include "esp32s2beta/rom/uart.h"
#include "soc/dport_reg.h"
@ -56,12 +56,6 @@ void IRAM_ATTR esp_restart_noos(void)
// instruction. This would cause memory pool to be locked by arbiter
// to the stalled CPU, preventing current CPU from accessing this pool.
const uint32_t core_id = xPortGetCoreID();
#if !CONFIG_FREERTOS_UNICORE
const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
esp_cpu_reset(other_core_id);
esp_cpu_stall(other_core_id);
#endif
// Disable TG0/TG1 watchdogs
TIMERG0.wdt_wprotect = TIMG_WDT_WKEY_VALUE;
TIMERG0.wdt_config0.en = 0;
@ -100,30 +94,14 @@ void IRAM_ATTR esp_restart_noos(void)
DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
// Set CPU back to XTAL source, no PLL, same as hard reset
#if !CONFIG_IDF_ENV_FPGA
rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL);
#if !CONFIG_FREERTOS_UNICORE
// Clear entry point for APP CPU
DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0);
#endif
// Reset CPUs
if (core_id == 0) {
// Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
#if !CONFIG_FREERTOS_UNICORE
esp_cpu_reset(1);
#endif
esp_cpu_reset(0);
}
#if !CONFIG_FREERTOS_UNICORE
else {
// Running on APP CPU: need to reset PRO CPU and unstall it,
// then reset APP CPU
esp_cpu_reset(0);
esp_cpu_unstall(0);
esp_cpu_reset(1);
}
#endif
while (true) {
;
}

5
components/esp_adc_cal/CMakeLists.txt
View File

@ -1,5 +1,6 @@
# TODO esp32s2beta: Use require_idf_targets here
if(IDF_TARGET STREQUAL "esp32s2beta")
idf_build_get_property(target IDF_TARGET)
# ToDo: re-enable adc-cal for other target
if(NOT ${target} STREQUAL "esp32")
return()
endif()

1610
components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.ld
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File diff suppressed because it is too large Load Diff

190
components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.libgcc.ld
View File

@ -1,98 +1,92 @@
/* Unlike other ROM functions which are exported using PROVIDE, which declares
weak symbols, these libgcc functions are exported using assignment,
which declares strong symbols. This is done so that ROM functions are always
used instead of the ones provided by libgcc.a.
*/
__absvdi2 = 0x40005eb4;
__absvsi2 = 0x40005ea0;
__adddf3 = 0x40008a3c;
__addsf3 = 0x40008594;
__addvdi3 = 0x4000916c;
__addvsi3 = 0x40009148;
__ashldi3 = 0x4001622c;
__ashrdi3 = 0x40016244;
__bswapdi2 = 0x40007110;
__bswapsi2 = 0x400070e8;
__clrsbdi2 = 0x40007184;
__clrsbsi2 = 0x4000716c;
__clzdi2 = 0x40016464;
__clzsi2 = 0x400161fc;
__cmpdi2 = 0x40005e58;
__ctzdi2 = 0x40016478;
__ctzsi2 = 0x40016204;
__divdc3 = 0x40006c30;
__divdf3 = 0x40008e00;
__divdi3 = 0x40016498;
__divsc3 = 0x40006920;
__divsf3 = 0x400087f8;
__divsi3 = 0x400161cc;
__eqdf2 = 0x40005ce0;
__eqsf2 = 0x400059ac;
__extendsfdf2 = 0x400090e4;
__ffsdi2 = 0x40016440;
__ffssi2 = 0x40016218;
__fixdfdi = 0x40008f74;
__fixdfsi = 0x40008f28;
__fixsfdi = 0x400088f8;
__fixsfsi = 0x400088b8;
__fixunsdfsi = 0x40008fe0;
__fixunssfdi = 0x400089b0;
__fixunssfsi = 0x40008958;
__floatdidf = 0x4001639c;
__floatdisf = 0x400162d4;
__floatsidf = 0x40016358;
__floatsisf = 0x40016284;
__floatundidf = 0x4001638c;
__floatundisf = 0x400162c4;
__floatunsidf = 0x4001634c;
__floatunsisf = 0x40016278;
__gcc_bcmp = 0x400071bc;
__gedf2 = 0x40005da0;
__gesf2 = 0x40005a44;
__gtdf2 = 0x40005d14;
__gtsf2 = 0x400059d8;
__ledf2 = 0x40005d3c;
__lesf2 = 0x400059f8;
__lshrdi3 = 0x40016260;
__ltdf2 = 0x40005dc8;
__ltsf2 = 0x40005a64;
__moddi3 = 0x40016760;
__modsi3 = 0x400161d4;
__muldc3 = 0x400062e8;
__muldf3 = 0x40005bc4;
__muldi3 = 0x40016410;
__mulsc3 = 0x40005f80;
__mulsf3 = 0x40005900;
__mulsi3 = 0x400161c4;
__mulvdi3 = 0x4000922c;
__mulvsi3 = 0x40009214;
__nedf2 = 0x40005ce0;
__negdf2 = 0x40005ad8;
__negdi2 = 0x40016428;
__negsf2 = 0x4000856c;
__negvdi2 = 0x40009348;
__negvsi2 = 0x40009328;
__nesf2 = 0x400059ac;
__nsau_data = 0x3ffaba70;
__paritysi2 = 0x40009414;
__popcountdi2 = 0x400093bc;
__popcountsi2 = 0x40009384;
__popcount_tab = 0x3ffaba70;
__powidf2 = 0x40005f1c;
__powisf2 = 0x40005ed4;
__subdf3 = 0x40008b90;
__subsf3 = 0x4000867c;
__subvdi3 = 0x400091d0;
__subvsi3 = 0x400091ac;
__truncdfsf2 = 0x40009040;
__ucmpdi2 = 0x40005e78;
__udivdi3 = 0x40016a08;
__udivmoddi4 = 0x400071fc;
__udivsi3 = 0x400161dc;
__udiv_w_sdiv = 0x400071f4;
__umoddi3 = 0x40016c8c;
__umodsi3 = 0x400161e4;
__umulsidi3 = 0x400161ec;
__unorddf2 = 0x40005e2c;
__unordsf2 = 0x40005ab0;
__absvdi2 = 0x40005ad8;
__absvsi2 = 0x40005ac4;
__adddf3 = 0x40008660;
__addsf3 = 0x400081b8;
__addvdi3 = 0x40008d90;
__addvsi3 = 0x40008d6c;
__ashldi3 = 0x4001b000;
__ashrdi3 = 0x4001b018;
__bswapdi2 = 0x40006d34;
__bswapsi2 = 0x40006d0c;
__clrsbdi2 = 0x40006da8;
__clrsbsi2 = 0x40006d90;
__clzdi2 = 0x4001b238;
__clzsi2 = 0x4001afd0;
__cmpdi2 = 0x40005a7c;
__ctzdi2 = 0x4001b24c;
__ctzsi2 = 0x4001afd8;
__divdc3 = 0x40006854;
__divdf3 = 0x40008a24;
__divdi3 = 0x4001b26c;
__divsc3 = 0x40006544;
__divsf3 = 0x4000841c;
__divsi3 = 0x4001afa0;
__eqdf2 = 0x40005904;
__eqsf2 = 0x400055d0;
__extendsfdf2 = 0x40008d08;
__ffsdi2 = 0x4001b214;
__ffssi2 = 0x4001afec;
__fixdfdi = 0x40008b98;
__fixdfsi = 0x40008b4c;
__fixsfdi = 0x4000851c;
__fixsfsi = 0x400084dc;
__fixunsdfsi = 0x40008c04;
__fixunssfdi = 0x400085d4;
__fixunssfsi = 0x4000857c;
__floatdidf = 0x4001b170;
__floatdisf = 0x4001b0a8;
__floatsidf = 0x4001b12c;
__floatsisf = 0x4001b058;
__floatundidf = 0x4001b160;
__floatundisf = 0x4001b098;
__floatunsidf = 0x4001b120;
__floatunsisf = 0x4001b04c;
__gcc_bcmp = 0x40006de0;
__gedf2 = 0x400059c4;
__gesf2 = 0x40005668;
__gtdf2 = 0x40005938;
__gtsf2 = 0x400055fc;
__ledf2 = 0x40005960;
__lesf2 = 0x4000561c;
__lshrdi3 = 0x4001b034;
__ltdf2 = 0x400059ec;
__ltsf2 = 0x40005688;
__moddi3 = 0x4001b534;
__modsi3 = 0x4001afa8;
__muldc3 = 0x40005f0c;
__muldf3 = 0x400057e8;
__muldi3 = 0x4001b1e4;
__mulsc3 = 0x40005ba4;
__mulsf3 = 0x40005524;
__mulsi3 = 0x4001af98;
__mulvdi3 = 0x40008e50;
__mulvsi3 = 0x40008e38;
__nedf2 = 0x40005904;
__negdf2 = 0x400056fc;
__negdi2 = 0x4001b1fc;
__negsf2 = 0x40008190;
__negvdi2 = 0x40008f6c;
__negvsi2 = 0x40008f4c;
__nesf2 = 0x400055d0;
__nsau_data = 0x3ffac870;
__paritysi2 = 0x40009038;
__popcountdi2 = 0x40008fe0;
__popcountsi2 = 0x40008fa8;
__popcount_tab = 0x3ffac870;
__powidf2 = 0x40005b40;
__powisf2 = 0x40005af8;
__subdf3 = 0x400087b4;
__subsf3 = 0x400082a0;
__subvdi3 = 0x40008df4;
__subvsi3 = 0x40008dd0;
__truncdfsf2 = 0x40008c64;
__ucmpdi2 = 0x40005a9c;
__udivdi3 = 0x4001b7dc;
__udivmoddi4 = 0x40006e20;
__udivsi3 = 0x4001afb0;
__udiv_w_sdiv = 0x40006e18;
__umoddi3 = 0x4001ba60;
__umodsi3 = 0x4001afb8;
__umulsidi3 = 0x4001afc0;
__unorddf2 = 0x40005a50;
__unordsf2 = 0x400056d4;

28
components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.newlib-data.ld
View File

@ -1,19 +1,9 @@
/* These are the .bss/.data symbols used by newlib functions present in ESP32S2beta ROM.
See also esp32s2beta.rom.newlib-funcs.ld for the list of general newlib functions,
and esp32s2beta.rom.newlib-stdio.ld for stdio related newlib functions.
Unlike other ROM functions and data which are exported using PROVIDE, which declares
weak symbols, newlib related functions are exported using assignment,
which declares strong symbols. This is done so that ROM functions are always
used instead of the ones provided by libc.a.
*/
_ctype_ = 0x3ffab96c;
__default_global_locale = 0x3ffab800;
_global_impure_ptr = 0x3fffc04c;
__global_locale_ptr = 0x3fffc030;
__locale_ctype_ptr = 0x40002008;
__locale_ctype_ptr_l = 0x40002000;
__locale_mb_cur_max = 0x40001fe8;
__packed = 0x3fffc530;
_PathLocale = 0x3fffc040;
_ctype_ = 0x3ffac76c;
__default_global_locale = 0x3ffac600;
_global_impure_ptr = 0x3ffffd8c;
__global_locale_ptr = 0x3ffffd7c;
__locale_ctype_ptr = 0x40001c2c;
__locale_ctype_ptr_l = 0x40001c24;
__locale_mb_cur_max = 0x40001c0c;
__packed = 0x3ffffcec;
_PathLocale = 0x3ffffd80;

187
components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.newlib-funcs.ld
View File

@ -1,96 +1,93 @@
/* These are the newlib functions present in ESP32S2beta ROM.
See also esp32s2beta.rom.newlib-data.ld for the list of .data/.bss symbols
used by these functions, and esp32s2beta.rom.newlib-stdio.ld for stdio related
functions.
Unlike other ROM functions which are exported using PROVIDE, which declares
weak symbols, newlib related functions are exported using assignment,
which declares strong symbols. This is done so that ROM functions are always
used instead of the ones provided by libc.a.
abs = 0x40000618;
__ascii_mbtowc = 0x40007a04;
__ascii_wctomb = 0x400018d0;
__assert = 0x4001a430;
__assert_func = 0x4001a408;
/*
atoi = ;
_atoi_r = ;
atol = ;
_atol_r = ;
*/
abs = 0x4000073c;
__ascii_mbtowc = 0x40007de0;
__ascii_wctomb = 0x40001cac;
__assert = 0x4001565c;
__assert_func = 0x40015634;
atoi = 0x40000adc;
_atoi_r = 0x40000aec;
atol = 0x40000b04;
_atol_r = 0x40000b14;
bzero = 0x40007ca4;
_cvt = 0x4000c6d8;
div = 0x40000744;
isalnum = 0x40007cb4;
isalpha = 0x40007cc4;
isascii = 0x40015d18;
isblank = 0x40007cd4;
iscntrl = 0x40007cf4;
isdigit = 0x40007d0c;
isgraph = 0x40007d44;
islower = 0x40007d24;
isprint = 0x40007d5c;
ispunct = 0x40007d70;
isspace = 0x40007d88;
isupper = 0x40007da0;
itoa = 0x40000acc;
__itoa = 0x40000a90;
labs = 0x4000076c;
ldiv = 0x40000774;
longjmp = 0x400006c8;
_mbtowc_r = 0x40007dbc;
memccpy = 0x40015d2c;
memchr = 0x40015d50;
memcmp = 0x40015d6c;
memcpy = 0x40015dd4;
memmove = 0x40015edc;
memrchr = 0x40015f18;
memset = 0x40015f68;
pthread_setcancelstate = 0x400151d4;
qsort = 0x40000818;
rand = 0x40007e54;
rand_r = 0x40007ed0;
setjmp = 0x40000664;
srand = 0x40007e00;
strcasecmp = 0x40007f14;
strcasestr = 0x40007f58;
strcat = 0x40015fbc;
strchr = 0x40015fdc;
strcmp = 0x40007fc0;
strcoll = 0x400080c4;
strcpy = 0x400080d8;
strcspn = 0x40015ff8;
strdup = 0x40008160;
_strdup_r = 0x40008174;
strlcat = 0x40008194;
strlcpy = 0x40016024;
strlen = 0x400081e4;
strlwr = 0x40008244;
strncasecmp = 0x40008270;
strncat = 0x40016060;
strncmp = 0x40016090;
strncpy = 0x400082fc;
strndup = 0x400083c4;
_strndup_r = 0x400083d8;
strnlen = 0x400160c8;
strrchr = 0x4000841c;
strsep = 0x40008448;
strspn = 0x400160e8;
strstr = 0x40016114;
__strtok_r = 0x40016144;
strtok_r = 0x400161a8;
strtol = 0x40000c70;
strtol_l = 0x40000c58;
_strtol_r = 0x40000c34;
strtoul = 0x40000dcc;
strtoul_l = 0x40000db4;
_strtoul_r = 0x40000d90;
strupr = 0x40008460;
toascii = 0x400161bc;
tolower = 0x40008534;
toupper = 0x40008550;
utoa = 0x40000654;
__utoa = 0x400005f0;
wcrtomb = 0x400016d0;
_wcrtomb_r = 0x4000167c;
_wctomb_r = 0x40001c88;
bzero = 0x400078c8;
_cvt = 0x4000f9b8;
div = 0x40000620;
isalnum = 0x400078d8;
isalpha = 0x400078e8;
isascii = 0x4001aaec;
isblank = 0x400078f8;
iscntrl = 0x40007918;
isdigit = 0x40007930;
isgraph = 0x40007968;
islower = 0x40007948;
isprint = 0x40007980;
ispunct = 0x40007994;
isspace = 0x400079ac;
isupper = 0x400079c4;
/*
itoa = ;
__itoa = ;
*/
labs = 0x40000648;
ldiv = 0x40000650;
longjmp = 0x400005a4;
_mbtowc_r = 0x400079e0;
memccpy = 0x4001ab00;
memchr = 0x4001ab24;
memcmp = 0x4001ab40;
memcpy = 0x4001aba8;
memmove = 0x4001acb0;
memrchr = 0x4001acec;
memset = 0x4001ad3c;
pthread_setcancelstate = 0x40019fa8;
qsort = 0x400006f4;
rand = 0x40007a78;
rand_r = 0x40007af4;
setjmp = 0x40000540;
srand = 0x40007a24;
strcasecmp = 0x40007b38;
strcasestr = 0x40007b7c;
strcat = 0x4001ad90;
strchr = 0x4001adb0;
strcmp = 0x40007be4;
strcoll = 0x40007ce8;
strcpy = 0x40007cfc;
strcspn = 0x4001adcc;
strdup = 0x40007d84;
_strdup_r = 0x40007d98;
strlcat = 0x40007db8;
strlcpy = 0x4001adf8;
strlen = 0x40007e08;
strlwr = 0x40007e68;
strncasecmp = 0x40007e94;
strncat = 0x4001ae34;
strncmp = 0x4001ae64;
strncpy = 0x40007f20;
strndup = 0x40007fe8;
_strndup_r = 0x40007ffc;
strnlen = 0x4001ae9c;
strrchr = 0x40008040;
strsep = 0x4000806c;
strspn = 0x4001aebc;
strstr = 0x4001aee8;
__strtok_r = 0x4001af18;
strtok_r = 0x4001af7c;
/*
strtol = ;
strtol_l = ;
_strtol_r = ;
strtoul = ;
strtoul_l = ;
_strtoul_r = ;
*/
strupr = 0x40008084;
toascii = 0x4001af90;
tolower = 0x40008158;
toupper = 0x40008174;
/*
utoa = ;
__utoa = ;
*/
wcrtomb = 0x400012f4;
_wcrtomb_r = 0x400012a0;
_wctomb_r = 0x400018ac;

0
components/esp_rom/esp_rom.c
View File

278
components/esp_rom/include/esp32s2beta/rom/cache.h
View File

@ -15,7 +15,6 @@
#ifndef _ROM_CACHE_H_
#define _ROM_CACHE_H_
#include "esp_bit_defs.h"
#ifdef __cplusplus
extern "C" {
@ -32,18 +31,23 @@ extern "C" {
#define MIN_CACHE_SIZE 8192
#define MAX_CACHE_SIZE 16384
#define MIN_CACHE_WAYS 4
#define MAX_CACHE_WAYS 8
#define MAX_CACHE_WAYS 4
#define MIN_CACHE_LINE_SIZE 16
#define MAX_CACHE_LINE_SIZE 64
//normally should be (MAX_CACHE_SIZE / MIN_CACHE_WAYS / MIN_CACHE_LINE_SIZE), however, the items not all in one tag memory block.
#define MAX_TAG_BLOCK_ITEMS (MAX_CACHE_SIZE / MAX_CACHE_WAYS / MIN_CACHE_LINE_SIZE)
#define MAX_TAG_BLOCK_ITEMS (MAX_CACHE_SIZE / 8 / MIN_CACHE_LINE_SIZE)
#define TAG_SIZE 4
#define MAX_TAG_BLOCK_SIZE (MAX_TAG_BLOCK_ITEMS * TAG_SIZE)
#define INVALID_PHY_PAGE 0xffff
#define ESP_CACHE_TEMP_ADDR DROM0_ADDRESS_LOW
#define CACHE_MAX_OPERATION_SIZE BUS_ADDR_SIZE
typedef enum {
CACHE_DCACHE = 0,
CACHE_ICACHE = 1,
} cache_t;
typedef enum {
CACHE_MEMORY_INVALID = 0,
CACHE_MEMORY_ICACHE_LOW = BIT(0),
@ -52,27 +56,22 @@ typedef enum {
CACHE_MEMORY_DCACHE_HIGH = BIT(3),
} cache_layout_t;
#define CACHE_SIZE_8KB CACHE_SIZE_HALF
#define CACHE_SIZE_16KB CACHE_SIZE_FULL
typedef enum {
CACHE_SIZE_8KB = 0,
CACHE_SIZE_16KB = 1,
CACHE_SIZE_HALF = 0, /*!< 8KB for icache and dcache */
CACHE_SIZE_FULL = 1, /*!< 16KB for icache and dcache */
} cache_size_t;
typedef enum {
CACHE_4WAYS_ASSOC = 0,
CACHE_8WAYS_ASSOC = 1,
CACHE_4WAYS_ASSOC = 0, /*!< 4 way associated cache */
} cache_ways_t;
typedef enum {
CACHE_LINE_SIZE_16B = 0,
CACHE_LINE_SIZE_32B = 1,
CACHE_LINE_SIZE_64B = 2,
CACHE_LINE_SIZE_16B = 0, /*!< 16 Byte cache line size */
CACHE_LINE_SIZE_32B = 1, /*!< 32 Byte cache line size */
} cache_line_size_t;
typedef enum {
CACHE_AUTOLOAD_NORMAL_MODE = 0, /*!< normal mode will autoload anytime if enabled */
CACHE_AUTOLOAD_REGION_MODE = 1, /*!< region mode only autoload if access the memory in regions */
} cache_autoload_mode_t;
typedef enum {
CACHE_AUTOLOAD_POSITIVE = 0, /*!< cache autoload step is positive */
CACHE_AUTOLOAD_NEGATIVE = 1, /*!< cache autoload step is negative */
@ -87,10 +86,10 @@ typedef enum {
} cache_autoload_trigger_t;
struct cache_mode {
uint32_t cache_size;
uint16_t cache_line_size;
uint8_t cache_ways;
uint8_t icache;
uint32_t cache_size; /*!< cache size in byte */
uint16_t cache_line_size; /*!< cache line size in byte */
uint8_t cache_ways; /*!< cache ways, always 4 */
uint8_t icache; /*!< the cache index, 0 for dcache, 1 for icache */
};
struct tag_item {
@ -105,11 +104,10 @@ struct tag_item {
};
struct autoload_config {
uint8_t mode; /*!< autoload mode */
uint8_t order; /*!< autoload step is positive or negative */
uint8_t step; /*!< autoload step */
uint8_t trigger; /*!< autoload trigger */
uint32_t autoload_size; /*!< autoload size */
uint8_t ena0; /*!< autoload region0 enable */
uint8_t ena1; /*!< autoload region1 enable */
uint32_t addr0; /*!< autoload region0 start address */
uint32_t size0; /*!< autoload region0 size */
uint32_t addr1; /*!< autoload region1 start address */
@ -118,6 +116,7 @@ struct autoload_config {
struct tag_group_info {
struct cache_mode mode; /*!< cache and cache mode */
uint32_t filter_addr; /*!< the address that used to generate the struct */
uint32_t vaddr_offset; /*!< virtual address offset of the cache ways */
uint32_t tag_addr[MAX_CACHE_WAYS]; /*!< tag memory address, only [0~mode.ways-1] is valid to use */
uint32_t cache_memory_offset[MAX_CACHE_WAYS]; /*!< cache memory address, only [0~mode.ways-1] is valid to use */
@ -129,9 +128,10 @@ struct lock_config {
uint16_t group; /*!< manual lock group, 0 or 1*/
};
#define MMU_SET_ADDR_ALIGNED_ERROR 1
#define ESP_ROM_ERR_INVALID_ARG 1
#define MMU_SET_ADDR_ALIGNED_ERROR 2
#define MMU_SET_PASE_SIZE_ERROR 3
#define MMU_SET_VADDR_OUT_RANGE 5
#define MMU_SET_VADDR_OUT_RANGE 4
/**
* @brief Initialise cache mmu, mark all entries as invalid.
@ -164,9 +164,9 @@ void Cache_MMU_Init(void);
*
* @return uint32_t: error status
* 0 : mmu set success
* 1 : vaddr or paddr is not aligned
* 2 : vaddr or paddr is not aligned
* 3 : psize error
* 5 : vaddr is out of range
* 4 : vaddr is out of range
*/
int Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed);
@ -191,32 +191,12 @@ int Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32
*
* @return uint32_t: error status
* 0 : mmu set success
* 1 : vaddr or paddr is not aligned
* 2 : vaddr or paddr is not aligned
* 3 : psize error
* 5 : vaddr is out of range
* 4 : vaddr is out of range
*/
int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed);
/**
* @brief Copy DRom0 ICache MMU to DCache MMU.
* Please do not call this function in your SDK application.
*
* @param None
*
* @return None
*/
void MMU_Drom0_I2D_Copy(void);
/**
* @brief Unmap DRom0 ICache MMU.
* Please do not call this function in your SDK application.
*
* @param None
*
* @return None
*/
void MMU_Drom_ICache_Unmap(void);
/**
* @brief Count the pages in the bus room address which map to Flash.
* Please do not call this function in your SDK application.
@ -266,7 +246,7 @@ void Cache_Allocate_SRAM(cache_layout_t sram0_layout, cache_layout_t sram1_layou
* @brief Get cache mode of ICache or DCache.
* Please do not call this function in your SDK application.
*
* @param struct cache_mode * mode : the pointer of cache mode struct
* @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field
*
* return none
*/
@ -276,13 +256,11 @@ void Cache_Get_Mode(struct cache_mode * mode);
* @brief set ICache modes: cache size, associate ways and cache line size.
* Please do not call this function in your SDK application.
*
* @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_8KB and CACHE_SIZE_16KB
* @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_HALF and CACHE_SIZE_FULL
*
* @param cache_ways_t ways : the associate ways of cache, cane be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC
* @param cache_ways_t ways : the associate ways of cache, can only be CACHE_4WAYS_ASSOC
*
* @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B and CACHE_LINE_SIZE_64B
*
* @param cache_layout_t sram3_layout : the usage of forth 8KB internal memory block
* @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B
*
* return none
*/
@ -292,13 +270,11 @@ void Cache_Set_ICache_Mode(cache_size_t cache_size, cache_ways_t ways, cache_lin
* @brief set DCache modes: cache size, associate ways and cache line size.
* Please do not call this function in your SDK application.
*
* @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_8KB and CACHE_SIZE_16KB
* @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_HALF and CACHE_SIZE_FULL
*
* @param cache_ways_t ways : the associate ways of cache, cane be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC
* @param cache_ways_t ways : the associate ways of cache, can only be CACHE_4WAYS_ASSOC
*
* @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B and CACHE_LINE_SIZE_64B
*
* @param cache_layout_t sram3_layout : the usage of forth 8KB internal memory block
* @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B
*
* return none
*/
@ -327,92 +303,100 @@ uint32_t Cache_Address_Through_DCache(uint32_t addr);
/**
* @brief Invalidate the cache items for ICache.
* Operation will be done CACHE_LINE_SIZE aligned.
* If the addr is not in our addr room, we will Flush all Cache.
* If the region is not in ICache addr room, nothing will be done.
* Please do not call this function in your SDK application.
*
* @param uint32_t addr: start address to invalidate
*
* @param uint32_t size: size to invalidate, should <= 4MB
* @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(4MB)
*
* @return None
*/
void Cache_Invalidate_ICache_Items(uint32_t addr, uint32_t size);
void Cache_Invalidate_ICache_Items(uint32_t addr, uint32_t items);
/**
* @brief Invalidate the cache items for DCache.
* Operation will be done CACHE_LINE_SIZE aligned.
* If the addr is not in our addr room, we will Flush all Cache.
* If the region is not in DCache addr room, nothing will be done.
* Please do not call this function in your SDK application.
*
* @param uint32_t addr: start address to invalidate
*
* @param uint32_t size: size to invalidate, should <= 4MB
* @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(4MB)
*
* @return None
*/
void Cache_Invalidate_DCache_Items(uint32_t addr, uint32_t size);
void Cache_Invalidate_DCache_Items(uint32_t addr, uint32_t items);
/**
* @brief Clean the dirty bit of cache Items of DCache.
* Operation will be done CACHE_LINE_SIZE aligned.
* If the region is not in DCache addr room, nothing will be done.
* Please do not call this function in your SDK application.
*
* @param uint32_t addr: start address to Clean
*
* @param uint32_t size: size to Clean, should <= 4MB
* @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(4MB)
*
* @return None
*/
void Cache_Clean_Items(uint32_t addr, uint32_t size);
void Cache_Clean_Items(uint32_t addr, uint32_t items);
/**
* @brief Write back the cache items of DCache.
* Operation will be done CACHE_LINE_SIZE aligned.
* If the region is not in DCache addr room, nothing will be done.
* Please do not call this function in your SDK application.
*
* @param uint32_t addr: start address to write back
*
* @param uint32_t size: size to write back, should <= 4MB
* @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(4MB)
*
* @return None
*/
void Cache_WriteBack_Items(uint32_t addr, uint32_t size);
void Cache_WriteBack_Items(uint32_t addr, uint32_t items);
/**
* @brief Invalidate the Cache items in the region from ICache or DCache.
* If the region is not in Cache addr room, nothing will be done.
* Please do not call this function in your SDK application.
*
* @param uint32_t addr : invalidated region start address.
*
* @param uint32_t size : invalidated region size.
*
* @return None
* @return 0 for success
* 1 for invalid argument
*/
void Cache_Invalidate_Addr(uint32_t addr, uint32_t size);
int Cache_Invalidate_Addr(uint32_t addr, uint32_t size);
/**
* @brief Clean the dirty bit of Cache items in the region from DCache.
* If the region is not in DCache addr room, nothing will be done.
* Please do not call this function in your SDK application.
*
* @param uint32_t addr : cleaned region start address.
*
* @param uint32_t size : cleaned region size.
*
* @return None
* @return 0 for success
* 1 for invalid argument
*/
void Cache_Clean_Addr(uint32_t addr, uint32_t size);
int Cache_Clean_Addr(uint32_t addr, uint32_t size);
/**
* @brief Writeback the Cache items(also clean the dirty bit) in the region from DCache.
* If the region is not in DCache addr room, nothing will be done.
* Please do not call this function in your SDK application.
*
* @param uint32_t addr : writeback region start address.
*
* @param uint32_t size : writeback region size.
*
* @return None
* @return 0 for success
* 1 for invalid argument
*/
void Cache_WriteBack_Addr(uint32_t addr, uint32_t size);
int Cache_WriteBack_Addr(uint32_t addr, uint32_t size);
/**
@ -466,7 +450,7 @@ void Cache_WriteBack_All(void);
void Cache_Mask_All(void);
/**
* @brief UnMask DRom0 bus through ICache or DCache.
* @brief UnMask DRom0 bus through ICache.
* Please do not call this function in your SDK application.
*
* @param None
@ -644,17 +628,18 @@ void Cache_Enable_DCache_Autoload(void);
void Cache_Disable_DCache_Autoload(void);
/**
* @brief Config a group of lock parameters of ICache.
* @brief Config a group of prelock parameters of ICache.
* Please do not call this function in your SDK application.
*
* @param struct lock_config * config : a group of lock parameters.
*
* @return None
*/
void Cache_Enable_ICache_Lock(const struct lock_config *config);
void Cache_Enable_ICache_PreLock(const struct lock_config *config);
/**
* @brief Disable a group of lock parameters for ICache.
* @brief Disable a group of prelock parameters for ICache.
* However, the locked data will not be released.
* Please do not call this function in your SDK application.
*
@ -662,32 +647,48 @@ void Cache_Enable_ICache_Lock(const struct lock_config *config);
*
* @return None
*/
void Cache_Disable_ICache_Lock(uint16_t group);
void Cache_Disable_ICache_PreLock(uint16_t group);
/**
* @brief Unlock the cache items in tag memory for ICache.
* @brief Lock the cache items for ICache.
* Operation will be done CACHE_LINE_SIZE aligned.
* If the region is not in ICache addr room, nothing will be done.
* Please do not call this function in your SDK application.
*
* @param uint32_t addr : start address of unlock region.
* @param uint32_t addr: start address to lock
*
* @param uint32_t size : size of unlock region.
* @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(4MB)
*
* @return None
*/
void Cache_Unlock_ICache(uint32_t addr, uint32_t size);
void Cache_Lock_ICache_Items(uint32_t addr, uint32_t items);
/**
* @brief Config a group of lock parameters of DCache.
* @brief Unlock the cache items for ICache.
* Operation will be done CACHE_LINE_SIZE aligned.
* If the region is not in ICache addr room, nothing will be done.
* Please do not call this function in your SDK application.
*
* @param uint32_t addr: start address to unlock
*
* @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(4MB)
*
* @return None
*/
void Cache_Unlock_ICache_Items(uint32_t addr, uint32_t items);
/**
* @brief Config a group of prelock parameters of DCache.
* Please do not call this function in your SDK application.
*
* @param struct lock_config * config : a group of lock parameters.
*
* @return None
*/
void Cache_Enable_DCache_Lock(const struct lock_config *config);
void Cache_Enable_DCache_PreLock(const struct lock_config *config);
/**
* @brief Disable a group of lock parameters for DCache.
* @brief Disable a group of prelock parameters for DCache.
* However, the locked data will not be released.
* Please do not call this function in your SDK application.
*
@ -695,19 +696,61 @@ void Cache_Enable_DCache_Lock(const struct lock_config *config);
*
* @return None
*/
void Cache_Disable_DCache_Lock(uint16_t group);
void Cache_Disable_DCache_PreLock(uint16_t group);
/**
* @brief Unlock the cache items in tag memory for DCache.
* @brief Lock the cache items for DCache.
* Operation will be done CACHE_LINE_SIZE aligned.
* If the region is not in DCache addr room, nothing will be done.
* Please do not call this function in your SDK application.
*
* @param uint32_t addr: start address to lock
*
* @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(4MB)
*
* @return None
*/
void Cache_Lock_DCache_Items(uint32_t addr, uint32_t items);
/**
* @brief Unlock the cache items for DCache.
* Operation will be done CACHE_LINE_SIZE aligned.
* If the region is not in DCache addr room, nothing will be done.
* Please do not call this function in your SDK application.
*
* @param uint32_t addr: start address to unlock
*
* @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(4MB)
*
* @return None
*/
void Cache_Unlock_DCache_Items(uint32_t addr, uint32_t items);
/**
* @brief Lock the cache items in tag memory for ICache or DCache.
* Please do not call this function in your SDK application.
*
* @param uint32_t addr : start address of lock region.
*
* @param uint32_t size : size of lock region.
*
* @return 0 for success
* 1 for invalid argument
*/
int Cache_Lock_Addr(uint32_t addr, uint32_t size);
/**
* @brief Unlock the cache items in tag memory for ICache or DCache.
* Please do not call this function in your SDK application.
*
* @param uint32_t addr : start address of unlock region.
*
* @param uint32_t size : size of unlock region.
*
* @return None
* @return 0 for success
* 1 for invalid argument
*/
void Cache_Unlock_DCache(uint32_t addr, uint32_t size);
int Cache_Unlock_Addr(uint32_t addr, uint32_t size);
/**
* @brief Disable ICache access for the cpu.
@ -791,48 +834,12 @@ uint32_t Cache_Suspend_DCache(void);
*/
void Cache_Resume_DCache(uint32_t autoload);
/**
* @brief Make Drom0 bus access from ICache.
*
* @param None
*
* @return None
*/
void Cache_Drom0_Source_ICache(void);
/**
* @brief Make Drom0 bus access from DCache.
*
* @param None
*
* @return None
*/
void Cache_Drom0_Source_DCache(void);
/**
* @brief Return if Drom0 bus access from ICache.
*
* @param None
*
* @return uint32_t: 0 for no, other for yes
*/
uint32_t Cache_Drom0_Using_ICache(void);
/**
* @brief Return if Drom0 bus access from DCache.
*
* @param None
*
* @return uint32_t: 0 for no, other for yes
*/
uint32_t Cache_Drom0_Using_DCache(void);
/**
* @brief Get ICache cache line size
*
* @param None
*
* @return uint32_t: 16, 32, 64 Byte
* @return uint32_t: 16, 32 Byte
*/
uint32_t Cache_Get_ICache_Line_Size(void);
@ -841,12 +848,12 @@ uint32_t Cache_Get_ICache_Line_Size(void);
*
* @param None
*
* @return uint32_t: 16, 32, 64 Byte
* @return uint32_t: 16, 32 Byte
*/
uint32_t Cache_Get_DCache_Line_Size(void);
/**
* @brief Set default mode from boot.
* @brief Set default mode from boot, 8KB ICache, 16Byte cache line size.
*
* @param None
*
@ -854,6 +861,15 @@ uint32_t Cache_Get_DCache_Line_Size(void);
*/
void Cache_Set_Default_Mode(void);
/**
* @brief Set default mode from boot, 8KB DCache, 16Byte cache line size.
*
* @param None
*
* @return None
*/
void Cache_Enable_Defalut_DCache_Mode(void);
/**
* @brief Travel tag memory to run a call back function.
* ICache and DCache are suspend when doing this.

148
components/esp_rom/include/esp32s2beta/rom/digital_signature.h Normal file
View File

@ -0,0 +1,148 @@
/*
ROM functions for hardware Digital Signature peripheral verification
*/
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#define ETS_DS_IV_LEN 16
/* Length of parameter 'C' stored in flash */
#define ETS_DS_C_LEN (12672 / 8)
/* Encrypted ETS data. Recommended to store in flash in this format.
*/
typedef struct {
/* RSA LENGTH register parameters
* (number of words in RSA key & operands, minus one).
*
* Max value 127 (for RSA 4096).
*
* This value must match the length field encrypted and stored in 'c',
* or invalid results will be returned. (The DS peripheral will
* always use the value in 'c', not this value, so an attacker can't
* alter the DS peripheral results this way, it will just truncate or
* extend the message and the resulting signature in software.)
*/
unsigned rsa_length;
/* IV value used to encrypt 'c' */
uint8_t iv[ETS_DS_IV_LEN];
/* Encrypted Digital Signature parameters. Result of AES-CBC encryption
of plaintext values. Includes an encrypted message digest.
*/
uint8_t c[ETS_DS_C_LEN];
} ets_ds_data_t;
typedef enum {
ETS_DS_OK,
ETS_DS_INVALID_PARAM, /* Supplied parameters are invalid */
ETS_DS_INVALID_KEY, /* HMAC peripheral failed to supply key */
ETS_DS_INVALID_PADDING, /* 'c' decrypted with invalid padding */
ETS_DS_INVALID_DIGEST, /* 'c' decrypted with invalid digest */
} ets_ds_result_t;
void ets_ds_enable(void);
void ets_ds_disable(void);
/*
* @brief Start signing a message (or padded message digest) using the Digital Signature peripheral
*
* - @param message Pointer to message (or padded digest) containing the message to sign. Should be
* (data->rsa_length + 1)*4 bytes long. @param data Pointer to DS data. Can be a pointer to data
* in flash.
*
* Caller must have already called ets_ds_enable() and ets_hmac_calculate_downstream() before calling
* this function, and is responsible for calling ets_ds_finish_sign() and then
* ets_hmac_invalidate_downstream() afterwards.
*
* @return ETS_DS_OK if signature is in progress, ETS_DS_INVALID_PARAM if param is invalid,
* EST_DS_INVALID_KEY if key or HMAC peripheral is configured incorrectly.
*/
ets_ds_result_t ets_ds_start_sign(const void *message, const ets_ds_data_t *data);
/*
* @brief Returns true if the DS peripheral is busy following a call to ets_ds_start_sign()
*
* A result of false indicates that a call to ets_ds_finish_sign() will not block.
*
* Only valid if ets_ds_enable() has been called.
*/
bool ets_ds_is_busy(void);
/* @brief Finish signing a message using the Digital Signature peripheral
*
* Must be called after ets_ds_start_sign(). Can use ets_ds_busy() to wait until
* peripheral is no longer busy.
*
* - @param signature Pointer to buffer to contain the signature. Should be
* (data->rsa_length + 1)*4 bytes long.
* - @param data Should match the 'data' parameter passed to ets_ds_start_sign()
*
* @param ETS_DS_OK if signing succeeded, ETS_DS_INVALID_PARAM if param is invalid,
* ETS_DS_INVALID_DIGEST or ETS_DS_INVALID_PADDING if there is a problem with the
* encrypted data digest or padding bytes (in case of ETS_DS_INVALID_PADDING, a
* digest is produced anyhow.)
*/
ets_ds_result_t ets_ds_finish_sign(void *signature, const ets_ds_data_t *data);
/* Plaintext parameters used by Digital Signature.
Not used for signing with DS peripheral, but can be encrypted
in-device by calling ets_ds_encrypt_params()
*/
typedef struct {
uint32_t Y[4096/32];
uint32_t M[4096/32];
uint32_t Rb[4096/32];
uint32_t M_prime;
uint32_t length;
} ets_ds_p_data_t;
typedef enum {
ETS_DS_KEY_HMAC, /* The HMAC key (as stored in efuse) */
ETS_DS_KEY_AES, /* The AES key (as derived from HMAC key by HMAC peripheral in downstream mode) */
} ets_ds_key_t;
/* @brief Encrypt DS parameters suitable for storing and later use with DS peripheral
*
* @param data Output buffer to store encrypted data, suitable for later use generating signatures.
* @param iv Pointer to 16 byte IV buffer, will be copied into 'data'. Should be randomly generated bytes each time.
* @param p_data Pointer to input plaintext key data. The expectation is this data will be deleted after this process is done and 'data' is stored.
* @param key Pointer to 32 bytes of key data. Type determined by key_type parameter. The expectation is the corresponding HMAC key will be stored to efuse and then permanently erased.
* @param key_type Type of key stored in 'key' (either the AES-256 DS key, or an HMAC DS key from which the AES DS key is derived using HMAC peripheral)
*
* @return ETS_DS_INVALID_PARAM if any parameter is invalid, or ETS_DS_OK if 'data' is successfully generated from the input parameters.
*/
ets_ds_result_t ets_ds_encrypt_params(ets_ds_data_t *data, const void *iv, const ets_ds_p_data_t *p_data, const void *key, ets_ds_key_t key_type);
#ifdef __cplusplus
}
#endif

92
components/esp_rom/include/esp32s2beta/rom/efuse.h
View File

@ -50,7 +50,7 @@ typedef enum {
typedef enum {
ETS_EFUSE_BLOCK0 = 0,
ETS_EFUSE_MAC_SPI_8M_0 = 1,
ETS_EFUSE_MAC_SPI_SYS_0 = 1,
ETS_EFUSE_BLOCK_SYS_DATA = 2,
ETS_EFUSE_BLOCK_USR_DATA = 3,
ETS_EFUSE_BLOCK_KEY0 = 4,
@ -63,6 +63,15 @@ typedef enum {
ETS_EFUSE_BLOCK_MAX,
} ets_efuse_block_t;
/**
* @brief set timing accroding the apb clock, so no read error or write error happens.
*
* @param clock: apb clock in HZ, only accept 20M, 40M, 80M.
*
* @return : 0 if success, others if clock not accepted
*/
int ets_efuse_set_timing(uint32_t clock);
/**
* @brief Enable efuse subsystem. Called after reset. Doesn't need to be called again.
*/
@ -73,18 +82,18 @@ void ets_efuse_start(void);
*
* @param null
*
* @return null
* @return : 0 is success, others if apb clock is not accepted
*/
void ets_efuse_read(void);
int ets_efuse_read(void);
/**
* @brief Efuse write operation: Copies data from efuse write registers to efuse. Operates on a single block of efuses at a time.
*
* @note This function does not update read efuses, call ets_efuse_read() once all programming is complete.
*
* @return null
* @return : 0 is success, others if apb clock is not accepted
*/
void ets_efuse_program(ets_efuse_block_t block);
int ets_efuse_program(ets_efuse_block_t block);
/**
* @brief Set all Efuse program registers to zero.
@ -97,7 +106,7 @@ void ets_efuse_clear_program_registers(void);
* @brief Program a block of key data to an efuse block
*
* @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. Key block must be unused (@ref ets_efuse_key_block_unused).
* @param purpose Purpose to set for this key.
* @param purpose Purpose to set for this key. Purpose must be already unset.
* @param data Pointer to data to write.
* @param data_len Length of data to write.
*
@ -167,25 +176,6 @@ unsigned ets_efuse_count_unused_key_blocks(void);
*/
void ets_efuse_rs_calculate(const void *data, void *rs_values);
/**
* @brief Read 8M Analog Clock value(12 bits) in efuse, the analog clock will not change with temperature.
* It can be used to test the external xtal frequency, do not touch this efuse field.
*
* @param null
*
* @return uint32_t: 1 for 10KHZ, range is 0 to 4095.
*/
uint32_t ets_efuse_get_8M_clock(void);
/**
* @brief Read xtal frequency value(6 bits) in efuse.
*
* @param null
*
* @return uint32_t: 1 for 1MHz, range is 0 to 63, 0 means the xtal frequency not record in efuse.
*/
uint32_t ets_efuse_get_xtal_freq(void);
/**
* @brief Read spi flash pads configuration from Efuse
*
@ -207,6 +197,16 @@ uint32_t ets_efuse_get_spiconfig(void);
*/
uint32_t ets_efuse_get_wp_pad(void);
/**
* @brief Read opi flash pads configuration from Efuse
*
* @return
* - 0 for default SPI pins.
* - Other values define a custom pin configuration mask. From the LSB, every 6 bits represent a GPIO number which stand for:
* DQS, D4, D5, D6, D7 accordingly.
*/
uint32_t ets_efuse_get_opiconfig(void);
/**
* @brief Read if download mode disabled from Efuse
*
@ -246,7 +246,10 @@ uint32_t ets_efuse_get_uart_print_control(void);
uint32_t ets_efuse_get_uart_print_channel(void);
/**
* @brief Read if usb dowload mode disabled from Efuse
* @brief Read if usb download mode disabled from Efuse
*
* (Also returns true if security download mode is enabled, as this mode
* disables USB download.)
*
* @return
* - true for efuse disable usb download mode.
@ -282,10 +285,45 @@ bool ets_efuse_usb_module_disabled(void);
bool ets_efuse_security_download_modes_enabled(void);
/**
* @brief Return true if secure boot enable in EFuse
* @brief Return true if secure boot is enabled in EFuse
*/
bool ets_efuse_secure_boot_enabled(void);
/**
* @brief Return true if secure boot aggressive revoke is enabled in EFuse
*/
bool ets_efuse_secure_boot_aggressive_revoke_enabled(void);
/**
* @brief Return true if cache encryption (flash, PSRAM, etc) is enabled from boot via EFuse
*/
bool ets_efuse_cache_encryption_enabled(void);
/**
* @brief Return true if EFuse indicates an external phy needs to be used for USB
*/
bool ets_efuse_usb_use_ext_phy(void);
/**
* @brief Return true if EFuse indicates USB device persistence is disabled
*/
bool ets_efuse_usb_force_nopersist(void);
/**
* @brief Return true if OPI pins GPIO33-37 are powered by VDDSPI, otherwise by VDD33CPU
*/
bool ets_efuse_flash_opi_5pads_power_sel_vddspi(void);
/**
* @brief Return true if EFuse indicates an opi flash is attached.
*/
bool ets_efuse_flash_opi_mode(void);
/**
* @brief Return true if EFuse indicates to send a flash resume command.
*/
bool ets_efuse_force_send_resume(void);
/**
* @brief return the time in us ROM boot need wait flash to power on from Efuse
*

69
components/esp_rom/include/esp32s2beta/rom/ets_sys.h
View File

@ -12,7 +12,8 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _ROM_ETS_SYS_H_
#define _ROM_ETS_SYS_H_
#include <stdint.h>
#include <stdbool.h>
@ -188,6 +189,23 @@ void ets_set_appcpu_boot_addr(uint32_t start);
*/
int ets_printf(const char *fmt, ...);
/**
* @brief Set the uart channel of ets_printf(uart_tx_one_char).
* ROM will set it base on the efuse and gpio setting, however, this can be changed after booting.
*
* @param uart_no : 0 for UART0, 1 for UART1, 2 for UART2.
*
* @return None
*/
void ets_set_printf_channel(uint8_t uart_no);
/**
* @brief Get the uart channel of ets_printf(uart_tx_one_char).
*
* @return uint8_t uart channel used by ets_printf(uart_tx_one_char).
*/
uint8_t ets_get_printf_channel(void);
/**
* @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function.
* Can not print float point data format, or longlong data format
@ -359,6 +377,18 @@ void ets_delay_us(uint32_t us);
*/
void ets_update_cpu_frequency(uint32_t ticks_per_us);
/**
* @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate.
*
* @note This function only sets the tick rate for the current CPU. It is located in ROM,
* so the deep sleep stub can use it even if IRAM is not initialized yet.
*
* @param uint32_t ticks_per_us : CPU ticks per us.
*
* @return None
*/
void ets_update_cpu_frequency_rom(uint32_t ticks_per_us);
/**
* @brief Get the real CPU ticks per us to the ets.
* This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency.
@ -369,15 +399,6 @@ void ets_update_cpu_frequency(uint32_t ticks_per_us);
*/
uint32_t ets_get_cpu_frequency(void);
/**
* @brief Get xtal_freq/analog_8M*256 value calibrated in rtc module.
*
* @param None
*
* @return uint32_t : xtal_freq/analog_8M*256.
*/
uint32_t ets_get_xtal_scale(void);
/**
* @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store.
*
@ -391,6 +412,32 @@ uint32_t ets_get_xtal_scale(void);
*/
uint32_t ets_get_xtal_freq(void);
/**
* @brief Get the apb divisor. The xtal frequency gets divided
* by this value to generate the APB clock.
* When any types of reset happens, the default value is 2.
*
* @param None
*
* @return uint32_t : 1 or 2.
*/
uint32_t ets_get_xtal_div(void);
/**
* @brief Modifies the apb divisor. The xtal frequency gets divided by this to
* generate the APB clock.
*
* @note The xtal frequency divisor is 2 by default as the glitch detector
* doesn't properly stop glitches when it is 1. Please do not set the
* divisor to 1 before the PLL is active without being aware that you
* may be introducing a security risk.
*
* @param div Divisor. 1 = xtal freq, 2 = 1/2th xtal freq.
*/
void ets_set_xtal_div(int div);
/**
* @brief Get apb_freq value, If value not stored in RTC_STORE5, than store.
*
@ -607,3 +654,5 @@ typedef enum {
#ifdef __cplusplus
}
#endif
#endif /* _ROM_ETS_SYS_H_ */

32
components/esp_rom/include/esp32s2beta/rom/gpio.h
View File

@ -242,18 +242,18 @@ void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_
*
* @return None
*/
void gpio_pad_select_gpio(uint8_t gpio_num);
void gpio_pad_select_gpio(uint32_t gpio_num);
/**
* @brief Set pad driver capability.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
*
* @param uint8_t drv : 0-3
* @param uint32_t drv : 0-3
*
* @return None
*/
void gpio_pad_set_drv(uint8_t gpio_num, uint8_t drv);
void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv);
/**
* @brief Pull up the pad from gpio number.
@ -262,7 +262,7 @@ void gpio_pad_set_drv(uint8_t gpio_num, uint8_t drv);
*
* @return None
*/
void gpio_pad_pullup(uint8_t gpio_num);
void gpio_pad_pullup(uint32_t gpio_num);
/**
* @brief Pull down the pad from gpio number.
@ -271,7 +271,7 @@ void gpio_pad_pullup(uint8_t gpio_num);
*
* @return None
*/
void gpio_pad_pulldown(uint8_t gpio_num);
void gpio_pad_pulldown(uint32_t gpio_num);
/**
* @brief Unhold the pad from gpio number.
@ -280,7 +280,7 @@ void gpio_pad_pulldown(uint8_t gpio_num);
*
* @return None
*/
void gpio_pad_unhold(uint8_t gpio_num);
void gpio_pad_unhold(uint32_t gpio_num);
/**
* @brief Hold the pad from gpio number.
@ -289,7 +289,25 @@ void gpio_pad_unhold(uint8_t gpio_num);
*
* @return None
*/
void gpio_pad_hold(uint8_t gpio_num);
void gpio_pad_hold(uint32_t gpio_num);
/**
* @brief enable gpio pad input.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
*
* @return None
*/
void gpio_pad_input_enable(uint32_t gpio_num);
/**
* @brief disable gpio pad input.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
*
* @return None
*/
void gpio_pad_input_disable(uint32_t gpio_num);
/**
* @}

2
components/esp_rom/include/esp32s2beta/rom/lldesc.h
View File

@ -71,7 +71,7 @@ typedef struct lldesc_s {
sosf : 1, /* start of sub-frame */
eof : 1, /* end of frame */
owner : 1; /* hw or sw */
volatile uint8_t *buf; /* point to buffer data */
volatile const uint8_t *buf; /* point to buffer data */
union{
volatile uint32_t empty;
STAILQ_ENTRY(lldesc_s) qe; /* pointing to the next desc */

1
components/esp_rom/include/esp32s2beta/rom/rsa_pss.h
View File

@ -16,6 +16,7 @@
#define _ROM_RSA_PSS_H_
#include <stdint.h>
#include "rsa_pss.h"
#define ETS_SIG_LEN 384 /* Bytes */
#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */

8
components/esp_rom/include/esp32s2beta/rom/rtc.h
View File

@ -82,8 +82,7 @@ typedef enum {
NO_MEAN = 0,
POWERON_RESET = 1, /**<1, Vbat power on reset*/
RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core*/
DEEPSLEEP_RESET = 5, /**<3, Deep Sleep reset digital core*/
SDIO_RESET = 6, /**<6, Reset by SLC module, reset digital core*/
DEEPSLEEP_RESET = 5, /**<5, Deep Sleep reset digital core*/
TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/
TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/
RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/
@ -93,8 +92,9 @@ typedef enum {
RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/
TG1WDT_CPU_RESET = 17, /**<11, Time Group1 reset CPU*/
SUPER_WDT_RESET = 18, /**<11, super watchdog reset digital core and rtc module*/
TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/
SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/
GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/
} RESET_REASON;
typedef enum {

10
components/esp_rom/include/esp32s2beta/rom/spi_flash.h
View File

@ -83,18 +83,18 @@ extern "C" {
#define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1)
#define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1)
#define SPI0_R_QIO_DUMMY_CYCLELEN 3
#define SPI0_R_QIO_ADDR_BITSLEN 31
#define SPI0_R_QIO_DUMMY_CYCLELEN 5
#define SPI0_R_QIO_ADDR_BITSLEN 23
#define SPI0_R_FAST_DUMMY_CYCLELEN 7
#define SPI0_R_DIO_DUMMY_CYCLELEN 3
#define SPI0_R_FAST_ADDR_BITSLEN 23
#define SPI0_R_SIO_ADDR_BITSLEN 23
#define SPI1_R_QIO_DUMMY_CYCLELEN 3
#define SPI1_R_QIO_ADDR_BITSLEN 31
#define SPI1_R_QIO_DUMMY_CYCLELEN 5
#define SPI1_R_QIO_ADDR_BITSLEN 23
#define SPI1_R_FAST_DUMMY_CYCLELEN 7
#define SPI1_R_DIO_DUMMY_CYCLELEN 3
#define SPI1_R_DIO_ADDR_BITSLEN 31
#define SPI1_R_DIO_ADDR_BITSLEN 23
#define SPI1_R_FAST_ADDR_BITSLEN 23
#define SPI1_R_SIO_ADDR_BITSLEN 23

49
components/esp_rom/include/esp32s2beta/rom/uart.h
View File

@ -33,7 +33,7 @@ extern "C" {
* @{
*/
#define RX_BUFF_SIZE 0x100
#define RX_BUFF_SIZE 0x400
#define TX_BUFF_SIZE 100
//uart int enalbe register ctrl bits
@ -156,7 +156,6 @@ typedef struct {
UartStopBitsNum stop_bits;
UartFlowCtrl flow_ctrl;
uint8_t buff_uart_no; //indicate which uart use tx/rx buffer
uint8_t tx_uart_no;
RcvMsgBuff rcv_buff;
// TrxMsgBuff trx_buff;
RcvMsgState rcv_state;
@ -167,11 +166,11 @@ typedef struct {
* @brief Init uart device struct value and reset uart0/uart1 rx.
* Please do not call this function in SDK.
*
* @param None
* @param rxBuffer, must be a pointer to RX_BUFF_SIZE bytes or NULL
*
* @return None
*/
void uartAttach(void);
void uartAttach(void *rxBuffer);
/**
* @brief Init uart0 or uart1 for UART download booting mode.
@ -197,6 +196,21 @@ void Uart_Init(uint8_t uart_no, uint32_t clock);
*/
void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue);
/**
* @brief Re-calculate UART baudrate divisor for a given (changed)
* clock speed.
* This function will not reset RX/TX fifo for uart.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @param uint32_t clock : clock used by uart module, to adjust baudrate.
*
* @return None
*/
void uart_div_reinit(uint8_t uart_no, uint32_t clock);
/**
* @brief Init uart0 or uart1 for UART download booting mode.
* Please do not call this function in SDK.
@ -401,6 +415,33 @@ STATUS SendMsg(uint8_t *pData, uint16_t DataLen);
*/
STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync);
/**
* @brief Check if this UART is in download connection.
* Please do not call this function in SDK.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @return ETS_NO_BOOT = 0 for no.
* SEL_UART_BOOT = BIT(1) for yes.
*/
uint8_t UartConnCheck(uint8_t uart_no);
/**
* @brief Initialize the USB ACM UART
* Needs to be fed a buffer of at least 128 bytes, plus any rx buffer you may want to have.
*
* @param cdc_acm_work_mem Pointer to work mem for CDC-ACM code
* @param cdc_acm_work_mem_len Length of work mem
*/
void Uart_Init_USB(void *cdc_acm_work_mem, int cdc_acm_work_mem_len);
/**
* @brief Install handler to reset the chip when a RTS change has been detected on the CDC-ACM 'UART'.
*/
void uart_usb_enable_reset_on_rts(void);
extern UartDevice UartDev;
/**

2
components/espcoredump/src/core_dump_common.c
View File

@ -21,7 +21,7 @@ const static DRAM_ATTR char TAG[] __attribute__((unused)) = "esp_core_dump_commo
#if CONFIG_ESP32_COREDUMP_DATA_FORMAT_BIN
static inline uint32_t esp_core_dump_get_tcb_len()
static inline uint32_t esp_core_dump_get_tcb_len(void)
{
if (COREDUMP_TCB_SIZE % sizeof(uint32_t)) {
return ((COREDUMP_TCB_SIZE / sizeof(uint32_t) + 1) * sizeof(uint32_t));

2
components/esptool_py/esptool

@ -1 +1 @@
Subproject commit f04d34bcab29ace798d2d3800ba87020cccbbfdd
Subproject commit abdceb512db1cf2faffbb261a5e474442bc41bdb

2
components/freertos/test/test_thread_local.c
View File

@ -24,7 +24,7 @@ static __thread struct test_tls_var {
uint8_t farr[10];
} tl_test_struct_var;
static void task_test_tls(void *arg)
static __attribute__((unused)) void task_test_tls(void *arg)
{
bool *running = (bool *)arg;
uint32_t tp = (uint32_t)-1;

4
components/heap/test/test_leak.c
View File

@ -46,13 +46,13 @@ TEST_CASE_MULTIPLE_STAGES("Not check for leaks in MULTIPLE_STAGES mode", "[heap]
TEST_CASE_MULTIPLE_STAGES("Check for leaks in MULTIPLE_STAGES mode (leak)", "[heap][ignore]", test_fn, test_fn, test_fn);
static void test_fn2(void)
static __attribute__((unused)) void test_fn2(void)
{
check_calloc(1000);
esp_restart();
}
static void test_fn3(void)
static __attribute__((unused)) void test_fn3(void)
{
check_calloc(1000);
}

1132
components/mbedtls/port/esp32s2beta/aes.c
View File

File diff suppressed because it is too large Load Diff

14
components/mbedtls/port/esp32s2beta/esp_bignum.c
View File

@ -56,11 +56,10 @@ void esp_mpi_acquire_hardware( void )
/* newlib locks lazy initialize on ESP-IDF */
_lock_acquire(&mpi_lock);
DPORT_REG_SET_BIT(DPORT_PERI_CLK_EN_REG, DPORT_CLK_EN_RSA);
/* also clear reset on digital signature & secure boot, otherwise RSA is held in reset */
DPORT_REG_CLR_BIT(DPORT_PERI_RST_EN_REG, DPORT_RST_EN_RSA
| DPORT_RST_EN_DIGITAL_SIGNATURE
| DPORT_RST_EN_SECURE_BOOT);
DPORT_REG_SET_BIT(DPORT_PERIP_CLK_EN1_REG, DPORT_CRYPTO_RSA_CLK_EN);
/* also clear reset on digital signature, otherwise RSA is held in reset */
DPORT_REG_CLR_BIT(DPORT_PERIP_RST_EN1_REG, DPORT_CRYPTO_RSA_RST
| DPORT_CRYPTO_DS_RST);
DPORT_REG_CLR_BIT(DPORT_RSA_PD_CTRL_REG, DPORT_RSA_MEM_PD);
@ -74,8 +73,8 @@ void esp_mpi_release_hardware( void )
DPORT_REG_SET_BIT(DPORT_RSA_PD_CTRL_REG, DPORT_RSA_PD);
/* don't reset digital signature unit, as this resets AES also */
DPORT_REG_SET_BIT(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_RSA);
DPORT_REG_CLR_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_RSA);
DPORT_REG_SET_BIT(DPORT_PERIP_RST_EN1_REG, DPORT_CRYPTO_RSA_RST);
DPORT_REG_CLR_BIT(DPORT_PERIP_CLK_EN1_REG, DPORT_CRYPTO_RSA_CLK_EN);
_lock_release(&mpi_lock);
}
@ -213,6 +212,7 @@ static inline void start_op(uint32_t op_reg)
{
/* Clear interrupt status */
DPORT_REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1);
DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);
/* Note: above REG_WRITE includes a memw, so we know any writes
to the memory blocks are also complete. */

212
components/mbedtls/port/esp32s2beta/sha.c
View File

@ -29,22 +29,37 @@
#include <stdio.h>
#include <sys/lock.h>
#include <assert.h>
#include "soc/soc.h"
#include "esp32s2beta/crypto_dma.h"
#include "esp32s2beta/sha.h"
#include "soc/crypto_dma_reg.h"
#include "esp32s2beta/rom/ets_sys.h"
#include "soc/dport_reg.h"
#include "soc/hwcrypto_reg.h"
#include "esp32s2beta/rom/lldesc.h"
#include "esp32s2beta/rom/cache.h"
#include "esp_intr_alloc.h"
#include "esp_log.h"
#include "soc/periph_defs.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
/* Single lock for SHA engine
*/
static _lock_t s_sha_lock;
/* This API was designed for ESP32, which has seperate
engines for SHA1,256,512. ESP32C has a single engine.
*/
/* Enable if want to use SHA interrupt */
//#define CONFIG_MBEDTLS_SHA_USE_INTERRUPT
#if defined(CONFIG_MBEDTLS_SHA_USE_INTERRUPT)
static SemaphoreHandle_t op_complete_sem;
#endif
/* Return block size (in bytes) for a given SHA type */
inline static size_t block_length(esp_sha_type type) {
inline static size_t block_length(esp_sha_type type)
{
switch (type) {
case SHA1:
case SHA2_224:
@ -52,6 +67,9 @@ inline static size_t block_length(esp_sha_type type) {
return 64;
case SHA2_384:
case SHA2_512:
case SHA2_512224:
case SHA2_512256:
case SHA2_512T:
return 128;
default:
return 0;
@ -59,7 +77,8 @@ inline static size_t block_length(esp_sha_type type) {
}
/* Return state size (in bytes) for a given SHA type */
inline static size_t state_length(esp_sha_type type) {
inline static size_t state_length(esp_sha_type type)
{
switch (type) {
case SHA1:
return 160 / 8;
@ -68,36 +87,18 @@ inline static size_t state_length(esp_sha_type type) {
return 256 / 8;
case SHA2_384:
case SHA2_512:
case SHA2_512224:
case SHA2_512256:
case SHA2_512T:
return 512 / 8;
default:
return 0;
}
}
/* Copy words in memory (to/from a memory block), byte swapping as we go. */
static void memcpy_endianswap(void *to, const void *from, size_t num_bytes)
{
uint32_t *to_words = (uint32_t *)to;
const uint32_t *from_words = (const uint32_t *)from;
assert(num_bytes % 4 == 0);
for (int i = 0; i < num_bytes / 4; i++) {
to_words[i] = __builtin_bswap32(from_words[i]);
}
asm volatile ("memw");
}
static void memcpy_swapwords(void *to, const void *from, size_t num_bytes)
{
uint32_t *to_words = (uint32_t *)to;
const uint32_t *from_words = (const uint32_t *)from;
assert(num_bytes % 8 == 0);
for (int i = 0; i < num_bytes / 4; i += 2) {
to_words[i] = from_words[i+1];
to_words[i+1] = from_words[i];
}
asm volatile ("memw");
}
/* This API was designed for ESP32, which has seperate
engines for SHA1,256,512. ESP32C has a single engine.
*/
static void esp_sha_lock_engine_inner(void);
bool esp_sha_try_lock_engine(esp_sha_type sha_type)
@ -117,55 +118,156 @@ void esp_sha_lock_engine(esp_sha_type sha_type)
esp_sha_lock_engine_inner();
}
/* Enable SHA block and then lock it */
static void esp_sha_lock_engine_inner(void)
{
ets_sha_enable();
/* Need to lock DMA since it is shared with AES block */
portENTER_CRITICAL(&crypto_dma_spinlock);
REG_SET_BIT(DPORT_PERIP_CLK_EN1_REG, DPORT_CRYPTO_SHA_CLK_EN | DPORT_CRYPTO_DMA_CLK_EN);
REG_CLR_BIT(DPORT_PERIP_RST_EN1_REG, DPORT_CRYPTO_SHA_RST | DPORT_CRYPTO_HMAC_RST |
DPORT_CRYPTO_DMA_RST | DPORT_CRYPTO_DS_RST);
/* DMA for SHA */
REG_WRITE(CRYPTO_DMA_AES_SHA_SELECT_REG, 1);
}
/* Disable SHA block and then unlock it */
void esp_sha_unlock_engine(esp_sha_type sha_type)
{
ets_sha_disable();
REG_WRITE(CRYPTO_DMA_AES_SHA_SELECT_REG, 0);
REG_SET_BIT(DPORT_PERIP_RST_EN1_REG, DPORT_CRYPTO_SHA_RST | DPORT_CRYPTO_DMA_RST |
DPORT_CRYPTO_DS_RST);
REG_CLR_BIT(DPORT_PERIP_CLK_EN1_REG, DPORT_CRYPTO_SHA_CLK_EN | DPORT_CRYPTO_DMA_CLK_EN);
portEXIT_CRITICAL(&crypto_dma_spinlock);
_lock_release(&s_sha_lock);
}
#if defined (CONFIG_MBEDTLS_SHA_USE_INTERRUPT)
static IRAM_ATTR void esp_sha_dma_isr(void *arg)
{
BaseType_t higher_woken;
REG_WRITE(SHA_CLEAR_IRQ_REG, 1);
xSemaphoreGiveFromISR(op_complete_sem, &higher_woken);
if (higher_woken) {
portYIELD_FROM_ISR();
}
}
#endif
/* Check if SHA operation completed */
static int esp_sha_dma_complete(void)
{
#if defined (CONFIG_MBEDTLS_SHA_USE_INTERRUPT)
if (!xSemaphoreTake(op_complete_sem, 2000 / portTICK_PERIOD_MS)) {
ESP_LOGE("SHA", "Timed out waiting for completion of SHA Interrupt");
return -1;
}
#else
esp_sha_wait_idle();
#endif
return 0;
}
/* Wait until SHA is busy */
void esp_sha_wait_idle(void)
{
while (DPORT_REG_READ(SHA_BUSY_REG) != 0) { }
}
/* Read the SHA digest from hardware */
void esp_sha_read_digest_state(esp_sha_type sha_type, void *digest_state)
{
/* engine should be locked */
esp_sha_wait_idle();
if (sha_type != SHA2_512 && sha_type != SHA2_384) {
/* <SHA-512, read out directly */
memcpy(digest_state, (void *)SHA_H_BASE, state_length(sha_type));
} else {
/* SHA-512, read out with each pair of words swapped */
memcpy_swapwords(digest_state, (void *)SHA_H_BASE, state_length(sha_type));
}
}
/* Internally calls DMA API for single block */
void esp_sha_block(esp_sha_type sha_type, const void *data_block, bool is_first_block)
{
/* engine should be locked */
REG_WRITE(SHA_MODE_REG, sha_type);
/* ESP32C SHA unit can be loaded while previous block is processing */
memcpy_endianswap((void *)SHA_M_BASE, data_block, block_length(sha_type));
esp_sha_wait_idle();
if (is_first_block) {
REG_WRITE(SHA_START_REG, 1);
} else {
REG_WRITE(SHA_CONTINUE_REG, 1);
esp_sha_dma(sha_type, data_block, block_length(sha_type), is_first_block);
}
/* Note: deliberately not waiting for this operation to complete,
as a performance tweak - delay waiting until the next time we need the SHA
unit, instead.
*/
/* Performs SHA on multiple blocks at a time */
int esp_sha_dma(esp_sha_type sha_type, const void *data_block, uint32_t ilen, bool is_first_block)
{
size_t blk_len = 0;
const uint8_t *local_buf = data_block;
int ret = 0;
volatile lldesc_t dma_descr;
if (ilen == 0) {
return ret;
}
blk_len = block_length(sha_type);
REG_WRITE(SHA_MODE_REG, sha_type);
if ((sha_type == SHA2_512T) && (is_first_block == true)) {
REG_WRITE(SHA_START_REG, 1);
}
REG_WRITE(SHA_BLOCK_NUM_REG, (ilen / blk_len));
if ((sha_type == SHA2_512T) && (is_first_block == true)) {
esp_sha_wait_idle();
is_first_block = false;
}
bzero( (void *)&dma_descr, sizeof( dma_descr ) );
/* DMA descriptor for Memory to DMA-AES transfer */
dma_descr.length = ilen;
dma_descr.size = ilen;
dma_descr.owner = 1;
dma_descr.eof = 1;
dma_descr.buf = local_buf;
dma_descr.sosf = 0;
dma_descr.empty = 0;
#if (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC)
if ((unsigned int)data_block >= SOC_EXTRAM_DATA_LOW && (unsigned int)data_block <= SOC_EXTRAM_DATA_HIGH) {
Cache_WriteBack_All();
}
#endif
/* Reset DMA */
SET_PERI_REG_MASK(CRYPTO_DMA_CONF0_REG, CONF0_REG_AHBM_RST | CONF0_REG_OUT_RST | CONF0_REG_AHBM_FIFO_RST);
CLEAR_PERI_REG_MASK(CRYPTO_DMA_CONF0_REG, CONF0_REG_AHBM_RST | CONF0_REG_OUT_RST | CONF0_REG_AHBM_FIFO_RST);
/* Set descriptors */
CLEAR_PERI_REG_MASK(CRYPTO_DMA_OUT_LINK_REG, OUT_LINK_REG_OUTLINK_ADDR);
SET_PERI_REG_MASK(CRYPTO_DMA_OUT_LINK_REG, ((uint32_t)(&dma_descr))&OUT_LINK_REG_OUTLINK_ADDR);
/* Start transfer */
SET_PERI_REG_MASK(CRYPTO_DMA_OUT_LINK_REG, OUT_LINK_REG_OUTLINK_START);
#if defined (CONFIG_MBEDTLS_SHA_USE_INTERRUPT)
REG_WRITE(SHA_CLEAR_IRQ_REG, 1);
if (op_complete_sem == NULL) {
op_complete_sem = xSemaphoreCreateBinary();
esp_intr_alloc(ETS_SHA_INTR_SOURCE, 0, esp_sha_dma_isr, 0, 0);
}
REG_WRITE(SHA_INT_ENA_REG, 1);
#endif
if (is_first_block) {
REG_WRITE(SHA_DMA_START_REG, 1);
} else {
REG_WRITE(SHA_DMA_CONTINUE_REG, 1);
}
ret = esp_sha_dma_complete();
#if (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC)
if ((unsigned int)data_block >= SOC_EXTRAM_DATA_LOW && (unsigned int)data_block <= SOC_EXTRAM_DATA_HIGH) {
Cache_Invalidate_DCache_All();
}
#endif
return ret;
}
void esp_sha(esp_sha_type sha_type, const unsigned char *input, size_t ilen, unsigned char *output)

40
components/mbedtls/port/include/esp32s2beta/crypto_dma.h Normal file
View File

@ -0,0 +1,40 @@
/**
* Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
* Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*
*/
#ifndef ESP_CRYPTO_DMA_H
#define ESP_CRYPTO_DMA_H
#include <freertos/FreeRTOS.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Since crypto DMA is shared between DMA-AES and SHA blocks
* Needs to be taken by respective blocks before using Crypto DMA
*/
extern portMUX_TYPE crypto_dma_spinlock;
#ifdef __cplusplus
}
#endif
#endif /* crypto_dma.h */

224
components/mbedtls/port/include/esp32s2beta/gcm.h Normal file
View File

@ -0,0 +1,224 @@
/**
* \brief AES block cipher, ESP32C hardware accelerated version
* Based on mbedTLS FIPS-197 compliant version.
*
* Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
* Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*
*/
#ifndef ESP_GCM_H
#define ESP_GCM_H
#include "aes.h"
#include "mbedtls/cipher.h"
#ifdef __cplusplus
extern "C" {
#endif
#define MBEDTLS_ERR_GCM_AUTH_FAILED -0x0012 /**< Authenticated decryption failed. */
#define MBEDTLS_ERR_GCM_BAD_INPUT -0x0014 /**< Bad input parameters to function.*/
/**
* \brief The GCM context structure.
*/
typedef struct {
uint8_t H[16]; /*!< H */
size_t iv_len; /*!< The length of IV. */
uint64_t aad_len; /*!< The total length of the additional data. */
const unsigned char *aad; /*!< The additional data. */
esp_aes_context aes_ctx;
}
esp_aes_gcm_context;
/**
* \brief This function initializes the specified GCM context
*
* \param ctx The GCM context to initialize.
*/
void esp_aes_gcm_init( esp_aes_gcm_context *ctx);
/**
* \brief This function associates a GCM context with a
* key.
*
* \param ctx The GCM context to initialize.
* \param cipher The 128-bit block cipher to use.
* \param key The encryption key.
* \param keybits The key size in bits. Valid options are:
* <ul><li>128 bits</li>
* <li>192 bits</li>
* <li>256 bits</li></ul>
*
* \return \c 0 on success.
* \return A cipher-specific error code on failure.
*/
int esp_aes_gcm_setkey( esp_aes_gcm_context *ctx,
mbedtls_cipher_id_t cipher,
const unsigned char *key,
unsigned int keybits );
/**
* \brief This function starts a GCM encryption or decryption
* operation.
*
* \param ctx The GCM context.
* \param mode The operation to perform: #MBEDTLS_GCM_ENCRYPT or
* #MBEDTLS_GCM_DECRYPT.
* \param iv The initialization vector.
* \param iv_len The length of the IV.
* \param add The buffer holding the additional data, or NULL
* if \p add_len is 0.
* \param add_len The length of the additional data. If 0,
* \p add is NULL.
*
* \return \c 0 on success.
*/
int esp_aes_gcm_starts( esp_aes_gcm_context *ctx,
int mode,
const unsigned char *iv,
size_t iv_len,
const unsigned char *aad,
size_t aad_len );
/**
* \brief This function feeds an input buffer into an ongoing GCM
* encryption or decryption operation.
*
* ` The function expects input to be a multiple of 16
* Bytes. Only the last call before calling
* mbedtls_gcm_finish() can be less than 16 Bytes.
*
* \note For decryption, the output buffer cannot be the same as
* input buffer. If the buffers overlap, the output buffer
* must trail at least 8 Bytes behind the input buffer.
*
* \param ctx The GCM context.
* \param length The length of the input data. This must be a multiple of
* 16 except in the last call before mbedtls_gcm_finish().
* \param input The buffer holding the input data.
* \param output The buffer for holding the output data.
*
* \return \c 0 on success.
* \return #MBEDTLS_ERR_GCM_BAD_INPUT on failure.
*/
int esp_aes_gcm_update( esp_aes_gcm_context *ctx,
size_t length,
const unsigned char *input,
unsigned char *output );
/**
* \brief This function finishes the GCM operation and generates
* the authentication tag.
*
* It wraps up the GCM stream, and generates the
* tag. The tag can have a maximum length of 16 Bytes.
*
* \param ctx The GCM context.
* \param tag The buffer for holding the tag.
* \param tag_len The length of the tag to generate. Must be at least four.
*
* \return \c 0 on success.
* \return #MBEDTLS_ERR_GCM_BAD_INPUT on failure.
*/
int esp_aes_gcm_finish( esp_aes_gcm_context *ctx,
unsigned char *tag,
size_t tag_len );
/**
* \brief This function clears a GCM context
*
* \param ctx The GCM context to clear.
*/
void esp_aes_gcm_free( esp_aes_gcm_context *ctx);
/**
* \brief This function performs GCM encryption or decryption of a buffer.
*
* \note For encryption, the output buffer can be the same as the
* input buffer. For decryption, the output buffer cannot be
* the same as input buffer. If the buffers overlap, the output
* buffer must trail at least 8 Bytes behind the input buffer.
*
* \param ctx The GCM context to use for encryption or decryption.
* \param mode The operation to perform: #MBEDTLS_GCM_ENCRYPT or
* #MBEDTLS_GCM_DECRYPT.
* \param length The length of the input data. This must be a multiple of
* 16 except in the last call before mbedtls_gcm_finish().
* \param iv The initialization vector.
* \param iv_len The length of the IV.
* \param add The buffer holding the additional data.
* \param add_len The length of the additional data.
* \param input The buffer holding the input data.
* \param output The buffer for holding the output data.
* \param tag_len The length of the tag to generate.
* \param tag The buffer for holding the tag.
*
* \return \c 0 on success.
*/
int esp_aes_gcm_crypt_and_tag( esp_aes_gcm_context *ctx,
int mode,
size_t length,
const unsigned char *iv,
size_t iv_len,
const unsigned char *add,
size_t add_len,
const unsigned char *input,
unsigned char *output,
size_t tag_len,
unsigned char *tag );
/**
* \brief This function performs a GCM authenticated decryption of a
* buffer.
*
* \note For decryption, the output buffer cannot be the same as
* input buffer. If the buffers overlap, the output buffer
* must trail at least 8 Bytes behind the input buffer.
*
* \param ctx The GCM context.
* \param length The length of the input data. This must be a multiple
* of 16 except in the last call before mbedtls_gcm_finish().
* \param iv The initialization vector.
* \param iv_len The length of the IV.
* \param add The buffer holding the additional data.
* \param add_len The length of the additional data.
* \param tag The buffer holding the tag.
* \param tag_len The length of the tag.
* \param input The buffer holding the input data.
* \param output The buffer for holding the output data.
*
* \return 0 if successful and authenticated.
* \return #MBEDTLS_ERR_GCM_AUTH_FAILED if the tag does not match.
*/
int esp_aes_gcm_auth_decrypt( esp_aes_gcm_context *ctx,
size_t length,
const unsigned char *iv,
size_t iv_len,
const unsigned char *add,
size_t add_len,
const unsigned char *tag,
size_t tag_len,
const unsigned char *input,
unsigned char *output );
#ifdef __cplusplus
}
#endif
#endif /* gcm.h */

26
components/mbedtls/port/include/esp32s2beta/sha.h
View File

@ -11,6 +11,7 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ESP_SHA_H_
#define _ESP_SHA_H_
@ -101,6 +102,31 @@ void esp_sha(esp_sha_type sha_type, const unsigned char *input, size_t ilen, uns
*/
void esp_sha_block(esp_sha_type sha_type, const void *data_block, bool is_first_block);
/* @brief Begin to execute SHA block operation using DMA
*
* @note This is a piece of a SHA algorithm, rather than an entire SHA
* algorithm.
*
* @note Call esp_sha_try_lock_engine() before calling this
* function. Do not call esp_sha_lock_memory_block() beforehand, this
* is done inside the function.
*
* @param sha_type SHA algorithm to use.
*
* @param data_block Pointer to block of data. Block size is
* determined by algorithm (SHA1/SHA2_256 = 64 bytes,
* SHA2_384/SHA2_512 = 128 bytes)
*
* @param ilen length of input data should be multiple of block length.
*
* @param is_first_block If this parameter is true, the SHA state will
* be initialised (with the initial state of the given SHA algorithm)
* before the block is calculated. If false, the existing state of the
* SHA engine will be used.
*
*/
int esp_sha_dma(esp_sha_type sha_type, const void *data_block, uint32_t ilen, bool is_first_block);
/** @brief Read out the current state of the SHA digest loaded in the engine.
*
* @note This is a piece of a SHA algorithm, rather than an entire SHA algorithm.

2
components/mbedtls/test/test_mbedtls_sha.c
View File

@ -264,7 +264,7 @@ typedef struct {
bool done;
} finalise_sha_param_t;
static void tskFinaliseSha(void *v_param)
static __attribute__((unused)) void tskFinaliseSha(void *v_param)
{
finalise_sha_param_t *param = (finalise_sha_param_t *)v_param;

45
components/soc/esp32s2beta/include/hal/adc_ll.h
View File

@ -2,6 +2,7 @@
#include "soc/adc_periph.h"
#include "hal/adc_types.h"
#include "soc/apb_ctrl_struct.h"
#include <stdbool.h>
typedef enum {
@ -78,11 +79,11 @@ typedef enum {
static inline void adc_ll_dig_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait)
{
// Internal FSM reset wait time
SYSCON.saradc_fsm_wait.rstb_wait = rst_wait;
APB_CTRL.saradc_fsm_wait.rstb_wait = rst_wait;
// Internal FSM start wait time
SYSCON.saradc_fsm_wait.xpd_wait = start_wait;
APB_CTRL.saradc_fsm_wait.xpd_wait = start_wait;
// Internal FSM standby wait time
SYSCON.saradc_fsm_wait.standby_wait = standby_wait;
APB_CTRL.saradc_fsm_wait.standby_wait = standby_wait;
}
/**
@ -94,7 +95,7 @@ static inline void adc_ll_dig_set_fsm_time(uint32_t rst_wait, uint32_t start_wai
*/
static inline void adc_ll_dig_set_sample_cycle(uint32_t sample_cycle)
{
SYSCON.saradc_fsm.sample_cycle = sample_cycle;
APB_CTRL.saradc_fsm.sample_cycle = sample_cycle;
}
/**
@ -104,7 +105,7 @@ static inline void adc_ll_dig_set_sample_cycle(uint32_t sample_cycle)
*/
static inline void adc_ll_dig_set_output_format(adc_ll_dig_output_format_t format)
{
SYSCON.saradc_ctrl.data_sar_sel = format;
APB_CTRL.saradc_ctrl.data_sar_sel = format;
}
/**
@ -115,7 +116,7 @@ static inline void adc_ll_dig_set_output_format(adc_ll_dig_output_format_t forma
*/
static inline void adc_ll_dig_set_convert_limit_num(uint32_t meas_num)
{
SYSCON.saradc_ctrl2.max_meas_num = meas_num;
APB_CTRL.saradc_ctrl2.max_meas_num = meas_num;
}
/**
@ -124,7 +125,7 @@ static inline void adc_ll_dig_set_convert_limit_num(uint32_t meas_num)
*/
static inline void adc_ll_dig_convert_limit_enable(void)
{
SYSCON.saradc_ctrl2.meas_num_limit = 1;
APB_CTRL.saradc_ctrl2.meas_num_limit = 1;
}
/**
@ -133,7 +134,7 @@ static inline void adc_ll_dig_convert_limit_enable(void)
*/
static inline void adc_ll_dig_convert_limit_disable(void)
{
SYSCON.saradc_ctrl2.meas_num_limit = 0;
APB_CTRL.saradc_ctrl2.meas_num_limit = 0;
}
/**
@ -146,15 +147,15 @@ static inline void adc_ll_dig_convert_limit_disable(void)
static inline void adc_ll_dig_set_convert_mode(adc_ll_convert_mode_t mode)
{
if (mode == ADC_CONV_SINGLE_UNIT_1) {
SYSCON.saradc_ctrl.work_mode = 0;
SYSCON.saradc_ctrl.sar_sel = 0;
APB_CTRL.saradc_ctrl.work_mode = 0;
APB_CTRL.saradc_ctrl.sar_sel = 0;
} else if (mode == ADC_CONV_SINGLE_UNIT_2) {
SYSCON.saradc_ctrl.work_mode = 0;
SYSCON.saradc_ctrl.sar_sel = 1;
APB_CTRL.saradc_ctrl.work_mode = 0;
APB_CTRL.saradc_ctrl.sar_sel = 1;
} else if (mode == ADC_CONV_BOTH_UNIT) {
SYSCON.saradc_ctrl.work_mode = 1;
APB_CTRL.saradc_ctrl.work_mode = 1;
} else if (mode == ADC_CONV_ALTER_UNIT) {
SYSCON.saradc_ctrl.work_mode = 2;
APB_CTRL.saradc_ctrl.work_mode = 2;
}
}
@ -166,7 +167,7 @@ static inline void adc_ll_dig_set_convert_mode(adc_ll_convert_mode_t mode)
static inline void adc_ll_dig_set_data_source(adc_i2s_source_t src)
{
/* 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix */
SYSCON.saradc_ctrl.data_to_i2s = src;
APB_CTRL.saradc_ctrl.data_to_i2s = src;
}
/**
@ -181,9 +182,9 @@ static inline void adc_ll_dig_set_data_source(adc_i2s_source_t src)
static inline void adc_ll_set_pattern_table_len(adc_ll_num_t adc_n, uint32_t patt_len)
{
if (adc_n == ADC_NUM_1) {
SYSCON.saradc_ctrl.sar1_patt_len = patt_len - 1;
APB_CTRL.saradc_ctrl.sar1_patt_len = patt_len - 1;
} else { // adc_n == ADC_NUM_2
SYSCON.saradc_ctrl.sar2_patt_len = patt_len - 1;
APB_CTRL.saradc_ctrl.sar2_patt_len = patt_len - 1;
}
}
@ -202,15 +203,15 @@ static inline void adc_ll_set_pattern_table(adc_ll_num_t adc_n, uint32_t pattern
uint32_t tab;
uint8_t *arg;
if (adc_n == ADC_NUM_1) {
tab = SYSCON.saradc_sar1_patt_tab[pattern_index / 4];
tab = *(uint32_t *)(&APB_CTRL.saradc_sar1_patt_tab1 + pattern_index / 4);
arg = (uint8_t *)&tab;
arg[pattern_index % 4] = pattern.val;
SYSCON.saradc_sar1_patt_tab[pattern_index / 4] = tab;
*(uint32_t *)(&APB_CTRL.saradc_sar1_patt_tab1 + pattern_index / 4) = tab;
} else { // adc_n == ADC_NUM_2
tab = SYSCON.saradc_sar2_patt_tab[pattern_index / 4];
tab = *(uint32_t *)(&APB_CTRL.saradc_sar2_patt_tab1 + pattern_index / 4);
arg = (uint8_t *)&tab;
arg[pattern_index % 4] = pattern.val;
SYSCON.saradc_sar2_patt_tab[pattern_index / 4] = tab;
*(uint32_t *)(&APB_CTRL.saradc_sar2_patt_tab1 + pattern_index / 4) = tab;
}
}
@ -385,7 +386,7 @@ static inline adc_ll_power_t adc_ll_get_power_manage(void)
static inline void adc_ll_set_clk_div(uint32_t div)
{
/* ADC clock devided from APB clk, e.g. 80 / 2 = 40Mhz, */
SYSCON.saradc_ctrl.sar_clk_div = div;
APB_CTRL.saradc_ctrl.sar_clk_div = div;
}
/**

11
components/soc/esp32s2beta/include/hal/gpspi_flash_ll.h
View File

@ -33,8 +33,7 @@
#define gpspi_flash_ll_get_hw(host_id) (((host_id)==SPI2_HOST ? &GPSPI2 \
: ((host_id)==SPI3_HOST ? &GPSPI3 \
: ((host_id)==SPI4_HOST ? &GPSPI4 \
: ({abort();(spi_dev_t*)0;})))))
: ({abort();(spi_dev_t*)0;}))))
typedef typeof(GPSPI2.clock) gpspi_flash_ll_clock_reg_t;
@ -196,7 +195,7 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod
ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M);
user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M);
ctrl.val |= SPI_FAST_RD_MODE_M;
// ctrl.val |= SPI_FAST_RD_MODE_M;
switch (read_mode) {
case SPI_FLASH_FASTRD:
//the default option
@ -219,9 +218,9 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod
ctrl.fread_dual = 1;
user.fwrite_dual = 1;
break;
case SPI_FLASH_SLOWRD:
ctrl.fast_rd_mode = 0;
break;
// case SPI_FLASH_SLOWRD:
// ctrl.fast_rd_mode = 0;
// break;
default:
abort();
}

25
components/soc/esp32s2beta/include/hal/spi_ll.h
View File

@ -22,12 +22,12 @@
#pragma once
#include "hal/hal_defs.h"
#include "soc/spi_periph.h"
#include "esp32/rom/lldesc.h"
#include <string.h>
#include <esp_types.h>
#include <stdlib.h> //for abs()
#include <string.h>
#include "hal/hal_defs.h"
#include "esp_types.h"
#include "soc/spi_periph.h"
#include "esp32s2beta/rom/lldesc.h"
/// Registers to reset during initialization. Don't use in app.
#define SPI_LL_RST_MASK (SPI_OUT_RST | SPI_IN_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST)
@ -36,7 +36,7 @@
/// Swap the bit order to its correct place to send
#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)data<<(32-len))
#define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):((ID)==1? &GPSPI2 : ((ID)==2? &GPSPI3: &GPSPI4)))
#define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):((ID)==1? &GPSPI2 : &GPSPI3))
/**
* The data structure holding calculated clock configuration. Since the
@ -249,7 +249,7 @@ static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw)
*/
static inline void spi_ll_disable_int(spi_dev_t *hw)
{
hw->slave.int_trans_done_en = 0;
hw->slave.trans_inten = 0;
}
/**
@ -280,7 +280,7 @@ static inline void spi_ll_set_int_stat(spi_dev_t *hw)
*/
static inline void spi_ll_enable_int(spi_dev_t *hw)
{
hw->slave.int_trans_done_en = 1;
hw->slave.trans_inten = 1;
}
/**
@ -291,17 +291,16 @@ static inline void spi_ll_enable_int(spi_dev_t *hw)
*/
static inline void spi_ll_slave_set_int_type(spi_dev_t *hw, spi_ll_slave_intr_type int_type)
{
switch (int_type)
{
switch (int_type) {
case SPI_LL_INT_TYPE_SEG:
hw->dma_int_ena.in_suc_eof = 1;
hw->dma_int_ena.out_total_eof = 1;
hw->slave.int_trans_done_en = 0;
hw->slave.trans_inten = 0;
break;
default:
hw->dma_int_ena.in_suc_eof = 0;
hw->dma_int_ena.out_total_eof = 0;
hw->slave.int_trans_done_en = 1;
hw->slave.trans_inten = 1;
}
}
@ -687,7 +686,7 @@ static inline void spi_ll_master_set_cs_setup(spi_dev_t *hw, uint8_t setup)
*/
static inline void spi_ll_slave_set_seg_en(spi_dev_t *hw, bool en)
{
hw->dma_conf.slv_rx_seg_trans_en = en;
hw->dma_conf.dma_seg_trans_en = en;
}
/*------------------------------------------------------------------------------

454
components/soc/esp32s2beta/include/soc/apb_ctrl_reg.h
View File

@ -49,7 +49,7 @@ extern "C" {
#define APB_CTRL_CLK_320M_EN_M (BIT(10))
#define APB_CTRL_CLK_320M_EN_V 0x1
#define APB_CTRL_CLK_320M_EN_S 10
/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
/*description: */
#define APB_CTRL_PRE_DIV_CNT 0x000003FF
#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S))
@ -76,297 +76,7 @@ extern "C" {
#define APB_CTRL_XTAL_TICK_NUM_V 0xFF
#define APB_CTRL_XTAL_TICK_NUM_S 0
#define APB_CTRL_SARADC_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x008)
/* APB_CTRL_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
/*description: force option to xpd sar blocks*/
#define APB_CTRL_SARADC_XPD_SAR_FORCE 0x00000003
#define APB_CTRL_SARADC_XPD_SAR_FORCE_M ((APB_CTRL_SARADC_XPD_SAR_FORCE_V)<<(APB_CTRL_SARADC_XPD_SAR_FORCE_S))
#define APB_CTRL_SARADC_XPD_SAR_FORCE_V 0x3
#define APB_CTRL_SARADC_XPD_SAR_FORCE_S 27
/* APB_CTRL_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data
is from GPIO matrix*/
#define APB_CTRL_SARADC_DATA_TO_I2S (BIT(26))
#define APB_CTRL_SARADC_DATA_TO_I2S_M (BIT(26))
#define APB_CTRL_SARADC_DATA_TO_I2S_V 0x1
#define APB_CTRL_SARADC_DATA_TO_I2S_S 26
/* APB_CTRL_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data
in this case the resolution should not be larger than 11 bits.*/
#define APB_CTRL_SARADC_DATA_SAR_SEL (BIT(25))
#define APB_CTRL_SARADC_DATA_SAR_SEL_M (BIT(25))
#define APB_CTRL_SARADC_DATA_SAR_SEL_V 0x1
#define APB_CTRL_SARADC_DATA_SAR_SEL_S 25
/* APB_CTRL_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */
/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/
#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR (BIT(24))
#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24))
#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_V 0x1
#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_S 24
/* APB_CTRL_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/
#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR (BIT(23))
#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23))
#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_V 0x1
#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_S 23
/* APB_CTRL_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */
/*description: 0 ~ 15 means length 1 ~ 16*/
#define APB_CTRL_SARADC_SAR2_PATT_LEN 0x0000000F
#define APB_CTRL_SARADC_SAR2_PATT_LEN_M ((APB_CTRL_SARADC_SAR2_PATT_LEN_V)<<(APB_CTRL_SARADC_SAR2_PATT_LEN_S))
#define APB_CTRL_SARADC_SAR2_PATT_LEN_V 0xF
#define APB_CTRL_SARADC_SAR2_PATT_LEN_S 19
/* APB_CTRL_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */
/*description: 0 ~ 15 means length 1 ~ 16*/
#define APB_CTRL_SARADC_SAR1_PATT_LEN 0x0000000F
#define APB_CTRL_SARADC_SAR1_PATT_LEN_M ((APB_CTRL_SARADC_SAR1_PATT_LEN_V)<<(APB_CTRL_SARADC_SAR1_PATT_LEN_S))
#define APB_CTRL_SARADC_SAR1_PATT_LEN_V 0xF
#define APB_CTRL_SARADC_SAR1_PATT_LEN_S 15
/* APB_CTRL_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
/*description: SAR clock divider*/
#define APB_CTRL_SARADC_SAR_CLK_DIV 0x000000FF
#define APB_CTRL_SARADC_SAR_CLK_DIV_M ((APB_CTRL_SARADC_SAR_CLK_DIV_V)<<(APB_CTRL_SARADC_SAR_CLK_DIV_S))
#define APB_CTRL_SARADC_SAR_CLK_DIV_V 0xFF
#define APB_CTRL_SARADC_SAR_CLK_DIV_S 7
/* APB_CTRL_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_SARADC_SAR_CLK_GATED (BIT(6))
#define APB_CTRL_SARADC_SAR_CLK_GATED_M (BIT(6))
#define APB_CTRL_SARADC_SAR_CLK_GATED_V 0x1
#define APB_CTRL_SARADC_SAR_CLK_GATED_S 6
/* APB_CTRL_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */
/*description: 0: SAR1 1: SAR2 only work for single SAR mode*/
#define APB_CTRL_SARADC_SAR_SEL (BIT(5))
#define APB_CTRL_SARADC_SAR_SEL_M (BIT(5))
#define APB_CTRL_SARADC_SAR_SEL_V 0x1
#define APB_CTRL_SARADC_SAR_SEL_S 5
/* APB_CTRL_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
/*description: 0: single mode 1: double mode 2: alternate mode*/
#define APB_CTRL_SARADC_WORK_MODE 0x00000003
#define APB_CTRL_SARADC_WORK_MODE_M ((APB_CTRL_SARADC_WORK_MODE_V)<<(APB_CTRL_SARADC_WORK_MODE_S))
#define APB_CTRL_SARADC_WORK_MODE_V 0x3
#define APB_CTRL_SARADC_WORK_MODE_S 3
/* APB_CTRL_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
/*description: */
#define APB_CTRL_SARADC_START (BIT(1))
#define APB_CTRL_SARADC_START_M (BIT(1))
#define APB_CTRL_SARADC_START_V 0x1
#define APB_CTRL_SARADC_START_S 1
/* APB_CTRL_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
#define APB_CTRL_SARADC_START_FORCE (BIT(0))
#define APB_CTRL_SARADC_START_FORCE_M (BIT(0))
#define APB_CTRL_SARADC_START_FORCE_V 0x1
#define APB_CTRL_SARADC_START_FORCE_S 0
#define APB_CTRL_SARADC_CTRL2_REG (DR_REG_APB_CTRL_BASE + 0x00C)
/* APB_CTRL_SARADC_TIMER_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
/*description: to enable saradc timer trigger*/
#define APB_CTRL_SARADC_TIMER_EN (BIT(20))
#define APB_CTRL_SARADC_TIMER_EN_M (BIT(20))
#define APB_CTRL_SARADC_TIMER_EN_V 0x1
#define APB_CTRL_SARADC_TIMER_EN_S 20
/* APB_CTRL_SARADC_TIMER_TARGET : R/W ;bitpos:[19:12] ;default: 8'd10 ; */
/*description: to set saradc timer target*/
#define APB_CTRL_SARADC_TIMER_TARGET 0x000000FF
#define APB_CTRL_SARADC_TIMER_TARGET_M ((APB_CTRL_SARADC_TIMER_TARGET_V)<<(APB_CTRL_SARADC_TIMER_TARGET_S))
#define APB_CTRL_SARADC_TIMER_TARGET_V 0xFF
#define APB_CTRL_SARADC_TIMER_TARGET_S 12
/* APB_CTRL_SARADC_TIMER_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
/*description: 1: select saradc timer 0: i2s_ws trigger*/
#define APB_CTRL_SARADC_TIMER_SEL (BIT(11))
#define APB_CTRL_SARADC_TIMER_SEL_M (BIT(11))
#define APB_CTRL_SARADC_TIMER_SEL_V 0x1
#define APB_CTRL_SARADC_TIMER_SEL_S 11
/* APB_CTRL_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/
#define APB_CTRL_SARADC_SAR2_INV (BIT(10))
#define APB_CTRL_SARADC_SAR2_INV_M (BIT(10))
#define APB_CTRL_SARADC_SAR2_INV_V 0x1
#define APB_CTRL_SARADC_SAR2_INV_S 10
/* APB_CTRL_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/
#define APB_CTRL_SARADC_SAR1_INV (BIT(9))
#define APB_CTRL_SARADC_SAR1_INV_M (BIT(9))
#define APB_CTRL_SARADC_SAR1_INV_V 0x1
#define APB_CTRL_SARADC_SAR1_INV_S 9
/* APB_CTRL_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
/*description: max conversion number*/
#define APB_CTRL_SARADC_MAX_MEAS_NUM 0x000000FF
#define APB_CTRL_SARADC_MAX_MEAS_NUM_M ((APB_CTRL_SARADC_MAX_MEAS_NUM_V)<<(APB_CTRL_SARADC_MAX_MEAS_NUM_S))
#define APB_CTRL_SARADC_MAX_MEAS_NUM_V 0xFF
#define APB_CTRL_SARADC_MAX_MEAS_NUM_S 1
/* APB_CTRL_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
#define APB_CTRL_SARADC_MEAS_NUM_LIMIT (BIT(0))
#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_M (BIT(0))
#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_V 0x1
#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_S 0
#define APB_CTRL_SARADC_FSM_REG (DR_REG_APB_CTRL_BASE + 0x010)
/* APB_CTRL_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */
/*description: sample cycles*/
#define APB_CTRL_SARADC_SAMPLE_CYCLE 0x000000FF
#define APB_CTRL_SARADC_SAMPLE_CYCLE_M ((APB_CTRL_SARADC_SAMPLE_CYCLE_V)<<(APB_CTRL_SARADC_SAMPLE_CYCLE_S))
#define APB_CTRL_SARADC_SAMPLE_CYCLE_V 0xFF
#define APB_CTRL_SARADC_SAMPLE_CYCLE_S 24
/* APB_CTRL_SARADC_SAMPLE_NUM : R/W ;bitpos:[23:16] ;default: 8'd0 ; */
/*description: sample number*/
#define APB_CTRL_SARADC_SAMPLE_NUM 0x000000FF
#define APB_CTRL_SARADC_SAMPLE_NUM_M ((APB_CTRL_SARADC_SAMPLE_NUM_V)<<(APB_CTRL_SARADC_SAMPLE_NUM_S))
#define APB_CTRL_SARADC_SAMPLE_NUM_V 0xFF
#define APB_CTRL_SARADC_SAMPLE_NUM_S 16
#define APB_CTRL_SARADC_FSM_WAIT_REG (DR_REG_APB_CTRL_BASE + 0x014)
/* APB_CTRL_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
/*description: */
#define APB_CTRL_SARADC_STANDBY_WAIT 0x000000FF
#define APB_CTRL_SARADC_STANDBY_WAIT_M ((APB_CTRL_SARADC_STANDBY_WAIT_V)<<(APB_CTRL_SARADC_STANDBY_WAIT_S))
#define APB_CTRL_SARADC_STANDBY_WAIT_V 0xFF
#define APB_CTRL_SARADC_STANDBY_WAIT_S 16
/* APB_CTRL_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
/*description: */
#define APB_CTRL_SARADC_RSTB_WAIT 0x000000FF
#define APB_CTRL_SARADC_RSTB_WAIT_M ((APB_CTRL_SARADC_RSTB_WAIT_V)<<(APB_CTRL_SARADC_RSTB_WAIT_S))
#define APB_CTRL_SARADC_RSTB_WAIT_V 0xFF
#define APB_CTRL_SARADC_RSTB_WAIT_S 8
/* APB_CTRL_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
/*description: */
#define APB_CTRL_SARADC_XPD_WAIT 0x000000FF
#define APB_CTRL_SARADC_XPD_WAIT_M ((APB_CTRL_SARADC_XPD_WAIT_V)<<(APB_CTRL_SARADC_XPD_WAIT_S))
#define APB_CTRL_SARADC_XPD_WAIT_V 0xFF
#define APB_CTRL_SARADC_XPD_WAIT_S 0
#define APB_CTRL_SARADC_SAR1_STATUS_REG (DR_REG_APB_CTRL_BASE + 0x018)
/* APB_CTRL_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define APB_CTRL_SARADC_SAR1_STATUS 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR1_STATUS_M ((APB_CTRL_SARADC_SAR1_STATUS_V)<<(APB_CTRL_SARADC_SAR1_STATUS_S))
#define APB_CTRL_SARADC_SAR1_STATUS_V 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR1_STATUS_S 0
#define APB_CTRL_SARADC_SAR2_STATUS_REG (DR_REG_APB_CTRL_BASE + 0x01C)
/* APB_CTRL_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define APB_CTRL_SARADC_SAR2_STATUS 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR2_STATUS_M ((APB_CTRL_SARADC_SAR2_STATUS_V)<<(APB_CTRL_SARADC_SAR2_STATUS_S))
#define APB_CTRL_SARADC_SAR2_STATUS_V 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR2_STATUS_S 0
#define APB_CTRL_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_CTRL_BASE + 0x020)
/* APB_CTRL_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/
#define APB_CTRL_SARADC_SAR1_PATT_TAB1 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR1_PATT_TAB1_M ((APB_CTRL_SARADC_SAR1_PATT_TAB1_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB1_S))
#define APB_CTRL_SARADC_SAR1_PATT_TAB1_V 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR1_PATT_TAB1_S 0
#define APB_CTRL_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_CTRL_BASE + 0x024)
/* APB_CTRL_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/
#define APB_CTRL_SARADC_SAR1_PATT_TAB2 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR1_PATT_TAB2_M ((APB_CTRL_SARADC_SAR1_PATT_TAB2_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB2_S))
#define APB_CTRL_SARADC_SAR1_PATT_TAB2_V 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR1_PATT_TAB2_S 0
#define APB_CTRL_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_CTRL_BASE + 0x028)
/* APB_CTRL_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/
#define APB_CTRL_SARADC_SAR1_PATT_TAB3 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR1_PATT_TAB3_M ((APB_CTRL_SARADC_SAR1_PATT_TAB3_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB3_S))
#define APB_CTRL_SARADC_SAR1_PATT_TAB3_V 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR1_PATT_TAB3_S 0
#define APB_CTRL_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_CTRL_BASE + 0x02C)
/* APB_CTRL_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/
#define APB_CTRL_SARADC_SAR1_PATT_TAB4 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR1_PATT_TAB4_M ((APB_CTRL_SARADC_SAR1_PATT_TAB4_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB4_S))
#define APB_CTRL_SARADC_SAR1_PATT_TAB4_V 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR1_PATT_TAB4_S 0
#define APB_CTRL_SARADC_SAR2_PATT_TAB1_REG (DR_REG_APB_CTRL_BASE + 0x030)
/* APB_CTRL_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/
#define APB_CTRL_SARADC_SAR2_PATT_TAB1 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR2_PATT_TAB1_M ((APB_CTRL_SARADC_SAR2_PATT_TAB1_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB1_S))
#define APB_CTRL_SARADC_SAR2_PATT_TAB1_V 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR2_PATT_TAB1_S 0
#define APB_CTRL_SARADC_SAR2_PATT_TAB2_REG (DR_REG_APB_CTRL_BASE + 0x034)
/* APB_CTRL_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/
#define APB_CTRL_SARADC_SAR2_PATT_TAB2 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR2_PATT_TAB2_M ((APB_CTRL_SARADC_SAR2_PATT_TAB2_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB2_S))
#define APB_CTRL_SARADC_SAR2_PATT_TAB2_V 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR2_PATT_TAB2_S 0
#define APB_CTRL_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_CTRL_BASE + 0x038)
/* APB_CTRL_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/
#define APB_CTRL_SARADC_SAR2_PATT_TAB3 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR2_PATT_TAB3_M ((APB_CTRL_SARADC_SAR2_PATT_TAB3_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB3_S))
#define APB_CTRL_SARADC_SAR2_PATT_TAB3_V 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR2_PATT_TAB3_S 0
#define APB_CTRL_SARADC_SAR2_PATT_TAB4_REG (DR_REG_APB_CTRL_BASE + 0x03C)
/* APB_CTRL_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/
#define APB_CTRL_SARADC_SAR2_PATT_TAB4 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR2_PATT_TAB4_M ((APB_CTRL_SARADC_SAR2_PATT_TAB4_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB4_S))
#define APB_CTRL_SARADC_SAR2_PATT_TAB4_V 0xFFFFFFFF
#define APB_CTRL_SARADC_SAR2_PATT_TAB4_S 0
#define APB_CTRL_ADC_ARB_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x040)
/* APB_CTRL_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: adc2 arbiter uses fixed priority*/
#define APB_CTRL_ADC_ARB_FIX_PRIORITY (BIT(12))
#define APB_CTRL_ADC_ARB_FIX_PRIORITY_M (BIT(12))
#define APB_CTRL_ADC_ARB_FIX_PRIORITY_V 0x1
#define APB_CTRL_ADC_ARB_FIX_PRIORITY_S 12
/* APB_CTRL_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */
/*description: Set adc2 arbiter wifi priority*/
#define APB_CTRL_ADC_ARB_WIFI_PRIORITY 0x00000003
#define APB_CTRL_ADC_ARB_WIFI_PRIORITY_M ((APB_CTRL_ADC_ARB_WIFI_PRIORITY_V)<<(APB_CTRL_ADC_ARB_WIFI_PRIORITY_S))
#define APB_CTRL_ADC_ARB_WIFI_PRIORITY_V 0x3
#define APB_CTRL_ADC_ARB_WIFI_PRIORITY_S 10
/* APB_CTRL_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */
/*description: Set adc2 arbiter rtc priority*/
#define APB_CTRL_ADC_ARB_RTC_PRIORITY 0x00000003
#define APB_CTRL_ADC_ARB_RTC_PRIORITY_M ((APB_CTRL_ADC_ARB_RTC_PRIORITY_V)<<(APB_CTRL_ADC_ARB_RTC_PRIORITY_S))
#define APB_CTRL_ADC_ARB_RTC_PRIORITY_V 0x3
#define APB_CTRL_ADC_ARB_RTC_PRIORITY_S 8
/* APB_CTRL_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
/*description: Set adc2 arbiter apb priority*/
#define APB_CTRL_ADC_ARB_APB_PRIORITY 0x00000003
#define APB_CTRL_ADC_ARB_APB_PRIORITY_M ((APB_CTRL_ADC_ARB_APB_PRIORITY_V)<<(APB_CTRL_ADC_ARB_APB_PRIORITY_S))
#define APB_CTRL_ADC_ARB_APB_PRIORITY_V 0x3
#define APB_CTRL_ADC_ARB_APB_PRIORITY_S 6
/* APB_CTRL_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: adc2 arbiter force grant*/
#define APB_CTRL_ADC_ARB_GRANT_FORCE (BIT(5))
#define APB_CTRL_ADC_ARB_GRANT_FORCE_M (BIT(5))
#define APB_CTRL_ADC_ARB_GRANT_FORCE_V 0x1
#define APB_CTRL_ADC_ARB_GRANT_FORCE_S 5
/* APB_CTRL_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enable wifi controller*/
#define APB_CTRL_ADC_ARB_WIFI_FORCE (BIT(4))
#define APB_CTRL_ADC_ARB_WIFI_FORCE_M (BIT(4))
#define APB_CTRL_ADC_ARB_WIFI_FORCE_V 0x1
#define APB_CTRL_ADC_ARB_WIFI_FORCE_S 4
/* APB_CTRL_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enable rtc controller*/
#define APB_CTRL_ADC_ARB_RTC_FORCE (BIT(3))
#define APB_CTRL_ADC_ARB_RTC_FORCE_M (BIT(3))
#define APB_CTRL_ADC_ARB_RTC_FORCE_V 0x1
#define APB_CTRL_ADC_ARB_RTC_FORCE_S 3
/* APB_CTRL_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enable apb controller*/
#define APB_CTRL_ADC_ARB_APB_FORCE (BIT(2))
#define APB_CTRL_ADC_ARB_APB_FORCE_M (BIT(2))
#define APB_CTRL_ADC_ARB_APB_FORCE_V 0x1
#define APB_CTRL_ADC_ARB_APB_FORCE_S 2
#define APB_CTRL_CLK_OUT_EN_REG (DR_REG_APB_CTRL_BASE + 0x044)
#define APB_CTRL_CLK_OUT_EN_REG (DR_REG_APB_CTRL_BASE + 0x008)
/* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK_XTAL_OEN (BIT(10))
@ -434,25 +144,7 @@ extern "C" {
#define APB_CTRL_CLK20_OEN_V 0x1
#define APB_CTRL_CLK20_OEN_S 0
#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_APB_CTRL_BASE + 0x048)
/* APB_CTRL_SPI_PRIOR : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_SPI_PRIOR (BIT(13))
#define APB_CTRL_SPI_PRIOR_M (BIT(13))
#define APB_CTRL_SPI_PRIOR_V 0x1
#define APB_CTRL_SPI_PRIOR_S 13
/* APB_CTRL_SPI1_HOLD : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_SPI1_HOLD (BIT(9))
#define APB_CTRL_SPI1_HOLD_M (BIT(9))
#define APB_CTRL_SPI1_HOLD_V 0x1
#define APB_CTRL_SPI1_HOLD_S 9
/* APB_CTRL_SPI0_HOLD : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_SPI0_HOLD (BIT(8))
#define APB_CTRL_SPI0_HOLD_M (BIT(8))
#define APB_CTRL_SPI0_HOLD_V 0x1
#define APB_CTRL_SPI0_HOLD_S 8
#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_APB_CTRL_BASE + 0x00C)
/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define APB_CTRL_PERI_IO_SWAP 0x000000FF
@ -460,7 +152,7 @@ extern "C" {
#define APB_CTRL_PERI_IO_SWAP_V 0xFF
#define APB_CTRL_PERI_IO_SWAP_S 0
#define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_APB_CTRL_BASE + 0x04C)
#define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_APB_CTRL_BASE + 0x010)
/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_EXT_MEM_PMS_LOCK (BIT(0))
@ -468,7 +160,7 @@ extern "C" {
#define APB_CTRL_EXT_MEM_PMS_LOCK_V 0x1
#define APB_CTRL_EXT_MEM_PMS_LOCK_S 0
#define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x050)
#define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x014)
/* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_FLASH_ACE0_ATTR 0x00000007
@ -476,7 +168,7 @@ extern "C" {
#define APB_CTRL_FLASH_ACE0_ATTR_V 0x7
#define APB_CTRL_FLASH_ACE0_ATTR_S 0
#define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x054)
#define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x018)
/* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_FLASH_ACE1_ATTR 0x00000007
@ -484,7 +176,7 @@ extern "C" {
#define APB_CTRL_FLASH_ACE1_ATTR_V 0x7
#define APB_CTRL_FLASH_ACE1_ATTR_S 0
#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x058)
#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x01C)
/* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_FLASH_ACE2_ATTR 0x00000007
@ -492,7 +184,7 @@ extern "C" {
#define APB_CTRL_FLASH_ACE2_ATTR_V 0x7
#define APB_CTRL_FLASH_ACE2_ATTR_S 0
#define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x05C)
#define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x020)
/* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_FLASH_ACE3_ATTR 0x00000007
@ -500,7 +192,7 @@ extern "C" {
#define APB_CTRL_FLASH_ACE3_ATTR_V 0x7
#define APB_CTRL_FLASH_ACE3_ATTR_S 0
#define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x060)
#define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x024)
/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_FLASH_ACE0_ADDR_S 0xFFFFFFFF
@ -508,7 +200,7 @@ extern "C" {
#define APB_CTRL_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE0_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x064)
#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x028)
/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE1_ADDR_S 0xFFFFFFFF
@ -516,7 +208,7 @@ extern "C" {
#define APB_CTRL_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE1_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x068)
#define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x02C)
/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE2_ADDR_S 0xFFFFFFFF
@ -524,7 +216,7 @@ extern "C" {
#define APB_CTRL_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE2_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x06C)
#define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x030)
/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE3_ADDR_S 0xFFFFFFFF
@ -532,7 +224,7 @@ extern "C" {
#define APB_CTRL_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE3_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x070)
#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x034)
/* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE0_SIZE 0x0000FFFF
@ -540,7 +232,7 @@ extern "C" {
#define APB_CTRL_FLASH_ACE0_SIZE_V 0xFFFF
#define APB_CTRL_FLASH_ACE0_SIZE_S 0
#define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x074)
#define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x038)
/* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE1_SIZE 0x0000FFFF
@ -548,7 +240,7 @@ extern "C" {
#define APB_CTRL_FLASH_ACE1_SIZE_V 0xFFFF
#define APB_CTRL_FLASH_ACE1_SIZE_S 0
#define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x078)
#define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x03C)
/* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE2_SIZE 0x0000FFFF
@ -556,7 +248,7 @@ extern "C" {
#define APB_CTRL_FLASH_ACE2_SIZE_V 0xFFFF
#define APB_CTRL_FLASH_ACE2_SIZE_S 0
#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x07C)
#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x040)
/* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_FLASH_ACE3_SIZE 0x0000FFFF
@ -564,7 +256,7 @@ extern "C" {
#define APB_CTRL_FLASH_ACE3_SIZE_V 0xFFFF
#define APB_CTRL_FLASH_ACE3_SIZE_S 0
#define APB_CTRL_SRAM_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x080)
#define APB_CTRL_SRAM_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x044)
/* APB_CTRL_SRAM_ACE0_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_SRAM_ACE0_ATTR 0x00000007
@ -572,7 +264,7 @@ extern "C" {
#define APB_CTRL_SRAM_ACE0_ATTR_V 0x7
#define APB_CTRL_SRAM_ACE0_ATTR_S 0
#define APB_CTRL_SRAM_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x084)
#define APB_CTRL_SRAM_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x048)
/* APB_CTRL_SRAM_ACE1_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_SRAM_ACE1_ATTR 0x00000007
@ -580,7 +272,7 @@ extern "C" {
#define APB_CTRL_SRAM_ACE1_ATTR_V 0x7
#define APB_CTRL_SRAM_ACE1_ATTR_S 0
#define APB_CTRL_SRAM_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x088)
#define APB_CTRL_SRAM_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x04C)
/* APB_CTRL_SRAM_ACE2_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_SRAM_ACE2_ATTR 0x00000007
@ -588,7 +280,7 @@ extern "C" {
#define APB_CTRL_SRAM_ACE2_ATTR_V 0x7
#define APB_CTRL_SRAM_ACE2_ATTR_S 0
#define APB_CTRL_SRAM_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x08C)
#define APB_CTRL_SRAM_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x050)
/* APB_CTRL_SRAM_ACE3_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define APB_CTRL_SRAM_ACE3_ATTR 0x00000007
@ -596,7 +288,7 @@ extern "C" {
#define APB_CTRL_SRAM_ACE3_ATTR_V 0x7
#define APB_CTRL_SRAM_ACE3_ATTR_S 0
#define APB_CTRL_SRAM_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x090)
#define APB_CTRL_SRAM_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x054)
/* APB_CTRL_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_SRAM_ACE0_ADDR_S 0xFFFFFFFF
@ -604,7 +296,7 @@ extern "C" {
#define APB_CTRL_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE0_ADDR_S_S 0
#define APB_CTRL_SRAM_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x094)
#define APB_CTRL_SRAM_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x058)
/* APB_CTRL_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
/*description: */
#define APB_CTRL_SRAM_ACE1_ADDR_S 0xFFFFFFFF
@ -612,7 +304,7 @@ extern "C" {
#define APB_CTRL_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE1_ADDR_S_S 0
#define APB_CTRL_SRAM_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x098)
#define APB_CTRL_SRAM_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x05C)
/* APB_CTRL_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
/*description: */
#define APB_CTRL_SRAM_ACE2_ADDR_S 0xFFFFFFFF
@ -620,7 +312,7 @@ extern "C" {
#define APB_CTRL_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE2_ADDR_S_S 0
#define APB_CTRL_SRAM_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x09C)
#define APB_CTRL_SRAM_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x060)
/* APB_CTRL_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
/*description: */
#define APB_CTRL_SRAM_ACE3_ADDR_S 0xFFFFFFFF
@ -628,7 +320,7 @@ extern "C" {
#define APB_CTRL_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE3_ADDR_S_S 0
#define APB_CTRL_SRAM_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x0A0)
#define APB_CTRL_SRAM_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x064)
/* APB_CTRL_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_SRAM_ACE0_SIZE 0x0000FFFF
@ -636,7 +328,7 @@ extern "C" {
#define APB_CTRL_SRAM_ACE0_SIZE_V 0xFFFF
#define APB_CTRL_SRAM_ACE0_SIZE_S 0
#define APB_CTRL_SRAM_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x0A4)
#define APB_CTRL_SRAM_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x068)
/* APB_CTRL_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_SRAM_ACE1_SIZE 0x0000FFFF
@ -644,7 +336,7 @@ extern "C" {
#define APB_CTRL_SRAM_ACE1_SIZE_V 0xFFFF
#define APB_CTRL_SRAM_ACE1_SIZE_S 0
#define APB_CTRL_SRAM_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x0A8)
#define APB_CTRL_SRAM_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x06C)
/* APB_CTRL_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_SRAM_ACE2_SIZE 0x0000FFFF
@ -652,7 +344,7 @@ extern "C" {
#define APB_CTRL_SRAM_ACE2_SIZE_V 0xFFFF
#define APB_CTRL_SRAM_ACE2_SIZE_S 0
#define APB_CTRL_SRAM_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x0AC)
#define APB_CTRL_SRAM_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x070)
/* APB_CTRL_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define APB_CTRL_SRAM_ACE3_SIZE 0x0000FFFF
@ -660,63 +352,35 @@ extern "C" {
#define APB_CTRL_SRAM_ACE3_SIZE_V 0xFFFF
#define APB_CTRL_SRAM_ACE3_SIZE_S 0
#define APB_CTRL_SPI0_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x0B0)
/* APB_CTRL_SPI0_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
#define APB_CTRL_SPI_MEM_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x074)
/* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
/*description: */
#define APB_CTRL_SPI0_REJECT_CDE 0x0000001F
#define APB_CTRL_SPI0_REJECT_CDE_M ((APB_CTRL_SPI0_REJECT_CDE_V)<<(APB_CTRL_SPI0_REJECT_CDE_S))
#define APB_CTRL_SPI0_REJECT_CDE_V 0x1F
#define APB_CTRL_SPI0_REJECT_CDE_S 2
/* APB_CTRL_SPI0_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
#define APB_CTRL_SPI_MEM_REJECT_CDE 0x0000001F
#define APB_CTRL_SPI_MEM_REJECT_CDE_M ((APB_CTRL_SPI_MEM_REJECT_CDE_V)<<(APB_CTRL_SPI_MEM_REJECT_CDE_S))
#define APB_CTRL_SPI_MEM_REJECT_CDE_V 0x1F
#define APB_CTRL_SPI_MEM_REJECT_CDE_S 2
/* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_SPI0_REJECT_CLR (BIT(1))
#define APB_CTRL_SPI0_REJECT_CLR_M (BIT(1))
#define APB_CTRL_SPI0_REJECT_CLR_V 0x1
#define APB_CTRL_SPI0_REJECT_CLR_S 1
/* APB_CTRL_SPI0_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
#define APB_CTRL_SPI_MEM_REJECT_CLR (BIT(1))
#define APB_CTRL_SPI_MEM_REJECT_CLR_M (BIT(1))
#define APB_CTRL_SPI_MEM_REJECT_CLR_V 0x1
#define APB_CTRL_SPI_MEM_REJECT_CLR_S 1
/* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_SPI0_REJECT_INT (BIT(0))
#define APB_CTRL_SPI0_REJECT_INT_M (BIT(0))
#define APB_CTRL_SPI0_REJECT_INT_V 0x1
#define APB_CTRL_SPI0_REJECT_INT_S 0
#define APB_CTRL_SPI_MEM_REJECT_INT (BIT(0))
#define APB_CTRL_SPI_MEM_REJECT_INT_M (BIT(0))
#define APB_CTRL_SPI_MEM_REJECT_INT_V 0x1
#define APB_CTRL_SPI_MEM_REJECT_INT_S 0
#define APB_CTRL_SPI0_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x0B4)
/* APB_CTRL_SPI0_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x078)
/* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_SPI0_REJECT_ADDR 0xFFFFFFFF
#define APB_CTRL_SPI0_REJECT_ADDR_M ((APB_CTRL_SPI0_REJECT_ADDR_V)<<(APB_CTRL_SPI0_REJECT_ADDR_S))
#define APB_CTRL_SPI0_REJECT_ADDR_V 0xFFFFFFFF
#define APB_CTRL_SPI0_REJECT_ADDR_S 0
#define APB_CTRL_SPI_MEM_REJECT_ADDR 0xFFFFFFFF
#define APB_CTRL_SPI_MEM_REJECT_ADDR_M ((APB_CTRL_SPI_MEM_REJECT_ADDR_V)<<(APB_CTRL_SPI_MEM_REJECT_ADDR_S))
#define APB_CTRL_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF
#define APB_CTRL_SPI_MEM_REJECT_ADDR_S 0
#define APB_CTRL_SPI1_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x0B8)
/* APB_CTRL_SPI1_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
/*description: */
#define APB_CTRL_SPI1_REJECT_CDE 0x0000001F
#define APB_CTRL_SPI1_REJECT_CDE_M ((APB_CTRL_SPI1_REJECT_CDE_V)<<(APB_CTRL_SPI1_REJECT_CDE_S))
#define APB_CTRL_SPI1_REJECT_CDE_V 0x1F
#define APB_CTRL_SPI1_REJECT_CDE_S 2
/* APB_CTRL_SPI1_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_SPI1_REJECT_CLR (BIT(1))
#define APB_CTRL_SPI1_REJECT_CLR_M (BIT(1))
#define APB_CTRL_SPI1_REJECT_CLR_V 0x1
#define APB_CTRL_SPI1_REJECT_CLR_S 1
/* APB_CTRL_SPI1_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_SPI1_REJECT_INT (BIT(0))
#define APB_CTRL_SPI1_REJECT_INT_M (BIT(0))
#define APB_CTRL_SPI1_REJECT_INT_V 0x1
#define APB_CTRL_SPI1_REJECT_INT_S 0
#define APB_CTRL_SPI1_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x0BC)
/* APB_CTRL_SPI1_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_SPI1_REJECT_ADDR 0xFFFFFFFF
#define APB_CTRL_SPI1_REJECT_ADDR_M ((APB_CTRL_SPI1_REJECT_ADDR_V)<<(APB_CTRL_SPI1_REJECT_ADDR_S))
#define APB_CTRL_SPI1_REJECT_ADDR_V 0xFFFFFFFF
#define APB_CTRL_SPI1_REJECT_ADDR_S 0
#define APB_CTRL_SDIO_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x0C0)
#define APB_CTRL_SDIO_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x07C)
/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define APB_CTRL_SDIO_WIN_ACCESS_EN (BIT(0))
@ -724,7 +388,7 @@ extern "C" {
#define APB_CTRL_SDIO_WIN_ACCESS_EN_V 0x1
#define APB_CTRL_SDIO_WIN_ACCESS_EN_S 0
#define APB_CTRL_REDCY_SIG0_REG (DR_REG_APB_CTRL_BASE + 0x0C4)
#define APB_CTRL_REDCY_SIG0_REG (DR_REG_APB_CTRL_BASE + 0x080)
/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define APB_CTRL_REDCY_ANDOR (BIT(31))
@ -738,7 +402,7 @@ extern "C" {
#define APB_CTRL_REDCY_SIG0_V 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG0_S 0
#define APB_CTRL_REDCY_SIG1_REG (DR_REG_APB_CTRL_BASE + 0x0C8)
#define APB_CTRL_REDCY_SIG1_REG (DR_REG_APB_CTRL_BASE + 0x084)
/* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define APB_CTRL_REDCY_NANDOR (BIT(31))
@ -752,7 +416,7 @@ extern "C" {
#define APB_CTRL_REDCY_SIG1_V 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG1_S 0
#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0x0CC)
#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0x088)
/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_WIFI_BB_CFG 0xFFFFFFFF
@ -760,7 +424,7 @@ extern "C" {
#define APB_CTRL_WIFI_BB_CFG_V 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_S 0
#define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_APB_CTRL_BASE + 0x0D0)
#define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_APB_CTRL_BASE + 0x08C)
/* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_WIFI_BB_CFG_2 0xFFFFFFFF
@ -768,7 +432,7 @@ extern "C" {
#define APB_CTRL_WIFI_BB_CFG_2_V 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_2_S 0
#define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_APB_CTRL_BASE + 0x0D4)
#define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_APB_CTRL_BASE + 0x090)
/* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
/*description: */
#define APB_CTRL_WIFI_CLK_EN 0xFFFFFFFF
@ -776,7 +440,7 @@ extern "C" {
#define APB_CTRL_WIFI_CLK_EN_V 0xFFFFFFFF
#define APB_CTRL_WIFI_CLK_EN_S 0
#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_APB_CTRL_BASE + 0x0D8)
#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_APB_CTRL_BASE + 0x094)
/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_WIFI_RST 0xFFFFFFFF
@ -784,7 +448,7 @@ extern "C" {
#define APB_CTRL_WIFI_RST_V 0xFFFFFFFF
#define APB_CTRL_WIFI_RST_S 0
#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x0DC)
#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x098)
/* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_DC_MEM_FORCE_PD (BIT(5))
@ -823,7 +487,7 @@ extern "C" {
#define APB_CTRL_AGC_MEM_FORCE_PU_S 0
#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x3FC)
/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h18102500 ; */
/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h1906210 ; */
/*description: */
#define APB_CTRL_DATE 0xFFFFFFFF
#define APB_CTRL_DATE_M ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S))

10
components/soc/esp32s2beta/include/soc/apb_ctrl_struct.h
View File

@ -91,8 +91,14 @@ typedef volatile struct {
} saradc_fsm_wait;
uint32_t saradc_sar1_status; /**/
uint32_t saradc_sar2_status; /**/
uint32_t saradc_sar1_patt_tab[4]; /*item 0 ~ 15 for pattern table 1 (each item one byte)*/
uint32_t saradc_sar2_patt_tab[4]; /*item 0 ~ 15 for pattern table 2 (each item one byte)*/
uint32_t saradc_sar1_patt_tab1; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/
uint32_t saradc_sar1_patt_tab2; /*Item 4 ~ 7 for pattern table 1 (each item one byte)*/
uint32_t saradc_sar1_patt_tab3; /*Item 8 ~ 11 for pattern table 1 (each item one byte)*/
uint32_t saradc_sar1_patt_tab4; /*Item 12 ~ 15 for pattern table 1 (each item one byte)*/
uint32_t saradc_sar2_patt_tab1; /*item 0 ~ 3 for pattern table 2 (each item one byte)*/
uint32_t saradc_sar2_patt_tab2; /*Item 4 ~ 7 for pattern table 2 (each item one byte)*/
uint32_t saradc_sar2_patt_tab3; /*Item 8 ~ 11 for pattern table 2 (each item one byte)*/
uint32_t saradc_sar2_patt_tab4; /*Item 12 ~ 15 for pattern table 2 (each item one byte)*/
union {
struct {
uint32_t reserved0: 2;

618
components/soc/esp32s2beta/include/soc/apb_saradc_reg.h Normal file
View File

@ -0,0 +1,618 @@
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_APB_SARADC_REG_H_
#define _SOC_APB_SARADC_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x000)
/* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */
/*description: wait arbit signal stable after sar_done*/
#define APB_SARADC_WAIT_ARB_CYCLE 0x00000003
#define APB_SARADC_WAIT_ARB_CYCLE_M ((APB_SARADC_WAIT_ARB_CYCLE_V)<<(APB_SARADC_WAIT_ARB_CYCLE_S))
#define APB_SARADC_WAIT_ARB_CYCLE_V 0x3
#define APB_SARADC_WAIT_ARB_CYCLE_S 30
/* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
/*description: force option to xpd sar blocks*/
#define APB_SARADC_XPD_SAR_FORCE 0x00000003
#define APB_SARADC_XPD_SAR_FORCE_M ((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S))
#define APB_SARADC_XPD_SAR_FORCE_V 0x3
#define APB_SARADC_XPD_SAR_FORCE_S 27
/* APB_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data
is from GPIO matrix*/
#define APB_SARADC_DATA_TO_I2S (BIT(26))
#define APB_SARADC_DATA_TO_I2S_M (BIT(26))
#define APB_SARADC_DATA_TO_I2S_V 0x1
#define APB_SARADC_DATA_TO_I2S_S 26
/* APB_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data
in this case the resolution should not be larger than 11 bits.*/
#define APB_SARADC_DATA_SAR_SEL (BIT(25))
#define APB_SARADC_DATA_SAR_SEL_M (BIT(25))
#define APB_SARADC_DATA_SAR_SEL_V 0x1
#define APB_SARADC_DATA_SAR_SEL_S 25
/* APB_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */
/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/
#define APB_SARADC_SAR2_PATT_P_CLEAR (BIT(24))
#define APB_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24))
#define APB_SARADC_SAR2_PATT_P_CLEAR_V 0x1
#define APB_SARADC_SAR2_PATT_P_CLEAR_S 24
/* APB_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/
#define APB_SARADC_SAR1_PATT_P_CLEAR (BIT(23))
#define APB_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23))
#define APB_SARADC_SAR1_PATT_P_CLEAR_V 0x1
#define APB_SARADC_SAR1_PATT_P_CLEAR_S 23
/* APB_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */
/*description: 0 ~ 15 means length 1 ~ 16*/
#define APB_SARADC_SAR2_PATT_LEN 0x0000000F
#define APB_SARADC_SAR2_PATT_LEN_M ((APB_SARADC_SAR2_PATT_LEN_V)<<(APB_SARADC_SAR2_PATT_LEN_S))
#define APB_SARADC_SAR2_PATT_LEN_V 0xF
#define APB_SARADC_SAR2_PATT_LEN_S 19
/* APB_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */
/*description: 0 ~ 15 means length 1 ~ 16*/
#define APB_SARADC_SAR1_PATT_LEN 0x0000000F
#define APB_SARADC_SAR1_PATT_LEN_M ((APB_SARADC_SAR1_PATT_LEN_V)<<(APB_SARADC_SAR1_PATT_LEN_S))
#define APB_SARADC_SAR1_PATT_LEN_V 0xF
#define APB_SARADC_SAR1_PATT_LEN_S 15
/* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
/*description: SAR clock divider*/
#define APB_SARADC_SAR_CLK_DIV 0x000000FF
#define APB_SARADC_SAR_CLK_DIV_M ((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S))
#define APB_SARADC_SAR_CLK_DIV_V 0xFF
#define APB_SARADC_SAR_CLK_DIV_S 7
/* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
#define APB_SARADC_SAR_CLK_GATED (BIT(6))
#define APB_SARADC_SAR_CLK_GATED_M (BIT(6))
#define APB_SARADC_SAR_CLK_GATED_V 0x1
#define APB_SARADC_SAR_CLK_GATED_S 6
/* APB_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */
/*description: 0: SAR1 1: SAR2 only work for single SAR mode*/
#define APB_SARADC_SAR_SEL (BIT(5))
#define APB_SARADC_SAR_SEL_M (BIT(5))
#define APB_SARADC_SAR_SEL_V 0x1
#define APB_SARADC_SAR_SEL_S 5
/* APB_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
/*description: 0: single mode 1: double mode 2: alternate mode*/
#define APB_SARADC_WORK_MODE 0x00000003
#define APB_SARADC_WORK_MODE_M ((APB_SARADC_WORK_MODE_V)<<(APB_SARADC_WORK_MODE_S))
#define APB_SARADC_WORK_MODE_V 0x3
#define APB_SARADC_WORK_MODE_S 3
/* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
/*description: */
#define APB_SARADC_START (BIT(1))
#define APB_SARADC_START_M (BIT(1))
#define APB_SARADC_START_V 0x1
#define APB_SARADC_START_S 1
/* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
#define APB_SARADC_START_FORCE (BIT(0))
#define APB_SARADC_START_FORCE_M (BIT(0))
#define APB_SARADC_START_FORCE_V 0x1
#define APB_SARADC_START_FORCE_S 0
#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x004)
/* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */
/*description: to enable saradc timer trigger*/
#define APB_SARADC_TIMER_EN (BIT(24))
#define APB_SARADC_TIMER_EN_M (BIT(24))
#define APB_SARADC_TIMER_EN_V 0x1
#define APB_SARADC_TIMER_EN_S 24
/* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */
/*description: to set saradc timer target*/
#define APB_SARADC_TIMER_TARGET 0x00000FFF
#define APB_SARADC_TIMER_TARGET_M ((APB_SARADC_TIMER_TARGET_V)<<(APB_SARADC_TIMER_TARGET_S))
#define APB_SARADC_TIMER_TARGET_V 0xFFF
#define APB_SARADC_TIMER_TARGET_S 12
/* APB_SARADC_TIMER_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
/*description: 1: select saradc timer 0: i2s_ws trigger*/
#define APB_SARADC_TIMER_SEL (BIT(11))
#define APB_SARADC_TIMER_SEL_M (BIT(11))
#define APB_SARADC_TIMER_SEL_V 0x1
#define APB_SARADC_TIMER_SEL_S 11
/* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/
#define APB_SARADC_SAR2_INV (BIT(10))
#define APB_SARADC_SAR2_INV_M (BIT(10))
#define APB_SARADC_SAR2_INV_V 0x1
#define APB_SARADC_SAR2_INV_S 10
/* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/
#define APB_SARADC_SAR1_INV (BIT(9))
#define APB_SARADC_SAR1_INV_M (BIT(9))
#define APB_SARADC_SAR1_INV_V 0x1
#define APB_SARADC_SAR1_INV_S 9
/* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
/*description: max conversion number*/
#define APB_SARADC_MAX_MEAS_NUM 0x000000FF
#define APB_SARADC_MAX_MEAS_NUM_M ((APB_SARADC_MAX_MEAS_NUM_V)<<(APB_SARADC_MAX_MEAS_NUM_S))
#define APB_SARADC_MAX_MEAS_NUM_V 0xFF
#define APB_SARADC_MAX_MEAS_NUM_S 1
/* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
#define APB_SARADC_MEAS_NUM_LIMIT (BIT(0))
#define APB_SARADC_MEAS_NUM_LIMIT_M (BIT(0))
#define APB_SARADC_MEAS_NUM_LIMIT_V 0x1
#define APB_SARADC_MEAS_NUM_LIMIT_S 0
#define APB_SARADC_FSM_REG (DR_REG_APB_SARADC_BASE + 0x008)
/* APB_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */
/*description: sample cycles*/
#define APB_SARADC_SAMPLE_CYCLE 0x000000FF
#define APB_SARADC_SAMPLE_CYCLE_M ((APB_SARADC_SAMPLE_CYCLE_V)<<(APB_SARADC_SAMPLE_CYCLE_S))
#define APB_SARADC_SAMPLE_CYCLE_V 0xFF
#define APB_SARADC_SAMPLE_CYCLE_S 24
/* APB_SARADC_SAMPLE_NUM : R/W ;bitpos:[23:16] ;default: 8'd0 ; */
/*description: sample number*/
#define APB_SARADC_SAMPLE_NUM 0x000000FF
#define APB_SARADC_SAMPLE_NUM_M ((APB_SARADC_SAMPLE_NUM_V)<<(APB_SARADC_SAMPLE_NUM_S))
#define APB_SARADC_SAMPLE_NUM_V 0xFF
#define APB_SARADC_SAMPLE_NUM_S 16
#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0x00C)
/* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
/*description: */
#define APB_SARADC_STANDBY_WAIT 0x000000FF
#define APB_SARADC_STANDBY_WAIT_M ((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S))
#define APB_SARADC_STANDBY_WAIT_V 0xFF
#define APB_SARADC_STANDBY_WAIT_S 16
/* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
/*description: */
#define APB_SARADC_RSTB_WAIT 0x000000FF
#define APB_SARADC_RSTB_WAIT_M ((APB_SARADC_RSTB_WAIT_V)<<(APB_SARADC_RSTB_WAIT_S))
#define APB_SARADC_RSTB_WAIT_V 0xFF
#define APB_SARADC_RSTB_WAIT_S 8
/* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
/*description: */
#define APB_SARADC_XPD_WAIT 0x000000FF
#define APB_SARADC_XPD_WAIT_M ((APB_SARADC_XPD_WAIT_V)<<(APB_SARADC_XPD_WAIT_S))
#define APB_SARADC_XPD_WAIT_V 0xFF
#define APB_SARADC_XPD_WAIT_S 0
#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x010)
/* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define APB_SARADC_SAR1_STATUS 0xFFFFFFFF
#define APB_SARADC_SAR1_STATUS_M ((APB_SARADC_SAR1_STATUS_V)<<(APB_SARADC_SAR1_STATUS_S))
#define APB_SARADC_SAR1_STATUS_V 0xFFFFFFFF
#define APB_SARADC_SAR1_STATUS_S 0
#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x014)
/* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define APB_SARADC_SAR2_STATUS 0xFFFFFFFF
#define APB_SARADC_SAR2_STATUS_M ((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S))
#define APB_SARADC_SAR2_STATUS_V 0xFFFFFFFF
#define APB_SARADC_SAR2_STATUS_S 0
#define APB_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x018)
/* APB_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/
#define APB_SARADC_SAR1_PATT_TAB1 0xFFFFFFFF
#define APB_SARADC_SAR1_PATT_TAB1_M ((APB_SARADC_SAR1_PATT_TAB1_V)<<(APB_SARADC_SAR1_PATT_TAB1_S))
#define APB_SARADC_SAR1_PATT_TAB1_V 0xFFFFFFFF
#define APB_SARADC_SAR1_PATT_TAB1_S 0
#define APB_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x01C)
/* APB_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/
#define APB_SARADC_SAR1_PATT_TAB2 0xFFFFFFFF
#define APB_SARADC_SAR1_PATT_TAB2_M ((APB_SARADC_SAR1_PATT_TAB2_V)<<(APB_SARADC_SAR1_PATT_TAB2_S))
#define APB_SARADC_SAR1_PATT_TAB2_V 0xFFFFFFFF
#define APB_SARADC_SAR1_PATT_TAB2_S 0
#define APB_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x020)
/* APB_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/
#define APB_SARADC_SAR1_PATT_TAB3 0xFFFFFFFF
#define APB_SARADC_SAR1_PATT_TAB3_M ((APB_SARADC_SAR1_PATT_TAB3_V)<<(APB_SARADC_SAR1_PATT_TAB3_S))
#define APB_SARADC_SAR1_PATT_TAB3_V 0xFFFFFFFF
#define APB_SARADC_SAR1_PATT_TAB3_S 0
#define APB_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x024)
/* APB_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/
#define APB_SARADC_SAR1_PATT_TAB4 0xFFFFFFFF
#define APB_SARADC_SAR1_PATT_TAB4_M ((APB_SARADC_SAR1_PATT_TAB4_V)<<(APB_SARADC_SAR1_PATT_TAB4_S))
#define APB_SARADC_SAR1_PATT_TAB4_V 0xFFFFFFFF
#define APB_SARADC_SAR1_PATT_TAB4_S 0
#define APB_SARADC_SAR2_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x028)
/* APB_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/
#define APB_SARADC_SAR2_PATT_TAB1 0xFFFFFFFF
#define APB_SARADC_SAR2_PATT_TAB1_M ((APB_SARADC_SAR2_PATT_TAB1_V)<<(APB_SARADC_SAR2_PATT_TAB1_S))
#define APB_SARADC_SAR2_PATT_TAB1_V 0xFFFFFFFF
#define APB_SARADC_SAR2_PATT_TAB1_S 0
#define APB_SARADC_SAR2_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x02C)
/* APB_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/
#define APB_SARADC_SAR2_PATT_TAB2 0xFFFFFFFF
#define APB_SARADC_SAR2_PATT_TAB2_M ((APB_SARADC_SAR2_PATT_TAB2_V)<<(APB_SARADC_SAR2_PATT_TAB2_S))
#define APB_SARADC_SAR2_PATT_TAB2_V 0xFFFFFFFF
#define APB_SARADC_SAR2_PATT_TAB2_S 0
#define APB_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x030)
/* APB_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/
#define APB_SARADC_SAR2_PATT_TAB3 0xFFFFFFFF
#define APB_SARADC_SAR2_PATT_TAB3_M ((APB_SARADC_SAR2_PATT_TAB3_V)<<(APB_SARADC_SAR2_PATT_TAB3_S))
#define APB_SARADC_SAR2_PATT_TAB3_V 0xFFFFFFFF
#define APB_SARADC_SAR2_PATT_TAB3_S 0
#define APB_SARADC_SAR2_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x034)
/* APB_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/
#define APB_SARADC_SAR2_PATT_TAB4 0xFFFFFFFF
#define APB_SARADC_SAR2_PATT_TAB4_M ((APB_SARADC_SAR2_PATT_TAB4_V)<<(APB_SARADC_SAR2_PATT_TAB4_S))
#define APB_SARADC_SAR2_PATT_TAB4_V 0xFFFFFFFF
#define APB_SARADC_SAR2_PATT_TAB4_S 0
#define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x038)
/* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: adc2 arbiter uses fixed priority*/
#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12))
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (BIT(12))
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x1
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12
/* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */
/*description: Set adc2 arbiter wifi priority*/
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V)<<(APB_SARADC_ADC_ARB_WIFI_PRIORITY_S))
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x3
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10
/* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */
/*description: Set adc2 arbiter rtc priority*/
#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V)<<(APB_SARADC_ADC_ARB_RTC_PRIORITY_S))
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x3
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8
/* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
/*description: Set adc2 arbiterapb priority*/
#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003
#define APB_SARADC_ADC_ARB_APB_PRIORITY_M ((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S))
#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x3
#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6
/* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: adc2 arbiter force grant*/
#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5))
#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (BIT(5))
#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x1
#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5
/* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enable wifi controller*/
#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4))
#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (BIT(4))
#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x1
#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4
/* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enable rtc controller*/
#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3))
#define APB_SARADC_ADC_ARB_RTC_FORCE_M (BIT(3))
#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x1
#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3
/* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enableapb controller*/
#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2))
#define APB_SARADC_ADC_ARB_APB_FORCE_M (BIT(2))
#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x1
#define APB_SARADC_ADC_ARB_APB_FORCE_S 2
#define APB_SARADC_FILTER_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x03C)
/* APB_SARADC_ADC1_FILTER_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: enable apb_adc1_filter*/
#define APB_SARADC_ADC1_FILTER_EN (BIT(31))
#define APB_SARADC_ADC1_FILTER_EN_M (BIT(31))
#define APB_SARADC_ADC1_FILTER_EN_V 0x1
#define APB_SARADC_ADC1_FILTER_EN_S 31
/* APB_SARADC_ADC2_FILTER_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: enable apb_adc2_filter*/
#define APB_SARADC_ADC2_FILTER_EN (BIT(30))
#define APB_SARADC_ADC2_FILTER_EN_M (BIT(30))
#define APB_SARADC_ADC2_FILTER_EN_V 0x1
#define APB_SARADC_ADC2_FILTER_EN_S 30
/* APB_SARADC_ADC1_FILTER_FACTOR : R/W ;bitpos:[29:23] ;default: 7'd64 ; */
/*description: apb_adc1_filter_factor*/
#define APB_SARADC_ADC1_FILTER_FACTOR 0x0000007F
#define APB_SARADC_ADC1_FILTER_FACTOR_M ((APB_SARADC_ADC1_FILTER_FACTOR_V)<<(APB_SARADC_ADC1_FILTER_FACTOR_S))
#define APB_SARADC_ADC1_FILTER_FACTOR_V 0x7F
#define APB_SARADC_ADC1_FILTER_FACTOR_S 23
/* APB_SARADC_ADC2_FILTER_FACTOR : R/W ;bitpos:[22:16] ;default: 7'd64 ; */
/*description: apb_adc2_filter_factor*/
#define APB_SARADC_ADC2_FILTER_FACTOR 0x0000007F
#define APB_SARADC_ADC2_FILTER_FACTOR_M ((APB_SARADC_ADC2_FILTER_FACTOR_V)<<(APB_SARADC_ADC2_FILTER_FACTOR_S))
#define APB_SARADC_ADC2_FILTER_FACTOR_V 0x7F
#define APB_SARADC_ADC2_FILTER_FACTOR_S 16
/* APB_SARADC_ADC1_FILTER_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: reset_adc1_filter*/
#define APB_SARADC_ADC1_FILTER_RESET (BIT(1))
#define APB_SARADC_ADC1_FILTER_RESET_M (BIT(1))
#define APB_SARADC_ADC1_FILTER_RESET_V 0x1
#define APB_SARADC_ADC1_FILTER_RESET_S 1
/* APB_SARADC_ADC2_FILTER_RESET : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: reset_adc2_filter*/
#define APB_SARADC_ADC2_FILTER_RESET (BIT(0))
#define APB_SARADC_ADC2_FILTER_RESET_M (BIT(0))
#define APB_SARADC_ADC2_FILTER_RESET_V 0x1
#define APB_SARADC_ADC2_FILTER_RESET_S 0
#define APB_SARADC_FILTER_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x040)
/* APB_SARADC_ADC1_FILTER_DATA : RO ;bitpos:[31:16] ;default: 16'd0 ; */
/*description: */
#define APB_SARADC_ADC1_FILTER_DATA 0x0000FFFF
#define APB_SARADC_ADC1_FILTER_DATA_M ((APB_SARADC_ADC1_FILTER_DATA_V)<<(APB_SARADC_ADC1_FILTER_DATA_S))
#define APB_SARADC_ADC1_FILTER_DATA_V 0xFFFF
#define APB_SARADC_ADC1_FILTER_DATA_S 16
/* APB_SARADC_ADC2_FILTER_DATA : RO ;bitpos:[15:0] ;default: 16'd0 ; */
/*description: */
#define APB_SARADC_ADC2_FILTER_DATA 0x0000FFFF
#define APB_SARADC_ADC2_FILTER_DATA_M ((APB_SARADC_ADC2_FILTER_DATA_V)<<(APB_SARADC_ADC2_FILTER_DATA_S))
#define APB_SARADC_ADC2_FILTER_DATA_V 0xFFFF
#define APB_SARADC_ADC2_FILTER_DATA_S 0
#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x044)
/* APB_SARADC_ADC1_THRES_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC1_THRES_EN (BIT(31))
#define APB_SARADC_ADC1_THRES_EN_M (BIT(31))
#define APB_SARADC_ADC1_THRES_EN_V 0x1
#define APB_SARADC_ADC1_THRES_EN_S 31
/* APB_SARADC_ADC2_THRES_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC2_THRES_EN (BIT(30))
#define APB_SARADC_ADC2_THRES_EN_M (BIT(30))
#define APB_SARADC_ADC2_THRES_EN_V 0x1
#define APB_SARADC_ADC2_THRES_EN_S 30
/* APB_SARADC_ADC1_THRES : R/W ;bitpos:[29:17] ;default: 13'd0 ; */
/*description: */
#define APB_SARADC_ADC1_THRES 0x00001FFF
#define APB_SARADC_ADC1_THRES_M ((APB_SARADC_ADC1_THRES_V)<<(APB_SARADC_ADC1_THRES_S))
#define APB_SARADC_ADC1_THRES_V 0x1FFF
#define APB_SARADC_ADC1_THRES_S 17
/* APB_SARADC_ADC2_THRES : R/W ;bitpos:[16:4] ;default: 13'd0 ; */
/*description: */
#define APB_SARADC_ADC2_THRES 0x00001FFF
#define APB_SARADC_ADC2_THRES_M ((APB_SARADC_ADC2_THRES_V)<<(APB_SARADC_ADC2_THRES_S))
#define APB_SARADC_ADC2_THRES_V 0x1FFF
#define APB_SARADC_ADC2_THRES_S 4
/* APB_SARADC_ADC1_THRES_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
/*description: */
#define APB_SARADC_ADC1_THRES_MODE (BIT(3))
#define APB_SARADC_ADC1_THRES_MODE_M (BIT(3))
#define APB_SARADC_ADC1_THRES_MODE_V 0x1
#define APB_SARADC_ADC1_THRES_MODE_S 3
/* APB_SARADC_ADC2_THRES_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: */
#define APB_SARADC_ADC2_THRES_MODE (BIT(2))
#define APB_SARADC_ADC2_THRES_MODE_M (BIT(2))
#define APB_SARADC_ADC2_THRES_MODE_V 0x1
#define APB_SARADC_ADC2_THRES_MODE_S 2
/* APB_SARADC_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_CLK_EN (BIT(0))
#define APB_SARADC_CLK_EN_M (BIT(0))
#define APB_SARADC_CLK_EN_V 0x1
#define APB_SARADC_CLK_EN_S 0
#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x048)
/* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC1_DONE_INT_ENA (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_ENA_M (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_ENA_V 0x1
#define APB_SARADC_ADC1_DONE_INT_ENA_S 31
/* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC2_DONE_INT_ENA (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ENA_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ENA_V 0x1
#define APB_SARADC_ADC2_DONE_INT_ENA_S 30
/* APB_SARADC_ADC1_THRES_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC1_THRES_INT_ENA (BIT(29))
#define APB_SARADC_ADC1_THRES_INT_ENA_M (BIT(29))
#define APB_SARADC_ADC1_THRES_INT_ENA_V 0x1
#define APB_SARADC_ADC1_THRES_INT_ENA_S 29
/* APB_SARADC_ADC2_THRES_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC2_THRES_INT_ENA (BIT(28))
#define APB_SARADC_ADC2_THRES_INT_ENA_M (BIT(28))
#define APB_SARADC_ADC2_THRES_INT_ENA_V 0x1
#define APB_SARADC_ADC2_THRES_INT_ENA_S 28
#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x04C)
/* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC1_DONE_INT_RAW (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_RAW_M (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_RAW_V 0x1
#define APB_SARADC_ADC1_DONE_INT_RAW_S 31
/* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC2_DONE_INT_RAW (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_RAW_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_RAW_V 0x1
#define APB_SARADC_ADC2_DONE_INT_RAW_S 30
/* APB_SARADC_ADC1_THRES_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC1_THRES_INT_RAW (BIT(29))
#define APB_SARADC_ADC1_THRES_INT_RAW_M (BIT(29))
#define APB_SARADC_ADC1_THRES_INT_RAW_V 0x1
#define APB_SARADC_ADC1_THRES_INT_RAW_S 29
/* APB_SARADC_ADC2_THRES_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC2_THRES_INT_RAW (BIT(28))
#define APB_SARADC_ADC2_THRES_INT_RAW_M (BIT(28))
#define APB_SARADC_ADC2_THRES_INT_RAW_V 0x1
#define APB_SARADC_ADC2_THRES_INT_RAW_S 28
#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x050)
/* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC1_DONE_INT_ST (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_ST_M (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_ST_V 0x1
#define APB_SARADC_ADC1_DONE_INT_ST_S 31
/* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC2_DONE_INT_ST (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ST_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ST_V 0x1
#define APB_SARADC_ADC2_DONE_INT_ST_S 30
/* APB_SARADC_ADC1_THRES_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC1_THRES_INT_ST (BIT(29))
#define APB_SARADC_ADC1_THRES_INT_ST_M (BIT(29))
#define APB_SARADC_ADC1_THRES_INT_ST_V 0x1
#define APB_SARADC_ADC1_THRES_INT_ST_S 29
/* APB_SARADC_ADC2_THRES_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC2_THRES_INT_ST (BIT(28))
#define APB_SARADC_ADC2_THRES_INT_ST_M (BIT(28))
#define APB_SARADC_ADC2_THRES_INT_ST_V 0x1
#define APB_SARADC_ADC2_THRES_INT_ST_S 28
#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x054)
/* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC1_DONE_INT_CLR (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_CLR_M (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_CLR_V 0x1
#define APB_SARADC_ADC1_DONE_INT_CLR_S 31
/* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC2_DONE_INT_CLR (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_CLR_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_CLR_V 0x1
#define APB_SARADC_ADC2_DONE_INT_CLR_S 30
/* APB_SARADC_ADC1_THRES_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC1_THRES_INT_CLR (BIT(29))
#define APB_SARADC_ADC1_THRES_INT_CLR_M (BIT(29))
#define APB_SARADC_ADC1_THRES_INT_CLR_V 0x1
#define APB_SARADC_ADC1_THRES_INT_CLR_S 29
/* APB_SARADC_ADC2_THRES_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ADC2_THRES_INT_CLR (BIT(28))
#define APB_SARADC_ADC2_THRES_INT_CLR_M (BIT(28))
#define APB_SARADC_ADC2_THRES_INT_CLR_V 0x1
#define APB_SARADC_ADC2_THRES_INT_CLR_S 28
#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x058)
/* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */
/*description: enable apb_adc use spi_dma*/
#define APB_SARADC_APB_ADC_TRANS (BIT(31))
#define APB_SARADC_APB_ADC_TRANS_M (BIT(31))
#define APB_SARADC_APB_ADC_TRANS_V 0x1
#define APB_SARADC_APB_ADC_TRANS_S 31
/* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: reset_apb_adc_state*/
#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30))
#define APB_SARADC_APB_ADC_RESET_FSM_M (BIT(30))
#define APB_SARADC_APB_ADC_RESET_FSM_V 0x1
#define APB_SARADC_APB_ADC_RESET_FSM_S 30
/* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */
/*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num*/
#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFF
#define APB_SARADC_APB_ADC_EOF_NUM_M ((APB_SARADC_APB_ADC_EOF_NUM_V)<<(APB_SARADC_APB_ADC_EOF_NUM_S))
#define APB_SARADC_APB_ADC_EOF_NUM_V 0xFFFF
#define APB_SARADC_APB_ADC_EOF_NUM_S 0
#define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x05c)
/* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */
/*description: Set this bit to enable clk_apll*/
#define APB_SARADC_CLK_SEL 0x00000003
#define APB_SARADC_CLK_SEL_M ((APB_SARADC_CLK_SEL_V)<<(APB_SARADC_CLK_SEL_S))
#define APB_SARADC_CLK_SEL_V 0x3
#define APB_SARADC_CLK_SEL_S 21
/* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */
/*description: Fractional clock divider denominator value*/
#define APB_SARADC_CLKM_DIV_A 0x0000003F
#define APB_SARADC_CLKM_DIV_A_M ((APB_SARADC_CLKM_DIV_A_V)<<(APB_SARADC_CLKM_DIV_A_S))
#define APB_SARADC_CLKM_DIV_A_V 0x3F
#define APB_SARADC_CLKM_DIV_A_S 14
/* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */
/*description: Fractional clock divider numerator value*/
#define APB_SARADC_CLKM_DIV_B 0x0000003F
#define APB_SARADC_CLKM_DIV_B_M ((APB_SARADC_CLKM_DIV_B_V)<<(APB_SARADC_CLKM_DIV_B_S))
#define APB_SARADC_CLKM_DIV_B_V 0x3F
#define APB_SARADC_CLKM_DIV_B_S 8
/* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */
/*description: Integral I2S clock divider value*/
#define APB_SARADC_CLKM_DIV_NUM 0x000000FF
#define APB_SARADC_CLKM_DIV_NUM_M ((APB_SARADC_CLKM_DIV_NUM_V)<<(APB_SARADC_CLKM_DIV_NUM_S))
#define APB_SARADC_CLKM_DIV_NUM_V 0xFF
#define APB_SARADC_CLKM_DIV_NUM_S 0
#define APB_SARADC_APB_DAC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x060)
/* APB_SARADC_APB_DAC_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_APB_DAC_RST (BIT(16))
#define APB_SARADC_APB_DAC_RST_M (BIT(16))
#define APB_SARADC_APB_DAC_RST_V 0x1
#define APB_SARADC_APB_DAC_RST_S 16
/* APB_SARADC_DAC_RESET_FIFO : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_DAC_RESET_FIFO (BIT(15))
#define APB_SARADC_DAC_RESET_FIFO_M (BIT(15))
#define APB_SARADC_DAC_RESET_FIFO_V 0x1
#define APB_SARADC_DAC_RESET_FIFO_S 15
/* APB_SARADC_APB_DAC_TRANS : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: enable dma_dac*/
#define APB_SARADC_APB_DAC_TRANS (BIT(14))
#define APB_SARADC_APB_DAC_TRANS_M (BIT(14))
#define APB_SARADC_APB_DAC_TRANS_V 0x1
#define APB_SARADC_APB_DAC_TRANS_S 14
/* APB_SARADC_APB_DAC_ALTER_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
/*description: enable dac alter mode*/
#define APB_SARADC_APB_DAC_ALTER_MODE (BIT(13))
#define APB_SARADC_APB_DAC_ALTER_MODE_M (BIT(13))
#define APB_SARADC_APB_DAC_ALTER_MODE_V 0x1
#define APB_SARADC_APB_DAC_ALTER_MODE_S 13
/* APB_SARADC_DAC_TIMER_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: enable read dac data*/
#define APB_SARADC_DAC_TIMER_EN (BIT(12))
#define APB_SARADC_DAC_TIMER_EN_M (BIT(12))
#define APB_SARADC_DAC_TIMER_EN_V 0x1
#define APB_SARADC_DAC_TIMER_EN_S 12
/* APB_SARADC_DAC_TIMER_TARGET : R/W ;bitpos:[11:0] ;default: 12'd100 ; */
/*description: dac_timer target*/
#define APB_SARADC_DAC_TIMER_TARGET 0x00000FFF
#define APB_SARADC_DAC_TIMER_TARGET_M ((APB_SARADC_DAC_TIMER_TARGET_V)<<(APB_SARADC_DAC_TIMER_TARGET_S))
#define APB_SARADC_DAC_TIMER_TARGET_V 0xFFF
#define APB_SARADC_DAC_TIMER_TARGET_S 0
#define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3FC)
/* APB_SARADC_APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h01907162 ; */
/*description: */
#define APB_SARADC_APB_CTRL_DATE 0xFFFFFFFF
#define APB_SARADC_APB_CTRL_DATE_M ((APB_SARADC_APB_CTRL_DATE_V)<<(APB_SARADC_APB_CTRL_DATE_S))
#define APB_SARADC_APB_CTRL_DATE_V 0xFFFFFFFF
#define APB_SARADC_APB_CTRL_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_APB_SARADC_REG_H_ */

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components/soc/esp32s2beta/include/soc/apb_saradc_struct.h Normal file
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_APB_SARADC_STRUCT_H_
#define _SOC_APB_SARADC_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t start_force: 1;
uint32_t start: 1;
uint32_t reserved2: 1;
uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/
uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/
uint32_t sar_clk_gated: 1;
uint32_t sar_clk_div: 8; /*SAR clock divider*/
uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/
uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/
uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/
uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/
uint32_t xpd_sar_force: 2; /*force option to xpd sar blocks*/
uint32_t reserved29: 1;
uint32_t wait_arb_cycle: 2; /*wait arbit signal stable after sar_done*/
};
uint32_t val;
} ctrl;
union {
struct {
uint32_t meas_num_limit: 1;
uint32_t max_meas_num: 8; /*max conversion number*/
uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/
uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/
uint32_t timer_sel: 1; /*1: select saradc timer 0: i2s_ws trigger*/
uint32_t timer_target: 12; /*to set saradc timer target*/
uint32_t timer_en: 1; /*to enable saradc timer trigger*/
uint32_t reserved25: 7;
};
uint32_t val;
} ctrl2;
union {
struct {
uint32_t reserved0: 16;
uint32_t sample_num: 8; /*sample number*/
uint32_t sample_cycle: 8; /*sample cycles*/
};
uint32_t val;
} fsm;
union {
struct {
uint32_t xpd_wait: 8;
uint32_t rstb_wait: 8;
uint32_t standby_wait: 8;
uint32_t reserved24: 8;
};
uint32_t val;
} fsm_wait;
uint32_t sar1_status; /**/
uint32_t sar2_status; /**/
uint32_t sar1_patt_tab[4]; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/
uint32_t sar2_patt_tab[4];
// uint32_t sar1_patt_tab2; /*Item 4 ~ 7 for pattern table 1 (each item one byte)*/
// uint32_t sar1_patt_tab3; /*Item 8 ~ 11 for pattern table 1 (each item one byte)*/
// uint32_t sar1_patt_tab4; /*Item 12 ~ 15 for pattern table 1 (each item one byte)*/
// uint32_t sar2_patt_tab1; /*item 0 ~ 3 for pattern table 2 (each item one byte)*/
// uint32_t sar2_patt_tab2; /*Item 4 ~ 7 for pattern table 2 (each item one byte)*/
// uint32_t sar2_patt_tab3; /*Item 8 ~ 11 for pattern table 2 (each item one byte)*/
// uint32_t sar2_patt_tab4; /*Item 12 ~ 15 for pattern table 2 (each item one byte)*/
union {
struct {
uint32_t reserved0: 2;
uint32_t adc_arb_apb_force: 1; /*adc2 arbiter force to enableapb controller*/
uint32_t adc_arb_rtc_force: 1; /*adc2 arbiter force to enable rtc controller*/
uint32_t adc_arb_wifi_force: 1; /*adc2 arbiter force to enable wifi controller*/
uint32_t adc_arb_grant_force: 1; /*adc2 arbiter force grant*/
uint32_t adc_arb_apb_priority: 2; /*Set adc2 arbiterapb priority*/
uint32_t adc_arb_rtc_priority: 2; /*Set adc2 arbiter rtc priority*/
uint32_t adc_arb_wifi_priority: 2; /*Set adc2 arbiter wifi priority*/
uint32_t adc_arb_fix_priority: 1; /*adc2 arbiter uses fixed priority*/
uint32_t reserved13: 19;
};
uint32_t val;
} apb_adc_arb_ctrl;
union {
struct {
uint32_t adc2_filter_reset: 1; /*reset_adc2_filter*/
uint32_t adc1_filter_reset: 1; /*reset_adc1_filter*/
uint32_t reserved2: 14;
uint32_t adc2_filter_factor: 7; /*apb_adc2_filter_factor*/
uint32_t adc1_filter_factor: 7; /*apb_adc1_filter_factor*/
uint32_t adc2_filter_en: 1; /*enable apb_adc2_filter*/
uint32_t adc1_filter_en: 1; /*enable apb_adc1_filter*/
};
uint32_t val;
} filter_ctrl;
union {
struct {
uint32_t adc2_filter_data:16;
uint32_t adc1_filter_data:16;
};
uint32_t val;
} filter_status;
union {
struct {
uint32_t clk_en: 1;
uint32_t reserved1: 1;
uint32_t adc2_thres_mode: 1;
uint32_t adc1_thres_mode: 1;
uint32_t adc2_thres: 13;
uint32_t adc1_thres: 13;
uint32_t adc2_thres_en: 1;
uint32_t adc1_thres_en: 1;
};
uint32_t val;
} thres_ctrl;
union {
struct {
uint32_t reserved0: 28;
uint32_t adc2_thres: 1;
uint32_t adc1_thres: 1;
uint32_t adc2_done: 1;
uint32_t adc1_done: 1;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t reserved0: 28;
uint32_t adc2_thres: 1;
uint32_t adc1_thres: 1;
uint32_t adc2_done: 1;
uint32_t adc1_done: 1;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t reserved0: 28;
uint32_t adc2_thres: 1;
uint32_t adc1_thres: 1;
uint32_t adc2_done: 1;
uint32_t adc1_done: 1;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t reserved0: 28;
uint32_t adc2_thres: 1;
uint32_t adc1_thres: 1;
uint32_t adc2_done: 1;
uint32_t adc1_done: 1;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t apb_adc_eof_num: 16; /*the dma_in_suc_eof gen when sample cnt = spi_eof_num*/
uint32_t reserved16: 14;
uint32_t apb_adc_reset_fsm: 1; /*reset_apb_adc_state*/
uint32_t apb_adc_trans: 1; /*enable apb_adc use spi_dma*/
};
uint32_t val;
} dma_conf;
union {
struct {
uint32_t clkm_div_num: 8; /*Integral I2S clock divider value*/
uint32_t clkm_div_b: 6; /*Fractional clock divider numerator value*/
uint32_t clkm_div_a: 6; /*Fractional clock divider denominator value*/
uint32_t reserved20: 1;
uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/
uint32_t reserved23: 9;
};
uint32_t val;
} apb_adc_clkm_conf;
union {
struct {
uint32_t dac_timer_target: 12; /*dac_timer target*/
uint32_t dac_timer_en: 1; /*enable read dac data*/
uint32_t apb_dac_alter_mode: 1; /*enable dac alter mode*/
uint32_t apb_dac_trans: 1; /*enable dma_dac*/
uint32_t dac_reset_fifo: 1;
uint32_t apb_dac_rst: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} apb_dac_ctrl;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t reserved_fc;
uint32_t reserved_100;
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
uint32_t reserved_110;
uint32_t reserved_114;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t reserved_1fc;
uint32_t reserved_200;
uint32_t reserved_204;
uint32_t reserved_208;
uint32_t reserved_20c;
uint32_t reserved_210;
uint32_t reserved_214;
uint32_t reserved_218;
uint32_t reserved_21c;
uint32_t reserved_220;
uint32_t reserved_224;
uint32_t reserved_228;
uint32_t reserved_22c;
uint32_t reserved_230;
uint32_t reserved_234;
uint32_t reserved_238;
uint32_t reserved_23c;
uint32_t reserved_240;
uint32_t reserved_244;
uint32_t reserved_248;
uint32_t reserved_24c;
uint32_t reserved_250;
uint32_t reserved_254;
uint32_t reserved_258;
uint32_t reserved_25c;
uint32_t reserved_260;
uint32_t reserved_264;
uint32_t reserved_268;
uint32_t reserved_26c;
uint32_t reserved_270;
uint32_t reserved_274;
uint32_t reserved_278;
uint32_t reserved_27c;
uint32_t reserved_280;
uint32_t reserved_284;
uint32_t reserved_288;
uint32_t reserved_28c;
uint32_t reserved_290;
uint32_t reserved_294;
uint32_t reserved_298;
uint32_t reserved_29c;
uint32_t reserved_2a0;
uint32_t reserved_2a4;
uint32_t reserved_2a8;
uint32_t reserved_2ac;
uint32_t reserved_2b0;
uint32_t reserved_2b4;
uint32_t reserved_2b8;
uint32_t reserved_2bc;
uint32_t reserved_2c0;
uint32_t reserved_2c4;
uint32_t reserved_2c8;
uint32_t reserved_2cc;
uint32_t reserved_2d0;
uint32_t reserved_2d4;
uint32_t reserved_2d8;
uint32_t reserved_2dc;
uint32_t reserved_2e0;
uint32_t reserved_2e4;
uint32_t reserved_2e8;
uint32_t reserved_2ec;
uint32_t reserved_2f0;
uint32_t reserved_2f4;
uint32_t reserved_2f8;
uint32_t reserved_2fc;
uint32_t reserved_300;
uint32_t reserved_304;
uint32_t reserved_308;
uint32_t reserved_30c;
uint32_t reserved_310;
uint32_t reserved_314;
uint32_t reserved_318;
uint32_t reserved_31c;
uint32_t reserved_320;
uint32_t reserved_324;
uint32_t reserved_328;
uint32_t reserved_32c;
uint32_t reserved_330;
uint32_t reserved_334;
uint32_t reserved_338;
uint32_t reserved_33c;
uint32_t reserved_340;
uint32_t reserved_344;
uint32_t reserved_348;
uint32_t reserved_34c;
uint32_t reserved_350;
uint32_t reserved_354;
uint32_t reserved_358;
uint32_t reserved_35c;
uint32_t reserved_360;
uint32_t reserved_364;
uint32_t reserved_368;
uint32_t reserved_36c;
uint32_t reserved_370;
uint32_t reserved_374;
uint32_t reserved_378;
uint32_t reserved_37c;
uint32_t reserved_380;
uint32_t reserved_384;
uint32_t reserved_388;
uint32_t reserved_38c;
uint32_t reserved_390;
uint32_t reserved_394;
uint32_t reserved_398;
uint32_t reserved_39c;
uint32_t reserved_3a0;
uint32_t reserved_3a4;
uint32_t reserved_3a8;
uint32_t reserved_3ac;
uint32_t reserved_3b0;
uint32_t reserved_3b4;
uint32_t reserved_3b8;
uint32_t reserved_3bc;
uint32_t reserved_3c0;
uint32_t reserved_3c4;
uint32_t reserved_3c8;
uint32_t reserved_3cc;
uint32_t reserved_3d0;
uint32_t reserved_3d4;
uint32_t reserved_3d8;
uint32_t reserved_3dc;
uint32_t reserved_3e0;
uint32_t reserved_3e4;
uint32_t reserved_3e8;
uint32_t reserved_3ec;
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
uint32_t apb_ctrl_date; /**/
} apb_saradc_dev_t;
extern apb_saradc_dev_t APB_SARADC;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_APB_SARADC_STRUCT_H_ */

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components/soc/esp32s2beta/include/soc/assist_debug_reg.h
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@ -4,32 +4,53 @@
#define ASSIST_DEBUG_INTERRUPT_RAW ((ASSIST_DEBUG_BASE) +0x04)
#define ASSIST_DEBUG_INTERRUPT_RLS ((ASSIST_DEBUG_BASE) +0x08)
#define ASSIST_DEBUG_INTERRUPT_CLR ((ASSIST_DEBUG_BASE) +0x0C)
#define ASSIST_DEBUG_INTERRUPT_AREA_0_TOUCH_PRO_RD BIT(0)
#define ASSIST_DEBUG_INTERRUPT_AREA_0_TOUCH_PRO_WR BIT(1)
#define ASSIST_DEBUG_INTERRUPT_AREA_1_TOUCH_PRO_RD BIT(2)
#define ASSIST_DEBUG_INTERRUPT_AREA_1_TOUCH_PRO_WR BIT(3)
#define ASSIST_DEBUG_INTERRUPT_PRO_SP_SPILL_MIN BIT(4)
#define ASSIST_DEBUG_INTERRUPT_PRO_SP_SPILL_MAX BIT(5)
#define ASSIST_DEBUG_SP_SPILL_MAX BIT(19)
#define ASSIST_DEBUG_SP_SPILL_MIN BIT(18)
#define ASSIST_DEBUG_AREA_2_1_AHB_WR BIT(17)
#define ASSIST_DEBUG_AREA_2_1_AHB_RD BIT(16)
#define ASSIST_DEBUG_AREA_2_0_AHB_WR BIT(15)
#define ASSIST_DEBUG_AREA_2_0_AHB_RD BIT(14)
#define ASSIST_DEBUG_AREA_1_1_DROM0_RD BIT(13)
#define ASSIST_DEBUG_AREA_1_0_DROM0_RD BIT(12)
#define ASSIST_DEBUG_AREA_0_1_DPORT0_WR BIT(11)
#define ASSIST_DEBUG_AREA_0_1_DPORT0_RD BIT(10)
#define ASSIST_DEBUG_AREA_0_1_DRAM1_WR BIT(9)
#define ASSIST_DEBUG_AREA_0_1_DRAM1_RD BIT(8)
#define ASSIST_DEBUG_AREA_0_1_DRAM0_WR BIT(7)
#define ASSIST_DEBUG_AREA_0_1_DRAM0_RD BIT(6)
#define ASSIST_DEBUG_AREA_0_0_DPORT0_WR BIT(5)
#define ASSIST_DEBUG_AREA_0_0_DPORT0_RD BIT(4)
#define ASSIST_DEBUG_AREA_0_0_DRAM1_WR BIT(3)
#define ASSIST_DEBUG_AREA_0_0_DRAM1_RD BIT(2)
#define ASSIST_DEBUG_AREA_0_0_DRAM0_WR BIT(1)
#define ASSIST_DEBUG_AREA_0_0_DRAM0_RD BIT(0)
#define ASSIST_DEBUG_AREA_0_MIN ((ASSIST_DEBUG_BASE) +0x10)
#define ASSIST_DEBUG_AREA_0_MAX ((ASSIST_DEBUG_BASE) +0x14)
#define ASSIST_DEBUG_AREA_0_PC ((ASSIST_DEBUG_BASE) +0x18)
#define ASSIST_DEBUG_AREA_0_SP ((ASSIST_DEBUG_BASE) +0x1C)
#define ASSIST_DEBUG_AREA_0_0_MIN ((ASSIST_DEBUG_BASE) +0x10)
#define ASSIST_DEBUG_AREA_0_0_MAX ((ASSIST_DEBUG_BASE) +0x14)
#define ASSIST_DEBUG_AREA_0_1_MIN ((ASSIST_DEBUG_BASE) +0x18)
#define ASSIST_DEBUG_AREA_0_1_MAX ((ASSIST_DEBUG_BASE) +0x1C)
#define ASSIST_DEBUG_AREA_1_0_MIN ((ASSIST_DEBUG_BASE) +0x20)
#define ASSIST_DEBUG_AREA_1_0_MAX ((ASSIST_DEBUG_BASE) +0x24)
#define ASSIST_DEBUG_AREA_1_1_MIN ((ASSIST_DEBUG_BASE) +0x28)
#define ASSIST_DEBUG_AREA_1_1_MAX ((ASSIST_DEBUG_BASE) +0x2C)
#define ASSIST_DEBUG_AREA_2_0_MIN ((ASSIST_DEBUG_BASE) +0x30)
#define ASSIST_DEBUG_AREA_2_0_MAX ((ASSIST_DEBUG_BASE) +0x34)
#define ASSIST_DEBUG_AREA_2_1_MIN ((ASSIST_DEBUG_BASE) +0x38)
#define ASSIST_DEBUG_AREA_2_1_MAX ((ASSIST_DEBUG_BASE) +0x3C)
#define ASSIST_DEBUG_AREA_PC ((ASSIST_DEBUG_BASE) +0x40)
#define ASSIST_DEBUG_AREA_SP ((ASSIST_DEBUG_BASE) +0x44)
#define ASSIST_DEBUG_AREA_1_MIN ((ASSIST_DEBUG_BASE) +0x20)
#define ASSIST_DEBUG_AREA_1_MAX ((ASSIST_DEBUG_BASE) +0x24)
#define ASSIST_DEBUG_AREA_1_PC ((ASSIST_DEBUG_BASE) +0x28)
#define ASSIST_DEBUG_AREA_1_SP ((ASSIST_DEBUG_BASE) +0x2C)
#define ASSIST_DEBUG_PRO_SP_UNSTABLE ((ASSIST_DEBUG_BASE) +0x30)
#define ASSIST_DEBUG_PRO_SP_MIN ((ASSIST_DEBUG_BASE) +0x34)
#define ASSIST_DEBUG_PRO_SP_MAX ((ASSIST_DEBUG_BASE) +0x38)
#define ASSIST_DEBUG_PRO_SP_PC ((ASSIST_DEBUG_BASE) +0x3C)
#define ASSIST_DEBUG_PRO_SP_UNSTABLE ((ASSIST_DEBUG_BASE) +0x48)
#define ASSIST_DEBUG_PRO_SP_MIN ((ASSIST_DEBUG_BASE) +0x4C)
#define ASSIST_DEBUG_PRO_SP_MAX ((ASSIST_DEBUG_BASE) +0x50)
#define ASSIST_DEBUG_PRO_SP_PC ((ASSIST_DEBUG_BASE) +0x54)
#define ASSIST_DEBUG_PRO_PDEBUGENABLE ((ASSIST_DEBUG_BASE) +0x40)
#define ASSIST_DEBUG_PRO_RCD_RECORDING ((ASSIST_DEBUG_BASE) +0x44)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGINST ((ASSIST_DEBUG_BASE) +0x48)
#define ASSIST_DEBUG_PRO_PDEBUGENABLE ((ASSIST_DEBUG_BASE) +0x58)
#define ASSIST_DEBUG_PRO_RCD_RECORDING ((ASSIST_DEBUG_BASE) +0x5C)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGINST ((ASSIST_DEBUG_BASE) +0x60)
/* register layout:
* SIZE [7..0] : Instructions normally complete in the W stage. The size of the instruction in the W is given
* by this field in number of bytes. If it is 8’b0 in a given cycle the W stage has no completing
@ -57,7 +78,7 @@
#define DPORT_RECORD_PDEBUGINST_CINTL_S 24
#define DPORT_RECORD_PDEBUGINST_CINTL(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_CINTL_S) & DPORT_RECORD_PDEBUGINST_CINTL_V)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGSTATUS ((ASSIST_DEBUG_BASE) +0x4C)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGSTATUS ((ASSIST_DEBUG_BASE) +0x64)
/* register layout:
* BBCAUSE [5..0]: Indicates cause for bubble cycle. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ == 0
* INSNTYPE[5..0]: Indicates type of instruction retiring in the W stage. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ > 0
@ -106,10 +127,12 @@
#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_DEF 0x3C /* Default */
#define ASSIST_DEBUG_PRO_RCD_PDEBUGDATA ((ASSIST_DEBUG_BASE) +0x50)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGPC ((ASSIST_DEBUG_BASE) +0x54)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGLS0STAT ((ASSIST_DEBUG_BASE) +0x58)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGLS0ADDR ((ASSIST_DEBUG_BASE) +0x5C)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGLS0DATA ((ASSIST_DEBUG_BASE) +0x60)
#define ASSIST_DEBUG_PRO_RCD_SP ((ASSIST_DEBUG_BASE) +0x64)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGDATA ((ASSIST_DEBUG_BASE) +0x68)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGPC ((ASSIST_DEBUG_BASE) +0x6C)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGLS0STAT ((ASSIST_DEBUG_BASE) +0x70)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGLS0ADDR ((ASSIST_DEBUG_BASE) +0x74)
#define ASSIST_DEBUG_PRO_RCD_PDEBUGLS0DATA ((ASSIST_DEBUG_BASE) +0x78)
#define ASSIST_DEBUG_PRO_RCD_SP ((ASSIST_DEBUG_BASE) +0x7C)
#define ASSIST_DEBUG_CLOCK_GATE ((ASSIST_DEBUG_BASE) +0x80)
#define ASSIST_DEBUG_REG_DATE ((ASSIST_DEBUG_BASE) +0xFFC)

29
components/soc/esp32s2beta/include/soc/boot_mode.h
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@ -20,7 +20,7 @@
/*SPI Boot*/
#define IS_1XXX(v) (((v)&0x08)==0x08)
/*Download Boot, USB/SDIO/UART0/UART1*/
/*Download Boot, USB/SPI(or SDIO_V2)/UART0/UART1*/
#define IS_00XX(v) (((v)&0x0c)==0x00)
/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/
@ -35,18 +35,18 @@
/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/
#define IS_0011(v) (((v)&0x0f)==0x03)
/*ATE/ANALOG Mode*/
#define IS_0101(v) (((v)&0x0f)==0x05)
/*Diagnostic Mode+UART0 download Mode*/
#define IS_0111(v) (((v)&0x0f)==0x07)
/*legacy SPI Boot*/
#define IS_0100(v) (((v)&0x0f)==0x04)
/*SDIO_Slave download Mode V1.1*/
/*ATE/ANALOG Mode*/
#define IS_0101(v) (((v)&0x0f)==0x05)
/*SPI(or SDIO_V1) download Mode*/
#define IS_0110(v) (((v)&0x0f)==0x06)
/*Diagnostic Mode+UART0 download Mode*/
#define IS_0111(v) (((v)&0x0f)==0x07)
#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG))
@ -60,6 +60,8 @@
/*all faster spi boot including spi*/
#define ETS_IS_FAST_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET())
#if SUPPORT_SDIO_DOWNLOAD
/*all sdio V2 of failing edge input, failing edge output*/
#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_0000(BOOT_MODE_GET())
@ -75,11 +77,17 @@
/*all sdio V1 of raising edge input, failing edge output*/
#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_0110(BOOT_MODE_GET())
/*do not include download mode*/
/*do not include joint download mode*/
#define ETS_IS_SDIO_BOOT() IS_0110(BOOT_MODE_GET())
#else
/*do not include joint download mode*/
#define ETS_IS_SPI_DOWNLOAD_BOOT() IS_0110(BOOT_MODE_GET())
#endif
/*joint download boot*/
#define ETS_IS_USB_SDIO_UART_BOOT() IS_00XX(BOOT_MODE_GET())
#define ETS_IS_JOINT_DOWNLOAD_BOOT() IS_00XX(BOOT_MODE_GET())
/*ATE mode*/
#define ETS_IS_ATE_BOOT() IS_0101(BOOT_MODE_GET())
@ -88,5 +96,6 @@
#define SEL_NO_BOOT 0
#define SEL_SDIO_BOOT BIT0
#define SEL_UART_BOOT BIT1
#define SEL_SPI_SLAVE_BOOT BIT2
#endif /* _SOC_BOOT_MODE_H_ */

139
components/soc/esp32s2beta/include/soc/cache_memory.h Normal file
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@ -0,0 +1,139 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _CACHE_MEMORY_H_
#define _CACHE_MEMORY_H_
#ifdef __cplusplus
extern "C" {
#endif
/*IRAM0 is connected with Cache IBUS0*/
#define IRAM0_ADDRESS_LOW 0x40000000
#define IRAM0_ADDRESS_HIGH 0x40400000
#define IRAM0_CACHE_ADDRESS_LOW 0x40080000
#define IRAM0_CACHE_ADDRESS_HIGH 0x40400000
/*IRAM1 is connected with Cache IBUS1*/
#define IRAM1_ADDRESS_LOW 0x40400000
#define IRAM1_ADDRESS_HIGH 0x40800000
/*DROM0 is connected with Cache IBUS2*/
#define DROM0_ADDRESS_LOW 0x3f000000
#define DROM0_ADDRESS_HIGH 0x3f400000
/*DRAM0 is connected with Cache DBUS0*/
#define DRAM0_ADDRESS_LOW 0x3fc00000
#define DRAM0_ADDRESS_HIGH 0x40000000
#define DRAM0_CACHE_ADDRESS_LOW 0x3fc00000
#define DRAM0_CACHE_ADDRESS_HIGH 0x3ff80000
/*DRAM1 is connected with Cache DBUS1*/
#define DRAM1_ADDRESS_LOW 0x3f800000
#define DRAM1_ADDRESS_HIGH 0x3fc00000
/*DPORT is connected with Cache DBUS2*/
#define DPORT_ADDRESS_LOW 0x3f400000
#define DPORT_ADDRESS_HIGH 0x3f800000
#define DPORT_CACHE_ADDRESS_LOW 0x3f500000
#define DPORT_CACHE_ADDRESS_HIGH 0x3f800000
#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
#define ADDRESS_IN_IRAM1(vaddr) ADDRESS_IN_BUS(IRAM1, vaddr)
#define ADDRESS_IN_DROM0(vaddr) ADDRESS_IN_BUS(DROM0, vaddr)
#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
#define ADDRESS_IN_DRAM1(vaddr) ADDRESS_IN_BUS(DRAM1, vaddr)
#define ADDRESS_IN_DPORT(vaddr) ADDRESS_IN_BUS(DPORT, vaddr)
#define ADDRESS_IN_DPORT_CACHE(vaddr) ADDRESS_IN_BUS(DPORT_CACHE, vaddr)
#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
#define BUS_IRAM1_CACHE_SIZE BUS_SIZE(IRAM1)
#define BUS_IROM0_CACHE_SIZE BUS_SIZE(IROM0)
#define BUS_DROM0_CACHE_SIZE BUS_SIZE(DROM0)
#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
#define BUS_DRAM1_CACHE_SIZE BUS_SIZE(DRAM1)
#define BUS_DPORT_CACHE_SIZE BUS_SIZE(DPORT)
#define PRO_CACHE_IBUS0 0
#define PRO_CACHE_IBUS0_MMU_START 0
#define PRO_CACHE_IBUS0_MMU_END 0x100
#define PRO_CACHE_IBUS1 1
#define PRO_CACHE_IBUS1_MMU_START 0x100
#define PRO_CACHE_IBUS1_MMU_END 0x200
#define PRO_CACHE_IBUS2 2
#define PRO_CACHE_IBUS2_MMU_START 0x200
#define PRO_CACHE_IBUS2_MMU_END 0x300
#define PRO_CACHE_DBUS0 3
#define PRO_CACHE_DBUS0_MMU_START 0x300
#define PRO_CACHE_DBUS0_MMU_END 0x400
#define PRO_CACHE_DBUS1 4
#define PRO_CACHE_DBUS1_MMU_START 0x400
#define PRO_CACHE_DBUS1_MMU_END 0x500
#define PRO_CACHE_DBUS2 5
#define PRO_CACHE_DBUS2_MMU_START 0x500
#define PRO_CACHE_DBUS2_MMU_END 0x600
// #define MMU_SIZE 0x600
#define ICACHE_MMU_SIZE 0x300
#define DCACHE_MMU_SIZE 0x300
#define MMU_BUS_START(i) ((i) * 0x100)
#define MMU_BUS_SIZE 0x100
#define MMU_INVALID BIT(14)
#define MMU_ACCESS_FLASH BIT(15)
#define MMU_ACCESS_SPIRAM BIT(16)
#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t))
#define MMU_TABLE_INVALID_VAL 0x4000
#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
#define MMU_ADDRESS_MASK 0x3fff
#define MMU_PAGE_SIZE 0x10000
#define BUS_ADDR_SIZE 0x400000
#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
#define BUS_NUM_MASK 0x3
#define CACHE_MEMORY_BANK_SIZE 8192
#define CACHE_MEMORY_BANK_NUM 4
#define CACHE_MEMORY_BANK_NUM_MASK 0x3
#define CACHE_MEMORY_LAYOUT_SHIFT 4
#define CACHE_MEMORY_LAYOUT_SHIFT0 0
#define CACHE_MEMORY_LAYOUT_SHIFT1 4
#define CACHE_MEMORY_LAYOUT_SHIFT2 8
#define CACHE_MEMORY_LAYOUT_SHIFT3 12
#define CACHE_MEMORY_LAYOUT_MASK 0xf
#define CACHE_MEMORY_BANK0_ADDR 0x3FFB0000
#define CACHE_MEMORY_BANK1_ADDR 0x3FFB2000
#define CACHE_MEMORY_BANK2_ADDR 0x3FFB4000
#define CACHE_MEMORY_BANK3_ADDR 0x3FFB6000
#ifdef __cplusplus
}
#endif
#endif /*_CACHE_MEMORY_H_ */

187
components/soc/esp32s2beta/include/soc/crypto_dma_reg.h Normal file
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@ -0,0 +1,187 @@
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_CRYPTO_DMA_REG_H_
#define _SOC_CRYPTO_DMA_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
/* CRYPTO_DMA_CONF0 : RO ;bitpos:[31:14] ;default: 18'h0 ; */
/* CONF0_REG_GEN_CLK_EN : RW ;bitpos:[13] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_GEN_CLK_EN (BIT(13))
#define CONF0_REG_GEN_CLK_EN_M (BIT(13))
#define CONF0_REG_GEN_CLK_EN_V 0x1
#define CONF0_REG_GEN_CLK_EN_S 13
/* CONF0_REG_MEM_TRANS_EN: RW ;bitpos:[12] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_MEM_TRANS_EN (BIT(12))
#define CONF0_REG_MEM_TRANS_EN_M (BIT(12))
#define CONF0_REG_MEM_TRANS_EN_V 0x1
#define CONF0_REG_MEM_TRANS_EN_S 12
/* CONF0_REG_OUT_DATA_BURST_EN: RW ;bitpos:[11] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_OUT_DATA_BURST_EN (BIT(11))
#define CONF0_REG_OUT_DATA_BURST_EN_M (BIT(11))
#define CONF0_REG_OUT_DATA_BURST_EN_V 0x1
#define CONF0_REG_OUT_DATA_BURST_EN_S 11
/* CONF0_REG_INDSCR_BURST_EN: RW ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_INDSCR_BURST_EN (BIT(10))
#define CONF0_REG_INDSCR_BURST_EN_M (BIT(10))
#define CONF0_REG_INDSCR_BURST_EN_V 0x1
#define CONF0_REG_INDSCR_BURST_EN_S 10
/* CONF0_REG_OUTDSCR_BURST_EN: RW ;bitpos:[9] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_OUTDSCR_BURST_EN (BIT(9))
#define CONF0_REG_OUTDSCR_BURST_EN_M (BIT(9))
#define CONF0_REG_OUTDSCR_BURST_EN_V 0x1
#define CONF0_REG_OUTDSCR_BURST_EN_S 9
/* CONF0_REG_OUT_EOF_MODE: RW ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_OUT_EOF_MODE (BIT(8))
#define CONF0_REG_OUT_EOF_MODE_M (BIT(8))
#define CONF0_REG_OUT_EOF_MODE_V 0x1
#define CONF0_REG_OUT_EOF_MODE_S 8
/* CONF0_REG_OUT_NO_RESTART_CLR: RW ;bitpos:[7] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_OUT_NO_RESTART_CLR (BIT(7))
#define CONF0_REG_OUT_NO_RESTART_CLR_M (BIT(7))
#define CONF0_REG_OUT_NO_RESTART_CLR_V 0x1
#define CONF0_REG_OUT_NO_RESTART_CLR_S 7
/* CONF0_REG_OUT_AUTO_WRBACK: RW ;bitpos:[6] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_OUT_AUTO_WRBACK (BIT(6))
#define CONF0_REG_OUT_AUTO_WRBACK_M (BIT(6))
#define CONF0_REG_OUT_AUTO_WRBACK_V 0x1
#define CONF0_REG_OUT_AUTO_WRBACK_S 6
/* CONF0_REG_OUT_LOOP_TEST: RW ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_OUT_LOOP_TEST (BIT(5))
#define CONF0_REG_OUT_LOOP_TEST_M (BIT(5))
#define CONF0_REG_OUT_LOOP_TEST_V 0x1
#define CONF0_REG_OUT_LOOP_TEST_S 5
/* CONF0_REG_IN_LOOP_TEST: RW ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_IN_LOOP_TEST (BIT(4))
#define CONF0_REG_IN_LOOP_TEST_M (BIT(4))
#define CONF0_REG_IN_LOOP_TEST_V 0x1
#define CONF0_REG_IN_LOOP_TEST_S 4
/* CONF0_REG_AHBM_RST: RW ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_AHBM_RST (BIT(3))
#define CONF0_REG_AHBM_RST_M (BIT(3))
#define CONF0_REG_AHBM_RST_V 0x1
#define CONF0_REG_AHBM_RST_S 3
/* CONF0_REG_AHBM_FIFO_RST: RW ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_AHBM_FIFO_RST (BIT(2))
#define CONF0_REG_AHBM_FIFO_RST_M (BIT(2))
#define CONF0_REG_AHBM_FIFO_RST_V 0x1
#define CONF0_REG_AHBM_FIFO_RST_S 2
/* CONF0_REG_OUT_RST: RW ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_OUT_RST (BIT(1))
#define CONF0_REG_OUT_RST_M (BIT(1))
#define CONF0_REG_OUT_RST_V 0x1
#define CONF0_REG_OUT_RST_S 1
/* CONF0_REG_IN_RST: RW ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define CONF0_REG_IN_RST (BIT(0))
#define CONF0_REG_IN_RST_M (BIT(0))
#define CONF0_REG_IN_RST_V 0x1
#define CONF0_REG_IN_RST_S 0
/* CRYPTO_DMA_INT_RAW : RO ;bitpos:[31:10] ;default: 22'h0 ; */
/* INT_RAW_OUT_TOTAL_EOF : RW ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
#define INT_RAW_OUT_TOTAL_EOF ( BIT(8))
#define INT_RAW_OUT_TOTAL_EOF_M (BIT(8))
#define INT_RAW_OUT_TOTAL_EOF_V 0x1
#define INT_RAW_OUT_TOTAL_EOF_S 8
/* INT_RAW_IN_SUC_EOF : RW ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define INT_RAW_IN_SUC_EOF ( BIT(1))
#define INT_RAW_IN_SUC_EOF_M (BIT(1))
#define INT_RAW_IN_SUC_EOF_V 0x1
#define INT_RAW_IN_SUC_EOF_S 1
/* CRYPTO_DMA_OUT_LINK : RO ;bitpos:[31] ;default: 1'h0 ; */
/* OUT_LINK_REG_OUTLINK_RESTART : RW ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
#define OUT_LINK_REG_OUTLINK_RESTART ( BIT(30))
#define OUT_LINK_REG_OUTLINK_RESTART_M (BIT(30))
#define OUT_LINK_REG_OUTLINK_RESTART_V 0x1
#define OUT_LINK_REG_OUTLINK_RESTART_S 30
/* OUT_LINK_REG_OUTLINK_START : RW ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
#define OUT_LINK_REG_OUTLINK_START ( BIT(29))
#define OUT_LINK_REG_OUTLINK_START_M (BIT(29))
#define OUT_LINK_REG_OUTLINK_START_V 0x1
#define OUT_LINK_REG_OUTLINK_START_S 29
/* OUT_LINK_REG_OUTLINK_STOP : RW ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
#define OUT_LINK_REG_OUTLINK_STOP ( BIT(28))
#define OUT_LINK_REG_OUTLINK_STOP_M (BIT(28))
#define OUT_LINK_REG_OUTLINK_STOP_V 0x1
#define OUT_LINK_REG_OUTLINK_STOP_S 28
/* OUT_LINK_REG_OUTLINK_ADDR : RW ;bitpos:[19:0] ;default: 20'h0 ; */
/*description: */
#define OUT_LINK_REG_OUTLINK_ADDR 0x000FFFFF
#define OUT_LINK_REG_OUTLINK_ADDR_M (OUT_LINK_REG_OUTLINK_ADDR_V<<OUT_LINK_REG_OUTLINK_ADDR_S)
#define OUT_LINK_REG_OUTLINK_ADDR_V 0xFFFFF
#define OUT_LINK_REG_OUTLINK_ADDR_S 0
/* CRYPTO_DMA_IN_LINK : RO ;bitpos:[31] ;default: 1'h0 ; */
/* IN_LINK_REG_INLINK_RESTART : RW ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
#define IN_LINK_REG_INLINK_RESTART ( BIT(30))
#define IN_LINK_REG_INLINK_RESTART_M (BIT(30))
#define IN_LINK_REG_INLINK_RESTART_V 0x1
#define IN_LINK_REG_INLINK_RESTART_S 30
/* IN_LINK_REG_INLINK_START : RW ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
#define IN_LINK_REG_INLINK_START ( BIT(29))
#define IN_LINK_REG_INLINK_START_M (BIT(29))
#define IN_LINK_REG_INLINK_START_V 0x1
#define IN_LINK_REG_INLINK_START_S 29
/* IN_LINK_REG_INLINK_STOP : RW ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
#define IN_LINK_REG_INLINK_STOP ( BIT(28))
#define IN_LINK_REG_INLINK_STOP_M (BIT(28))
#define IN_LINK_REG_INLINK_STOP_V 0x1
#define IN_LINK_REG_INLINK_STOP_S 28
/* IN_LINK_REG_INLINK_ADDR : RW ;bitpos:[19:0] ;default: 20'h0 ; */
/*description: */
#define IN_LINK_REG_INLINK_ADDR 0x000FFFFF
#define IN_LINK_REG_INLINK_ADDR_M (IN_LINK_REG_INLINK_ADDR_V<<IN_LINK_REG_INLINK_ADDR_S)
#define IN_LINK_REG_INLINK_ADDR_V 0xFFFFF
#define IN_LINK_REG_INLINK_ADDR_S 0
/* CRYPTO_DMA_AES_SHA_SELECT : RO ;bitpos:[31:1] ;default: 31'b0 ; */
/* AES_SHA_SELECT : RW ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define AES_SHA_SELECT ( BIT(0))
#define AES_SHA_SELECT_M (BIT(0))
#define AES_SHA_SELECT_V 0x1
#define AES_SHA_SELECT_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_CRYPTO_DMA_REG_H_ */

155
components/soc/esp32s2beta/include/soc/dport_reg.h
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@ -18,166 +18,11 @@
extern "C" {
#endif
#include"extmem_reg.h"
#include "interrupt_reg.h"
#include "system_reg.h"
#include "sensitive_reg.h"
#include "soc.h"
/*IRAM0 connected with Cache IBUS0*/
#define IRAM0_ADDRESS_LOW 0x40000000
#define IRAM0_ADDRESS_HIGH 0x40400000
#define IRAM0_CACHE_ADDRESS_LOW 0x40080000
#define IRAM0_CACHE_ADDRESS_HIGH 0x40400000
/*IRAM1 and AHB_IBUS1 connected with Cache IBUS1, alternative*/
#define IRAM1_ADDRESS_LOW 0x40400000
#define IRAM1_ADDRESS_HIGH 0x40800000
#define AHB_IBUS1_ADDRESS_LOW 0x60400000
#define AHB_IBUS1_ADDRESS_HIGH 0x60800000
/*IROM0 and AHB_IBUS2 connected with Cache IBUS2, alternative*/
#define IROM0_ADDRESS_LOW 0x40800000
#define IROM0_ADDRESS_HIGH 0x40c00000
#define AHB_IBUS2_ADDRESS_LOW 0x60800000
#define AHB_IBUS2_ADDRESS_HIGH 0x60c00000
/*DROM0 and AHB_IBUS2 connected with Cache IBUS3, alternative*/
/*DROM0 and AHB_DBUS2 connected with Cache DBUS3, alternative*/
#define DROM0_ADDRESS_LOW 0x3f000000
#define DROM0_ADDRESS_HIGH 0x3f400000
#define AHB_IBUS3_ADDRESS_LOW 0x60c00000
#define AHB_IBUS3_ADDRESS_HIGH 0x61000000
#define AHB_DBUS3_ADDRESS_LOW 0x61800000
#define AHB_DBUS3_ADDRESS_HIGH 0x61c00000
/*DRAM0 and AHB_DBUS2 connected with Cache DBUS0, alternative*/
#define DRAM0_ADDRESS_LOW 0x3fc00000
#define DRAM0_ADDRESS_HIGH 0x40000000
#define DRAM0_CACHE_ADDRESS_LOW 0x3fc00000
#define DRAM0_CACHE_ADDRESS_HIGH 0x3ff90000
#define AHB_DBUS0_ADDRESS_LOW 0x61000000
#define AHB_DBUS0_ADDRESS_HIGH 0x61400000
/*DRAM1 connected with Cache DBUS1*/
#define DRAM1_ADDRESS_LOW 0x3f800000
#define DRAM1_ADDRESS_HIGH 0x3fc00000
/*DPORT and AHB_DBUS2 connected with Cache DBUS2, alternative*/
#define DPORT_ADDRESS_LOW 0x3f400000
#define DPORT_ADDRESS_HIGH 0x3f800000
#define DPORT_CACHE_ADDRESS_LOW 0x3f500000
#define DPORT_CACHE_ADDRESS_HIGH 0x3f800000
#define AHB_DBUS2_ADDRESS_LOW 0x61400000
#define AHB_DBUS2_ADDRESS_HIGH 0x61800000
#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
#define ADDRESS_IN_IRAM1(vaddr) ADDRESS_IN_BUS(IRAM1, vaddr)
#define ADDRESS_IN_AHB_IBUS1(vaddr) ADDRESS_IN_BUS(AHB_IBUS1, vaddr)
#define ADDRESS_IN_IROM0(vaddr) ADDRESS_IN_BUS(IROM0, vaddr)
#define ADDRESS_IN_AHB_IBUS2(vaddr) ADDRESS_IN_BUS(AHB_IBUS2, vaddr)
#define ADDRESS_IN_DROM0(vaddr) ADDRESS_IN_BUS(DROM0, vaddr)
#define ADDRESS_IN_AHB_IBUS3(vaddr) ADDRESS_IN_BUS(AHB_IBUS3, vaddr)
#define ADDRESS_IN_AHB_DBUS3(vaddr) ADDRESS_IN_BUS(AHB_DBUS3, vaddr)
#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
#define ADDRESS_IN_AHB_DBUS0(vaddr) ADDRESS_IN_BUS(AHB_DBUS0, vaddr)
#define ADDRESS_IN_DRAM1(vaddr) ADDRESS_IN_BUS(DRAM1, vaddr)
#define ADDRESS_IN_DPORT(vaddr) ADDRESS_IN_BUS(DPORT, vaddr)
#define ADDRESS_IN_DPORT_CACHE(vaddr) ADDRESS_IN_BUS(DPORT_CACHE, vaddr)
#define ADDRESS_IN_AHB_DBUS2(vaddr) ADDRESS_IN_BUS(AHB_DBUS2, vaddr)
#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
#define BUS_IRAM1_CACHE_SIZE BUS_SIZE(IRAM1)
#define BUS_IROM0_CACHE_SIZE BUS_SIZE(IROM0)
#define BUS_DROM0_CACHE_SIZE BUS_SIZE(DROM0)
#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
#define BUS_DRAM1_CACHE_SIZE BUS_SIZE(DRAM1)
#define BUS_DPORT_CACHE_SIZE BUS_SIZE(DPORT)
#define BUS_AHB_IBUS1_CACHE_SIZE BUS_SIZE(AHB_IBUS1)
#define BUS_AHB_IBUS2_CACHE_SIZE BUS_SIZE(AHB_IBUS2)
#define BUS_AHB_IBUS3_CACHE_SIZE BUS_SIZE(AHB_IBUS3)
#define BUS_AHB_DBUS0_CACHE_SIZE BUS_SIZE(AHB_DBUS0)
#define BUS_AHB_DBUS2_CACHE_SIZE BUS_SIZE(AHB_DBUS2)
#define BUS_AHB_DBUS3_CACHE_SIZE BUS_SIZE(AHB_DBUS3)
#define PRO_CACHE_IBUS0 0
#define PRO_CACHE_IBUS0_MMU_START 0
#define PRO_CACHE_IBUS0_MMU_END 0x100
#define PRO_CACHE_IBUS1 1
#define PRO_CACHE_IBUS1_MMU_START 0x100
#define PRO_CACHE_IBUS1_MMU_END 0x200
#define PRO_CACHE_IBUS2 2
#define PRO_CACHE_IBUS2_MMU_START 0x200
#define PRO_CACHE_IBUS2_MMU_END 0x300
#define PRO_CACHE_IBUS3 3
#define PRO_CACHE_IBUS3_MMU_START 0x300
#define PRO_CACHE_IBUS3_MMU_END 0x400
#define PRO_CACHE_DBUS0 4
#define PRO_CACHE_DBUS0_MMU_START 0x400
#define PRO_CACHE_DBUS0_MMU_END 0x500
#define PRO_CACHE_DBUS1 5
#define PRO_CACHE_DBUS1_MMU_START 0x500
#define PRO_CACHE_DBUS1_MMU_END 0x600
#define PRO_CACHE_DBUS2 6
#define PRO_CACHE_DBUS2_MMU_START 0x600
#define PRO_CACHE_DBUS2_MMU_END 0x700
#define PRO_CACHE_DBUS3 7
#define PRO_CACHE_DBUS3_MMU_START 0x700
#define PRO_CACHE_DBUS3_MMU_END 0x800
#define DPORT_MMU_SIZE 0x800
#define DPORT_ICACHE_MMU_SIZE 0x400
#define DPORT_DCACHE_MMU_SIZE 0x400
#define DPORT_MMU_BUS_START(i) ((i) * 0x100)
#define DPORT_MMU_BUS_SIZE 0x100
#define DPORT_MMU_INVALID BIT(14)
#define DPORT_MMU_ACCESS_FLASH BIT(15)
#define DPORT_MMU_ACCESS_SPIRAM BIT(16)
/* Flash MMU table for PRO CPU */
#define DPORT_PRO_FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
#define DPORT_FLASH_MMU_TABLE_SIZE (DPORT_ICACHE_MMU_SIZE/sizeof(uint32_t))
#define DPORT_MMU_TABLE_INVALID_VAL 0x4000
#define DPORT_FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
#define DPORT_MMU_ADDRESS_MASK 0x3fff
#define BUS_ADDR_SIZE 0x400000
#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
#define BUS_NUM_MASK 0x3
#define CACHE_MEMORY_BLOCK_SIZE 8192
#define CACHE_MEMORY_BLOCK_NUM 4
#define CACHE_MEMORY_BLOCK_NUM_MASK 0x3
#define CACHE_MEMORY_LAYOUT_SHIFT 4
#define CACHE_MEMORY_LAYOUT_SHIFT0 0
#define CACHE_MEMORY_LAYOUT_SHIFT1 4
#define CACHE_MEMORY_LAYOUT_SHIFT2 8
#define CACHE_MEMORY_LAYOUT_SHIFT3 12
#define CACHE_MEMORY_LAYOUT_MASK 0xf
#define CACHE_MEMORY_BLOCK0_ADDR 0x40020000
#define CACHE_MEMORY_BLOCK1_ADDR 0x40022000
#define CACHE_MEMORY_BLOCK2_ADDR 0x40024000
#define CACHE_MEMORY_BLOCK3_ADDR 0x40026000
#define DPORT_DATE_REG SYSTEM_DATE_REG
#ifndef __ASSEMBLER__

2494
components/soc/esp32s2beta/include/soc/efuse_reg.h
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645
components/soc/esp32s2beta/include/soc/efuse_struct.h
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@ -18,189 +18,388 @@ extern "C" {
#endif
typedef volatile struct {
uint32_t pgm_data0; /**/
union {
struct {
uint32_t rd_efuse_wr_dis: 16;
uint32_t rd_efuse_rd_dis: 4;
uint32_t rd_flash_crypt_cnt: 8;
uint32_t reserved28: 4;
};
uint32_t val;
} blk0_rdata0;
uint32_t blk0_rdata1; /**/
union {
struct {
uint32_t rd_wifi_mac_crc_high:24;
uint32_t reserved24: 8;
};
uint32_t val;
} blk0_rdata2;
union {
struct {
uint32_t rd_soft_disable_jtag: 1;
uint32_t rd_chip_ver_dis_bt: 1;
uint32_t rd_chip_ver_32pad: 1;
uint32_t rd_chip_ver_dis_cache: 1;
uint32_t rd_chip_ver_reserve: 13;
uint32_t reserved17: 15;
};
uint32_t val;
} blk0_rdata3;
union {
struct {
uint32_t rd_ck8m_freq: 8;
uint32_t rd_sdio_drefh: 2;
uint32_t rd_sdio_drefm: 2;
uint32_t rd_sdio_drefl: 2;
uint32_t rd_xpd_sdio: 1;
uint32_t rd_sdio_tieh: 1;
uint32_t rd_sdio_force: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} blk0_rdata4;
union {
struct {
uint32_t rd_spi_pad_config: 20;
uint32_t rd_tsens_dos: 4;
uint32_t rd_reserve_use1: 4;
uint32_t rd_flash_crypt_config: 4;
};
uint32_t val;
} blk0_rdata5;
union {
struct {
uint32_t rd_coding_scheme: 2;
uint32_t rd_dig_reserve: 1;
uint32_t rd_disable_sdio_host: 1;
uint32_t rd_abs_done_0: 1;
uint32_t rd_abs_done_1: 1;
uint32_t rd_hard_disable_jtag: 1;
uint32_t rd_disable_dl_encrypt: 1;
uint32_t rd_disable_dl_decrypt: 1;
uint32_t rd_disable_dl_cache: 1;
uint32_t rd_key_status: 1;
uint32_t reserved11: 21;
};
uint32_t val;
} blk0_rdata6;
union {
struct {
uint32_t wr_dis: 16;
uint32_t rd_dis: 4;
uint32_t flash_crypt_cnt: 8;
uint32_t reserved28: 4;
};
uint32_t val;
} blk0_wdata0;
uint32_t blk0_wdata1; /**/
union {
struct {
uint32_t wifi_mac_crc_high:24;
uint32_t reserved24: 8;
};
uint32_t val;
} blk0_wdata2;
union {
struct {
uint32_t soft_disable_jtag: 1;
uint32_t chip_ver_dis_bt: 1;
uint32_t chip_ver_32pad: 1;
uint32_t chip_ver_dis_cache: 1;
uint32_t chip_ver_reserve: 13;
uint32_t reserved17: 15;
};
uint32_t val;
} blk0_wdata3;
union {
struct {
uint32_t ck8m_freq: 8;
uint32_t rd_dis: 7;
uint32_t dis_rtc_ram_boot: 1;
uint32_t dis_icache: 1;
uint32_t dis_dcache: 1;
uint32_t dis_download_icache: 1;
uint32_t dis_download_dcache: 1;
uint32_t dis_force_download: 1;
uint32_t dis_usb: 1;
uint32_t dis_can: 1;
uint32_t dis_sdio_access: 1;
uint32_t dis_efuse_ate_wr: 1;
uint32_t soft_dis_jtag: 1;
uint32_t hard_dis_jtag: 1;
uint32_t dis_download_manual_encrypt: 1;
uint32_t usb_drefh: 2;
uint32_t usb_drefl: 2;
uint32_t usb_exchg_pins: 1;
uint32_t ext_phy_enable: 1;
uint32_t usb_force_b: 1;
uint32_t usb_dres: 2;
uint32_t sdio_modecurlim: 1;
uint32_t sdio_drefh: 2;
};
uint32_t val;
} pgm_data1;
union {
struct {
uint32_t sdio_drefm: 2;
uint32_t sdio_drefl: 2;
uint32_t xpd_sdio: 1;
uint32_t sdio_xpd: 1;
uint32_t sdio_tieh: 1;
uint32_t sdio_force: 1;
uint32_t reserved17:15;
uint32_t sdio_en_init: 1;
uint32_t sdio_encurlim: 1;
uint32_t sdio_dcurlim: 3;
uint32_t sdio_init: 2;
uint32_t sdio_dcap: 2;
uint32_t wdt_delay_sel: 2;
uint32_t spi_boot_crypt_cnt: 3;
uint32_t secure_boot_key_revoke0: 1;
uint32_t secure_boot_key_revoke1: 1;
uint32_t secure_boot_key_revoke2: 1;
uint32_t key_purpose_0: 4;
uint32_t key_purpose_1: 4;
};
uint32_t val;
} blk0_wdata4;
} pgm_data2;
union {
struct {
uint32_t spi_pad_config: 20;
uint32_t tsens_dos: 4;
uint32_t reserve_use1: 4;
uint32_t flash_crypt_config: 4;
uint32_t key_purpose_2: 4;
uint32_t key_purpose_3: 4;
uint32_t key_purpose_4: 4;
uint32_t key_purpose_5: 4;
uint32_t key_purpose_6: 4;
uint32_t secure_boot_en: 1;
uint32_t secure_boot_aggressive_revoke: 1;
uint32_t xtal_freq: 6;
uint32_t flash_tpuw: 4;
};
uint32_t val;
} blk0_wdata5;
} pgm_data3;
union {
struct {
uint32_t coding_scheme: 2;
uint32_t dig_reserve: 1;
uint32_t disable_sdio_host: 1;
uint32_t abs_done_0: 1;
uint32_t abs_done_1: 1;
uint32_t hard_disable_jtag: 1;
uint32_t disable_dl_encrypt: 1;
uint32_t disable_dl_decrypt: 1;
uint32_t disable_dl_cache: 1;
uint32_t key_status: 1;
uint32_t reserved11: 21;
uint32_t dis_download_mode: 1;
uint32_t dis_legacy_spi_boot: 1;
uint32_t uart_print_channel: 1;
uint32_t dis_tiny_basic: 1;
uint32_t dis_usb_download_mode: 1;
uint32_t enable_security_download: 1;
uint32_t uart_print_control: 2;
uint32_t reserve: 24;
};
uint32_t val;
} blk0_wdata6;
uint32_t blk1_rdata0; /**/
uint32_t blk1_rdata1; /**/
uint32_t blk1_rdata2; /**/
uint32_t blk1_rdata3; /**/
uint32_t blk1_rdata4; /**/
uint32_t blk1_rdata5; /**/
uint32_t blk1_rdata6; /**/
uint32_t blk1_rdata7; /**/
uint32_t blk2_rdata0; /**/
uint32_t blk2_rdata1; /**/
uint32_t blk2_rdata2; /**/
uint32_t blk2_rdata3; /**/
uint32_t blk2_rdata4; /**/
uint32_t blk2_rdata5; /**/
uint32_t blk2_rdata6; /**/
uint32_t blk2_rdata7; /**/
uint32_t blk3_rdata0; /**/
uint32_t blk3_rdata1; /**/
uint32_t blk3_rdata2; /**/
uint32_t blk3_rdata3; /**/
uint32_t blk3_rdata4; /**/
uint32_t blk3_rdata5; /**/
uint32_t blk3_rdata6; /**/
uint32_t blk3_rdata7; /**/
uint32_t blk1_wdata0; /**/
uint32_t blk1_wdata1; /**/
uint32_t blk1_wdata2; /**/
uint32_t blk1_wdata3; /**/
uint32_t blk1_wdata4; /**/
uint32_t blk1_wdata5; /**/
uint32_t blk1_wdata6; /**/
uint32_t blk1_wdata7; /**/
uint32_t blk2_wdata0; /**/
uint32_t blk2_wdata1; /**/
uint32_t blk2_wdata2; /**/
uint32_t blk2_wdata3; /**/
uint32_t blk2_wdata4; /**/
uint32_t blk2_wdata5; /**/
uint32_t blk2_wdata6; /**/
uint32_t blk2_wdata7; /**/
uint32_t blk3_wdata0; /**/
uint32_t blk3_wdata1; /**/
uint32_t blk3_wdata2; /**/
uint32_t blk3_wdata3; /**/
uint32_t blk3_wdata4; /**/
uint32_t blk3_wdata5; /**/
uint32_t blk3_wdata6; /**/
uint32_t blk3_wdata7; /**/
} pgm_data4;
union {
struct {
uint32_t reserved0: 16;
uint32_t chip_version:24;
uint32_t rs_data_23: 8;
};
uint32_t val;
} pgm_data5;
uint32_t pgm_data6; /**/
uint32_t pgm_data7; /**/
uint32_t pgm_check_value0; /**/
uint32_t pgm_check_value1; /**/
uint32_t pgm_check_value2; /**/
uint32_t rd_wr_dis; /**/
union {
struct {
uint32_t rd_dis: 7;
uint32_t dis_rtc_ram_boot: 1;
uint32_t dis_icache: 1;
uint32_t dis_dcache: 1;
uint32_t dis_download_icache: 1;
uint32_t dis_download_dcache: 1;
uint32_t dis_force_download: 1;
uint32_t dis_usb: 1;
uint32_t dis_can: 1;
uint32_t dis_sdio_access: 1;
uint32_t dis_ate_wr: 1;
uint32_t soft_dis_jtag: 1;
uint32_t hard_dis_jtag: 1;
uint32_t dis_download_manual_encrypt: 1;
uint32_t usb_drefh: 2;
uint32_t usb_drefl: 2;
uint32_t usb_exchg_pins: 1;
uint32_t ext_phy_enable: 1;
uint32_t usb_force_b: 1;
uint32_t usb_dres: 2;
uint32_t sdio_modecurlim: 1;
uint32_t sdio_drefh: 2;
};
uint32_t val;
} rd_repeat_data0;
union {
struct {
uint32_t sdio_drefm: 2;
uint32_t sdio_drefl: 2;
uint32_t sdio_xpd: 1;
uint32_t sdio_tieh: 1;
uint32_t sdio_force: 1;
uint32_t sdio_en_init: 1;
uint32_t sdio_encurlim: 1;
uint32_t sdio_dcurlim: 3;
uint32_t sdio_init: 2;
uint32_t eufse_sdio_dcap: 2;
uint32_t wdt_delay_sel: 2;
uint32_t spi_boot_crypt_cnt: 3;
uint32_t secure_boot_key_revoke0: 1;
uint32_t secure_boot_key_revoke1: 1;
uint32_t secure_boot_key_revoke2: 1;
uint32_t key_purpose_0: 4;
uint32_t key_purpose_1: 4;
};
uint32_t val;
} rd_repeat_data1;
union {
struct {
uint32_t key_purpose_2: 4;
uint32_t key_purpose_3: 4;
uint32_t key_purpose_4: 4;
uint32_t key_purpose_5: 4;
uint32_t key_purpose_6: 4;
uint32_t secure_boot_en: 1;
uint32_t secure_boot_aggressive_revoke: 1;
uint32_t xtal_freq: 6;
uint32_t flash_tpuw: 4;
};
uint32_t val;
} rd_repeat_data2;
union {
struct {
uint32_t dis_download_mode: 1;
uint32_t dis_legacy_spi_boot: 1;
uint32_t uart_print_channel: 1;
uint32_t dis_tiny_basic: 1;
uint32_t dis_usb_download_mode: 1;
uint32_t enable_security_download: 1;
uint32_t uart_print_control: 2;
uint32_t reserve: 24;
};
uint32_t val;
} rd_repeat_data3;
union {
struct {
uint32_t chip_version:24;
uint32_t reserved24: 8;
};
uint32_t val;
} rd_repeat_data4;
uint32_t rd_mac_spi_8m_0; /**/
union {
struct {
uint32_t mac_1: 16;
uint32_t spi_pad_conf_0:16;
};
uint32_t val;
} rd_mac_spi_8m_1;
union {
struct {
uint32_t spi_pad_conf_1:20;
uint32_t clk8m_freq: 12;
};
uint32_t val;
} rd_mac_spi_8m_2;
uint32_t rd_mac_spi_8m_3; /**/
uint32_t rd_mac_spi_8m_4; /**/
uint32_t rd_mac_spi_8m_5; /**/
uint32_t rd_sys_data0; /**/
uint32_t rd_sys_data1; /**/
uint32_t rd_sys_data2; /**/
uint32_t rd_sys_data3; /**/
uint32_t rd_sys_data4; /**/
uint32_t rd_sys_data5; /**/
uint32_t rd_sys_data6; /**/
uint32_t rd_sys_data7; /**/
uint32_t rd_usr_data0; /**/
uint32_t rd_usr_data1; /**/
uint32_t rd_usr_data2; /**/
uint32_t rd_usr_data3; /**/
uint32_t rd_usr_data4; /**/
uint32_t rd_usr_data5; /**/
uint32_t rd_usr_data6; /**/
uint32_t rd_usr_data7; /**/
uint32_t rd_key0_data0; /**/
uint32_t rd_key0_data1; /**/
uint32_t rd_key0_data2; /**/
uint32_t rd_key0_data3; /**/
uint32_t rd_key0_data4; /**/
uint32_t rd_key0_data5; /**/
uint32_t rd_key0_data6; /**/
uint32_t rd_key0_data7; /**/
uint32_t rd_key1_data0; /**/
uint32_t rd_key1_data1; /**/
uint32_t rd_key1_data2; /**/
uint32_t rd_key1_data3; /**/
uint32_t rd_key1_data4; /**/
uint32_t rd_key1_data5; /**/
uint32_t rd_key1_data6; /**/
uint32_t rd_key1_data7; /**/
uint32_t rd_key2_data0; /**/
uint32_t rd_key2_data1; /**/
uint32_t rd_key2_data2; /**/
uint32_t rd_key2_data3; /**/
uint32_t rd_key2_data4; /**/
uint32_t rd_key2_data5; /**/
uint32_t rd_key2_data6; /**/
uint32_t rd_key2_data7; /**/
uint32_t rd_key3_data0; /**/
uint32_t rd_key3_data1; /**/
uint32_t rd_key3_data2; /**/
uint32_t rd_key3_data3; /**/
uint32_t rd_key3_data4; /**/
uint32_t rd_key3_data5; /**/
uint32_t rd_key3_data6; /**/
uint32_t rd_key3_data7; /**/
uint32_t rd_key4_data0; /**/
uint32_t rd_key4_data1; /**/
uint32_t rd_key4_data2; /**/
uint32_t rd_key4_data3; /**/
uint32_t rd_key4_data4; /**/
uint32_t rd_key4_data5; /**/
uint32_t rd_key4_data6; /**/
uint32_t rd_key4_data7; /**/
uint32_t rd_key5_data0; /**/
uint32_t rd_key5_data1; /**/
uint32_t rd_key5_data2; /**/
uint32_t rd_key5_data3; /**/
uint32_t rd_key5_data4; /**/
uint32_t rd_key5_data5; /**/
uint32_t rd_key5_data6; /**/
uint32_t rd_key5_data7; /**/
uint32_t rd_key6_data0; /**/
uint32_t rd_key6_data1; /**/
uint32_t rd_key6_data2; /**/
uint32_t rd_key6_data3; /**/
uint32_t rd_key6_data4; /**/
uint32_t rd_key6_data5; /**/
uint32_t rd_key6_data6; /**/
uint32_t rd_key6_data7; /**/
union {
struct {
uint32_t rd_rd_dis_err: 7;
uint32_t rd_dis_rtc_ram_boot_err: 1;
uint32_t rd_dis_icache_err: 1;
uint32_t rd_dis_dcache_err: 1;
uint32_t rd_dis_download_icache_err: 1;
uint32_t rd_dis_download_dcache_err: 1;
uint32_t rd_dis_force_download: 1;
uint32_t rd_dis_usb_err: 1;
uint32_t rd_dis_can_err: 1;
uint32_t rd_dis_sdio_access_err: 1;
uint32_t rd_dis_efuse_ate_wr_err: 1;
uint32_t rd_soft_dis_jtag_err: 1;
uint32_t rd_hard_dis_jtag_err: 1;
uint32_t rd_dis_download_manual_encrypt_err: 1;
uint32_t rd_usb_drefh_err: 2;
uint32_t rd_usb_drefl_err: 2;
uint32_t rd_usb_exchg_pins_err: 1;
uint32_t rd_ext_phy_enable: 1;
uint32_t rd_usb_force: 1;
uint32_t rd_usb_dres_err: 2;
uint32_t rd_sdio_modecurlim_err: 1;
uint32_t rd_sdio_drefh_err: 2;
};
uint32_t val;
} rd_repeat_err0;
union {
struct {
uint32_t rd_sdio_drefm_err: 2;
uint32_t rd_sdio_drefl_err: 2;
uint32_t rd_sdio_xpd_err: 1;
uint32_t rd_sdio_tieh_err: 1;
uint32_t rd_sdio_force_err: 1;
uint32_t rd_sdio_en_init_err: 1;
uint32_t rd_sdio_encurlim_err: 1;
uint32_t rd_sdio_dcurlim_err: 3;
uint32_t rd_sdio_init_err: 2;
uint32_t rd_sdio_dcap_err: 2;
uint32_t rd_wdt_delay_sel_err: 2;
uint32_t rd_spi_boot_crypt_cnt_err: 3;
uint32_t rd_secure_boot_key_revoke0_err: 1;
uint32_t rd_secure_boot_key_revoke1_err: 1;
uint32_t rd_secure_boot_key_revoke2_err: 1;
uint32_t rd_key_purpose_0_err: 4;
uint32_t rd_key_purpose_1_err: 4;
};
uint32_t val;
} rd_repeat_err1;
union {
struct {
uint32_t rd_key_purpose_2_err: 4;
uint32_t rd_key_purpose_3_err: 4;
uint32_t rd_key_purpose_4_err: 4;
uint32_t rd_key_purpose_5_err: 4;
uint32_t rd_key_purpose_6_err: 4;
uint32_t rd_secure_boot_en_err: 1;
uint32_t rd_secure_boot_aggressive_revoke_err: 1;
uint32_t rd_xtal_freq_err: 6;
uint32_t rd_flash_tpuw_err: 4;
};
uint32_t val;
} rd_repeat_err2;
union {
struct {
uint32_t rd_dis_download_mode_err: 1;
uint32_t rd_dis_legacy_spi_boot_err: 1;
uint32_t rd_uart_print_channel: 1;
uint32_t rd_dis_tiny_basic: 1;
uint32_t rd_dis_usb_download_mode: 1;
uint32_t rd_enable_security_download: 1;
uint32_t rd_uart_print_control: 2;
uint32_t rd_reserve_err: 24;
};
uint32_t val;
} rd_repeat_err3;
uint32_t reserved_18c;
union {
struct {
uint32_t rd_chip_version_err:24;
uint32_t reserved24: 8;
};
uint32_t val;
} rd_repeat_err4;
union {
struct {
uint32_t rd_mac_spi_8m_err_num: 3;
uint32_t rd_mac_spi_8m_fail: 1;
uint32_t rd_sys_err_num: 3;
uint32_t rd_sys_err_fail: 1;
uint32_t rd_usr_data_err_num: 3;
uint32_t rd_usr_data_fail: 1;
uint32_t rd_key0_err_num: 3;
uint32_t rd_key0_fail: 1;
uint32_t rd_key1_err_num: 3;
uint32_t rd_key1_fail: 1;
uint32_t rd_key2_err_num: 3;
uint32_t rd_key2_fail: 1;
uint32_t rd_key3_err_num: 3;
uint32_t rd_key3_fail: 1;
uint32_t rd_key4_err_num: 3;
uint32_t rd_key4_fail: 1;
};
uint32_t val;
} rd_rs_err0;
union {
struct {
uint32_t rd_key5_err_num: 3;
uint32_t rd_key5_fail: 1;
uint32_t rd_key6_err_num: 3;
uint32_t rd_key6_fail: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} rd_rs_err1;
union {
struct {
uint32_t mem_pd: 1;
uint32_t reserved1: 15;
uint32_t clk_en: 1;
uint32_t reserved17:15;
};
@ -209,17 +408,30 @@ typedef volatile struct {
union {
struct {
uint32_t op_code: 16;
uint32_t force_no_wr_rd_dis: 1;
uint32_t reserved17: 15;
uint32_t reserved16:16;
};
uint32_t val;
} conf;
uint32_t status; /**/
union {
struct {
uint32_t state: 3;
uint32_t otp_load_sw: 1;
uint32_t otp_vddq_c_sync2: 1;
uint32_t otp_strobe_sw: 1;
uint32_t otp_csb_sw: 1;
uint32_t otp_pgenb_sw: 1;
uint32_t otp_vddq_is_sw: 1;
uint32_t repeat_err_cnt: 8;
uint32_t reserved17: 15;
};
uint32_t val;
} status;
union {
struct {
uint32_t read_cmd: 1;
uint32_t pgm_cmd: 1;
uint32_t reserved2: 30;
uint32_t blk_num: 4;
uint32_t reserved6: 26;
};
uint32_t val;
} cmd;
@ -263,13 +475,6 @@ typedef volatile struct {
};
uint32_t val;
} dac_conf;
union {
struct {
uint32_t dec_warnings:12;
uint32_t reserved12: 20;
};
uint32_t val;
} dec_status;
union {
struct {
uint32_t thr_a: 8;
@ -295,96 +500,6 @@ typedef volatile struct {
};
uint32_t val;
} wr_tim_conf1;
union {
struct {
uint32_t rd_dis_err: 4;
uint32_t chip_ver_reserve_err:13;
uint32_t ck8m_freq_err: 8;
uint32_t sdio_drefh_err: 2;
uint32_t sdio_drefm_err: 2;
uint32_t sdio_drefl_err: 2;
uint32_t key_status_err: 1;
};
uint32_t val;
} repeat_err0;
union {
struct {
uint32_t spi_pad_config_err: 20;
uint32_t flash_crypt_config_err: 4;
uint32_t tsens_dos_err: 4;
uint32_t reserve_use1_err: 4;
};
uint32_t val;
} repeat_err1;
union {
struct {
uint32_t abs_done_0_err: 1;
uint32_t abs_done_1_err: 1;
uint32_t hard_disable_jtag_err: 1;
uint32_t disable_dl_encrypt_err: 1;
uint32_t disable_dl_decrypt_err: 1;
uint32_t disable_dl_cache_err: 1;
uint32_t disable_sdio_host_err: 1;
uint32_t dig_reserve_err: 1;
uint32_t soft_disable_jtag_err: 1;
uint32_t chip_ver_dis_bt_err: 1;
uint32_t chip_ver_32pad_err: 1;
uint32_t chip_ver_dis_cache_err: 1;
uint32_t xpd_sdio_err: 1;
uint32_t sdio_tieh_err: 1;
uint32_t sdio_force_err: 1;
uint32_t reserved15: 17;
};
uint32_t val;
} repeat_err2;
uint32_t repeat_blk1_err0; /**/
uint32_t repeat_blk1_err1; /**/
uint32_t repeat_blk1_err2; /**/
uint32_t repeat_blk1_err3; /**/
uint32_t repeat_blk2_err0; /**/
uint32_t repeat_blk2_err1; /**/
uint32_t repeat_blk2_err2; /**/
uint32_t repeat_blk2_err3; /**/
uint32_t repeat_blk3_err0; /**/
uint32_t repeat_blk3_err1; /**/
uint32_t repeat_blk3_err2; /**/
uint32_t repeat_blk3_err3; /**/
union {
struct {
uint32_t rs_errornum_blk1: 4;
uint32_t rs_fail_blk1: 1;
uint32_t rs_errornum_blk2: 4;
uint32_t rs_fail_blk2: 1;
uint32_t rs_errornum_blk3: 4;
uint32_t rs_fail_blk3: 1;
uint32_t reserved15: 17;
};
uint32_t val;
} rs_state;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;

3058
components/soc/esp32s2beta/include/soc/extmem_reg.h
View File

File diff suppressed because it is too large Load Diff

6
components/soc/esp32s2beta/include/soc/gpio_reg.h
View File

@ -83,7 +83,7 @@ extern "C" {
/* GPIO_OUT1_DATA : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: */
#define GPIO_OUT1_DATA 0x003FFFFF
#define GPIO_OUT1_DATA_M ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S))
#define GPIO_OUT1_DATA_M ((GPIO_OUT1_DATA_V)<<(GPIO_OUT1_DATA_S))
#define GPIO_OUT1_DATA_V 0x3FFFFF
#define GPIO_OUT1_DATA_S 0
@ -2664,7 +2664,7 @@ extern "C" {
#define GPIO_STATUS_INTERRUPT_NEXT_S 0
#define GPIO_STATUS_NEXT1_REG (DR_REG_GPIO_BASE + 0x150)
/* GPIO_STATUS_INTERRUPT_NEXT : RO ;bitpos:[21:0] ;default: 22'h0 ; */
/* GPIO_STATUS_INTERRUPT_NEXT1 : RO ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: */
#define GPIO_STATUS_INTERRUPT_NEXT1 0x003FFFFF
#define GPIO_STATUS_INTERRUPT_NEXT1_M ((GPIO_STATUS_INTERRUPT_NEXT1_V)<<(GPIO_STATUS_INTERRUPT_NEXT1_S))
@ -9204,7 +9204,7 @@ extern "C" {
#define GPIO_CLK_EN_S 0
#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0x6FC)
/* GPIO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1809040 ; */
/* GPIO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905061 ; */
/*description: */
#define GPIO_DATE 0x0FFFFFFF
#define GPIO_DATE_M ((GPIO_DATE_V)<<(GPIO_DATE_S))

95
components/soc/esp32s2beta/include/soc/gpio_sig_map.h
View File

@ -4,8 +4,18 @@
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_GPIO_SIG_MAP_H_
#define _SOC_GPIO_SIG_MAP_H_
#define SPICLK_OUT_IDX SPICLK_OUT_MUX_IDX
#define CLK_I2S_IDX CLK_I2S_MUX_IDX
#define FSPICLK_OUT_IDX FSPICLK_OUT_MUX_IDX
#define SPIQ_IN_IDX 0
#define SPIQ_OUT_IDX 0
@ -18,9 +28,16 @@
#define SPICLK_OUT_MUX_IDX 4
#define SPICS0_OUT_IDX 5
#define SPICS1_OUT_IDX 6
#define FSPICD_OUT_IDX 9
#define SPI3_CD_OUT_IDX 10
#define SPI4_CD_OUT_IDX 11
#define SPID4_IN_IDX 7
#define SPID4_OUT_IDX 7
#define SPID5_IN_IDX 8
#define SPID5_OUT_IDX 8
#define SPID6_IN_IDX 9
#define SPID6_OUT_IDX 9
#define SPID7_IN_IDX 10
#define SPID7_OUT_IDX 10
#define SPIDQS_IN_IDX 11
#define SPIDQS_OUT_IDX 11
#define U0RXD_IN_IDX 14
#define U0TXD_OUT_IDX 14
#define U0CTS_IN_IDX 15
@ -146,32 +163,31 @@
#define GPIO_SD5_OUT_IDX 105
#define GPIO_SD6_OUT_IDX 106
#define GPIO_SD7_OUT_IDX 107
#define SPI4_CLK_IN_IDX 108
#define SPI4_CLK_OUT_MUX_IDX 108
#define SPI4_Q_IN_IDX 109
#define SPI4_Q_OUT_IDX 109
#define SPI4_D_IN_IDX 110
#define SPI4_D_OUT_IDX 110
#define SPI4_HD_IN_IDX 111
#define SPI4_HD_OUT_IDX 111
#define SPI4_CS0_IN_IDX 112
#define SPI4_CS0_OUT_IDX 112
#define SPI4_CS1_OUT_IDX 113
#define SPI4_CS2_OUT_IDX 114
#define FSPICLK_IN_IDX 115
#define FSPICLK_OUT_MUX_IDX 115
#define FSPIQ_IN_IDX 116
#define FSPIQ_OUT_IDX 116
#define FSPID_IN_IDX 117
#define FSPID_OUT_IDX 117
#define FSPIHD_IN_IDX 118
#define FSPIHD_OUT_IDX 118
#define FSPIWP_IN_IDX 119
#define FSPIWP_OUT_IDX 119
#define FSPICS0_IN_IDX 120
#define FSPICS0_OUT_IDX 120
#define FSPICS1_OUT_IDX 121
#define FSPICS2_OUT_IDX 122
#define FSPICLK_IN_IDX 108
#define FSPICLK_OUT_MUX_IDX 108
#define FSPIQ_IN_IDX 109
#define FSPIQ_OUT_IDX 109
#define FSPID_IN_IDX 110
#define FSPID_OUT_IDX 110
#define FSPIHD_IN_IDX 111
#define FSPIHD_OUT_IDX 111
#define FSPIWP_IN_IDX 112
#define FSPIWP_OUT_IDX 112
#define FSPIIO4_IN_IDX 113
#define FSPIIO4_OUT_IDX 113
#define FSPIIO5_IN_IDX 114
#define FSPIIO5_OUT_IDX 114
#define FSPIIO6_IN_IDX 115
#define FSPIIO6_OUT_IDX 115
#define FSPIIO7_IN_IDX 116
#define FSPIIO7_OUT_IDX 116
#define FSPICS0_IN_IDX 117
#define FSPICS0_OUT_IDX 117
#define FSPICS1_OUT_IDX 118
#define FSPICS2_OUT_IDX 119
#define FSPICS3_OUT_IDX 120
#define FSPICS4_OUT_IDX 121
#define FSPICS5_OUT_IDX 122
#define CAN_RX_IDX 123
#define CAN_TX_IDX 123
#define CAN_BUS_OFF_ON_IDX 124
@ -188,8 +204,12 @@
#define SUBSPICS0_OUT_IDX 131
#define SUBSPICS1_OUT_IDX 132
#define FSPIDQS_OUT_IDX 133
#define SPI3_DQS_OUT_IDX 134
#define SPI4_DQS_OUT_IDX 135
#define FSPI_HSYNC_OUT_IDX 134
#define FSPI_VSYNC_OUT_IDX 135
#define FSPI_DE_OUT_IDX 136
#define FSPICD_OUT_IDX 137
#define SPI3_CD_OUT_IDX 139
#define SPI3_DQS_OUT_IDX 140
#define I2S0I_DATA_IN0_IDX 143
#define I2S0O_DATA_OUT0_IDX 143
#define I2S0I_DATA_IN1_IDX 144
@ -230,6 +250,16 @@
#define I2S0O_DATA_OUT21_IDX 164
#define I2S0O_DATA_OUT22_IDX 165
#define I2S0O_DATA_OUT23_IDX 166
#define SUBSPID4_IN_IDX 167
#define SUBSPID4_OUT_IDX 167
#define SUBSPID5_IN_IDX 168
#define SUBSPID5_OUT_IDX 168
#define SUBSPID6_IN_IDX 169
#define SUBSPID6_OUT_IDX 169
#define SUBSPID7_IN_IDX 170
#define SUBSPID7_OUT_IDX 170
#define SUBSPIDQS_IN_IDX 171
#define SUBSPIDQS_OUT_IDX 171
#define I2S0I_H_SYNC_IDX 193
#define I2S0I_V_SYNC_IDX 194
#define I2S0I_H_ENABLE_IDX 195
@ -285,4 +315,5 @@
#define PRO_ALONEGPIO_OUT7_IDX 242
#define CLK_I2S_MUX_IDX 251
#define SIG_GPIO_OUT_IDX 256
#define GPIO_MAP_DATE_IDX 0x18102600
#define GPIO_MAP_DATE_IDX 0x1904100
#endif /* _SOC_GPIO_SIG_MAP_H_ */

166
components/soc/esp32s2beta/include/soc/hwcrypto_reg.h
View File

@ -42,9 +42,7 @@
/* Interrupt registers */
#define RSA_QUERY_INTERRUPT_REG (DR_REG_RSA_BASE + 0x818)
#define RSA_CLEAR_INTERRUPT_REG (DR_REG_RSA_BASE + 0x81C)
/* SHA acceleration registers */
#define SHA_MODE_REG ((DR_REG_SHA_BASE) + 0x00)
#define RSA_INTERRUPT_REG (DR_REG_RSA_BASE + 0x82C)
#define SHA_MODE_SHA1 0
#define SHA_MODE_SHA224 1
@ -55,24 +53,112 @@
#define SHA_MODE_SHA512_256 6
#define SHA_MODE_SHA512_T 7
/* SHA acceleration registers */
#define SHA_MODE_REG ((DR_REG_SHA_BASE) + 0x00)
#define SHA_T_STRING_REG ((DR_REG_SHA_BASE) + 0x04)
#define SHA_T_LENGTH_REG ((DR_REG_SHA_BASE) + 0x08)
#define SHA_START_REG ((DR_REG_SHA_BASE) + 0x0c)
#define SHA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x10)
#define SHA_BUSY_REG ((DR_REG_SHA_BASE) + 0x14)
#define SHA_BLOCK_NUM_REG ((DR_REG_SHA_BASE) + 0x0C)
#define SHA_START_REG ((DR_REG_SHA_BASE) + 0x10)
#define SHA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x14)
#define SHA_BUSY_REG ((DR_REG_SHA_BASE) + 0x18)
#define SHA_DMA_START_REG ((DR_REG_SHA_BASE) + 0x1C)
#define SHA_DMA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x20)
#define SHA_CLEAR_IRQ_REG ((DR_REG_SHA_BASE) + 0x24)
#define SHA_INT_ENA_REG ((DR_REG_SHA_BASE) + 0x28)
#define SHA_H_BASE ((DR_REG_SHA_BASE) + 0x40)
#define SHA_M_BASE ((DR_REG_SHA_BASE) + 0x80)
#define SHA_TEXT_BASE ((DR_REG_SHA_BASE) + 0x80)
/* AES Block operation modes */
#define AES_BLOCK_MODE_ECB 0
#define AES_BLOCK_MODE_CBC 1
#define AES_BLOCK_MODE_OFB 2
#define AES_BLOCK_MODE_CTR 3
#define AES_BLOCK_MODE_CFB8 4
#define AES_BLOCK_MODE_CFB128 5
#define AES_BLOCK_MODE_GCM 6
/* AES Block operation modes (used with DMA) */
#define AES_BLOCK_MODE_ECB 0
#define AES_BLOCK_MODE_CBC 1
#define AES_BLOCK_MODE_OFB 2
#define AES_BLOCK_MODE_CTR 3
#define AES_BLOCK_MODE_CFB8 4
#define AES_BLOCK_MODE_CFB128 5
#define AES_BLOCK_MODE_GCM 6
/* AES acceleration registers */
#define AES_MODE_REG ((DR_REG_AES_BASE) + 0x40)
#define AES_ENDIAN_REG ((DR_REG_AES_BASE) + 0x44)
#define AES_TRIGGER_REG ((DR_REG_AES_BASE) + 0x48)
#define AES_STATE_REG ((DR_REG_AES_BASE) + 0x4c)
#define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90)
#define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94)
#define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98)
#define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C)
#define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0)
#define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4)
#define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8)
#define AES_INT_CLEAR_REG ((DR_REG_AES_BASE) + 0xAC)
#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0)
#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4)
#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8)
#define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90)
#define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94)
#define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98)
#define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C)
#define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0)
#define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4)
#define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8)
#define AES_KEY_BASE ((DR_REG_AES_BASE) + 0x00)
#define AES_TEXT_IN_BASE ((DR_REG_AES_BASE) + 0x20)
#define AES_TEXT_OUT_BASE ((DR_REG_AES_BASE) + 0x30)
#define AES_IV_BASE ((DR_REG_AES_BASE) + 0x50)
#define AES_H_BASE ((DR_REG_AES_BASE) + 0x60)
#define AES_J_BASE ((DR_REG_AES_BASE) + 0x70)
#define AES_T_BASE ((DR_REG_AES_BASE) + 0x80)
#define AES_INT_CLR_REG ((DR_REG_AES_BASE) + 0xAC)
#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0)
#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4)
#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8)
/* AES_STATE_REG values */
#define AES_STATE_IDLE 0
#define AES_STATE_BUSY 1
#define AES_STATE_DONE 2
/* Crypto DMA */
#define CRYPTO_DMA_CONF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x00)
#define CRYPTO_DMA_INT_RAW_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x04)
#define CRYPTO_DMA_INT_ST_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x08)
#define CRYPTO_DMA_INT_ENA_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x0C)
#define CRYPTO_DMA_INT_CLR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x10)
#define CRYPTO_DMA_OUT_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x14)
#define CRYPTO_DMA_OUT_PUSH_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x18)
#define CRYPTO_DMA_IN_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x1C)
#define CRYPTO_DMA_IN_POP_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x20)
#define CRYPTO_DMA_OUT_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x24)
#define CRYPTO_DMA_IN_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x28)
#define CRYPTO_DMA_CONF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x2C)
#define CRYPTO_DMA_STATE0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x30)
#define CRYPTO_DMA_STATE1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x34)
#define CRYPTO_DMA_OUT_EOF_DES_ADDR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x38)
#define CRYPTO_DMA_IN_SUC_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x3C)
#define CRYPTO_DMA_IN_ERR_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x40)
#define CRYPTO_DMA_OUT_EOF_BFR_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x44)
#define CRYPTO_DMA_AHB_TEST ((DR_REG_CRYPTO_DMA_BASE) + 0x48)
#define CRYPTO_DMA_IN_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x4C)
#define CRYPTO_DMA_IN_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x50)
#define CRYPTO_DMA_IN_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x54)
#define CRYPTO_DMA_OUT_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x58)
#define CRYPTO_DMA_OUT_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x5C)
#define CRYPTO_DMA_OUT_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x60)
#define CRYPTO_DMA_AES_SHA_SELECT_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x64)
#define CRYPTO_DMA_DATE_REG ((DR_REG_CRYPTO_DMA_BASE) + 0xFC)
/* HMAC Module */
#define HMAC_SET_START_REG ((DR_REG_HMAC_BASE) + 0x40)
@ -88,20 +174,68 @@
#define HMAC_QUERY_ERROR_REG ((DR_REG_HMAC_BASE) + 0x68)
#define HMAC_QUERY_BUSY_REG ((DR_REG_HMAC_BASE) + 0x6c)
#define HMAC_WDATA_BASE ((DR_REG_HMAC_BASE) + 0x80)
#define HMAC_RDATA_BASE ((DR_REG_HMAC_BASE) + 0xC0)
#define HMAC_SET_MESSAGE_PAD_REG ((DR_REG_HMAC_BASE) + 0xF0)
#define HMAC_ONE_BLOCK_REG ((DR_REG_HMAC_BASE) + 0xF4)
/* AES-XTS registers */
#define AES_XTS_PLAIN_BASE ((DR_REG_AES_BASE) + 0x80)
#define AES_XTS_SIZE_REG ((DR_REG_AES_BASE) + 0xC0)
#define AES_XTS_DESTINATION_REG ((DR_REG_AES_BASE) + 0xC4)
#define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_BASE) + 0xC8)
#define AES_XTS_PLAIN_BASE ((DR_REG_AES_BASE) + 0x100)
#define AES_XTS_SIZE_REG ((DR_REG_AES_BASE) + 0x140)
#define AES_XTS_DESTINATION_REG ((DR_REG_AES_BASE) + 0x144)
#define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_BASE) + 0x148)
#define AES_XTS_TRIGGER_REG ((DR_REG_AES_BASE) + 0xCC)
#define AES_XTS_RELEASE_REG ((DR_REG_AES_BASE) + 0xD0)
#define AES_XTS_DESTROY_REG ((DR_REG_AES_BASE) + 0xD4)
#define AES_XTS_STATE_REG ((DR_REG_AES_BASE) + 0xD8)
#define AES_XTS_TRIGGER_REG ((DR_REG_AES_BASE) + 0x14C)
#define AES_XTS_RELEASE_REG ((DR_REG_AES_BASE) + 0x150)
#define AES_XTS_DESTROY_REG ((DR_REG_AES_BASE) + 0x154)
#define AES_XTS_STATE_REG ((DR_REG_AES_BASE) + 0x158)
/* Digital Signature registers*/
#define DS_C_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 )
#define DS_IV_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x630 )
#define DS_X_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x800 )
#define DS_Z_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xA00 )
#define DS_SET_START_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE00)
#define DS_SET_ME_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE04)
#define DS_SET_FINISH_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE08)
#define DS_QUERY_BUSY_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE0C)
#define DS_QUERY_KEY_WRONG_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE10)
#define DS_QUERY_CHECK_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE14)
#define DS_QUERY_CHECK_INVALID_DIGEST (1<<0)
#define DS_QUERY_CHECK_INVALID_PADDING (1<<1)
#define DS_DATE_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE20)
/* Crypto DMA */
#define CRYPTO_DMA_CONF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x00)
#define CRYPTO_DMA_INT_RAW_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x04)
#define CRYPTO_DMA_INT_ST_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x08)
#define CRYPTO_DMA_INT_ENA_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x0C)
#define CRYPTO_DMA_INT_CLR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x10)
#define CRYPTO_DMA_OUT_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x14)
#define CRYPTO_DMA_OUT_PUSH_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x18)
#define CRYPTO_DMA_IN_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x1C)
#define CRYPTO_DMA_IN_POP_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x20)
#define CRYPTO_DMA_OUT_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x24)
#define CRYPTO_DMA_IN_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x28)
#define CRYPTO_DMA_CONF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x2C)
#define CRYPTO_DMA_STATE0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x30)
#define CRYPTO_DMA_STATE1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x34)
#define CRYPTO_DMA_OUT_EOF_DES_ADDR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x38)
#define CRYPTO_DMA_IN_SUC_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x3C)
#define CRYPTO_DMA_IN_ERR_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x40)
#define CRYPTO_DMA_OUT_EOF_BFR_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x44)
#define CRYPTO_DMA_AHB_TEST ((DR_REG_CRYPTO_DMA_BASE) + 0x48)
#define CRYPTO_DMA_IN_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x4C)
#define CRYPTO_DMA_IN_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x50)
#define CRYPTO_DMA_IN_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x54)
#define CRYPTO_DMA_OUT_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x58)
#define CRYPTO_DMA_OUT_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x5C)
#define CRYPTO_DMA_OUT_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x60)
#define CRYPTO_DMA_AES_SHA_SELECT_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x64)
#define CRYPTO_DMA_DATE_REG ((DR_REG_CRYPTO_DMA_BASE) + 0xFC)
#endif

310
components/soc/esp32s2beta/include/soc/i2c_reg.h
View File

@ -21,7 +21,7 @@ extern "C" {
#include "soc.h"
#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0000)
/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This register is used to configure the low level width of SCL clock.*/
/*description: */
#define I2C_SCL_LOW_PERIOD 0x00003FFF
#define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S))
#define I2C_SCL_LOW_PERIOD_V 0x3FFF
@ -47,34 +47,31 @@ extern "C" {
#define I2C_ARBITRATION_EN_V 0x1
#define I2C_ARBITRATION_EN_S 9
/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: This is the clock gating control bit for reading or writing registers.*/
/*description: */
#define I2C_CLK_EN (BIT(8))
#define I2C_CLK_EN_M (BIT(8))
#define I2C_CLK_EN_V 0x1
#define I2C_CLK_EN_S 8
/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */
/*description: This bit is used to control the storage mode for received datas.
1: receive data from most significant bit 0: receive data from least significant bit*/
/*description: */
#define I2C_RX_LSB_FIRST (BIT(7))
#define I2C_RX_LSB_FIRST_M (BIT(7))
#define I2C_RX_LSB_FIRST_V 0x1
#define I2C_RX_LSB_FIRST_S 7
/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: This bit is used to control the sending mode for data need to
be send. 1: receive data from most significant bit 0: receive data from least significant bit*/
/*description: */
#define I2C_TX_LSB_FIRST (BIT(6))
#define I2C_TX_LSB_FIRST_M (BIT(6))
#define I2C_TX_LSB_FIRST_V 0x1
#define I2C_TX_LSB_FIRST_S 6
/* I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: Set this bit to start sending data in txfifo.*/
/*description: */
#define I2C_TRANS_START (BIT(5))
#define I2C_TRANS_START_M (BIT(5))
#define I2C_TRANS_START_V 0x1
#define I2C_TRANS_START_S 5
/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: Set this bit to configure the module as i2c master clear this
bit to configure the module as i2c slave.*/
/*description: */
#define I2C_MS_MODE (BIT(4))
#define I2C_MS_MODE_M (BIT(4))
#define I2C_MS_MODE_V 0x1
@ -86,22 +83,19 @@ extern "C" {
#define I2C_ACK_LEVEL_V 0x1
#define I2C_ACK_LEVEL_S 3
/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set this bit to sample data in SCL low level. clear this bit
to sample data in SCL high level.*/
/*description: */
#define I2C_SAMPLE_SCL_LEVEL (BIT(2))
#define I2C_SAMPLE_SCL_LEVEL_M (BIT(2))
#define I2C_SAMPLE_SCL_LEVEL_V 0x1
#define I2C_SAMPLE_SCL_LEVEL_S 2
/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: 1: normally ouput scl clock 0: exchange the function of scl_o
and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/
/*description: */
#define I2C_SCL_FORCE_OUT (BIT(1))
#define I2C_SCL_FORCE_OUT_M (BIT(1))
#define I2C_SCL_FORCE_OUT_V 0x1
#define I2C_SCL_FORCE_OUT_S 1
/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: 1: normally ouput sda data 0: exchange the function of sda_o
and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/
/*description: */
#define I2C_SDA_FORCE_OUT (BIT(0))
#define I2C_SDA_FORCE_OUT_M (BIT(0))
#define I2C_SDA_FORCE_OUT_V 0x1
@ -109,71 +103,67 @@ extern "C" {
#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x0008)
/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
/*description: This register stores the value of state machine to produce SCL.
3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/
/*description: */
#define I2C_SCL_STATE_LAST 0x00000007
#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S))
#define I2C_SCL_STATE_LAST_V 0x7
#define I2C_SCL_STATE_LAST_S 28
/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
/*description: This register stores the value of state machine for i2c module.
3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/
/*description: */
#define I2C_SCL_MAIN_STATE_LAST 0x00000007
#define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S))
#define I2C_SCL_MAIN_STATE_LAST_V 0x7
#define I2C_SCL_MAIN_STATE_LAST_S 24
/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */
/*description: This register stores the amount of received data in ram.*/
/*description: */
#define I2C_TXFIFO_CNT 0x0000003F
#define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S))
#define I2C_TXFIFO_CNT_V 0x3F
#define I2C_TXFIFO_CNT_S 18
/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */
/*description: This register represent the amount of data need to send.*/
/*description: */
#define I2C_RXFIFO_CNT 0x0000003F
#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S))
#define I2C_RXFIFO_CNT_V 0x3F
#define I2C_RXFIFO_CNT_S 8
/* I2C_BYTE_TRANS : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: This register changes to high level when one byte is transferred.*/
/*description: */
#define I2C_BYTE_TRANS (BIT(6))
#define I2C_BYTE_TRANS_M (BIT(6))
#define I2C_BYTE_TRANS_V 0x1
#define I2C_BYTE_TRANS_S 6
/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: when configured as i2c slave and the address send by master
is equal to slave's address then this bit will be high level.*/
/*description: */
#define I2C_SLAVE_ADDRESSED (BIT(5))
#define I2C_SLAVE_ADDRESSED_M (BIT(5))
#define I2C_SLAVE_ADDRESSED_V 0x1
#define I2C_SLAVE_ADDRESSED_S 5
/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: 1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/
/*description: */
#define I2C_BUS_BUSY (BIT(4))
#define I2C_BUS_BUSY_M (BIT(4))
#define I2C_BUS_BUSY_V 0x1
#define I2C_BUS_BUSY_S 4
/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: when I2C lost control of SDA line this register changes to high level.*/
/*description: */
#define I2C_ARB_LOST (BIT(3))
#define I2C_ARB_LOST_M (BIT(3))
#define I2C_ARB_LOST_V 0x1
#define I2C_ARB_LOST_S 3
/* I2C_TIME_OUT : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: when I2C takes more than time_out_reg clocks to receive a data
then this register changes to high level.*/
/*description: */
#define I2C_TIME_OUT (BIT(2))
#define I2C_TIME_OUT_M (BIT(2))
#define I2C_TIME_OUT_V 0x1
#define I2C_TIME_OUT_S 2
/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: when in slave mode 1: master read slave 0: master write slave.*/
/*description: */
#define I2C_SLAVE_RW (BIT(1))
#define I2C_SLAVE_RW_M (BIT(1))
#define I2C_SLAVE_RW_V 0x1
#define I2C_SLAVE_RW_S 1
/* I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: This register stores the value of ACK bit.*/
/*description: */
#define I2C_ACK_REC (BIT(0))
#define I2C_ACK_REC_M (BIT(0))
#define I2C_ACK_REC_V 0x1
@ -195,14 +185,13 @@ extern "C" {
#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0010)
/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: This register is used to enable slave 10bit address mode.*/
/*description: */
#define I2C_ADDR_10BIT_EN (BIT(31))
#define I2C_ADDR_10BIT_EN_M (BIT(31))
#define I2C_ADDR_10BIT_EN_V 0x1
#define I2C_ADDR_10BIT_EN_S 31
/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
/*description: when configured as i2c slave this register is used to configure
slave's address.*/
/*description: */
#define I2C_SLAVE_ADDR 0x00007FFF
#define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S))
#define I2C_SLAVE_ADDR_V 0x7FFF
@ -234,29 +223,25 @@ extern "C" {
#define I2C_RX_UPDATE_V 0x1
#define I2C_RX_UPDATE_S 20
/* I2C_TXFIFO_END_ADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */
/*description: This is the offset address of the last sending data as described
in nonfifo_tx_thres register.*/
/*description: */
#define I2C_TXFIFO_END_ADDR 0x0000001F
#define I2C_TXFIFO_END_ADDR_M ((I2C_TXFIFO_END_ADDR_V)<<(I2C_TXFIFO_END_ADDR_S))
#define I2C_TXFIFO_END_ADDR_V 0x1F
#define I2C_TXFIFO_END_ADDR_S 15
/* I2C_TXFIFO_START_ADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */
/*description: This is the offset address of the first sending data as described
in nonfifo_tx_thres register.*/
/*description: */
#define I2C_TXFIFO_START_ADDR 0x0000001F
#define I2C_TXFIFO_START_ADDR_M ((I2C_TXFIFO_START_ADDR_V)<<(I2C_TXFIFO_START_ADDR_S))
#define I2C_TXFIFO_START_ADDR_V 0x1F
#define I2C_TXFIFO_START_ADDR_S 10
/* I2C_RXFIFO_END_ADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */
/*description: This is the offset address of the first receiving data as described
in nonfifo_rx_thres_register.*/
/*description: */
#define I2C_RXFIFO_END_ADDR 0x0000001F
#define I2C_RXFIFO_END_ADDR_M ((I2C_RXFIFO_END_ADDR_V)<<(I2C_RXFIFO_END_ADDR_S))
#define I2C_RXFIFO_END_ADDR_V 0x1F
#define I2C_RXFIFO_END_ADDR_S 5
/* I2C_RXFIFO_START_ADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */
/*description: This is the offset address of the last receiving data as described
in nonfifo_rx_thres_register.*/
/*description: */
#define I2C_RXFIFO_START_ADDR 0x0000001F
#define I2C_RXFIFO_START_ADDR_M ((I2C_RXFIFO_START_ADDR_V)<<(I2C_RXFIFO_START_ADDR_S))
#define I2C_RXFIFO_START_ADDR_V 0x1F
@ -264,46 +249,43 @@ extern "C" {
#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x0018)
/* I2C_NONFIFO_TX_THRES : R/W ;bitpos:[25:20] ;default: 6'h15 ; */
/*description: when I2C sends more than nonfifo_tx_thres data it will produce
tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/
/*description: */
#define I2C_NONFIFO_TX_THRES 0x0000003F
#define I2C_NONFIFO_TX_THRES_M ((I2C_NONFIFO_TX_THRES_V)<<(I2C_NONFIFO_TX_THRES_S))
#define I2C_NONFIFO_TX_THRES_V 0x3F
#define I2C_NONFIFO_TX_THRES_S 20
/* I2C_NONFIFO_RX_THRES : R/W ;bitpos:[19:14] ;default: 6'h15 ; */
/*description: when I2C receives more than nonfifo_rx_thres data it will produce
rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/
/*description: */
#define I2C_NONFIFO_RX_THRES 0x0000003F
#define I2C_NONFIFO_RX_THRES_M ((I2C_NONFIFO_RX_THRES_V)<<(I2C_NONFIFO_RX_THRES_S))
#define I2C_NONFIFO_RX_THRES_V 0x3F
#define I2C_NONFIFO_RX_THRES_S 14
/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: Set this bit to reset tx fifo when using apb fifo access.*/
/*description: */
#define I2C_TX_FIFO_RST (BIT(13))
#define I2C_TX_FIFO_RST_M (BIT(13))
#define I2C_TX_FIFO_RST_V 0x1
#define I2C_TX_FIFO_RST_S 13
/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: Set this bit to reset rx fifo when using apb fifo access.*/
/*description: */
#define I2C_RX_FIFO_RST (BIT(12))
#define I2C_RX_FIFO_RST_M (BIT(12))
#define I2C_RX_FIFO_RST_V 0x1
#define I2C_RX_FIFO_RST_S 12
/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: When this bit is set to 1 then the byte after address represent
the offset address of I2C Slave's ram.*/
/*description: */
#define I2C_FIFO_ADDR_CFG_EN (BIT(11))
#define I2C_FIFO_ADDR_CFG_EN_M (BIT(11))
#define I2C_FIFO_ADDR_CFG_EN_V 0x1
#define I2C_FIFO_ADDR_CFG_EN_S 11
/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: Set this bit to enble apb nonfifo access.*/
/*description: */
#define I2C_NONFIFO_EN (BIT(10))
#define I2C_NONFIFO_EN_M (BIT(10))
#define I2C_NONFIFO_EN_V 0x1
#define I2C_NONFIFO_EN_S 10
/* I2C_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */
/*description: Config txfifo empty threhd value when using apb fifo access*/
/*description: */
#define I2C_TXFIFO_EMPTY_THRHD 0x0000001F
#define I2C_TXFIFO_EMPTY_THRHD_M ((I2C_TXFIFO_EMPTY_THRHD_V)<<(I2C_TXFIFO_EMPTY_THRHD_S))
#define I2C_TXFIFO_EMPTY_THRHD_V 0x1F
@ -319,7 +301,7 @@ extern "C" {
#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x001c)
/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */
/*description: The register represent the byte data read from rxfifo when use apb fifo access*/
/*description: */
#define I2C_FIFO_RDATA 0x000000FF
#define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S))
#define I2C_FIFO_RDATA_V 0xFF
@ -345,90 +327,79 @@ extern "C" {
#define I2C_SCL_ST_TO_INT_RAW_V 0x1
#define I2C_SCL_ST_TO_INT_RAW_S 13
/* I2C_TX_SEND_EMPTY_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for tx_send_empty_int interrupt.when
I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/
/*description: */
#define I2C_TX_SEND_EMPTY_INT_RAW (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_RAW_M (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_RAW_V 0x1
#define I2C_TX_SEND_EMPTY_INT_RAW_S 12
/* I2C_RX_REC_FULL_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for rx_rec_full_int interrupt. when
I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/
/*description: */
#define I2C_RX_REC_FULL_INT_RAW (BIT(11))
#define I2C_RX_REC_FULL_INT_RAW_M (BIT(11))
#define I2C_RX_REC_FULL_INT_RAW_V 0x1
#define I2C_RX_REC_FULL_INT_RAW_S 11
/* I2C_ACK_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for ack_err_int interrupt. when
I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/
/*description: */
#define I2C_ACK_ERR_INT_RAW (BIT(10))
#define I2C_ACK_ERR_INT_RAW_M (BIT(10))
#define I2C_ACK_ERR_INT_RAW_V 0x1
#define I2C_ACK_ERR_INT_RAW_S 10
/* I2C_TRANS_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for trans_start_int interrupt. when
I2C sends the START bit it will produce trans_start_int interrupt.*/
/*description: */
#define I2C_TRANS_START_INT_RAW (BIT(9))
#define I2C_TRANS_START_INT_RAW_M (BIT(9))
#define I2C_TRANS_START_INT_RAW_V 0x1
#define I2C_TRANS_START_INT_RAW_S 9
/* I2C_TIME_OUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for time_out_int interrupt. when
I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/
/*description: */
#define I2C_TIME_OUT_INT_RAW (BIT(8))
#define I2C_TIME_OUT_INT_RAW_M (BIT(8))
#define I2C_TIME_OUT_INT_RAW_V 0x1
#define I2C_TIME_OUT_INT_RAW_S 8
/* I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for trans_complete_int interrupt.
when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/
/*description: */
#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7))
#define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7))
#define I2C_TRANS_COMPLETE_INT_RAW_V 0x1
#define I2C_TRANS_COMPLETE_INT_RAW_S 7
/* I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for master_tra_comp_int interrupt.
when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/
/*description: */
#define I2C_MASTER_TRAN_COMP_INT_RAW (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1
#define I2C_MASTER_TRAN_COMP_INT_RAW_S 6
/* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for arbitration_lost_int interrupt.when
I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/
/*description: */
#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5))
#define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5))
#define I2C_ARBITRATION_LOST_INT_RAW_V 0x1
#define I2C_ARBITRATION_LOST_INT_RAW_S 5
/* I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for slave_tran_comp_int interrupt.
when I2C Slave detectsthe STOP bit it will produce slave_tran_comp_int interrupt.*/
/*description: */
#define I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1
#define I2C_SLAVE_TRAN_COMP_INT_RAW_S 4
/* I2C_END_DETECT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for end_detect_int interrupt. when
I2C deals with the END command it will produce end_detect_int interrupt.*/
/*description: */
#define I2C_END_DETECT_INT_RAW (BIT(3))
#define I2C_END_DETECT_INT_RAW_M (BIT(3))
#define I2C_END_DETECT_INT_RAW_V 0x1
#define I2C_END_DETECT_INT_RAW_S 3
/* I2C_RXFIFO_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for receiving data overflow when
use apb fifo access.*/
/*description: */
#define I2C_RXFIFO_OVF_INT_RAW (BIT(2))
#define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2))
#define I2C_RXFIFO_OVF_INT_RAW_V 0x1
#define I2C_RXFIFO_OVF_INT_RAW_S 2
/* I2C_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for txfifo empty when use apb fifo access.*/
/*description: */
#define I2C_TXFIFO_EMPTY_INT_RAW (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_RAW_M (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_RAW_V 0x1
#define I2C_TXFIFO_EMPTY_INT_RAW_S 1
/* I2C_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for rxfifo full when use apb fifo access.*/
/*description: */
#define I2C_RXFIFO_FULL_INT_RAW (BIT(0))
#define I2C_RXFIFO_FULL_INT_RAW_M (BIT(0))
#define I2C_RXFIFO_FULL_INT_RAW_V 0x1
@ -454,79 +425,79 @@ extern "C" {
#define I2C_SCL_ST_TO_INT_CLR_V 0x1
#define I2C_SCL_ST_TO_INT_CLR_S 13
/* I2C_TX_SEND_EMPTY_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
/*description: Set this bit to clear the tx_send_empty_int interrupt.*/
/*description: */
#define I2C_TX_SEND_EMPTY_INT_CLR (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_CLR_M (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_CLR_V 0x1
#define I2C_TX_SEND_EMPTY_INT_CLR_S 12
/* I2C_RX_REC_FULL_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
/*description: Set this bit to clear the rx_rec_full_int interrupt.*/
/*description: */
#define I2C_RX_REC_FULL_INT_CLR (BIT(11))
#define I2C_RX_REC_FULL_INT_CLR_M (BIT(11))
#define I2C_RX_REC_FULL_INT_CLR_V 0x1
#define I2C_RX_REC_FULL_INT_CLR_S 11
/* I2C_ACK_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
/*description: Set this bit to clear the ack_err_int interrupt.*/
/*description: */
#define I2C_ACK_ERR_INT_CLR (BIT(10))
#define I2C_ACK_ERR_INT_CLR_M (BIT(10))
#define I2C_ACK_ERR_INT_CLR_V 0x1
#define I2C_ACK_ERR_INT_CLR_S 10
/* I2C_TRANS_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
/*description: Set this bit to clear the trans_start_int interrupt.*/
/*description: */
#define I2C_TRANS_START_INT_CLR (BIT(9))
#define I2C_TRANS_START_INT_CLR_M (BIT(9))
#define I2C_TRANS_START_INT_CLR_V 0x1
#define I2C_TRANS_START_INT_CLR_S 9
/* I2C_TIME_OUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
/*description: Set this bit to clear the time_out_int interrupt.*/
/*description: */
#define I2C_TIME_OUT_INT_CLR (BIT(8))
#define I2C_TIME_OUT_INT_CLR_M (BIT(8))
#define I2C_TIME_OUT_INT_CLR_V 0x1
#define I2C_TIME_OUT_INT_CLR_S 8
/* I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
/*description: Set this bit to clear the trans_complete_int interrupt.*/
/*description: */
#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7))
#define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7))
#define I2C_TRANS_COMPLETE_INT_CLR_V 0x1
#define I2C_TRANS_COMPLETE_INT_CLR_S 7
/* I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
/*description: Set this bit to clear the master_tran_comp interrupt.*/
/*description: */
#define I2C_MASTER_TRAN_COMP_INT_CLR (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1
#define I2C_MASTER_TRAN_COMP_INT_CLR_S 6
/* I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
/*description: Set this bit to clear the arbitration_lost_int interrupt.*/
/*description: */
#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5))
#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5))
#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1
#define I2C_ARBITRATION_LOST_INT_CLR_S 5
/* I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
/*description: Set this bit to clear the slave_tran_comp_int interrupt.*/
/*description: */
#define I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1
#define I2C_SLAVE_TRAN_COMP_INT_CLR_S 4
/* I2C_END_DETECT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
/*description: Set this bit to clear the end_detect_int interrupt.*/
/*description: */
#define I2C_END_DETECT_INT_CLR (BIT(3))
#define I2C_END_DETECT_INT_CLR_M (BIT(3))
#define I2C_END_DETECT_INT_CLR_V 0x1
#define I2C_END_DETECT_INT_CLR_S 3
/* I2C_RXFIFO_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set this bit to clear the rxfifo_ovf_int interrupt.*/
/*description: */
#define I2C_RXFIFO_OVF_INT_CLR (BIT(2))
#define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2))
#define I2C_RXFIFO_OVF_INT_CLR_V 0x1
#define I2C_RXFIFO_OVF_INT_CLR_S 2
/* I2C_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set this bit to clear the txfifo_empty_int interrupt.*/
/*description: */
#define I2C_TXFIFO_EMPTY_INT_CLR (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_CLR_M (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_CLR_V 0x1
#define I2C_TXFIFO_EMPTY_INT_CLR_S 1
/* I2C_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to clear the rxfifo_full_int interrupt.*/
/*description: */
#define I2C_RXFIFO_FULL_INT_CLR (BIT(0))
#define I2C_RXFIFO_FULL_INT_CLR_M (BIT(0))
#define I2C_RXFIFO_FULL_INT_CLR_V 0x1
@ -552,79 +523,79 @@ extern "C" {
#define I2C_SCL_ST_TO_INT_ENA_V 0x1
#define I2C_SCL_ST_TO_INT_ENA_S 13
/* I2C_TX_SEND_EMPTY_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: The enable bit for tx_send_empty_int interrupt.*/
/*description: */
#define I2C_TX_SEND_EMPTY_INT_ENA (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_ENA_M (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_ENA_V 0x1
#define I2C_TX_SEND_EMPTY_INT_ENA_S 12
/* I2C_RX_REC_FULL_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: The enable bit for rx_rec_full_int interrupt.*/
/*description: */
#define I2C_RX_REC_FULL_INT_ENA (BIT(11))
#define I2C_RX_REC_FULL_INT_ENA_M (BIT(11))
#define I2C_RX_REC_FULL_INT_ENA_V 0x1
#define I2C_RX_REC_FULL_INT_ENA_S 11
/* I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: The enable bit for ack_err_int interrupt.*/
/*description: */
#define I2C_ACK_ERR_INT_ENA (BIT(10))
#define I2C_ACK_ERR_INT_ENA_M (BIT(10))
#define I2C_ACK_ERR_INT_ENA_V 0x1
#define I2C_ACK_ERR_INT_ENA_S 10
/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: The enable bit for trans_start_int interrupt.*/
/*description: */
#define I2C_TRANS_START_INT_ENA (BIT(9))
#define I2C_TRANS_START_INT_ENA_M (BIT(9))
#define I2C_TRANS_START_INT_ENA_V 0x1
#define I2C_TRANS_START_INT_ENA_S 9
/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: The enable bit for time_out_int interrupt.*/
/*description: */
#define I2C_TIME_OUT_INT_ENA (BIT(8))
#define I2C_TIME_OUT_INT_ENA_M (BIT(8))
#define I2C_TIME_OUT_INT_ENA_V 0x1
#define I2C_TIME_OUT_INT_ENA_S 8
/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: The enable bit for trans_complete_int interrupt.*/
/*description: */
#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7))
#define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7))
#define I2C_TRANS_COMPLETE_INT_ENA_V 0x1
#define I2C_TRANS_COMPLETE_INT_ENA_S 7
/* I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: The enable bit for master_tran_comp_int interrupt.*/
/*description: */
#define I2C_MASTER_TRAN_COMP_INT_ENA (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1
#define I2C_MASTER_TRAN_COMP_INT_ENA_S 6
/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: The enable bit for arbitration_lost_int interrupt.*/
/*description: */
#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5))
#define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5))
#define I2C_ARBITRATION_LOST_INT_ENA_V 0x1
#define I2C_ARBITRATION_LOST_INT_ENA_S 5
/* I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The enable bit for slave_tran_comp_int interrupt.*/
/*description: */
#define I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1
#define I2C_SLAVE_TRAN_COMP_INT_ENA_S 4
/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: The enable bit for end_detect_int interrupt.*/
/*description: */
#define I2C_END_DETECT_INT_ENA (BIT(3))
#define I2C_END_DETECT_INT_ENA_M (BIT(3))
#define I2C_END_DETECT_INT_ENA_V 0x1
#define I2C_END_DETECT_INT_ENA_S 3
/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: The enable bit for rxfifo_ovf_int interrupt.*/
/*description: */
#define I2C_RXFIFO_OVF_INT_ENA (BIT(2))
#define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2))
#define I2C_RXFIFO_OVF_INT_ENA_V 0x1
#define I2C_RXFIFO_OVF_INT_ENA_S 2
/* I2C_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The enable bit for txfifo_empty_int interrupt.*/
/*description: */
#define I2C_TXFIFO_EMPTY_INT_ENA (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_ENA_M (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_ENA_V 0x1
#define I2C_TXFIFO_EMPTY_INT_ENA_S 1
/* I2C_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The enable bit for rxfifo_full_int interrupt.*/
/*description: */
#define I2C_RXFIFO_FULL_INT_ENA (BIT(0))
#define I2C_RXFIFO_FULL_INT_ENA_M (BIT(0))
#define I2C_RXFIFO_FULL_INT_ENA_V 0x1
@ -650,79 +621,79 @@ extern "C" {
#define I2C_SCL_ST_TO_INT_ST_V 0x1
#define I2C_SCL_ST_TO_INT_ST_S 13
/* I2C_TX_SEND_EMPTY_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
/*description: The masked interrupt status for tx_send_empty_int interrupt.*/
/*description: */
#define I2C_TX_SEND_EMPTY_INT_ST (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_ST_M (BIT(12))
#define I2C_TX_SEND_EMPTY_INT_ST_V 0x1
#define I2C_TX_SEND_EMPTY_INT_ST_S 12
/* I2C_RX_REC_FULL_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
/*description: The masked interrupt status for rx_rec_full_int interrupt.*/
/*description: */
#define I2C_RX_REC_FULL_INT_ST (BIT(11))
#define I2C_RX_REC_FULL_INT_ST_M (BIT(11))
#define I2C_RX_REC_FULL_INT_ST_V 0x1
#define I2C_RX_REC_FULL_INT_ST_S 11
/* I2C_ACK_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: The masked interrupt status for ack_err_int interrupt.*/
/*description: */
#define I2C_ACK_ERR_INT_ST (BIT(10))
#define I2C_ACK_ERR_INT_ST_M (BIT(10))
#define I2C_ACK_ERR_INT_ST_V 0x1
#define I2C_ACK_ERR_INT_ST_S 10
/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: The masked interrupt status for trans_start_int interrupt.*/
/*description: */
#define I2C_TRANS_START_INT_ST (BIT(9))
#define I2C_TRANS_START_INT_ST_M (BIT(9))
#define I2C_TRANS_START_INT_ST_V 0x1
#define I2C_TRANS_START_INT_ST_S 9
/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: The masked interrupt status for time_out_int interrupt.*/
/*description: */
#define I2C_TIME_OUT_INT_ST (BIT(8))
#define I2C_TIME_OUT_INT_ST_M (BIT(8))
#define I2C_TIME_OUT_INT_ST_V 0x1
#define I2C_TIME_OUT_INT_ST_S 8
/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: The masked interrupt status for trans_complete_int interrupt.*/
/*description: */
#define I2C_TRANS_COMPLETE_INT_ST (BIT(7))
#define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7))
#define I2C_TRANS_COMPLETE_INT_ST_V 0x1
#define I2C_TRANS_COMPLETE_INT_ST_S 7
/* I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The masked interrupt status for master_tran_comp_int interrupt.*/
/*description: */
#define I2C_MASTER_TRAN_COMP_INT_ST (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(6))
#define I2C_MASTER_TRAN_COMP_INT_ST_V 0x1
#define I2C_MASTER_TRAN_COMP_INT_ST_S 6
/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: The masked interrupt status for arbitration_lost_int interrupt.*/
/*description: */
#define I2C_ARBITRATION_LOST_INT_ST (BIT(5))
#define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5))
#define I2C_ARBITRATION_LOST_INT_ST_V 0x1
#define I2C_ARBITRATION_LOST_INT_ST_S 5
/* I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: The masked interrupt status for slave_tran_comp_int interrupt.*/
/*description: */
#define I2C_SLAVE_TRAN_COMP_INT_ST (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(4))
#define I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1
#define I2C_SLAVE_TRAN_COMP_INT_ST_S 4
/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The masked interrupt status for end_detect_int interrupt.*/
/*description: */
#define I2C_END_DETECT_INT_ST (BIT(3))
#define I2C_END_DETECT_INT_ST_M (BIT(3))
#define I2C_END_DETECT_INT_ST_V 0x1
#define I2C_END_DETECT_INT_ST_S 3
/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: The masked interrupt status for rxfifo_ovf_int interrupt.*/
/*description: */
#define I2C_RXFIFO_OVF_INT_ST (BIT(2))
#define I2C_RXFIFO_OVF_INT_ST_M (BIT(2))
#define I2C_RXFIFO_OVF_INT_ST_V 0x1
#define I2C_RXFIFO_OVF_INT_ST_S 2
/* I2C_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: The masked interrupt status for txfifo_empty_int interrupt.*/
/*description: */
#define I2C_TXFIFO_EMPTY_INT_ST (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_ST_M (BIT(1))
#define I2C_TXFIFO_EMPTY_INT_ST_V 0x1
#define I2C_TXFIFO_EMPTY_INT_ST_S 1
/* I2C_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The masked interrupt status for rxfifo_full_int interrupt.*/
/*description: */
#define I2C_RXFIFO_FULL_INT_ST (BIT(0))
#define I2C_RXFIFO_FULL_INT_ST_M (BIT(0))
#define I2C_RXFIFO_FULL_INT_ST_V 0x1
@ -730,8 +701,7 @@ extern "C" {
#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0030)
/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
/*description: This register is used to configure the clock num I2C used to
hold the data after the negedge of SCL.*/
/*description: */
#define I2C_SDA_HOLD_TIME 0x000003FF
#define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S))
#define I2C_SDA_HOLD_TIME_V 0x3FF
@ -739,8 +709,7 @@ extern "C" {
#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x0034)
/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
/*description: This register is used to configure the clock num I2C used to
sample data on SDA after the posedge of SCL*/
/*description: */
#define I2C_SDA_SAMPLE_TIME 0x000003FF
#define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S))
#define I2C_SDA_SAMPLE_TIME_V 0x3FF
@ -754,7 +723,7 @@ extern "C" {
#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x3FFF
#define I2C_SCL_WAIT_HIGH_PERIOD_S 14
/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This register is used to configure the clock num during SCL is low level.*/
/*description: */
#define I2C_SCL_HIGH_PERIOD 0x00003FFF
#define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S))
#define I2C_SCL_HIGH_PERIOD_V 0x3FFF
@ -762,8 +731,7 @@ extern "C" {
#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0040)
/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */
/*description: This register is used to configure the clock num between the
negedge of SDA and negedge of SCL for start mark.*/
/*description: */
#define I2C_SCL_START_HOLD_TIME 0x000003FF
#define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S))
#define I2C_SCL_START_HOLD_TIME_V 0x3FF
@ -771,8 +739,7 @@ extern "C" {
#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x0044)
/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */
/*description: This register is used to configure the clock num between the
posedge of SCL and the negedge of SDA for restart mark.*/
/*description: */
#define I2C_SCL_RSTART_SETUP_TIME 0x000003FF
#define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S))
#define I2C_SCL_RSTART_SETUP_TIME_V 0x3FF
@ -780,7 +747,7 @@ extern "C" {
#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0048)
/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This register is used to configure the clock num after the STOP bit's posedge.*/
/*description: */
#define I2C_SCL_STOP_HOLD_TIME 0x00003FFF
#define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S))
#define I2C_SCL_STOP_HOLD_TIME_V 0x3FFF
@ -788,8 +755,7 @@ extern "C" {
#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x004C)
/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
/*description: This register is used to configure the clock num between the
posedge of SCL and the posedge of SDA.*/
/*description: */
#define I2C_SCL_STOP_SETUP_TIME 0x000003FF
#define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S))
#define I2C_SCL_STOP_SETUP_TIME_V 0x3FF
@ -797,14 +763,13 @@ extern "C" {
#define I2C_SCL_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0050)
/* I2C_SCL_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: This is the filter enable bit for SCL.*/
/*description: */
#define I2C_SCL_FILTER_EN (BIT(3))
#define I2C_SCL_FILTER_EN_M (BIT(3))
#define I2C_SCL_FILTER_EN_V 0x1
#define I2C_SCL_FILTER_EN_S 3
/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: When input SCL's pulse width is smaller than this register value
I2C ignores this pulse.*/
/*description: */
#define I2C_SCL_FILTER_THRES 0x00000007
#define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S))
#define I2C_SCL_FILTER_THRES_V 0x7
@ -812,14 +777,13 @@ extern "C" {
#define I2C_SDA_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0054)
/* I2C_SDA_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: This is the filter enable bit for SDA.*/
/*description: */
#define I2C_SDA_FILTER_EN (BIT(3))
#define I2C_SDA_FILTER_EN_M (BIT(3))
#define I2C_SDA_FILTER_EN_V 0x1
#define I2C_SDA_FILTER_EN_S 3
/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: When input SCL's pulse width is smaller than this register value
I2C ignores this pulse.*/
/*description: */
#define I2C_SDA_FILTER_THRES 0x00000007
#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S))
#define I2C_SDA_FILTER_THRES_V 0x7
@ -827,14 +791,13 @@ extern "C" {
#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x0058)
/* I2C_COMMAND0_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command0 is done in I2C Master mode this bit changes to high level.*/
/*description: */
#define I2C_COMMAND0_DONE (BIT(31))
#define I2C_COMMAND0_DONE_M (BIT(31))
#define I2C_COMMAND0_DONE_V 0x1
#define I2C_COMMAND0_DONE_S 31
/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command0. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
/*description: */
#define I2C_COMMAND0 0x00003FFF
#define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S))
#define I2C_COMMAND0_V 0x3FFF
@ -842,14 +805,13 @@ extern "C" {
#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x005C)
/* I2C_COMMAND1_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command1 is done in I2C Master mode this bit changes to high level.*/
/*description: */
#define I2C_COMMAND1_DONE (BIT(31))
#define I2C_COMMAND1_DONE_M (BIT(31))
#define I2C_COMMAND1_DONE_V 0x1
#define I2C_COMMAND1_DONE_S 31
/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command1. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
/*description: */
#define I2C_COMMAND1 0x00003FFF
#define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S))
#define I2C_COMMAND1_V 0x3FFF
@ -857,14 +819,13 @@ extern "C" {
#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x0060)
/* I2C_COMMAND2_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command2 is done in I2C Master mode this bit changes to high level.*/
/*description: */
#define I2C_COMMAND2_DONE (BIT(31))
#define I2C_COMMAND2_DONE_M (BIT(31))
#define I2C_COMMAND2_DONE_V 0x1
#define I2C_COMMAND2_DONE_S 31
/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command2. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
/*description: */
#define I2C_COMMAND2 0x00003FFF
#define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S))
#define I2C_COMMAND2_V 0x3FFF
@ -872,14 +833,13 @@ extern "C" {
#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x0064)
/* I2C_COMMAND3_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command3 is done in I2C Master mode this bit changes to high level.*/
/*description: */
#define I2C_COMMAND3_DONE (BIT(31))
#define I2C_COMMAND3_DONE_M (BIT(31))
#define I2C_COMMAND3_DONE_V 0x1
#define I2C_COMMAND3_DONE_S 31
/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command3. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
/*description: */
#define I2C_COMMAND3 0x00003FFF
#define I2C_COMMAND3_M ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S))
#define I2C_COMMAND3_V 0x3FFF
@ -887,14 +847,13 @@ extern "C" {
#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x0068)
/* I2C_COMMAND4_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command4 is done in I2C Master mode this bit changes to high level.*/
/*description: */
#define I2C_COMMAND4_DONE (BIT(31))
#define I2C_COMMAND4_DONE_M (BIT(31))
#define I2C_COMMAND4_DONE_V 0x1
#define I2C_COMMAND4_DONE_S 31
/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command4. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
/*description: */
#define I2C_COMMAND4 0x00003FFF
#define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S))
#define I2C_COMMAND4_V 0x3FFF
@ -902,14 +861,13 @@ extern "C" {
#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x006C)
/* I2C_COMMAND5_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command5 is done in I2C Master mode this bit changes to high level.*/
/*description: */
#define I2C_COMMAND5_DONE (BIT(31))
#define I2C_COMMAND5_DONE_M (BIT(31))
#define I2C_COMMAND5_DONE_V 0x1
#define I2C_COMMAND5_DONE_S 31
/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command5. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
/*description: */
#define I2C_COMMAND5 0x00003FFF
#define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S))
#define I2C_COMMAND5_V 0x3FFF
@ -917,14 +875,13 @@ extern "C" {
#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x0070)
/* I2C_COMMAND6_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command6 is done in I2C Master mode this bit changes to high level.*/
/*description: */
#define I2C_COMMAND6_DONE (BIT(31))
#define I2C_COMMAND6_DONE_M (BIT(31))
#define I2C_COMMAND6_DONE_V 0x1
#define I2C_COMMAND6_DONE_S 31
/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command6. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
/*description: */
#define I2C_COMMAND6 0x00003FFF
#define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S))
#define I2C_COMMAND6_V 0x3FFF
@ -932,14 +889,13 @@ extern "C" {
#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x0074)
/* I2C_COMMAND7_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command7 is done in I2C Master mode this bit changes to high level.*/
/*description: */
#define I2C_COMMAND7_DONE (BIT(31))
#define I2C_COMMAND7_DONE_M (BIT(31))
#define I2C_COMMAND7_DONE_V 0x1
#define I2C_COMMAND7_DONE_S 31
/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command7. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
/*description: */
#define I2C_COMMAND7 0x00003FFF
#define I2C_COMMAND7_M ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S))
#define I2C_COMMAND7_V 0x3FFF
@ -947,14 +903,13 @@ extern "C" {
#define I2C_COMD8_REG(i) (REG_I2C_BASE(i) + 0x0078)
/* I2C_COMMAND8_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command8 is done in I2C Master mode this bit changes to high level.*/
/*description: */
#define I2C_COMMAND8_DONE (BIT(31))
#define I2C_COMMAND8_DONE_M (BIT(31))
#define I2C_COMMAND8_DONE_V 0x1
#define I2C_COMMAND8_DONE_S 31
/* I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command8. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
/*description: */
#define I2C_COMMAND8 0x00003FFF
#define I2C_COMMAND8_M ((I2C_COMMAND8_V)<<(I2C_COMMAND8_S))
#define I2C_COMMAND8_V 0x3FFF
@ -962,14 +917,13 @@ extern "C" {
#define I2C_COMD9_REG(i) (REG_I2C_BASE(i) + 0x007C)
/* I2C_COMMAND9_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command9 is done in I2C Master mode this bit changes to high level.*/
/*description: */
#define I2C_COMMAND9_DONE (BIT(31))
#define I2C_COMMAND9_DONE_M (BIT(31))
#define I2C_COMMAND9_DONE_V 0x1
#define I2C_COMMAND9_DONE_S 31
/* I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command9. It consists of three part. op_code
is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
/*description: */
#define I2C_COMMAND9 0x00003FFF
#define I2C_COMMAND9_M ((I2C_COMMAND9_V)<<(I2C_COMMAND9_S))
#define I2C_COMMAND9_V 0x3FFF
@ -977,14 +931,13 @@ extern "C" {
#define I2C_COMD10_REG(i) (REG_I2C_BASE(i) + 0x0080)
/* I2C_COMMAND10_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command10 is done in I2C Master mode this bit changes to high level.*/
/*description: */
#define I2C_COMMAND10_DONE (BIT(31))
#define I2C_COMMAND10_DONE_M (BIT(31))
#define I2C_COMMAND10_DONE_V 0x1
#define I2C_COMMAND10_DONE_S 31
/* I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command10. It consists of three part.
op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
/*description: */
#define I2C_COMMAND10 0x00003FFF
#define I2C_COMMAND10_M ((I2C_COMMAND10_V)<<(I2C_COMMAND10_S))
#define I2C_COMMAND10_V 0x3FFF
@ -992,14 +945,13 @@ extern "C" {
#define I2C_COMD11_REG(i) (REG_I2C_BASE(i) + 0x0084)
/* I2C_COMMAND11_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command11 is done in I2C Master mode this bit changes to high level.*/
/*description: */
#define I2C_COMMAND11_DONE (BIT(31))
#define I2C_COMMAND11_DONE_M (BIT(31))
#define I2C_COMMAND11_DONE_V 0x1
#define I2C_COMMAND11_DONE_S 31
/* I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command11. It consists of three part.
op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
/*description: */
#define I2C_COMMAND11 0x00003FFF
#define I2C_COMMAND11_M ((I2C_COMMAND11_V)<<(I2C_COMMAND11_S))
#define I2C_COMMAND11_V 0x3FFF
@ -1007,14 +959,13 @@ extern "C" {
#define I2C_COMD12_REG(i) (REG_I2C_BASE(i) + 0x0088)
/* I2C_COMMAND12_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command12 is done in I2C Master mode this bit changes to high level.*/
/*description: */
#define I2C_COMMAND12_DONE (BIT(31))
#define I2C_COMMAND12_DONE_M (BIT(31))
#define I2C_COMMAND12_DONE_V 0x1
#define I2C_COMMAND12_DONE_S 31
/* I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command12. It consists of three part.
op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
/*description: */
#define I2C_COMMAND12 0x00003FFF
#define I2C_COMMAND12_M ((I2C_COMMAND12_V)<<(I2C_COMMAND12_S))
#define I2C_COMMAND12_V 0x3FFF
@ -1022,14 +973,13 @@ extern "C" {
#define I2C_COMD13_REG(i) (REG_I2C_BASE(i) + 0x008C)
/* I2C_COMMAND13_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command13 is done in I2C Master mode this bit changes to high level.*/
/*description: */
#define I2C_COMMAND13_DONE (BIT(31))
#define I2C_COMMAND13_DONE_M (BIT(31))
#define I2C_COMMAND13_DONE_V 0x1
#define I2C_COMMAND13_DONE_S 31
/* I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command13. It consists of three part.
op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
/*description: */
#define I2C_COMMAND13 0x00003FFF
#define I2C_COMMAND13_M ((I2C_COMMAND13_V)<<(I2C_COMMAND13_S))
#define I2C_COMMAND13_V 0x3FFF
@ -1037,14 +987,13 @@ extern "C" {
#define I2C_COMD14_REG(i) (REG_I2C_BASE(i) + 0x0090)
/* I2C_COMMAND14_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command14 is done in I2C Master mode this bit changes to high level.*/
/*description: */
#define I2C_COMMAND14_DONE (BIT(31))
#define I2C_COMMAND14_DONE_M (BIT(31))
#define I2C_COMMAND14_DONE_V 0x1
#define I2C_COMMAND14_DONE_S 31
/* I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command14. It consists of three part.
op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
/*description: */
#define I2C_COMMAND14 0x00003FFF
#define I2C_COMMAND14_M ((I2C_COMMAND14_V)<<(I2C_COMMAND14_S))
#define I2C_COMMAND14_V 0x3FFF
@ -1052,14 +1001,13 @@ extern "C" {
#define I2C_COMD15_REG(i) (REG_I2C_BASE(i) + 0x0094)
/* I2C_COMMAND15_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: When command15 is done in I2C Master mode this bit changes to high level.*/
/*description: */
#define I2C_COMMAND15_DONE (BIT(31))
#define I2C_COMMAND15_DONE_M (BIT(31))
#define I2C_COMMAND15_DONE_V 0x1
#define I2C_COMMAND15_DONE_S 31
/* I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
/*description: This is the content of command15. It consists of three part.
op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/
/*description: */
#define I2C_COMMAND15 0x00003FFF
#define I2C_COMMAND15_M ((I2C_COMMAND15_V)<<(I2C_COMMAND15_S))
#define I2C_COMMAND15_V 0x3FFF

386
components/soc/esp32s2beta/include/soc/i2s_reg.h
View File

@ -1,4 +1,4 @@
// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -203,6 +203,12 @@ extern "C" {
#define I2S_TX_RESET_S 0
#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0x000c)
/* I2S_V_SYNC_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the i2s_v_sync_int interrupt*/
#define I2S_V_SYNC_INT_RAW (BIT(17))
#define I2S_V_SYNC_INT_RAW_M (BIT(17))
#define I2S_V_SYNC_INT_RAW_V 0x1
#define I2S_V_SYNC_INT_RAW_S 17
/* I2S_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the i2s_out_total_eof_int interrupt*/
#define I2S_OUT_TOTAL_EOF_INT_RAW (BIT(16))
@ -307,6 +313,12 @@ extern "C" {
#define I2S_RX_TAKE_DATA_INT_RAW_S 0
#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x0010)
/* I2S_V_SYNC_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
/*description: The masked interrupt status bit for the i2s_v_sync_int interrupt*/
#define I2S_V_SYNC_INT_ST (BIT(17))
#define I2S_V_SYNC_INT_ST_M (BIT(17))
#define I2S_V_SYNC_INT_ST_V 0x1
#define I2S_V_SYNC_INT_ST_S 17
/* I2S_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
/*description: The masked interrupt status bit for the i2s_out_total_eof_int interrupt*/
#define I2S_OUT_TOTAL_EOF_INT_ST (BIT(16))
@ -411,6 +423,12 @@ extern "C" {
#define I2S_RX_TAKE_DATA_INT_ST_S 0
#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x0014)
/* I2S_V_SYNC_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the i2s_v_sync_int interrupt*/
#define I2S_V_SYNC_INT_ENA (BIT(17))
#define I2S_V_SYNC_INT_ENA_M (BIT(17))
#define I2S_V_SYNC_INT_ENA_V 0x1
#define I2S_V_SYNC_INT_ENA_S 17
/* I2S_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the i2s_out_total_eof_int interrupt*/
#define I2S_OUT_TOTAL_EOF_INT_ENA (BIT(16))
@ -515,6 +533,12 @@ extern "C" {
#define I2S_RX_TAKE_DATA_INT_ENA_S 0
#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x0018)
/* I2S_V_SYNC_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
/*description: Set this bit to clear the i2s_v_sync_int interrupt*/
#define I2S_V_SYNC_INT_CLR (BIT(17))
#define I2S_V_SYNC_INT_CLR_M (BIT(17))
#define I2S_V_SYNC_INT_CLR_V 0x1
#define I2S_V_SYNC_INT_CLR_S 17
/* I2S_OUT_TOTAL_EOF_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
/*description: Set this bit to clear the i2s_out_total_eof_int interrupt*/
#define I2S_OUT_TOTAL_EOF_INT_CLR (BIT(16))
@ -952,6 +976,13 @@ extern "C" {
#define I2S_OUTLINK_DSCR_BF1_S 0
#define I2S_LC_CONF_REG(i) (REG_I2S_BASE(i) + 0x0060)
/* I2S_EXT_MEM_BK_SIZE : R/W ;bitpos:[15:14] ;default: 2'b0 ; */
/*description: DMA access external memory block size. 0: 16 bytes 1: 32
bytes 2:64 bytes 3:reserved*/
#define I2S_EXT_MEM_BK_SIZE 0x00000003
#define I2S_EXT_MEM_BK_SIZE_M ((I2S_EXT_MEM_BK_SIZE_V)<<(I2S_EXT_MEM_BK_SIZE_S))
#define I2S_EXT_MEM_BK_SIZE_V 0x3
#define I2S_EXT_MEM_BK_SIZE_S 14
/* I2S_MEM_TRANS_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: don't use*/
#define I2S_MEM_TRANS_EN (BIT(13))
@ -1168,226 +1199,6 @@ extern "C" {
#define I2S_LC_FIFO_TIMEOUT_V 0xFF
#define I2S_LC_FIFO_TIMEOUT_S 0
#define I2S_CVSD_CONF0_REG(i) (REG_I2S_BASE(i) + 0x0080)
/* I2S_CVSD_Y_MIN : R/W ;bitpos:[31:16] ;default: 16'h8000 ; */
/*description: don't use*/
#define I2S_CVSD_Y_MIN 0x0000FFFF
#define I2S_CVSD_Y_MIN_M ((I2S_CVSD_Y_MIN_V)<<(I2S_CVSD_Y_MIN_S))
#define I2S_CVSD_Y_MIN_V 0xFFFF
#define I2S_CVSD_Y_MIN_S 16
/* I2S_CVSD_Y_MAX : R/W ;bitpos:[15:0] ;default: 16'h7fff ; */
/*description: don't use*/
#define I2S_CVSD_Y_MAX 0x0000FFFF
#define I2S_CVSD_Y_MAX_M ((I2S_CVSD_Y_MAX_V)<<(I2S_CVSD_Y_MAX_S))
#define I2S_CVSD_Y_MAX_V 0xFFFF
#define I2S_CVSD_Y_MAX_S 0
#define I2S_CVSD_CONF1_REG(i) (REG_I2S_BASE(i) + 0x0084)
/* I2S_CVSD_SIGMA_MIN : R/W ;bitpos:[31:16] ;default: 16'd10 ; */
/*description: don't use*/
#define I2S_CVSD_SIGMA_MIN 0x0000FFFF
#define I2S_CVSD_SIGMA_MIN_M ((I2S_CVSD_SIGMA_MIN_V)<<(I2S_CVSD_SIGMA_MIN_S))
#define I2S_CVSD_SIGMA_MIN_V 0xFFFF
#define I2S_CVSD_SIGMA_MIN_S 16
/* I2S_CVSD_SIGMA_MAX : R/W ;bitpos:[15:0] ;default: 16'd1280 ; */
/*description: don't use*/
#define I2S_CVSD_SIGMA_MAX 0x0000FFFF
#define I2S_CVSD_SIGMA_MAX_M ((I2S_CVSD_SIGMA_MAX_V)<<(I2S_CVSD_SIGMA_MAX_S))
#define I2S_CVSD_SIGMA_MAX_V 0xFFFF
#define I2S_CVSD_SIGMA_MAX_S 0
#define I2S_CVSD_CONF2_REG(i) (REG_I2S_BASE(i) + 0x0088)
/* I2S_CVSD_H : R/W ;bitpos:[18:16] ;default: 3'd5 ; */
/*description: don't use*/
#define I2S_CVSD_H 0x00000007
#define I2S_CVSD_H_M ((I2S_CVSD_H_V)<<(I2S_CVSD_H_S))
#define I2S_CVSD_H_V 0x7
#define I2S_CVSD_H_S 16
/* I2S_CVSD_BETA : R/W ;bitpos:[15:6] ;default: 10'd10 ; */
/*description: don't use*/
#define I2S_CVSD_BETA 0x000003FF
#define I2S_CVSD_BETA_M ((I2S_CVSD_BETA_V)<<(I2S_CVSD_BETA_S))
#define I2S_CVSD_BETA_V 0x3FF
#define I2S_CVSD_BETA_S 6
/* I2S_CVSD_J : R/W ;bitpos:[5:3] ;default: 3'h4 ; */
/*description: don't use*/
#define I2S_CVSD_J 0x00000007
#define I2S_CVSD_J_M ((I2S_CVSD_J_V)<<(I2S_CVSD_J_S))
#define I2S_CVSD_J_V 0x7
#define I2S_CVSD_J_S 3
/* I2S_CVSD_K : R/W ;bitpos:[2:0] ;default: 3'h4 ; */
/*description: don't use*/
#define I2S_CVSD_K 0x00000007
#define I2S_CVSD_K_M ((I2S_CVSD_K_V)<<(I2S_CVSD_K_S))
#define I2S_CVSD_K_V 0x7
#define I2S_CVSD_K_S 0
#define I2S_PLC_CONF0_REG(i) (REG_I2S_BASE(i) + 0x008C)
/* I2S_N_MIN_ERR : R/W ;bitpos:[27:25] ;default: 3'd4 ; */
/*description: don't use*/
#define I2S_N_MIN_ERR 0x00000007
#define I2S_N_MIN_ERR_M ((I2S_N_MIN_ERR_V)<<(I2S_N_MIN_ERR_S))
#define I2S_N_MIN_ERR_V 0x7
#define I2S_N_MIN_ERR_S 25
/* I2S_PACK_LEN_8K : R/W ;bitpos:[24:20] ;default: 5'd10 ; */
/*description: don't use*/
#define I2S_PACK_LEN_8K 0x0000001F
#define I2S_PACK_LEN_8K_M ((I2S_PACK_LEN_8K_V)<<(I2S_PACK_LEN_8K_S))
#define I2S_PACK_LEN_8K_V 0x1F
#define I2S_PACK_LEN_8K_S 20
/* I2S_MAX_SLIDE_SAMPLE : R/W ;bitpos:[19:12] ;default: 8'd128 ; */
/*description: don't use*/
#define I2S_MAX_SLIDE_SAMPLE 0x000000FF
#define I2S_MAX_SLIDE_SAMPLE_M ((I2S_MAX_SLIDE_SAMPLE_V)<<(I2S_MAX_SLIDE_SAMPLE_S))
#define I2S_MAX_SLIDE_SAMPLE_V 0xFF
#define I2S_MAX_SLIDE_SAMPLE_S 12
/* I2S_SHIFT_RATE : R/W ;bitpos:[11:9] ;default: 3'h1 ; */
/*description: don't use*/
#define I2S_SHIFT_RATE 0x00000007
#define I2S_SHIFT_RATE_M ((I2S_SHIFT_RATE_V)<<(I2S_SHIFT_RATE_S))
#define I2S_SHIFT_RATE_V 0x7
#define I2S_SHIFT_RATE_S 9
/* I2S_N_ERR_SEG : R/W ;bitpos:[8:6] ;default: 3'h4 ; */
/*description: don't use*/
#define I2S_N_ERR_SEG 0x00000007
#define I2S_N_ERR_SEG_M ((I2S_N_ERR_SEG_V)<<(I2S_N_ERR_SEG_S))
#define I2S_N_ERR_SEG_V 0x7
#define I2S_N_ERR_SEG_S 6
/* I2S_GOOD_PACK_MAX : R/W ;bitpos:[5:0] ;default: 6'h39 ; */
/*description: don't use*/
#define I2S_GOOD_PACK_MAX 0x0000003F
#define I2S_GOOD_PACK_MAX_M ((I2S_GOOD_PACK_MAX_V)<<(I2S_GOOD_PACK_MAX_S))
#define I2S_GOOD_PACK_MAX_V 0x3F
#define I2S_GOOD_PACK_MAX_S 0
#define I2S_PLC_CONF1_REG(i) (REG_I2S_BASE(i) + 0x0090)
/* I2S_SLIDE_WIN_LEN : R/W ;bitpos:[31:24] ;default: 8'd160 ; */
/*description: don't use*/
#define I2S_SLIDE_WIN_LEN 0x000000FF
#define I2S_SLIDE_WIN_LEN_M ((I2S_SLIDE_WIN_LEN_V)<<(I2S_SLIDE_WIN_LEN_S))
#define I2S_SLIDE_WIN_LEN_V 0xFF
#define I2S_SLIDE_WIN_LEN_S 24
/* I2S_BAD_OLA_WIN2_PARA : R/W ;bitpos:[23:16] ;default: 8'd23 ; */
/*description: don't use*/
#define I2S_BAD_OLA_WIN2_PARA 0x000000FF
#define I2S_BAD_OLA_WIN2_PARA_M ((I2S_BAD_OLA_WIN2_PARA_V)<<(I2S_BAD_OLA_WIN2_PARA_S))
#define I2S_BAD_OLA_WIN2_PARA_V 0xFF
#define I2S_BAD_OLA_WIN2_PARA_S 16
/* I2S_BAD_OLA_WIN2_PARA_SHIFT : R/W ;bitpos:[15:12] ;default: 4'd8 ; */
/*description: don't use*/
#define I2S_BAD_OLA_WIN2_PARA_SHIFT 0x0000000F
#define I2S_BAD_OLA_WIN2_PARA_SHIFT_M ((I2S_BAD_OLA_WIN2_PARA_SHIFT_V)<<(I2S_BAD_OLA_WIN2_PARA_SHIFT_S))
#define I2S_BAD_OLA_WIN2_PARA_SHIFT_V 0xF
#define I2S_BAD_OLA_WIN2_PARA_SHIFT_S 12
/* I2S_BAD_CEF_ATTEN_PARA_SHIFT : R/W ;bitpos:[11:8] ;default: 4'd10 ; */
/*description: don't use*/
#define I2S_BAD_CEF_ATTEN_PARA_SHIFT 0x0000000F
#define I2S_BAD_CEF_ATTEN_PARA_SHIFT_M ((I2S_BAD_CEF_ATTEN_PARA_SHIFT_V)<<(I2S_BAD_CEF_ATTEN_PARA_SHIFT_S))
#define I2S_BAD_CEF_ATTEN_PARA_SHIFT_V 0xF
#define I2S_BAD_CEF_ATTEN_PARA_SHIFT_S 8
/* I2S_BAD_CEF_ATTEN_PARA : R/W ;bitpos:[7:0] ;default: 8'd5 ; */
/*description: don't use*/
#define I2S_BAD_CEF_ATTEN_PARA 0x000000FF
#define I2S_BAD_CEF_ATTEN_PARA_M ((I2S_BAD_CEF_ATTEN_PARA_V)<<(I2S_BAD_CEF_ATTEN_PARA_S))
#define I2S_BAD_CEF_ATTEN_PARA_V 0xFF
#define I2S_BAD_CEF_ATTEN_PARA_S 0
#define I2S_PLC_CONF2_REG(i) (REG_I2S_BASE(i) + 0x0094)
/* I2S_MIN_PERIOD : R/W ;bitpos:[6:2] ;default: 5'd10 ; */
/*description: don't use*/
#define I2S_MIN_PERIOD 0x0000001F
#define I2S_MIN_PERIOD_M ((I2S_MIN_PERIOD_V)<<(I2S_MIN_PERIOD_S))
#define I2S_MIN_PERIOD_V 0x1F
#define I2S_MIN_PERIOD_S 2
/* I2S_CVSD_SEG_MOD : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
/*description: don't use*/
#define I2S_CVSD_SEG_MOD 0x00000003
#define I2S_CVSD_SEG_MOD_M ((I2S_CVSD_SEG_MOD_V)<<(I2S_CVSD_SEG_MOD_S))
#define I2S_CVSD_SEG_MOD_V 0x3
#define I2S_CVSD_SEG_MOD_S 0
#define I2S_ESCO_CONF0_REG(i) (REG_I2S_BASE(i) + 0x0098)
/* I2S_PLC2DMA_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: don't use*/
#define I2S_PLC2DMA_EN (BIT(12))
#define I2S_PLC2DMA_EN_M (BIT(12))
#define I2S_PLC2DMA_EN_V 0x1
#define I2S_PLC2DMA_EN_S 12
/* I2S_PLC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: don't use*/
#define I2S_PLC_EN (BIT(11))
#define I2S_PLC_EN_M (BIT(11))
#define I2S_PLC_EN_V 0x1
#define I2S_PLC_EN_S 11
/* I2S_CVSD_DEC_RESET : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: don't use*/
#define I2S_CVSD_DEC_RESET (BIT(10))
#define I2S_CVSD_DEC_RESET_M (BIT(10))
#define I2S_CVSD_DEC_RESET_V 0x1
#define I2S_CVSD_DEC_RESET_S 10
/* I2S_CVSD_DEC_START : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: don't use*/
#define I2S_CVSD_DEC_START (BIT(9))
#define I2S_CVSD_DEC_START_M (BIT(9))
#define I2S_CVSD_DEC_START_V 0x1
#define I2S_CVSD_DEC_START_S 9
/* I2S_ESCO_CVSD_INF_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: don't use*/
#define I2S_ESCO_CVSD_INF_EN (BIT(8))
#define I2S_ESCO_CVSD_INF_EN_M (BIT(8))
#define I2S_ESCO_CVSD_INF_EN_V 0x1
#define I2S_ESCO_CVSD_INF_EN_S 8
/* I2S_ESCO_CVSD_PACK_LEN_8K : R/W ;bitpos:[7:3] ;default: 5'b0 ; */
/*description: don't use*/
#define I2S_ESCO_CVSD_PACK_LEN_8K 0x0000001F
#define I2S_ESCO_CVSD_PACK_LEN_8K_M ((I2S_ESCO_CVSD_PACK_LEN_8K_V)<<(I2S_ESCO_CVSD_PACK_LEN_8K_S))
#define I2S_ESCO_CVSD_PACK_LEN_8K_V 0x1F
#define I2S_ESCO_CVSD_PACK_LEN_8K_S 3
/* I2S_ESCO_CVSD_DEC_PACK_ERR : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: don't use*/
#define I2S_ESCO_CVSD_DEC_PACK_ERR (BIT(2))
#define I2S_ESCO_CVSD_DEC_PACK_ERR_M (BIT(2))
#define I2S_ESCO_CVSD_DEC_PACK_ERR_V 0x1
#define I2S_ESCO_CVSD_DEC_PACK_ERR_S 2
/* I2S_ESCO_CHAN_MOD : R/W ;bitpos:[1] ;default: 1'd0 ; */
/*description: don't use*/
#define I2S_ESCO_CHAN_MOD (BIT(1))
#define I2S_ESCO_CHAN_MOD_M (BIT(1))
#define I2S_ESCO_CHAN_MOD_V 0x1
#define I2S_ESCO_CHAN_MOD_S 1
/* I2S_ESCO_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: don't use*/
#define I2S_ESCO_EN (BIT(0))
#define I2S_ESCO_EN_M (BIT(0))
#define I2S_ESCO_EN_V 0x1
#define I2S_ESCO_EN_S 0
#define I2S_SCO_CONF0_REG(i) (REG_I2S_BASE(i) + 0x009c)
/* I2S_CVSD_ENC_RESET : R/W ;bitpos:[3] ;default: 1'd0 ; */
/*description: don't use*/
#define I2S_CVSD_ENC_RESET (BIT(3))
#define I2S_CVSD_ENC_RESET_M (BIT(3))
#define I2S_CVSD_ENC_RESET_V 0x1
#define I2S_CVSD_ENC_RESET_S 3
/* I2S_CVSD_ENC_START : R/W ;bitpos:[2] ;default: 1'd0 ; */
/*description: don't use*/
#define I2S_CVSD_ENC_START (BIT(2))
#define I2S_CVSD_ENC_START_M (BIT(2))
#define I2S_CVSD_ENC_START_V 0x1
#define I2S_CVSD_ENC_START_S 2
/* I2S_SCO_NO_I2S_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */
/*description: don't use*/
#define I2S_SCO_NO_I2S_EN (BIT(1))
#define I2S_SCO_NO_I2S_EN_M (BIT(1))
#define I2S_SCO_NO_I2S_EN_V 0x1
#define I2S_SCO_NO_I2S_EN_S 1
/* I2S_SCO_WITH_I2S_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: don't use*/
#define I2S_SCO_WITH_I2S_EN (BIT(0))
#define I2S_SCO_WITH_I2S_EN_M (BIT(0))
#define I2S_SCO_WITH_I2S_EN_V 0x1
#define I2S_SCO_WITH_I2S_EN_S 0
#define I2S_CONF1_REG(i) (REG_I2S_BASE(i) + 0x00a0)
/* I2S_TX_ZEROS_RM_EN : R/W ;bitpos:[9] ;default: 1'd0 ; */
/*description: don't use*/
@ -1430,6 +1241,24 @@ extern "C" {
#define I2S_TX_PCM_CONF_S 0
#define I2S_PD_CONF_REG(i) (REG_I2S_BASE(i) + 0x00a4)
/* I2S_DMA_RAM_CLK_FO : R/W ;bitpos:[6] ;default: 1'h0 ; */
/*description: */
#define I2S_DMA_RAM_CLK_FO (BIT(6))
#define I2S_DMA_RAM_CLK_FO_M (BIT(6))
#define I2S_DMA_RAM_CLK_FO_V 0x1
#define I2S_DMA_RAM_CLK_FO_S 6
/* I2S_DMA_RAM_FORCE_PU : R/W ;bitpos:[5] ;default: 1'h1 ; */
/*description: */
#define I2S_DMA_RAM_FORCE_PU (BIT(5))
#define I2S_DMA_RAM_FORCE_PU_M (BIT(5))
#define I2S_DMA_RAM_FORCE_PU_V 0x1
#define I2S_DMA_RAM_FORCE_PU_S 5
/* I2S_DMA_RAM_FORCE_PD : R/W ;bitpos:[4] ;default: 1'h0 ; */
/*description: */
#define I2S_DMA_RAM_FORCE_PD (BIT(4))
#define I2S_DMA_RAM_FORCE_PD_M (BIT(4))
#define I2S_DMA_RAM_FORCE_PD_V 0x1
#define I2S_DMA_RAM_FORCE_PD_S 4
/* I2S_PLC_MEM_FORCE_PU : R/W ;bitpos:[3] ;default: 1'h1 ; */
/*description: */
#define I2S_PLC_MEM_FORCE_PU (BIT(3))
@ -1590,127 +1419,16 @@ extern "C" {
#define I2S_TX_BCK_DIV_NUM_V 0x3F
#define I2S_TX_BCK_DIV_NUM_S 0
#define I2S_PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x00b4)
/* I2S_RX_PDM_WAY_MODE : R/W ;bitpos:[31:30] ;default: 2'h0 ; */
/*description: 0/1 pdm rx use one-way*/
#define I2S_RX_PDM_WAY_MODE 0x00000003
#define I2S_RX_PDM_WAY_MODE_M ((I2S_RX_PDM_WAY_MODE_V)<<(I2S_RX_PDM_WAY_MODE_S))
#define I2S_RX_PDM_WAY_MODE_V 0x3
#define I2S_RX_PDM_WAY_MODE_S 30
/* I2S_TX_PDM_WAY_MODE : R/W ;bitpos:[29:28] ;default: 2'b0 ; */
/*description: 0/1 pdm rx use one-way*/
#define I2S_TX_PDM_WAY_MODE 0x00000003
#define I2S_TX_PDM_WAY_MODE_M ((I2S_TX_PDM_WAY_MODE_V)<<(I2S_TX_PDM_WAY_MODE_S))
#define I2S_TX_PDM_WAY_MODE_V 0x3
#define I2S_TX_PDM_WAY_MODE_S 28
/* I2S_TX_PDM_CHAN_MOD : R/W ;bitpos:[27:26] ;default: 2'h0 ; */
/*description: pdm tx channel mode*/
#define I2S_TX_PDM_CHAN_MOD 0x00000003
#define I2S_TX_PDM_CHAN_MOD_M ((I2S_TX_PDM_CHAN_MOD_V)<<(I2S_TX_PDM_CHAN_MOD_S))
#define I2S_TX_PDM_CHAN_MOD_V 0x3
#define I2S_TX_PDM_CHAN_MOD_S 26
/* I2S_TX_PDM_HP_BYPASS : R/W ;bitpos:[25] ;default: 1'h0 ; */
/*description: Set this bit to enable tx pdm hp filter bypass*/
#define I2S_TX_PDM_HP_BYPASS (BIT(25))
#define I2S_TX_PDM_HP_BYPASS_M (BIT(25))
#define I2S_TX_PDM_HP_BYPASS_V 0x1
#define I2S_TX_PDM_HP_BYPASS_S 25
/* I2S_RX_PDM_SINC_DSR_16_EN : R/W ;bitpos:[24] ;default: 1'h1 ; */
/*description: PDM down-sampling rate for filter group1 in receiver mode. 0:
downsample rate = 64 1:downsample rate = 128*/
#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(24))
#define I2S_RX_PDM_SINC_DSR_16_EN_M (BIT(24))
#define I2S_RX_PDM_SINC_DSR_16_EN_V 0x1
#define I2S_RX_PDM_SINC_DSR_16_EN_S 24
/* I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W ;bitpos:[23:22] ;default: 2'h1 ; */
/*description: Adjust size of input signal to filter module. 0: divided by 2
1:multiplied by 1 2:multiplied by 2 3:multiplied by 4*/
#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT 0x00000003
#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M ((I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V)<<(I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S))
#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V 0x3
#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S 22
/* I2S_TX_PDM_SINC_IN_SHIFT : R/W ;bitpos:[21:20] ;default: 2'h1 ; */
/*description: Adjust size of input signal to filter module. 0: divided by 2
1:multiplied by 1 2:multiplied by 2 3:multiplied by 4*/
#define I2S_TX_PDM_SINC_IN_SHIFT 0x00000003
#define I2S_TX_PDM_SINC_IN_SHIFT_M ((I2S_TX_PDM_SINC_IN_SHIFT_V)<<(I2S_TX_PDM_SINC_IN_SHIFT_S))
#define I2S_TX_PDM_SINC_IN_SHIFT_V 0x3
#define I2S_TX_PDM_SINC_IN_SHIFT_S 20
/* I2S_TX_PDM_LP_IN_SHIFT : R/W ;bitpos:[19:18] ;default: 2'h1 ; */
/*description: Adjust size of input signal to filter module. 0: divided by 2
1:multiplied by 1 2:multiplied by 2 3:multiplied by 4*/
#define I2S_TX_PDM_LP_IN_SHIFT 0x00000003
#define I2S_TX_PDM_LP_IN_SHIFT_M ((I2S_TX_PDM_LP_IN_SHIFT_V)<<(I2S_TX_PDM_LP_IN_SHIFT_S))
#define I2S_TX_PDM_LP_IN_SHIFT_V 0x3
#define I2S_TX_PDM_LP_IN_SHIFT_S 18
/* I2S_TX_PDM_HP_IN_SHIFT : R/W ;bitpos:[17:16] ;default: 2'h1 ; */
/*description: Adjust size of input signal to filter module. 0: divided by 2
1:multiplied by 1 2:multiplied by 2 3:multiplied by 4*/
#define I2S_TX_PDM_HP_IN_SHIFT 0x00000003
#define I2S_TX_PDM_HP_IN_SHIFT_M ((I2S_TX_PDM_HP_IN_SHIFT_V)<<(I2S_TX_PDM_HP_IN_SHIFT_S))
#define I2S_TX_PDM_HP_IN_SHIFT_V 0x3
#define I2S_TX_PDM_HP_IN_SHIFT_S 16
/* I2S_TX_PDM_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
/*description: set to 0*/
#define I2S_TX_PDM_PRESCALE 0x000000FF
#define I2S_TX_PDM_PRESCALE_M ((I2S_TX_PDM_PRESCALE_V)<<(I2S_TX_PDM_PRESCALE_S))
#define I2S_TX_PDM_PRESCALE_V 0xFF
#define I2S_TX_PDM_PRESCALE_S 8
/* I2S_TX_PDM_SINC_OSR2 : R/W ;bitpos:[7:4] ;default: 4'h2 ; */
/*description: upsample rate = 64 * reg_tx_pdm_sinc_osr2*/
#define I2S_TX_PDM_SINC_OSR2 0x0000000F
#define I2S_TX_PDM_SINC_OSR2_M ((I2S_TX_PDM_SINC_OSR2_V)<<(I2S_TX_PDM_SINC_OSR2_S))
#define I2S_TX_PDM_SINC_OSR2_V 0xF
#define I2S_TX_PDM_SINC_OSR2_S 4
/* I2S_PDM2PCM_CONV_EN : R/W ;bitpos:[3] ;default: 1'h0 ; */
/*description: Set this bit to enable PDM-to-PCM converter*/
#define I2S_PDM2PCM_CONV_EN (BIT(3))
#define I2S_PDM2PCM_CONV_EN_M (BIT(3))
#define I2S_PDM2PCM_CONV_EN_V 0x1
#define I2S_PDM2PCM_CONV_EN_S 3
/* I2S_PCM2PDM_CONV_EN : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: Set this bit to enable PCM-to-PDM converter*/
#define I2S_PCM2PDM_CONV_EN (BIT(2))
#define I2S_PCM2PDM_CONV_EN_M (BIT(2))
#define I2S_PCM2PDM_CONV_EN_V 0x1
#define I2S_PCM2PDM_CONV_EN_S 2
/* I2S_RX_PDM_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: Set this bit to enable receiver PDM mode*/
#define I2S_RX_PDM_EN (BIT(1))
#define I2S_RX_PDM_EN_M (BIT(1))
#define I2S_RX_PDM_EN_V 0x1
#define I2S_RX_PDM_EN_S 1
/* I2S_TX_PDM_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: Set this bit to enable transmitter PDM mode*/
#define I2S_TX_PDM_EN (BIT(0))
#define I2S_TX_PDM_EN_M (BIT(0))
#define I2S_TX_PDM_EN_V 0x1
#define I2S_TX_PDM_EN_S 0
#define I2S_PDM_FREQ_CONF_REG(i) (REG_I2S_BASE(i) + 0x00b8)
/* I2S_TX_PDM_FP : R/W ;bitpos:[19:10] ;default: 10'd960 ; */
/*description: PCM-to-PDM converter PDM frequency parameter*/
#define I2S_TX_PDM_FP 0x000003FF
#define I2S_TX_PDM_FP_M ((I2S_TX_PDM_FP_V)<<(I2S_TX_PDM_FP_S))
#define I2S_TX_PDM_FP_V 0x3FF
#define I2S_TX_PDM_FP_S 10
/* I2S_TX_PDM_FS : R/W ;bitpos:[9:0] ;default: 10'd480 ; */
/*description: PCM-to-PDM converter PCM frequency parameter*/
#define I2S_TX_PDM_FS 0x000003FF
#define I2S_TX_PDM_FS_M ((I2S_TX_PDM_FS_V)<<(I2S_TX_PDM_FS_S))
#define I2S_TX_PDM_FS_V 0x3FF
#define I2S_TX_PDM_FS_S 0
#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x00bc)
/* I2S_TX_IDLE : RO ;bitpos:[0] ;default: 1'b1 ; */
/*description: 1: i2s_tx is idle state*/
/*description: */
#define I2S_TX_IDLE (BIT(0))
#define I2S_TX_IDLE_M (BIT(0))
#define I2S_TX_IDLE_V 0x1
#define I2S_TX_IDLE_S 0
#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x00fc)
/* I2S_I2SDATE : R/W ;bitpos:[31:0] ;default: 32'h18092900 ; */
/* I2S_I2SDATE : R/W ;bitpos:[31:0] ;default: 32'h19052500 ; */
/*description: */
#define I2S_I2SDATE 0xFFFFFFFF
#define I2S_I2SDATE_M ((I2S_I2SDATE_V)<<(I2S_I2SDATE_S))

5
components/soc/esp32s2beta/include/soc/i2s_struct.h
View File

@ -1,4 +1,4 @@
// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -250,7 +250,8 @@ typedef volatile struct {
uint32_t out_data_burst_en: 1; /*Transmitter data transfer mode configuration bit. 1: to prepare out data with burst mode 0: to prepare out data with byte mode*/
uint32_t check_owner: 1; /*Set this bit to enable check owner bit by hardware*/
uint32_t mem_trans_en: 1; /*don't use*/
uint32_t reserved14: 18;
uint32_t ext_mem_bk_size: 2; /*DMA access external memory block size. 0: 16 bytes 1: 32 bytes 2:64 bytes 3:reserved*/
uint32_t reserved16: 16;
};
uint32_t val;
} lc_conf;

166
components/soc/esp32s2beta/include/soc/interrupt_reg.h
View File

@ -459,15 +459,23 @@ extern "C" {
#define DPORT_PRO_RSA_INTR_MAP_V 0x1F
#define DPORT_PRO_RSA_INTR_MAP_S 0
#define DPORT_PRO_SPI1_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0DC)
/* DPORT_PRO_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
#define DPORT_PRO_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0DC)
/* DPORT_PRO_SHA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SPI1_DMA_INT_MAP 0x0000001F
#define DPORT_PRO_SPI1_DMA_INT_MAP_M ((DPORT_PRO_SPI1_DMA_INT_MAP_V)<<(DPORT_PRO_SPI1_DMA_INT_MAP_S))
#define DPORT_PRO_SPI1_DMA_INT_MAP_V 0x1F
#define DPORT_PRO_SPI1_DMA_INT_MAP_S 0
#define DPORT_PRO_SHA_INTR_MAP 0x0000001F
#define DPORT_PRO_SHA_INTR_MAP_M ((DPORT_PRO_SHA_INTR_MAP_V)<<(DPORT_PRO_SHA_INTR_MAP_S))
#define DPORT_PRO_SHA_INTR_MAP_V 0x1F
#define DPORT_PRO_SHA_INTR_MAP_S 0
#define DPORT_PRO_SPI2_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0E0)
#define DPORT_PRO_AES_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0E0)
/* DPORT_PRO_AES_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_AES_INTR_MAP 0x0000001F
#define DPORT_PRO_AES_INTR_MAP_M ((DPORT_PRO_AES_INTR_MAP_V)<<(DPORT_PRO_AES_INTR_MAP_S))
#define DPORT_PRO_AES_INTR_MAP_V 0x1F
#define DPORT_PRO_AES_INTR_MAP_S 0
#define DPORT_PRO_SPI2_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0E4)
/* DPORT_PRO_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SPI2_DMA_INT_MAP 0x0000001F
@ -475,7 +483,7 @@ extern "C" {
#define DPORT_PRO_SPI2_DMA_INT_MAP_V 0x1F
#define DPORT_PRO_SPI2_DMA_INT_MAP_S 0
#define DPORT_PRO_SPI3_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0E4)
#define DPORT_PRO_SPI3_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0E8)
/* DPORT_PRO_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SPI3_DMA_INT_MAP 0x0000001F
@ -483,7 +491,7 @@ extern "C" {
#define DPORT_PRO_SPI3_DMA_INT_MAP_V 0x1F
#define DPORT_PRO_SPI3_DMA_INT_MAP_S 0
#define DPORT_PRO_WDG_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0E8)
#define DPORT_PRO_WDG_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0EC)
/* DPORT_PRO_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_WDG_INT_MAP 0x0000001F
@ -491,7 +499,7 @@ extern "C" {
#define DPORT_PRO_WDG_INT_MAP_V 0x1F
#define DPORT_PRO_WDG_INT_MAP_S 0
#define DPORT_PRO_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0EC)
#define DPORT_PRO_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0F0)
/* DPORT_PRO_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TIMER_INT1_MAP 0x0000001F
@ -499,7 +507,7 @@ extern "C" {
#define DPORT_PRO_TIMER_INT1_MAP_V 0x1F
#define DPORT_PRO_TIMER_INT1_MAP_S 0
#define DPORT_PRO_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0F0)
#define DPORT_PRO_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0F4)
/* DPORT_PRO_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TIMER_INT2_MAP 0x0000001F
@ -507,7 +515,7 @@ extern "C" {
#define DPORT_PRO_TIMER_INT2_MAP_V 0x1F
#define DPORT_PRO_TIMER_INT2_MAP_S 0
#define DPORT_PRO_TG_T0_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0F4)
#define DPORT_PRO_TG_T0_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0F8)
/* DPORT_PRO_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG_T0_EDGE_INT_MAP 0x0000001F
@ -515,7 +523,7 @@ extern "C" {
#define DPORT_PRO_TG_T0_EDGE_INT_MAP_V 0x1F
#define DPORT_PRO_TG_T0_EDGE_INT_MAP_S 0
#define DPORT_PRO_TG_T1_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0F8)
#define DPORT_PRO_TG_T1_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0FC)
/* DPORT_PRO_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG_T1_EDGE_INT_MAP 0x0000001F
@ -523,7 +531,7 @@ extern "C" {
#define DPORT_PRO_TG_T1_EDGE_INT_MAP_V 0x1F
#define DPORT_PRO_TG_T1_EDGE_INT_MAP_S 0
#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0FC)
#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x100)
/* DPORT_PRO_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG_WDT_EDGE_INT_MAP 0x0000001F
@ -531,7 +539,7 @@ extern "C" {
#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_V 0x1F
#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_S 0
#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x100)
#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x104)
/* DPORT_PRO_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG_LACT_EDGE_INT_MAP 0x0000001F
@ -539,7 +547,7 @@ extern "C" {
#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_V 0x1F
#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_S 0
#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x104)
#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x108)
/* DPORT_PRO_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG1_T0_EDGE_INT_MAP 0x0000001F
@ -547,7 +555,7 @@ extern "C" {
#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_V 0x1F
#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_S 0
#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x108)
#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x10C)
/* DPORT_PRO_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG1_T1_EDGE_INT_MAP 0x0000001F
@ -555,7 +563,7 @@ extern "C" {
#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_V 0x1F
#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_S 0
#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x10C)
#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x110)
/* DPORT_PRO_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP 0x0000001F
@ -563,7 +571,7 @@ extern "C" {
#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V 0x1F
#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S 0
#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x110)
#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x114)
/* DPORT_PRO_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP 0x0000001F
@ -571,7 +579,7 @@ extern "C" {
#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V 0x1F
#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S 0
#define DPORT_PRO_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x114)
#define DPORT_PRO_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x118)
/* DPORT_PRO_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_CACHE_IA_INT_MAP 0x0000001F
@ -579,7 +587,7 @@ extern "C" {
#define DPORT_PRO_CACHE_IA_INT_MAP_V 0x1F
#define DPORT_PRO_CACHE_IA_INT_MAP_S 0
#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x118)
#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x11C)
/* DPORT_PRO_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP 0x0000001F
@ -587,7 +595,7 @@ extern "C" {
#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_V 0x1F
#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_S 0
#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x11C)
#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x120)
/* DPORT_PRO_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP 0x0000001F
@ -595,7 +603,7 @@ extern "C" {
#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_V 0x1F
#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_S 0
#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x120)
#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x124)
/* DPORT_PRO_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP 0x0000001F
@ -603,7 +611,7 @@ extern "C" {
#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_V 0x1F
#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_S 0
#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x124)
#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x128)
/* DPORT_PRO_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP 0x0000001F
@ -611,7 +619,7 @@ extern "C" {
#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP_V 0x1F
#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP_S 0
#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x128)
#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x12C)
/* DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP 0x0000001F
@ -619,7 +627,7 @@ extern "C" {
#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_V 0x1F
#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_S 0
#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x12C)
#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x130)
/* DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP 0x0000001F
@ -627,7 +635,7 @@ extern "C" {
#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_V 0x1F
#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_S 0
#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x130)
#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x134)
/* DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP 0x0000001F
@ -635,7 +643,7 @@ extern "C" {
#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_V 0x1F
#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_S 0
#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x134)
#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x138)
/* DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP 0x0000001F
@ -643,7 +651,7 @@ extern "C" {
#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_V 0x1F
#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_S 0
#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x138)
#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x13C)
/* DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP 0x0000001F
@ -651,7 +659,7 @@ extern "C" {
#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_V 0x1F
#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_S 0
#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x13C)
#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x140)
/* DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP 0x0000001F
@ -659,7 +667,7 @@ extern "C" {
#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_V 0x1F
#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_S 0
#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x140)
#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x144)
/* DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP 0x0000001F
@ -667,7 +675,7 @@ extern "C" {
#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_V 0x1F
#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_S 0
#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x144)
#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x148)
/* DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP 0x0000001F
@ -675,21 +683,13 @@ extern "C" {
#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_V 0x1F
#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_S 0
#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x148)
/* DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
#define DPORT_PRO_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x14C)
/* DPORT_PRO_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP 0x0000001F
#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_M ((DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_V)<<(DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_S))
#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_V 0x1F
#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_S 0
#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x14C)
/* DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP 0x0000001F
#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_M ((DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_V)<<(DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_S))
#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_V 0x1F
#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_S 0
#define DPORT_PRO_SPI_MEM_REJECT_INTR_MAP 0x0000001F
#define DPORT_PRO_SPI_MEM_REJECT_INTR_MAP_M ((DPORT_PRO_SPI_MEM_REJECT_INTR_MAP_V)<<(DPORT_PRO_SPI_MEM_REJECT_INTR_MAP_S))
#define DPORT_PRO_SPI_MEM_REJECT_INTR_MAP_V 0x1F
#define DPORT_PRO_SPI_MEM_REJECT_INTR_MAP_S 0
#define DPORT_PRO_DMA_COPY_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x150)
/* DPORT_PRO_DMA_COPY_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
@ -715,7 +715,71 @@ extern "C" {
#define DPORT_PRO_SPI_INTR_4_MAP_V 0x1F
#define DPORT_PRO_SPI_INTR_4_MAP_S 0
#define DPORT_PRO_INTR_STATUS_0_REG (DR_REG_INTERRUPT_BASE + 0x15C)
#define DPORT_PRO_DCACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x15C)
/* DPORT_PRO_DCACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_DCACHE_PRELOAD_INT_MAP 0x0000001F
#define DPORT_PRO_DCACHE_PRELOAD_INT_MAP_M ((DPORT_PRO_DCACHE_PRELOAD_INT_MAP_V)<<(DPORT_PRO_DCACHE_PRELOAD_INT_MAP_S))
#define DPORT_PRO_DCACHE_PRELOAD_INT_MAP_V 0x1F
#define DPORT_PRO_DCACHE_PRELOAD_INT_MAP_S 0
#define DPORT_PRO_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x160)
/* DPORT_PRO_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_ICACHE_PRELOAD_INT_MAP 0x0000001F
#define DPORT_PRO_ICACHE_PRELOAD_INT_MAP_M ((DPORT_PRO_ICACHE_PRELOAD_INT_MAP_V)<<(DPORT_PRO_ICACHE_PRELOAD_INT_MAP_S))
#define DPORT_PRO_ICACHE_PRELOAD_INT_MAP_V 0x1F
#define DPORT_PRO_ICACHE_PRELOAD_INT_MAP_S 0
#define DPORT_PRO_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x164)
/* DPORT_PRO_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_APB_ADC_INT_MAP 0x0000001F
#define DPORT_PRO_APB_ADC_INT_MAP_M ((DPORT_PRO_APB_ADC_INT_MAP_V)<<(DPORT_PRO_APB_ADC_INT_MAP_S))
#define DPORT_PRO_APB_ADC_INT_MAP_V 0x1F
#define DPORT_PRO_APB_ADC_INT_MAP_S 0
#define DPORT_PRO_CRYPTO_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x168)
/* DPORT_PRO_CRYPTO_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_CRYPTO_DMA_INT_MAP 0x0000001F
#define DPORT_PRO_CRYPTO_DMA_INT_MAP_M ((DPORT_PRO_CRYPTO_DMA_INT_MAP_V)<<(DPORT_PRO_CRYPTO_DMA_INT_MAP_S))
#define DPORT_PRO_CRYPTO_DMA_INT_MAP_V 0x1F
#define DPORT_PRO_CRYPTO_DMA_INT_MAP_S 0
#define DPORT_PRO_CPU_PERI_ERROR_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x16C)
/* DPORT_PRO_CPU_PERI_ERROR_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_CPU_PERI_ERROR_INT_MAP 0x0000001F
#define DPORT_PRO_CPU_PERI_ERROR_INT_MAP_M ((DPORT_PRO_CPU_PERI_ERROR_INT_MAP_V)<<(DPORT_PRO_CPU_PERI_ERROR_INT_MAP_S))
#define DPORT_PRO_CPU_PERI_ERROR_INT_MAP_V 0x1F
#define DPORT_PRO_CPU_PERI_ERROR_INT_MAP_S 0
#define DPORT_PRO_APB_PERI_ERROR_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x170)
/* DPORT_PRO_APB_PERI_ERROR_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_APB_PERI_ERROR_INT_MAP 0x0000001F
#define DPORT_PRO_APB_PERI_ERROR_INT_MAP_M ((DPORT_PRO_APB_PERI_ERROR_INT_MAP_V)<<(DPORT_PRO_APB_PERI_ERROR_INT_MAP_S))
#define DPORT_PRO_APB_PERI_ERROR_INT_MAP_V 0x1F
#define DPORT_PRO_APB_PERI_ERROR_INT_MAP_S 0
#define DPORT_PRO_DCACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x174)
/* DPORT_PRO_DCACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_DCACHE_SYNC_INT_MAP 0x0000001F
#define DPORT_PRO_DCACHE_SYNC_INT_MAP_M ((DPORT_PRO_DCACHE_SYNC_INT_MAP_V)<<(DPORT_PRO_DCACHE_SYNC_INT_MAP_S))
#define DPORT_PRO_DCACHE_SYNC_INT_MAP_V 0x1F
#define DPORT_PRO_DCACHE_SYNC_INT_MAP_S 0
#define DPORT_PRO_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x178)
/* DPORT_PRO_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define DPORT_PRO_ICACHE_SYNC_INT_MAP 0x0000001F
#define DPORT_PRO_ICACHE_SYNC_INT_MAP_M ((DPORT_PRO_ICACHE_SYNC_INT_MAP_V)<<(DPORT_PRO_ICACHE_SYNC_INT_MAP_S))
#define DPORT_PRO_ICACHE_SYNC_INT_MAP_V 0x1F
#define DPORT_PRO_ICACHE_SYNC_INT_MAP_S 0
#define DPORT_PRO_INTR_STATUS_0_REG (DR_REG_INTERRUPT_BASE + 0x17C)
/* DPORT_PRO_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_PRO_INTR_STATUS_0 0xFFFFFFFF
@ -723,7 +787,7 @@ extern "C" {
#define DPORT_PRO_INTR_STATUS_0_V 0xFFFFFFFF
#define DPORT_PRO_INTR_STATUS_0_S 0
#define DPORT_PRO_INTR_STATUS_1_REG (DR_REG_INTERRUPT_BASE + 0x160)
#define DPORT_PRO_INTR_STATUS_1_REG (DR_REG_INTERRUPT_BASE + 0x180)
/* DPORT_PRO_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_PRO_INTR_STATUS_1 0xFFFFFFFF
@ -731,7 +795,7 @@ extern "C" {
#define DPORT_PRO_INTR_STATUS_1_V 0xFFFFFFFF
#define DPORT_PRO_INTR_STATUS_1_S 0
#define DPORT_PRO_INTR_STATUS_2_REG (DR_REG_INTERRUPT_BASE + 0x164)
#define DPORT_PRO_INTR_STATUS_2_REG (DR_REG_INTERRUPT_BASE + 0x184)
/* DPORT_PRO_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define DPORT_PRO_INTR_STATUS_2 0xFFFFFFFF
@ -739,7 +803,7 @@ extern "C" {
#define DPORT_PRO_INTR_STATUS_2_V 0xFFFFFFFF
#define DPORT_PRO_INTR_STATUS_2_S 0
#define INTERRUPT_CLOCK_GATE_REG (DR_REG_INTERRUPT_BASE + 0x168)
#define INTERRUPT_CLOCK_GATE_REG (DR_REG_INTERRUPT_BASE + 0x188)
/* DPORT_PRO_NMI_MASK_HW : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define DPORT_PRO_NMI_MASK_HW (BIT(1))
@ -754,7 +818,7 @@ extern "C" {
#define INTERRUPT_CLK_EN_S 0
#define INTERRUPT_DATE_REG (DR_REG_INTERRUPT_BASE + 0xFFC)
/* INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h1809110 ; */
/* INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h1904180 ; */
/*description: */
#define INTERRUPT_DATE 0x0FFFFFFF
#define INTERRUPT_DATE_M ((INTERRUPT_DATE_V)<<(INTERRUPT_DATE_S))

91
components/soc/esp32s2beta/include/soc/io_mux_reg.h
View File

@ -131,7 +131,7 @@
#define PIN_FUNC_GPIO 1
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDOWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define U1RXD_GPIO_NUM 18
@ -139,18 +139,17 @@
#define U0RXD_GPIO_NUM 44
#define U0TXD_GPIO_NUM 43
#define SPI_HD_GPIO_NUM 27
#define SPI_WP_GPIO_NUM 28
#define SPI_CS0_GPIO_NUM 29
#define SPI_CLK_GPIO_NUM 30
#define SPI_Q_GPIO_NUM 31
#define SPI_D_GPIO_NUM 32
#define SPI_CS0_GPIO_NUM 29
#define SPI_HD_GPIO_NUM 27
#define SPI_WP_GPIO_NUM 28
#define SD_CLK_GPIO_NUM 12
#define SD_CMD_GPIO_NUM 11
#define SD_DATA0_GPIO_NUM 13
#define SD_DATA1_GPIO_NUM 14
#define SD_DATA2_GPIO_NUM 9
#define SD_DATA3_GPIO_NUM 10
#define SPI_D4_GPIO_NUM 33
#define SPI_D5_GPIO_NUM 34
#define SPI_D6_GPIO_NUM 35
#define SPI_D7_GPIO_NUM 36
#define SPI_DQS_GPIO_NUM 37
#define MAX_RTC_GPIO_NUM 21
#define MAX_PAD_GPIO_NUM 46
@ -158,6 +157,18 @@
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define PAD_POWER_SEL BIT(15)
#define PAD_POWER_SEL_V 0x1
#define PAD_POWER_SEL_M BIT(15)
#define PAD_POWER_SEL_S 15
#define PAD_POWER_SWITCH_DELAY 0x7
#define PAD_POWER_SWITCH_DELAY_V 0x7
#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
#define PAD_POWER_SWITCH_DELAY_S 12
#define CLK_OUT3 0xf
#define CLK_OUT3_V CLK_OUT3
#define CLK_OUT3_S 8
@ -209,40 +220,45 @@
#define FUNC_GPIO8_GPIO8_0 0
#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE +0x28)
#define FUNC_GPIO9_FSPIHD 4
#define FUNC_GPIO9_SUBSPIHD 3
#define FUNC_GPIO9_FSPIHD 2
#define FUNC_GPIO9_GPIO9 1
#define FUNC_GPIO9_SD_DATA2 0
#define FUNC_GPIO9_GPIO9_0 0
#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE +0x2c)
#define FUNC_GPIO10_FSPICS0 4
#define FUNC_GPIO10_SUBSPICS0 3
#define FUNC_GPIO10_FSPICS0 2
#define FUNC_GPIO10_FSPIIO4 2
#define FUNC_GPIO10_GPIO10 1
#define FUNC_GPIO10_SD_DATA3 0
#define FUNC_GPIO10_GPIO10_0 0
#define PERIPHS_IO_MUX_GPIO11_U (REG_IO_MUX_BASE +0x30)
#define FUNC_GPIO11_FSPID 4
#define FUNC_GPIO11_SUBSPID 3
#define FUNC_GPIO11_FSPID 2
#define FUNC_GPIO11_FSPIIO5 2
#define FUNC_GPIO11_GPIO11 1
#define FUNC_GPIO11_SD_CMD 0
#define FUNC_GPIO11_GPIO11_0 0
#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE +0x34)
#define FUNC_GPIO12_FSPICLK 4
#define FUNC_GPIO12_SUBSPICLK 3
#define FUNC_GPIO12_FSPICLK 2
#define FUNC_GPIO12_FSPIIO6 2
#define FUNC_GPIO12_GPIO12 1
#define FUNC_GPIO12_SD_CLK 0
#define FUNC_GPIO12_GPIO12_0 0
#define PERIPHS_IO_MUX_GPIO13_U (REG_IO_MUX_BASE +0x38)
#define FUNC_GPIO13_FSPIQ 4
#define FUNC_GPIO13_SUBSPIQ 3
#define FUNC_GPIO13_FSPIQ 2
#define FUNC_GPIO13_FSPIIO7 2
#define FUNC_GPIO13_GPIO13 1
#define FUNC_GPIO13_SD_DATA0 0
#define FUNC_GPIO13_GPIO13_0 0
#define PERIPHS_IO_MUX_GPIO14_U (REG_IO_MUX_BASE +0x3c)
#define FUNC_GPIO14_FSPIWP 4
#define FUNC_GPIO14_SUBSPIWP 3
#define FUNC_GPIO14_FSPIWP 2
#define FUNC_GPIO14_FSPIDQS 2
#define FUNC_GPIO14_GPIO14 1
#define FUNC_GPIO14_SD_DATA1 0
#define FUNC_GPIO14_GPIO14_0 0
#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE +0x40)
#define FUNC_XTAL_32K_P_U0RTS 2
@ -310,40 +326,45 @@
#define FUNC_SPID_SPID 0
#define PERIPHS_IO_MUX_GPIO33_U (REG_IO_MUX_BASE +0x88)
#define FUNC_GPIO33_SPIIO4 4
#define FUNC_GPIO33_SUBSPIHD 3
#define FUNC_GPIO33_SD_DATA2 2
#define FUNC_GPIO33_FSPIHD 2
#define FUNC_GPIO33_GPIO33 1
#define FUNC_GPIO33_FSPIHD 0
#define FUNC_GPIO33_GPIO33_0 0
#define PERIPHS_IO_MUX_GPIO34_U (REG_IO_MUX_BASE +0x8c)
#define FUNC_GPIO34_SPIIO5 4
#define FUNC_GPIO34_SUBSPICS0 3
#define FUNC_GPIO34_SD_DATA3 2
#define FUNC_GPIO34_FSPICS0 2
#define FUNC_GPIO34_GPIO34 1
#define FUNC_GPIO34_FSPICS0 0
#define FUNC_GPIO34_GPIO34_0 0
#define PERIPHS_IO_MUX_GPIO35_U (REG_IO_MUX_BASE +0x90)
#define FUNC_GPIO35_SPIIO6 4
#define FUNC_GPIO35_SUBSPID 3
#define FUNC_GPIO35_SD_CMD 2
#define FUNC_GPIO35_FSPID 2
#define FUNC_GPIO35_GPIO35 1
#define FUNC_GPIO35_FSPID 0
#define FUNC_GPIO35_GPIO35_0 0
#define PERIPHS_IO_MUX_GPIO36_U (REG_IO_MUX_BASE +0x94)
#define FUNC_GPIO36_SPIIO7 4
#define FUNC_GPIO36_SUBSPICLK 3
#define FUNC_GPIO36_SD_CLK 2
#define FUNC_GPIO36_FSPICLK 2
#define FUNC_GPIO36_GPIO36 1
#define FUNC_GPIO36_FSPICLK 0
#define FUNC_GPIO36_GPIO36_0 0
#define PERIPHS_IO_MUX_GPIO37_U (REG_IO_MUX_BASE +0x98)
#define FUNC_GPIO37_SPIDQS 4
#define FUNC_GPIO37_SUBSPIQ 3
#define FUNC_GPIO37_SD_DATA0 2
#define FUNC_GPIO37_FSPIQ 2
#define FUNC_GPIO37_GPIO37 1
#define FUNC_GPIO37_FSPIQ 0
#define FUNC_GPIO37_GPIO37_0 0
#define PERIPHS_IO_MUX_GPIO38_U (REG_IO_MUX_BASE +0x9c)
#define FUNC_GPIO38_SUBSPIWP 3
#define FUNC_GPIO38_SD_DATA1 2
#define FUNC_GPIO38_FSPIWP 2
#define FUNC_GPIO38_GPIO38 1
#define FUNC_GPIO38_FSPIWP 0
#define FUNC_GPIO38_GPIO38_0 0
#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE +0xa0)
#define FUNC_MTCK_SUBSPICS1 3
@ -386,6 +407,6 @@
#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
#define IO_MUX_DATE 0xFFFFFFFF
#define IO_MUX_DATE_S 0
#define IO_MUX_DATE_VERSION 0x1809060
#define IO_MUX_DATE_VERSION 0x1907160
#endif

20
components/soc/esp32s2beta/include/soc/ledc_reg.h
View File

@ -1,4 +1,4 @@
// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -20,12 +20,6 @@ extern "C" {
#endif
#include "soc.h"
#define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000)
/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define LEDC_CLK_EN (BIT(31))
#define LEDC_CLK_EN_M (BIT(31))
#define LEDC_CLK_EN_V 0x1
#define LEDC_CLK_EN_S 31
/* LEDC_OVF_CNT_RESET_ST_LSCH0 : RO ;bitpos:[17] ;default: 1'b0 ; */
/*description: */
#define LEDC_OVF_CNT_RESET_ST_LSCH0 (BIT(17))
@ -1546,6 +1540,12 @@ extern "C" {
#define LEDC_LSTIMER0_OVF_INT_CLR_S 0
#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x00d0)
/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define LEDC_CLK_EN (BIT(31))
#define LEDC_CLK_EN_M (BIT(31))
#define LEDC_CLK_EN_V 0x1
#define LEDC_CLK_EN_S 31
/* LEDC_APB_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: */
#define LEDC_APB_CLK_SEL 0x00000003
@ -1554,7 +1554,7 @@ extern "C" {
#define LEDC_APB_CLK_SEL_S 0
#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x00FC)
/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h18072700 ; */
/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h19040200 ; */
/*description: */
#define LEDC_DATE 0xFFFFFFFF
#define LEDC_DATE_M ((LEDC_DATE_V)<<(LEDC_DATE_S))
@ -1565,4 +1565,8 @@ extern "C" {
}
#endif
#endif /*_SOC_LEDC_REG_H_ */

90
components/soc/esp32s2beta/include/soc/ledc_struct.h
View File

@ -1,9 +1,9 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
@ -13,7 +13,6 @@
// limitations under the License.
#ifndef _SOC_LEDC_STRUCT_H_
#define _SOC_LEDC_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
@ -38,32 +37,32 @@ typedef volatile struct {
} conf0;
union {
struct {
uint32_t hpoint: 14; /*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/
uint32_t reserved14: 16;
uint32_t hpoint: 14;
uint32_t reserved14: 18;
};
uint32_t val;
} hpoint;
union {
struct {
uint32_t duty: 19; /*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
uint32_t reserved19: 11;
uint32_t duty: 19;
uint32_t reserved19:13;
};
uint32_t val;
} duty;
union {
struct {
uint32_t duty_scale:10; /*This register controls the increase or decrease step scale for high speed channel.*/
uint32_t duty_cycle:10; /*This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel.*/
uint32_t duty_num: 10; /*This register is used to control the number of increased or decreased times for high speed channel.*/
uint32_t duty_inc: 1; /*This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel.*/
uint32_t duty_start: 1; /*When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/
uint32_t duty_scale: 10;
uint32_t duty_cycle: 10;
uint32_t duty_num: 10;
uint32_t duty_inc: 1;
uint32_t duty_start: 1;
};
uint32_t val;
} conf1;
union {
struct {
uint32_t duty_read: 19; /*This register represents the current duty of the output signal for high speed channel.*/
uint32_t reserved19: 11;
uint32_t duty_read: 19;
uint32_t reserved19:13;
};
uint32_t val;
} duty_rd;
@ -85,8 +84,8 @@ typedef volatile struct {
} conf;
union {
struct {
uint32_t timer_cnt: 14; /*software can read this register to get the current counter value in high speed timer*/
uint32_t reserved14: 16;
uint32_t timer_cnt: 14;
uint32_t reserved14: 18;
};
uint32_t val;
} value;
@ -94,18 +93,18 @@ typedef volatile struct {
} timer_group[1]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/
union {
struct {
uint32_t lstimer0_ovf: 1; /*The interrupt raw bit for low speed channel0 counter overflow.*/
uint32_t lstimer1_ovf: 1; /*The interrupt raw bit for low speed channel1 counter overflow.*/
uint32_t lstimer2_ovf: 1; /*The interrupt raw bit for low speed channel2 counter overflow.*/
uint32_t lstimer3_ovf: 1; /*The interrupt raw bit for low speed channel3 counter overflow.*/
uint32_t duty_chng_end_lsch0: 1; /*The interrupt raw bit for low speed channel 0 duty change done.*/
uint32_t duty_chng_end_lsch1: 1; /*The interrupt raw bit for low speed channel 1 duty change done.*/
uint32_t duty_chng_end_lsch2: 1; /*The interrupt raw bit for low speed channel 2 duty change done.*/
uint32_t duty_chng_end_lsch3: 1; /*The interrupt raw bit for low speed channel 3 duty change done.*/
uint32_t duty_chng_end_lsch4: 1; /*The interrupt raw bit for low speed channel 4 duty change done.*/
uint32_t duty_chng_end_lsch5: 1; /*The interrupt raw bit for low speed channel 5 duty change done.*/
uint32_t duty_chng_end_lsch6: 1; /*The interrupt raw bit for low speed channel 6 duty change done.*/
uint32_t duty_chng_end_lsch7: 1; /*The interrupt raw bit for low speed channel 7 duty change done.*/
uint32_t lstimer0_ovf: 1;
uint32_t lstimer1_ovf: 1;
uint32_t lstimer2_ovf: 1;
uint32_t lstimer3_ovf: 1;
uint32_t duty_chng_end_lsch0: 1;
uint32_t duty_chng_end_lsch1: 1;
uint32_t duty_chng_end_lsch2: 1;
uint32_t duty_chng_end_lsch3: 1;
uint32_t duty_chng_end_lsch4: 1;
uint32_t duty_chng_end_lsch5: 1;
uint32_t duty_chng_end_lsch6: 1;
uint32_t duty_chng_end_lsch7: 1;
uint32_t ovf_cnt_lsch0: 1;
uint32_t ovf_cnt_lsch1: 1;
uint32_t ovf_cnt_lsch2: 1;
@ -203,32 +202,19 @@ typedef volatile struct {
};
uint32_t val;
} conf;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t date; /*This register represents the version .*/
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t date; /**/
} ledc_dev_t;
extern ledc_dev_t LEDC;
#ifdef __cplusplus
}
#endif

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@ -0,0 +1,462 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_MCPWM_STRUCT_H__
#define _SOC_MCPWM_STRUCT_H__
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t prescale: 8; /*Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/
uint32_t reserved8: 24;
};
uint32_t val;
}clk_cfg;
struct {
union {
struct {
uint32_t prescale: 8; /*period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)*/
uint32_t period: 16; /*period shadow reg of PWM timer0*/
uint32_t upmethod: 2; /*Update method for active reg of PWM timer0 period 0: immediate 1: TEZ 2: sync 3: TEZ | sync. TEZ here and below means timer equal zero event*/
uint32_t reserved26: 6;
};
uint32_t val;
}period;
union {
struct {
uint32_t start: 3; /*PWM timer0 start and stop control. 0: stop @ TEZ 1: stop @ TEP 2: free run 3: start and stop @ next TEZ 4: start and stop @ next TEP. TEP here and below means timer equal period event*/
uint32_t mode: 2; /*PWM timer0 working mode 0: freeze 1: increase mod 2: decrease mod 3: up-down mod*/
uint32_t reserved5: 27;
};
uint32_t val;
}mode;
union {
struct {
uint32_t in_en: 1; /*when set timer reload with phase on sync input event is enabled*/
uint32_t sync_sw: 1; /*write the negate value will trigger a software sync*/
uint32_t out_sel: 2; /*PWM timer0 synco selection 0: synci 1: TEZ 2: TEP else 0*/
uint32_t timer_phase: 17; /*phase for timer reload on sync event*/
uint32_t reserved21: 11;
};
uint32_t val;
}sync;
union {
struct {
uint32_t value: 16; /*current PWM timer0 counter value*/
uint32_t direction: 1; /*current PWM timer0 counter direction 0: increment 1: decrement*/
uint32_t reserved17: 15;
};
uint32_t val;
}status;
}timer[3];
union {
struct {
uint32_t t0_in_sel: 3; /*select sync input for PWM timer0 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/
uint32_t t1_in_sel: 3; /*select sync input for PWM timer1 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/
uint32_t t2_in_sel: 3; /*select sync input for PWM timer2 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/
uint32_t ext_in0_inv: 1; /*invert SYNC0 from GPIO matrix*/
uint32_t ext_in1_inv: 1; /*invert SYNC1 from GPIO matrix*/
uint32_t ext_in2_inv: 1; /*invert SYNC2 from GPIO matrix*/
uint32_t reserved12: 20;
};
uint32_t val;
}timer_synci_cfg;
union {
struct {
uint32_t operator0_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator0 0: timer0 1: timer1 2: timer2*/
uint32_t operator1_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator1 0: timer0 1: timer1 2: timer2*/
uint32_t operator2_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator2 0: timer0 1: timer1 2: timer2*/
uint32_t reserved6: 26;
};
uint32_t val;
}timer_sel;
struct {
union {
struct {
uint32_t a_upmethod: 4; /*Update method for PWM compare0 A's active reg. 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: freeze*/
uint32_t b_upmethod: 4; /*Update method for PWM compare0 B's active reg. 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: freeze*/
uint32_t a_shdw_full: 1; /*Set and reset by hardware. If set PWM compare0 A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared A's active reg has been updated with shadow reg latest value*/
uint32_t b_shdw_full: 1; /*Set and reset by hardware. If set PWM compare0 B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared B's active reg has been updated with shadow reg latest value*/
uint32_t reserved10: 22;
};
uint32_t val;
}cmpr_cfg;
union {
struct {
uint32_t cmpr_val: 16; /*PWM compare0 A's shadow reg*/
uint32_t reserved16:16;
};
uint32_t val;
}cmpr_value[2];
union {
struct {
uint32_t upmethod: 4; /*Update method for PWM generate0's active reg of configuration. 0: immediate bit0: TEZ bit1: TEP bit2: sync. bit3: freeze*/
uint32_t t0_sel: 3; /*Source selection for PWM generate0 event_t0 take effect immediately 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/
uint32_t t1_sel: 3; /*Source selection for PWM generate0 event_t1 take effect immediately 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/
uint32_t reserved10: 22;
};
uint32_t val;
}gen_cfg0;
union {
struct {
uint32_t cntu_force_upmethod: 6; /*Update method for continuous software force of PWM generate0. 0: immediate bit0: TEZ bit1: TEP bit2: TEA bit3: TEB bit4: sync bit5: freeze. (TEA/B here and below means timer equals A/B event)*/
uint32_t a_cntuforce_mode: 2; /*Continuous software force mode for PWM0A. 0: disabled 1: low 2: high 3: disabled*/
uint32_t b_cntuforce_mode: 2; /*Continuous software force mode for PWM0B. 0: disabled 1: low 2: high 3: disabled*/
uint32_t a_nciforce: 1; /*non-continuous immediate software force trigger for PWM0A a toggle will trigger a force event*/
uint32_t a_nciforce_mode: 2; /*non-continuous immediate software force mode for PWM0A 0: disabled 1: low 2: high 3: disabled*/
uint32_t b_nciforce: 1; /*non-continuous immediate software force trigger for PWM0B a toggle will trigger a force event*/
uint32_t b_nciforce_mode: 2; /*non-continuous immediate software force mode for PWM0B 0: disabled 1: low 2: high 3: disabled*/
uint32_t reserved16: 16;
};
uint32_t val;
}gen_force;
union {
struct {
uint32_t utez: 2; /*Action on PWM0A triggered by event TEZ when timer increasing*/
uint32_t utep: 2; /*Action on PWM0A triggered by event TEP when timer increasing*/
uint32_t utea: 2; /*Action on PWM0A triggered by event TEA when timer increasing*/
uint32_t uteb: 2; /*Action on PWM0A triggered by event TEB when timer increasing*/
uint32_t ut0: 2; /*Action on PWM0A triggered by event_t0 when timer increasing*/
uint32_t ut1: 2; /*Action on PWM0A triggered by event_t1 when timer increasing*/
uint32_t dtez: 2; /*Action on PWM0A triggered by event TEZ when timer decreasing*/
uint32_t dtep: 2; /*Action on PWM0A triggered by event TEP when timer decreasing*/
uint32_t dtea: 2; /*Action on PWM0A triggered by event TEA when timer decreasing*/
uint32_t dteb: 2; /*Action on PWM0A triggered by event TEB when timer decreasing*/
uint32_t dt0: 2; /*Action on PWM0A triggered by event_t0 when timer decreasing*/
uint32_t dt1: 2; /*Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change 1: low 2: high 3: toggle*/
uint32_t reserved24: 8;
};
uint32_t val;
}generator[2];
union {
struct {
uint32_t fed_upmethod: 4; /*Update method for FED (falling edge delay) active reg. 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/
uint32_t red_upmethod: 4; /*Update method for RED (rising edge delay) active reg. 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/
uint32_t deb_mode: 1; /*S8 in documentation dual-edge B mode 0: fed/red take effect on different path separately 1: fed/red take effect on B path A out is in bypass or dulpB mode*/
uint32_t a_outswap: 1; /*S6 in documentation*/
uint32_t b_outswap: 1; /*S7 in documentation*/
uint32_t red_insel: 1; /*S4 in documentation*/
uint32_t fed_insel: 1; /*S5 in documentation*/
uint32_t red_outinvert: 1; /*S2 in documentation*/
uint32_t fed_outinvert: 1; /*S3 in documentation*/
uint32_t a_outbypass: 1; /*S1 in documentation*/
uint32_t b_outbypass: 1; /*S0 in documentation*/
uint32_t clk_sel: 1; /*Dead band0 clock selection. 0: PWM_clk 1: PT_clk*/
uint32_t reserved18: 14;
};
uint32_t val;
}db_cfg;
union {
struct {
uint32_t fed: 16; /*Shadow reg for FED*/
uint32_t reserved16:16;
};
uint32_t val;
}db_fed_cfg;
union {
struct {
uint32_t red: 16; /*Shadow reg for RED*/
uint32_t reserved16:16;
};
uint32_t val;
}db_red_cfg;
union {
struct {
uint32_t en: 1; /*When set carrier0 function is enabled. When reset carrier0 is bypassed*/
uint32_t prescale: 4; /*carrier0 clk (CP_clk) prescale value. Period of CP_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)*/
uint32_t duty: 3; /*carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8*/
uint32_t oshtwth: 4; /*width of the fist pulse in number of periods of the carrier*/
uint32_t out_invert: 1; /*when set invert the output of PWM0A and PWM0B for this submodule*/
uint32_t in_invert: 1; /*when set invert the input of PWM0A and PWM0B for this submodule*/
uint32_t reserved14: 18;
};
uint32_t val;
}carrier_cfg;
union {
struct {
uint32_t sw_cbc: 1; /*Cycle-by-cycle tripping software force event will trigger cycle-by-cycle trip event. 0: disable 1: enable*/
uint32_t f2_cbc: 1; /*event_f2 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/
uint32_t f1_cbc: 1; /*event_f1 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/
uint32_t f0_cbc: 1; /*event_f0 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/
uint32_t sw_ost: 1; /*one-shot tripping software force event will trigger one-shot trip event. 0: disable 1: enable*/
uint32_t f2_ost: 1; /*event_f2 will trigger one-shot trip event. 0: disable 1: enable*/
uint32_t f1_ost: 1; /*event_f1 will trigger one-shot trip event. 0: disable 1: enable*/
uint32_t f0_ost: 1; /*event_f0 will trigger one-shot trip event. 0: disable 1: enable*/
uint32_t a_cbc_d: 2; /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t a_cbc_u: 2; /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t a_ost_d: 2; /*Action on PWM0A when one-shot trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t a_ost_u: 2; /*Action on PWM0A when one-shot trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t b_cbc_d: 2; /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t b_cbc_u: 2; /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t b_ost_d: 2; /*Action on PWM0B when one-shot trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t b_ost_u: 2; /*Action on PWM0B when one-shot trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t reserved24: 8;
};
uint32_t val;
}tz_cfg0;
union {
struct {
uint32_t clr_ost: 1; /*a toggle will clear on going one-shot tripping*/
uint32_t cbcpulse: 2; /*cycle-by-cycle tripping refresh moment selection. Bit0: TEZ bit1:TEP*/
uint32_t force_cbc: 1; /*a toggle trigger a cycle-by-cycle tripping software force event*/
uint32_t force_ost: 1; /*a toggle (software negate its value) trigger a one-shot tripping software force event*/
uint32_t reserved5: 27;
};
uint32_t val;
}tz_cfg1;
union {
struct {
uint32_t cbc_on: 1; /*Set and reset by hardware. If set an cycle-by-cycle trip event is on going*/
uint32_t ost_on: 1; /*Set and reset by hardware. If set an one-shot trip event is on going*/
uint32_t reserved2: 30;
};
uint32_t val;
}tz_status;
}channel[3];
union {
struct {
uint32_t f0_en: 1; /*When set event_f0 generation is enabled*/
uint32_t f1_en: 1; /*When set event_f1 generation is enabled*/
uint32_t f2_en: 1; /*When set event_f2 generation is enabled*/
uint32_t f0_pole: 1; /*Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/
uint32_t f1_pole: 1; /*Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/
uint32_t f2_pole: 1; /*Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/
uint32_t event_f0: 1; /*Set and reset by hardware. If set event_f0 is on going*/
uint32_t event_f1: 1; /*Set and reset by hardware. If set event_f1 is on going*/
uint32_t event_f2: 1; /*Set and reset by hardware. If set event_f2 is on going*/
uint32_t reserved9: 23;
};
uint32_t val;
}fault_detect;
union {
struct {
uint32_t timer_en: 1; /*When set capture timer incrementing under APB_clk is enabled.*/
uint32_t synci_en: 1; /*When set capture timer sync is enabled.*/
uint32_t synci_sel: 3; /*capture module sync input selection. 0: none 1: timer0 synco 2: timer1 synco 3: timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix*/
uint32_t sync_sw: 1; /*Write 1 will force a capture timer sync capture timer is loaded with value in phase register.*/
uint32_t reserved6: 26;
};
uint32_t val;
}cap_timer_cfg;
uint32_t cap_timer_phase; /*Phase value for capture timer sync operation.*/
union {
struct {
uint32_t en: 1; /*When set capture on channel 0 is enabled*/
uint32_t mode: 2; /*Edge of capture on channel 0 after prescale. bit0: negedge cap en bit1: posedge cap en*/
uint32_t prescale: 8; /*Value of prescale on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1*/
uint32_t in_invert: 1; /*when set CAP0 form GPIO matrix is inverted before prescale*/
uint32_t sw: 1; /*Write 1 will trigger a software forced capture on channel 0*/
uint32_t reserved13: 19;
};
uint32_t val;
}cap_cfg_ch[3];
uint32_t cap_val_ch[3]; /*Value of last capture on channel 0*/
union {
struct {
uint32_t cap0_edge: 1; /*Edge of last capture trigger on channel 0 0: posedge 1: negedge*/
uint32_t cap1_edge: 1; /*Edge of last capture trigger on channel 1 0: posedge 1: negedge*/
uint32_t cap2_edge: 1; /*Edge of last capture trigger on channel 2 0: posedge 1: negedge*/
uint32_t reserved3: 29;
};
uint32_t val;
}cap_status;
union {
struct {
uint32_t global_up_en: 1; /*The global enable of update of all active registers in MCPWM module*/
uint32_t global_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module*/
uint32_t op0_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 0 are enabled*/
uint32_t op0_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0*/
uint32_t op1_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 1 are enabled*/
uint32_t op1_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1*/
uint32_t op2_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 2 are enabled*/
uint32_t op2_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2*/
uint32_t reserved8: 24;
};
uint32_t val;
}update_cfg;
union {
struct {
uint32_t timer0_stop_int_ena: 1; /*Interrupt when timer 0 stops*/
uint32_t timer1_stop_int_ena: 1; /*Interrupt when timer 1 stops*/
uint32_t timer2_stop_int_ena: 1; /*Interrupt when timer 2 stops*/
uint32_t timer0_tez_int_ena: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/
uint32_t timer1_tez_int_ena: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/
uint32_t timer2_tez_int_ena: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/
uint32_t timer0_tep_int_ena: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/
uint32_t timer1_tep_int_ena: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/
uint32_t timer2_tep_int_ena: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/
uint32_t fault0_int_ena: 1; /*Interrupt when event_f0 starts*/
uint32_t fault1_int_ena: 1; /*Interrupt when event_f1 starts*/
uint32_t fault2_int_ena: 1; /*Interrupt when event_f2 starts*/
uint32_t fault0_clr_int_ena: 1; /*Interrupt when event_f0 ends*/
uint32_t fault1_clr_int_ena: 1; /*Interrupt when event_f1 ends*/
uint32_t fault2_clr_int_ena: 1; /*Interrupt when event_f2 ends*/
uint32_t cmpr0_tea_int_ena: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/
uint32_t cmpr1_tea_int_ena: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/
uint32_t cmpr2_tea_int_ena: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/
uint32_t cmpr0_teb_int_ena: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/
uint32_t cmpr1_teb_int_ena: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/
uint32_t cmpr2_teb_int_ena: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/
uint32_t tz0_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
uint32_t tz0_ost_int_ena: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_ost_int_ena: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_ost_int_ena: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/
uint32_t cap0_int_ena: 1; /*A capture on channel 0 will trigger this interrupt*/
uint32_t cap1_int_ena: 1; /*A capture on channel 1 will trigger this interrupt*/
uint32_t cap2_int_ena: 1; /*A capture on channel 2 will trigger this interrupt*/
uint32_t reserved30: 2;
};
uint32_t val;
}int_ena;
union {
struct {
uint32_t timer0_stop_int_raw: 1; /*Interrupt when timer 0 stops*/
uint32_t timer1_stop_int_raw: 1; /*Interrupt when timer 1 stops*/
uint32_t timer2_stop_int_raw: 1; /*Interrupt when timer 2 stops*/
uint32_t timer0_tez_int_raw: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/
uint32_t timer1_tez_int_raw: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/
uint32_t timer2_tez_int_raw: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/
uint32_t timer0_tep_int_raw: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/
uint32_t timer1_tep_int_raw: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/
uint32_t timer2_tep_int_raw: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/
uint32_t fault0_int_raw: 1; /*Interrupt when event_f0 starts*/
uint32_t fault1_int_raw: 1; /*Interrupt when event_f1 starts*/
uint32_t fault2_int_raw: 1; /*Interrupt when event_f2 starts*/
uint32_t fault0_clr_int_raw: 1; /*Interrupt when event_f0 ends*/
uint32_t fault1_clr_int_raw: 1; /*Interrupt when event_f1 ends*/
uint32_t fault2_clr_int_raw: 1; /*Interrupt when event_f2 ends*/
uint32_t cmpr0_tea_int_raw: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/
uint32_t cmpr1_tea_int_raw: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/
uint32_t cmpr2_tea_int_raw: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/
uint32_t cmpr0_teb_int_raw: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/
uint32_t cmpr1_teb_int_raw: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/
uint32_t cmpr2_teb_int_raw: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/
uint32_t tz0_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
uint32_t tz0_ost_int_raw: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_ost_int_raw: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_ost_int_raw: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/
uint32_t cap0_int_raw: 1; /*A capture on channel 0 will trigger this interrupt*/
uint32_t cap1_int_raw: 1; /*A capture on channel 1 will trigger this interrupt*/
uint32_t cap2_int_raw: 1; /*A capture on channel 2 will trigger this interrupt*/
uint32_t reserved30: 2;
};
uint32_t val;
}int_raw;
union {
struct {
uint32_t timer0_stop_int_st: 1; /*Interrupt when timer 0 stops*/
uint32_t timer1_stop_int_st: 1; /*Interrupt when timer 1 stops*/
uint32_t timer2_stop_int_st: 1; /*Interrupt when timer 2 stops*/
uint32_t timer0_tez_int_st: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/
uint32_t timer1_tez_int_st: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/
uint32_t timer2_tez_int_st: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/
uint32_t timer0_tep_int_st: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/
uint32_t timer1_tep_int_st: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/
uint32_t timer2_tep_int_st: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/
uint32_t fault0_int_st: 1; /*Interrupt when event_f0 starts*/
uint32_t fault1_int_st: 1; /*Interrupt when event_f1 starts*/
uint32_t fault2_int_st: 1; /*Interrupt when event_f2 starts*/
uint32_t fault0_clr_int_st: 1; /*Interrupt when event_f0 ends*/
uint32_t fault1_clr_int_st: 1; /*Interrupt when event_f1 ends*/
uint32_t fault2_clr_int_st: 1; /*Interrupt when event_f2 ends*/
uint32_t cmpr0_tea_int_st: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/
uint32_t cmpr1_tea_int_st: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/
uint32_t cmpr2_tea_int_st: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/
uint32_t cmpr0_teb_int_st: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/
uint32_t cmpr1_teb_int_st: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/
uint32_t cmpr2_teb_int_st: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/
uint32_t tz0_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
uint32_t tz0_ost_int_st: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_ost_int_st: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_ost_int_st: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/
uint32_t cap0_int_st: 1; /*A capture on channel 0 will trigger this interrupt*/
uint32_t cap1_int_st: 1; /*A capture on channel 1 will trigger this interrupt*/
uint32_t cap2_int_st: 1; /*A capture on channel 2 will trigger this interrupt*/
uint32_t reserved30: 2;
};
uint32_t val;
}int_st;
union {
struct {
uint32_t timer0_stop_int_clr: 1; /*Interrupt when timer 0 stops*/
uint32_t timer1_stop_int_clr: 1; /*Interrupt when timer 1 stops*/
uint32_t timer2_stop_int_clr: 1; /*Interrupt when timer 2 stops*/
uint32_t timer0_tez_int_clr: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/
uint32_t timer1_tez_int_clr: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/
uint32_t timer2_tez_int_clr: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/
uint32_t timer0_tep_int_clr: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/
uint32_t timer1_tep_int_clr: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/
uint32_t timer2_tep_int_clr: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/
uint32_t fault0_int_clr: 1; /*Interrupt when event_f0 starts*/
uint32_t fault1_int_clr: 1; /*Interrupt when event_f1 starts*/
uint32_t fault2_int_clr: 1; /*Interrupt when event_f2 starts*/
uint32_t fault0_clr_int_clr: 1; /*Interrupt when event_f0 ends*/
uint32_t fault1_clr_int_clr: 1; /*Interrupt when event_f1 ends*/
uint32_t fault2_clr_int_clr: 1; /*Interrupt when event_f2 ends*/
uint32_t cmpr0_tea_int_clr: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/
uint32_t cmpr1_tea_int_clr: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/
uint32_t cmpr2_tea_int_clr: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/
uint32_t cmpr0_teb_int_clr: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/
uint32_t cmpr1_teb_int_clr: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/
uint32_t cmpr2_teb_int_clr: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/
uint32_t tz0_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
uint32_t tz0_ost_int_clr: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_ost_int_clr: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_ost_int_clr: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/
uint32_t cap0_int_clr: 1; /*A capture on channel 0 will trigger this interrupt*/
uint32_t cap1_int_clr: 1; /*A capture on channel 1 will trigger this interrupt*/
uint32_t cap2_int_clr: 1; /*A capture on channel 2 will trigger this interrupt*/
uint32_t reserved30: 2;
};
uint32_t val;
}int_clr;
union {
struct {
uint32_t clk_en: 1; /*Force clock on for this reg file*/
uint32_t reserved1: 31;
};
uint32_t val;
}reg_clk;
union {
struct {
uint32_t date: 28; /*Version of this reg file*/
uint32_t reserved28: 4;
};
uint32_t val;
}version;
} mcpwm_dev_t;
extern mcpwm_dev_t MCPWM0;
extern mcpwm_dev_t MCPWM1;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_MCPWM_STRUCT_H__ */

125
components/soc/esp32s2beta/include/soc/pcnt_struct.h
View File

@ -1,4 +1,4 @@
// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -21,113 +21,134 @@ typedef volatile struct {
struct {
union {
struct {
uint32_t filter_thres: 10; /*This register is used to filter pulse whose width is smaller than this value for unit0.*/
uint32_t filter_en: 1; /*This is the enable bit for filtering input signals for unit0.*/
uint32_t thr_zero_en: 1; /*This is the enable bit for comparing unit0's count with 0 value.*/
uint32_t thr_h_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_h_lim value.*/
uint32_t thr_l_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_l_lim value.*/
uint32_t thr_thres0_en: 1; /*This is the enable bit for comparing unit0's count with thres0 value.*/
uint32_t thr_thres1_en: 1; /*This is the enable bit for comparing unit0's count with thres1 value .*/
uint32_t ch0_neg_mode: 2; /*This register is used to control the mode of channel0's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
uint32_t ch0_pos_mode: 2; /*This register is used to control the mode of channel0's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
uint32_t ch0_hctrl_mode: 2; /*This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/
uint32_t ch0_lctrl_mode: 2; /*This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/
uint32_t ch1_neg_mode: 2; /*This register is used to control the mode of channel1's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/
uint32_t ch1_pos_mode: 2; /*This register is used to control the mode of channel1's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/
uint32_t ch1_hctrl_mode: 2; /*This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/
uint32_t ch1_lctrl_mode: 2; /*This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/
uint32_t filter_thres: 10;
uint32_t filter_en: 1;
uint32_t thr_zero_en: 1;
uint32_t thr_h_lim_en: 1;
uint32_t thr_l_lim_en: 1;
uint32_t thr_thres0_en: 1;
uint32_t thr_thres1_en: 1;
uint32_t ch0_neg_mode: 2;
uint32_t ch0_pos_mode: 2;
uint32_t ch0_hctrl_mode: 2;
uint32_t ch0_lctrl_mode: 2;
uint32_t ch1_neg_mode: 2;
uint32_t ch1_pos_mode: 2;
uint32_t ch1_hctrl_mode: 2;
uint32_t ch1_lctrl_mode: 2;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t cnt_thres0:16; /*This register is used to configure thres0 value for unit0.*/
uint32_t cnt_thres1:16; /*This register is used to configure thres1 value for unit0.*/
uint32_t cnt_thres0: 16;
uint32_t cnt_thres1: 16;
};
uint32_t val;
} conf1;
union {
struct {
uint32_t cnt_h_lim:16; /*This register is used to configure thr_h_lim value for unit0.*/
uint32_t cnt_l_lim:16; /*This register is used to configure thr_l_lim value for unit0.*/
uint32_t cnt_h_lim: 16;
uint32_t cnt_l_lim: 16;
};
uint32_t val;
} conf2;
} conf_unit[4];
union {
struct {
uint32_t cnt_val : 16; /*This register stores the current pulse count value for unit0.*/
uint32_t cnt_val: 16;
uint32_t reserved16: 16;
};
uint32_t val;
} cnt_unit[4];
union {
struct {
uint32_t cnt_thr_event_u0: 1; /*This is the interrupt raw bit for channel0 event.*/
uint32_t cnt_thr_event_u1: 1; /*This is the interrupt raw bit for channel1 event.*/
uint32_t cnt_thr_event_u2: 1; /*This is the interrupt raw bit for channel2 event.*/
uint32_t cnt_thr_event_u3: 1; /*This is the interrupt raw bit for channel3 event.*/
uint32_t cnt_thr_event_u0: 1;
uint32_t cnt_thr_event_u1: 1;
uint32_t cnt_thr_event_u2: 1;
uint32_t cnt_thr_event_u3: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t cnt_thr_event_u0: 1; /*This is the interrupt status bit for channel0 event.*/
uint32_t cnt_thr_event_u1: 1; /*This is the interrupt status bit for channel1 event.*/
uint32_t cnt_thr_event_u2: 1; /*This is the interrupt status bit for channel2 event.*/
uint32_t cnt_thr_event_u3: 1; /*This is the interrupt status bit for channel3 event.*/
uint32_t cnt_thr_event_u0: 1;
uint32_t cnt_thr_event_u1: 1;
uint32_t cnt_thr_event_u2: 1;
uint32_t cnt_thr_event_u3: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t cnt_thr_event_u0: 1; /*This is the interrupt enable bit for channel0 event.*/
uint32_t cnt_thr_event_u1: 1; /*This is the interrupt enable bit for channel1 event.*/
uint32_t cnt_thr_event_u2: 1; /*This is the interrupt enable bit for channel2 event.*/
uint32_t cnt_thr_event_u3: 1; /*This is the interrupt enable bit for channel3 event.*/
uint32_t cnt_thr_event_u0: 1;
uint32_t cnt_thr_event_u1: 1;
uint32_t cnt_thr_event_u2: 1;
uint32_t cnt_thr_event_u3: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t cnt_thr_event_u0: 1; /*Set this bit to clear channel0 event interrupt.*/
uint32_t cnt_thr_event_u1: 1; /*Set this bit to clear channel1 event interrupt.*/
uint32_t cnt_thr_event_u2: 1; /*Set this bit to clear channel2 event interrupt.*/
uint32_t cnt_thr_event_u3: 1; /*Set this bit to clear channel3 event interrupt.*/
uint32_t cnt_thr_event_u0: 1;
uint32_t cnt_thr_event_u1: 1;
uint32_t cnt_thr_event_u2: 1;
uint32_t cnt_thr_event_u3: 1;
uint32_t reserved4: 28;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t cnt_mode:2; /*0: positive value to zero; 1: negative value to zero; 2: counter value negative ; 3: counter value positive*/
uint32_t thres1_lat:1; /* counter value equals to thresh1*/
uint32_t thres0_lat:1; /* counter value equals to thresh0*/
uint32_t l_lim_lat:1; /* counter value reaches h_lim*/
uint32_t h_lim_lat:1; /* counter value reaches l_lim*/
uint32_t zero_lat:1; /* counter value equals zero*/
uint32_t cnt_mode: 2;
uint32_t thres1_lat: 1;
uint32_t thres0_lat: 1;
uint32_t l_lim_lat: 1;
uint32_t h_lim_lat: 1;
uint32_t zero_lat: 1;
uint32_t reserved7: 25;
};
uint32_t val;
} status_unit[4];
union {
struct {
uint32_t cnt_rst_u0: 1; /*Set this bit to clear unit0's counter.*/
uint32_t cnt_pause_u0: 1; /*Set this bit to pause unit0's counter.*/
uint32_t cnt_rst_u1: 1; /*Set this bit to clear unit1's counter.*/
uint32_t cnt_pause_u1: 1; /*Set this bit to pause unit1's counter.*/
uint32_t cnt_rst_u2: 1; /*Set this bit to clear unit2's counter.*/
uint32_t cnt_pause_u2: 1; /*Set this bit to pause unit2's counter.*/
uint32_t cnt_rst_u3: 1; /*Set this bit to clear unit3's counter.*/
uint32_t cnt_pause_u3: 1; /*Set this bit to pause unit3's counter.*/
uint32_t cnt_rst_u0: 1;
uint32_t cnt_pause_u0: 1;
uint32_t cnt_rst_u1: 1;
uint32_t cnt_pause_u1: 1;
uint32_t cnt_rst_u2: 1;
uint32_t cnt_pause_u2: 1;
uint32_t cnt_rst_u3: 1;
uint32_t cnt_pause_u3: 1;
uint32_t reserved8: 8;
uint32_t clk_en: 1;
uint32_t reserved9: 13;
uint32_t reserved17: 15;
};
uint32_t val;
} ctrl;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;

109
components/soc/esp32s2beta/include/soc/periph_defs.h
View File

@ -23,7 +23,11 @@ typedef enum {
PERIPH_LEDC_MODULE = 0,
PERIPH_UART0_MODULE,
PERIPH_UART1_MODULE,
#ifdef CONFIG_CHIP_IS_ESP32
PERIPH_UART2_MODULE,
#else
PERIPH_USB_MODULE,
#endif
PERIPH_I2C0_MODULE,
PERIPH_I2C1_MODULE,
PERIPH_I2S0_MODULE,
@ -57,6 +61,111 @@ typedef enum {
PERIPH_BT_LC_MODULE,
} periph_module_t;
typedef enum {
ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/
ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
ETS_WIFI_PWR_INTR_SOURCE, /**< */
ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/
ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/
ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/
ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
ETS_RWBT_INTR_SOURCE, /**< interrupt of RWBT, level*/
ETS_RWBLE_INTR_SOURCE, /**< interrupt of RWBLE, level*/
ETS_RWBT_NMI_SOURCE, /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
ETS_RWBLE_NMI_SOURCE, /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
ETS_SLC0_INTR_SOURCE, /**< interrupt of SLC0, level*/
ETS_SLC1_INTR_SOURCE, /**< interrupt of SLC1, level*/
ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/
ETS_UHCI1_INTR_SOURCE, /**< interrupt of UHCI1, level*/
ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/
ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/
ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCHDOG, level*/
ETS_TG0_LACT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, level*/
ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/
ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/
ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
ETS_TG1_LACT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, LACT, level*/
ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/
ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/
ETS_GPIO_INTR_SOURCE2, /**< interrupt of GPIO, level*/
ETS_GPIO_NMI_SOURCE2, /**< interrupt of GPIO, NMI*/
ETS_DEDICATED_GPIO_INTR_SOURCE, /**< interrupt of dedicated GPIO, level*/
ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
ETS_SPI1_INTR_SOURCE = 32, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/
ETS_SPI3_INTR_SOURCE, /**< interrupt of SPI3, level*/
ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/
ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/
ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/
ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/
ETS_UART2_INTR_SOURCE, /**< interrupt of UART2, level*/
ETS_SDIO_HOST_INTR_SOURCE, /**< interrupt of SD/SDIO/MMC HOST, level*/
ETS_PWM0_INTR_SOURCE, /**< interrupt of PWM0, level, Reserved*/
ETS_PWM1_INTR_SOURCE, /**< interrupt of PWM1, level, Reserved*/
ETS_PWM2_INTR_SOURCE, /**< interrupt of PWM2, level*/
ETS_PWM3_INTR_SOURCE, /**< interruot of PWM3, level*/
ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/
ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/
ETS_CAN_INTR_SOURCE , /**< interrupt of can, level*/
ETS_USB_INTR_SOURCE = 48, /**< interrupt of USB, level*/
ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/
ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/
ETS_PCNT_INTR_SOURCE, /**< interrupt of pluse count, level*/
ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/
ETS_I2C_EXT1_INTR_SOURCE, /**< interrupt of I2C controller0, level*/
ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/
ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/
ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/
ETS_SPI2_DMA_INTR_SOURCE, /**< interrupt of SPI2 DMA, level*/
ETS_SPI3_DMA_INTR_SOURCE, /**< interrupt of SPI3 DMA, level*/
ETS_WDT_INTR_SOURCE, /**< will be cancelled*/
ETS_TIMER1_INTR_SOURCE, /**< will be cancelled*/
ETS_TIMER2_INTR_SOURCE, /**< will be cancelled*/
ETS_TG0_T0_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/
ETS_TG0_T1_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/
ETS_TG0_WDT_EDGE_INTR_SOURCE = 64, /**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/
ETS_TG0_LACT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, EDGE*/
ETS_TG1_T0_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/
ETS_TG1_T1_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/
ETS_TG1_WDT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/
ETS_TG1_LACT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, EDGE*/
ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/
ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/
ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/
ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/
ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/
ETS_PMS_PRO_IRAM0_ILG_INTR_SOURCE, /**< interrupt of illegal IRAM1 access, LEVEL*/
ETS_PMS_PRO_DRAM0_ILG_INTR_SOURCE, /**< interrupt of illegal DRAM0 access, LEVEL*/
ETS_PMS_PRO_DPORT_ILG_INTR_SOURCE, /**< interrupt of illegal DPORT access, LEVEL*/
ETS_PMS_PRO_AHB_ILG_INTR_SOURCE, /**< interrupt of illegal AHB access, LEVEL*/
ETS_PMS_PRO_CACHE_ILG_INTR_SOURCE, /**< interrupt of illegal CACHE access, LEVEL*/
ETS_PMS_DMA_APB_I_ILG_INTR_SOURCE = 80, /**< interrupt of illegal APB access, LEVEL*/
ETS_PMS_DMA_RX_I_ILG_INTR_SOURCE, /**< interrupt of illegal DMA RX access, LEVEL*/
ETS_PMS_DMA_TX_I_ILG_INTR_SOURCE, /**< interrupt of illegal DMA TX access, LEVEL*/
ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/
ETS_DMA_COPY_INTR_SOURCE, /**< interrupt of DMA copy, LEVEL*/
ETS_SPI4_DMA_INTR_SOURCE, /**< interrupt of SPI4 DMA, LEVEL*/
ETS_SPI4_INTR_SOURCE, /**< interrupt of SPI4, LEVEL*/
ETS_ICACHE_PRELOAD_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/
ETS_DCACHE_PRELOAD_INTR_SOURCE, /**< interrupt of DCache preload operation, LEVEL*/
ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/
ETS_CRYPTO_DMA_INTR_SOURCE, /**< interrupt of encrypted DMA, LEVEL*/
ETS_CPU_PERI_ERROR_INTR_SOURCE, /**< interrupt of CPU peripherals error, LEVEL*/
ETS_APB_PERI_ERROR_INTR_SOURCE, /**< interrupt of APB peripherals error, LEVEL*/
ETS_DCACHE_SYNC_INTR_SOURCE, /**< interrupt of data cache sync done, LEVEL*/
ETS_ICACHE_SYNC_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/
ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */
} periph_interrput_t;
#ifdef __cplusplus
}
#endif

146
components/soc/esp32s2beta/include/soc/rmt_reg.h
View File

@ -1,4 +1,4 @@
// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -28,18 +28,6 @@ extern "C" {
#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0x000c)
#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x0010)
/* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define RMT_CLK_EN (BIT(31))
#define RMT_CLK_EN_M (BIT(31))
#define RMT_CLK_EN_V 0x1
#define RMT_CLK_EN_S 31
/* RMT_MEM_PD : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
#define RMT_MEM_PD (BIT(30))
#define RMT_MEM_PD_M (BIT(30))
#define RMT_MEM_PD_V 0x1
#define RMT_MEM_PD_S 30
/* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[29] ;default: 1'b1 ; */
/*description: */
#define RMT_CARRIER_OUT_LV_CH0 (BIT(29))
@ -52,6 +40,12 @@ extern "C" {
#define RMT_CARRIER_EN_CH0_M (BIT(28))
#define RMT_CARRIER_EN_CH0_V 0x1
#define RMT_CARRIER_EN_CH0_S 28
/* RMT_CARRIER_EFF_EN_CH0 : R/W ;bitpos:[27] ;default: 1'b1 ; */
/*description: */
#define RMT_CARRIER_EFF_EN_CH0 (BIT(27))
#define RMT_CARRIER_EFF_EN_CH0_M (BIT(27))
#define RMT_CARRIER_EFF_EN_CH0_V 0x1
#define RMT_CARRIER_EFF_EN_CH0_S 27
/* RMT_MEM_SIZE_CH0 : R/W ;bitpos:[26:24] ;default: 3'h1 ; */
/*description: */
#define RMT_MEM_SIZE_CH0 0x00000007
@ -96,6 +90,12 @@ extern "C" {
#define RMT_REF_ALWAYS_ON_CH0_M (BIT(17))
#define RMT_REF_ALWAYS_ON_CH0_V 0x1
#define RMT_REF_ALWAYS_ON_CH0_S 17
/* RMT_CHK_RX_CARRIER_EN_CH0 : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: */
#define RMT_CHK_RX_CARRIER_EN_CH0 (BIT(16))
#define RMT_CHK_RX_CARRIER_EN_CH0_M (BIT(16))
#define RMT_CHK_RX_CARRIER_EN_CH0_V 0x1
#define RMT_CHK_RX_CARRIER_EN_CH0_S 16
/* RMT_RX_FILTER_THRES_CH0 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
/*description: */
#define RMT_RX_FILTER_THRES_CH0 0x000000FF
@ -164,6 +164,12 @@ extern "C" {
#define RMT_CARRIER_EN_CH1_M (BIT(28))
#define RMT_CARRIER_EN_CH1_V 0x1
#define RMT_CARRIER_EN_CH1_S 28
/* RMT_CARRIER_EFF_EN_CH1 : R/W ;bitpos:[27] ;default: 1'b1 ; */
/*description: */
#define RMT_CARRIER_EFF_EN_CH1 (BIT(27))
#define RMT_CARRIER_EFF_EN_CH1_M (BIT(27))
#define RMT_CARRIER_EFF_EN_CH1_V 0x1
#define RMT_CARRIER_EFF_EN_CH1_S 27
/* RMT_MEM_SIZE_CH1 : R/W ;bitpos:[26:24] ;default: 3'h1 ; */
/*description: */
#define RMT_MEM_SIZE_CH1 0x00000007
@ -208,6 +214,12 @@ extern "C" {
#define RMT_REF_ALWAYS_ON_CH1_M (BIT(17))
#define RMT_REF_ALWAYS_ON_CH1_V 0x1
#define RMT_REF_ALWAYS_ON_CH1_S 17
/* RMT_CHK_RX_CARRIER_EN_CH1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: */
#define RMT_CHK_RX_CARRIER_EN_CH1 (BIT(16))
#define RMT_CHK_RX_CARRIER_EN_CH1_M (BIT(16))
#define RMT_CHK_RX_CARRIER_EN_CH1_V 0x1
#define RMT_CHK_RX_CARRIER_EN_CH1_S 16
/* RMT_RX_FILTER_THRES_CH1 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
/*description: */
#define RMT_RX_FILTER_THRES_CH1 0x000000FF
@ -276,6 +288,12 @@ extern "C" {
#define RMT_CARRIER_EN_CH2_M (BIT(28))
#define RMT_CARRIER_EN_CH2_V 0x1
#define RMT_CARRIER_EN_CH2_S 28
/* RMT_CARRIER_EFF_EN_CH2 : R/W ;bitpos:[27] ;default: 1'b1 ; */
/*description: */
#define RMT_CARRIER_EFF_EN_CH2 (BIT(27))
#define RMT_CARRIER_EFF_EN_CH2_M (BIT(27))
#define RMT_CARRIER_EFF_EN_CH2_V 0x1
#define RMT_CARRIER_EFF_EN_CH2_S 27
/* RMT_MEM_SIZE_CH2 : R/W ;bitpos:[26:24] ;default: 3'h1 ; */
/*description: */
#define RMT_MEM_SIZE_CH2 0x00000007
@ -320,6 +338,12 @@ extern "C" {
#define RMT_REF_ALWAYS_ON_CH2_M (BIT(17))
#define RMT_REF_ALWAYS_ON_CH2_V 0x1
#define RMT_REF_ALWAYS_ON_CH2_S 17
/* RMT_CHK_RX_CARRIER_EN_CH2 : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: */
#define RMT_CHK_RX_CARRIER_EN_CH2 (BIT(16))
#define RMT_CHK_RX_CARRIER_EN_CH2_M (BIT(16))
#define RMT_CHK_RX_CARRIER_EN_CH2_V 0x1
#define RMT_CHK_RX_CARRIER_EN_CH2_S 16
/* RMT_RX_FILTER_THRES_CH2 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
/*description: */
#define RMT_RX_FILTER_THRES_CH2 0x000000FF
@ -388,6 +412,12 @@ extern "C" {
#define RMT_CARRIER_EN_CH3_M (BIT(28))
#define RMT_CARRIER_EN_CH3_V 0x1
#define RMT_CARRIER_EN_CH3_S 28
/* RMT_CARRIER_EFF_EN_CH3 : R/W ;bitpos:[27] ;default: 1'b1 ; */
/*description: */
#define RMT_CARRIER_EFF_EN_CH3 (BIT(27))
#define RMT_CARRIER_EFF_EN_CH3_M (BIT(27))
#define RMT_CARRIER_EFF_EN_CH3_V 0x1
#define RMT_CARRIER_EFF_EN_CH3_S 27
/* RMT_MEM_SIZE_CH3 : R/W ;bitpos:[26:24] ;default: 3'h1 ; */
/*description: */
#define RMT_MEM_SIZE_CH3 0x00000007
@ -432,6 +462,12 @@ extern "C" {
#define RMT_REF_ALWAYS_ON_CH3_M (BIT(17))
#define RMT_REF_ALWAYS_ON_CH3_V 0x1
#define RMT_REF_ALWAYS_ON_CH3_S 17
/* RMT_CHK_RX_CARRIER_EN_CH3 : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: */
#define RMT_CHK_RX_CARRIER_EN_CH3 (BIT(16))
#define RMT_CHK_RX_CARRIER_EN_CH3_M (BIT(16))
#define RMT_CHK_RX_CARRIER_EN_CH3_V 0x1
#define RMT_CHK_RX_CARRIER_EN_CH3_S 16
/* RMT_RX_FILTER_THRES_CH3 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
/*description: */
#define RMT_RX_FILTER_THRES_CH3 0x000000FF
@ -1392,6 +1428,30 @@ extern "C" {
#define RMT_TX_LIM_CH3_S 0
#define RMT_APB_CONF_REG (DR_REG_RMT_BASE + 0x0080)
/* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define RMT_CLK_EN (BIT(31))
#define RMT_CLK_EN_M (BIT(31))
#define RMT_CLK_EN_V 0x1
#define RMT_CLK_EN_S 31
/* RMT_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
#define RMT_MEM_FORCE_PU (BIT(4))
#define RMT_MEM_FORCE_PU_M (BIT(4))
#define RMT_MEM_FORCE_PU_V 0x1
#define RMT_MEM_FORCE_PU_S 4
/* RMT_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define RMT_MEM_FORCE_PD (BIT(3))
#define RMT_MEM_FORCE_PD_M (BIT(3))
#define RMT_MEM_FORCE_PD_V 0x1
#define RMT_MEM_FORCE_PD_S 3
/* RMT_MEM_CLK_FORCE_ON : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
#define RMT_MEM_CLK_FORCE_ON (BIT(2))
#define RMT_MEM_CLK_FORCE_ON_M (BIT(2))
#define RMT_MEM_CLK_FORCE_ON_V 0x1
#define RMT_MEM_CLK_FORCE_ON_S 2
/* RMT_MEM_TX_WRAP_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define RMT_MEM_TX_WRAP_EN (BIT(1))
@ -1463,8 +1523,64 @@ extern "C" {
#define RMT_REF_CNT_RST_CH0_V 0x1
#define RMT_REF_CNT_RST_CH0_S 0
#define RMT_CH0_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x008c)
/* RMT_CARRIER_HIGH_THRES_CH0 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
/*description: */
#define RMT_CARRIER_HIGH_THRES_CH0 0x0000FFFF
#define RMT_CARRIER_HIGH_THRES_CH0_M ((RMT_CARRIER_HIGH_THRES_CH0_V)<<(RMT_CARRIER_HIGH_THRES_CH0_S))
#define RMT_CARRIER_HIGH_THRES_CH0_V 0xFFFF
#define RMT_CARRIER_HIGH_THRES_CH0_S 16
/* RMT_CARRIER_LOW_THRES_CH0 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: */
#define RMT_CARRIER_LOW_THRES_CH0 0x0000FFFF
#define RMT_CARRIER_LOW_THRES_CH0_M ((RMT_CARRIER_LOW_THRES_CH0_V)<<(RMT_CARRIER_LOW_THRES_CH0_S))
#define RMT_CARRIER_LOW_THRES_CH0_V 0xFFFF
#define RMT_CARRIER_LOW_THRES_CH0_S 0
#define RMT_CH1_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x0090)
/* RMT_CARRIER_HIGH_THRES_CH1 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
/*description: */
#define RMT_CARRIER_HIGH_THRES_CH1 0x0000FFFF
#define RMT_CARRIER_HIGH_THRES_CH1_M ((RMT_CARRIER_HIGH_THRES_CH1_V)<<(RMT_CARRIER_HIGH_THRES_CH1_S))
#define RMT_CARRIER_HIGH_THRES_CH1_V 0xFFFF
#define RMT_CARRIER_HIGH_THRES_CH1_S 16
/* RMT_CARRIER_LOW_THRES_CH1 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: */
#define RMT_CARRIER_LOW_THRES_CH1 0x0000FFFF
#define RMT_CARRIER_LOW_THRES_CH1_M ((RMT_CARRIER_LOW_THRES_CH1_V)<<(RMT_CARRIER_LOW_THRES_CH1_S))
#define RMT_CARRIER_LOW_THRES_CH1_V 0xFFFF
#define RMT_CARRIER_LOW_THRES_CH1_S 0
#define RMT_CH2_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x0094)
/* RMT_CARRIER_HIGH_THRES_CH2 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
/*description: */
#define RMT_CARRIER_HIGH_THRES_CH2 0x0000FFFF
#define RMT_CARRIER_HIGH_THRES_CH2_M ((RMT_CARRIER_HIGH_THRES_CH2_V)<<(RMT_CARRIER_HIGH_THRES_CH2_S))
#define RMT_CARRIER_HIGH_THRES_CH2_V 0xFFFF
#define RMT_CARRIER_HIGH_THRES_CH2_S 16
/* RMT_CARRIER_LOW_THRES_CH2 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: */
#define RMT_CARRIER_LOW_THRES_CH2 0x0000FFFF
#define RMT_CARRIER_LOW_THRES_CH2_M ((RMT_CARRIER_LOW_THRES_CH2_V)<<(RMT_CARRIER_LOW_THRES_CH2_S))
#define RMT_CARRIER_LOW_THRES_CH2_V 0xFFFF
#define RMT_CARRIER_LOW_THRES_CH2_S 0
#define RMT_CH3_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x0098)
/* RMT_CARRIER_HIGH_THRES_CH3 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
/*description: */
#define RMT_CARRIER_HIGH_THRES_CH3 0x0000FFFF
#define RMT_CARRIER_HIGH_THRES_CH3_M ((RMT_CARRIER_HIGH_THRES_CH3_V)<<(RMT_CARRIER_HIGH_THRES_CH3_S))
#define RMT_CARRIER_HIGH_THRES_CH3_V 0xFFFF
#define RMT_CARRIER_HIGH_THRES_CH3_S 16
/* RMT_CARRIER_LOW_THRES_CH3 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: */
#define RMT_CARRIER_LOW_THRES_CH3 0x0000FFFF
#define RMT_CARRIER_LOW_THRES_CH3_M ((RMT_CARRIER_LOW_THRES_CH3_V)<<(RMT_CARRIER_LOW_THRES_CH3_S))
#define RMT_CARRIER_LOW_THRES_CH3_V 0xFFFF
#define RMT_CARRIER_LOW_THRES_CH3_S 0
#define RMT_DATE_REG (DR_REG_RMT_BASE + 0x0fc)
/* RMT_DATE : R/W ;bitpos:[31:0] ;default: 32'h18072600 ; */
/* RMT_DATE : R/W ;bitpos:[31:0] ;default: 32'h19040200 ; */
/*description: */
#define RMT_DATE 0xFFFFFFFF
#define RMT_DATE_M ((RMT_DATE_V)<<(RMT_DATE_S))
@ -1474,7 +1590,7 @@ extern "C" {
#ifdef __cplusplus
}
#endif
#define RMT_CHANNEL_MEM(i) (DR_REG_RMT_BASE + 0x400 + 64 * 4 * (i))
#endif /*_SOC_RMT_REG_H_ */

77
components/soc/esp32s2beta/include/soc/rmt_struct.h
View File

@ -1,4 +1,4 @@
// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -28,7 +28,7 @@ typedef volatile struct {
uint32_t div_cnt: 8;
uint32_t idle_thres: 16;
uint32_t mem_size: 3;
uint32_t reserved27: 1;
uint32_t carrier_eff_en: 1;
uint32_t carrier_en: 1;
uint32_t carrier_out_lv: 1;
uint32_t mem_pd: 1;
@ -47,12 +47,13 @@ typedef volatile struct {
uint32_t tx_conti_mode: 1;
uint32_t rx_filter_en: 1;
uint32_t rx_filter_thres: 8;
uint32_t reserved16: 1;
uint32_t chk_rx_carrier_en: 1;
uint32_t ref_always_on: 1;
uint32_t idle_out_lv: 1;
uint32_t idle_out_en: 1;
uint32_t tx_stop: 1;
uint32_t reserved21: 11;
uint32_t carrier_per: 5;
uint32_t reserved26: 6;
};
uint32_t val;
} conf1;
@ -232,14 +233,66 @@ typedef volatile struct {
};
uint32_t val;
} ref_cnt_rst;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
union {
struct {
uint32_t carrier_low_num_ch0: 15;
uint32_t carrier_high_num_ch0:15;
uint32_t reserved30: 2;
};
uint32_t val;
} ch0_rx_carrier_st;
union {
struct {
uint32_t carrier_low_thres_ch0: 16;
uint32_t carrier_high_thres_ch0:16;
};
uint32_t val;
} ch0_rx_carrier_rm;
union {
struct {
uint32_t carrier_low_num_ch1: 15;
uint32_t carrier_high_num_ch1:15;
uint32_t reserved30: 2;
};
uint32_t val;
} ch1_rx_carrier_st;
union {
struct {
uint32_t carrier_low_thres_ch1: 16;
uint32_t carrier_high_thres_ch1:16;
};
uint32_t val;
} ch1_rx_carrier_rm;
union {
struct {
uint32_t carrier_low_num_ch2: 15;
uint32_t carrier_high_num_ch2:15;
uint32_t reserved30: 2;
};
uint32_t val;
} ch2_rx_carrier_st;
union {
struct {
uint32_t carrier_low_thres_ch2: 16;
uint32_t carrier_high_thres_ch2:16;
};
uint32_t val;
} ch2_rx_carrier_rm;
union {
struct {
uint32_t carrier_low_num_ch3: 15;
uint32_t carrier_high_num_ch3:15;
uint32_t reserved30: 2;
};
uint32_t val;
} ch3_rx_carrier_st;
union {
struct {
uint32_t carrier_low_thres_ch3: 16;
uint32_t carrier_high_thres_ch3:16;
};
uint32_t val;
} ch3_rx_carrier_rm;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;

88
components/soc/esp32s2beta/include/soc/rtc.h
View File

@ -70,8 +70,6 @@ typedef enum {
RTC_CPU_FREQ_160M = 2, //!< 160 MHz
RTC_CPU_FREQ_240M = 3, //!< 240 MHz
RTC_CPU_FREQ_2M = 4, //!< 2 MHz
RTC_CPU_320M_80M = 5, //!< for test
RTC_CPU_320M_160M = 6, //!< for test
} rtc_cpu_freq_t;
/**
@ -111,8 +109,7 @@ typedef struct {
rtc_cpu_freq_t cpu_freq : 3; //!< CPU frequency to set
rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set
rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set
uint32_t clk_rtc_clk_div : 8;
uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
uint32_t clk_8m_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
} rtc_clk_config_t;
@ -125,16 +122,11 @@ typedef struct {
.cpu_freq = RTC_CPU_FREQ_80M, \
.fast_freq = RTC_FAST_FREQ_8M, \
.slow_freq = RTC_SLOW_FREQ_RTC, \
.clk_rtc_clk_div = 0, \
.clk_8m_clk_div = 0, \
.clk_8m_div = 0, \
.slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
.clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
}
void rtc_clk_divider_set(uint32_t div);
void rtc_clk_8m_divider_set(uint32_t div);
/**
* Initialize clocks and set CPU frequency
*
@ -232,12 +224,8 @@ bool rtc_clk_8md256_enabled(void);
* @param sdm2 frequency adjustment parameter, 0..63
* @param o_div frequency divider, 0..31
*/
void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div);
/**
* @brief Set XTAL wait cycles by RTC slow clock's period
*/
void rtc_clk_set_xtal_wait(void);
void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1,
uint32_t sdm2, uint32_t o_div);
/**
* @brief Select source for RTC_SLOW_CLK
@ -358,8 +346,6 @@ uint32_t rtc_clk_apb_freq_get(void);
#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
/**
* @brief Measure RTC slow clock's period, based on main XTAL frequency
*
@ -415,10 +401,6 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
*/
uint64_t rtc_time_get(void);
uint64_t rtc_light_slp_time_get(void);
uint64_t rtc_deep_slp_time_get(void);
/**
* @brief Busy loop until next RTC_SLOW_CLK cycle
*
@ -428,53 +410,27 @@ uint64_t rtc_deep_slp_time_get(void);
*/
void rtc_clk_wait_for_slow_cycle(void);
/**
* @brief Power down flags for rtc_sleep_pd function
*/
typedef struct {
uint32_t dig_fpu : 1; //!< Set to 1 to power down digital part in sleep
uint32_t rtc_fpu : 1; //!< Set to 1 to power down RTC memories in sleep
uint32_t cpu_fpu : 1; //!< Set to 1 to power down digital memories and CPU in sleep
uint32_t i2s_fpu : 1; //!< Set to 1 to power down I2S in sleep
uint32_t bb_fpu : 1; //!< Set to 1 to power down WiFi in sleep
uint32_t nrx_fpu : 1; //!< Set to 1 to power down WiFi in sleep
uint32_t fe_fpu : 1; //!< Set to 1 to power down WiFi in sleep
} rtc_sleep_pd_config_t;
/**
* Initializer for rtc_sleep_pd_config_t which sets all flags to the same value
*/
#define RTC_SLEEP_PD_CONFIG_ALL(val) {\
.dig_fpu = (val), \
.rtc_fpu = (val), \
.cpu_fpu = (val), \
.i2s_fpu = (val), \
.bb_fpu = (val), \
.nrx_fpu = (val), \
.fe_fpu = (val), \
}
void rtc_sleep_pd(rtc_sleep_pd_config_t cfg);
/**
* @brief sleep configuration for rtc_sleep_init function
*/
typedef struct {
uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory)
uint32_t rtc_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (RTC memory)
uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used)
uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory
uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory
uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals
uint32_t wifi_pd_en : 1; //!< power down WiFi
uint32_t rom_mem_pd_en : 1; //!< power down main RAM and ROM
uint32_t deep_slp : 1; //!< power down digital domain
uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode
uint32_t dig_dbias_wak : 3; //!< set bias for digital domain, in active mode
uint32_t dig_dbias_slp : 3; //!< set bias for digital domain, in sleep mode
uint32_t rtc_dbias_wak : 3; //!< set bias for RTC domain, in active mode
uint32_t rtc_dbias_slp : 3; //!< set bias for RTC domain, in sleep mode
uint32_t lslp_meminf_pd : 1; //!< remove all peripheral force power up flags
uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
uint32_t deep_slp_reject : 1;
uint32_t light_slp_reject : 1;
uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep
} rtc_sleep_config_t;
/**
@ -487,20 +443,22 @@ typedef struct {
*/
#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \
.lslp_mem_inf_fpu = 0, \
.rtc_mem_inf_fpu = 0, \
.rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \
.rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \
.rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \
.rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \
.wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \
.wifi_pd_en = 0, \
.rom_mem_pd_en = 0, \
.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
.wdt_flashboot_mod_en = 0, \
.dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \
.dig_dbias_slp = RTC_CNTL_DBIAS_0V90, \
.dig_dbias_slp = RTC_CNTL_DIG_DBIAS_0V90, \
.rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \
.rtc_dbias_slp = RTC_CNTL_DBIAS_0V90, \
.rtc_dbias_slp = RTC_CNTL_DIG_DBIAS_0V90, \
.lslp_meminf_pd = 1, \
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
.deep_slp_reject = 1, \
.light_slp_reject = 1 \
.xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1 \
};
#define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain)
@ -509,7 +467,7 @@ typedef struct {
#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory
#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
#define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator
#define RTC_SLEEP_PD_WIFI BIT(6)
#define RTC_SLEEP_PD_XTAL BIT(6) //!< Power down main XTAL
/**
* @brief Prepare the chip to enter sleep mode
@ -546,10 +504,6 @@ void rtc_sleep_set_wakeup_time(uint64_t t);
#define RTC_TOUCH_TRIG_EN BIT(8) //!< Touch wakeup
#define RTC_ULP_TRIG_EN BIT(9) //!< ULP wakeup
#define RTC_BT_TRIG_EN BIT(10) //!< BT wakeup (light sleep only)
#define RTC_COCPU_TRIG_EN BIT(11)
#define RTC_XTAL32K_DEAD_TRIG_EN BIT(12)
#define RTC_COCPU_TRAP_TRIG_EN BIT(13)
#define RTC_USB_TRIG_EN BIT(14)
/**
* @brief Enter deep or light sleep mode
@ -576,7 +530,7 @@ void rtc_sleep_set_wakeup_time(uint64_t t);
* an external host is communicating via SDIO slave
* @return non-zero if sleep was rejected by hardware
*/
uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu);
uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt);
/**
* RTC power and clock control initialization settings
@ -588,9 +542,6 @@ typedef struct {
uint32_t clkctl_init : 1; //!< Perform clock control related initialization
uint32_t pwrctl_init : 1; //!< Perform power control related initialization
uint32_t rtc_dboost_fpd : 1; //!< Force power down RTC_DBOOST
uint32_t xtal_fpu : 1;
uint32_t bbpll_fpu : 1;
uint32_t cpu_waiti_clk_gate : 1;
} rtc_config_t;
/**
@ -605,10 +556,7 @@ typedef struct {
.pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \
.clkctl_init = 1, \
.pwrctl_init = 1, \
.rtc_dboost_fpd = 1, \
.xtal_fpu = 0, \
.bbpll_fpu = 0, \
.cpu_waiti_clk_gate = 1\
.rtc_dboost_fpd = 1 \
}
/**

645
components/soc/esp32s2beta/include/soc/rtc_cntl_reg.h
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23
components/soc/esp32s2beta/include/soc/rtc_cntl_struct.h
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@ -68,7 +68,7 @@ typedef volatile struct {
uint32_t timer_sys_stall: 1; /*Enable to record system stall time*/
uint32_t timer_xtl_off: 1; /*Enable to record 40M XTAL OFF time*/
uint32_t timer_sys_rst: 1; /*enable to record system reset time*/
uint32_t valid: 1; /*To indicate the register is updated*/
uint32_t reserved30: 1;
uint32_t update: 1; /*Set 1: to update register with RTC timer*/
};
uint32_t val;
@ -188,7 +188,7 @@ typedef volatile struct {
uint32_t slp_reject: 1; /*enable sleep reject interrupt*/
uint32_t sdio_idle: 1; /*enable SDIO idle interrupt*/
uint32_t rtc_wdt: 1; /*enable RTC WDT interrupt*/
uint32_t rtc_time_valid: 1; /*enable RTC time valid interrupt*/
uint32_t reserved4: 1;
uint32_t rtc_ulp_cp: 1; /*enable ULP-coprocessor interrupt*/
uint32_t rtc_touch_done: 1; /*enable touch done interrupt*/
uint32_t rtc_touch_active: 1; /*enable touch active interrupt*/
@ -212,7 +212,7 @@ typedef volatile struct {
uint32_t slp_reject: 1; /*sleep reject interrupt raw*/
uint32_t sdio_idle: 1; /*SDIO idle interrupt raw*/
uint32_t rtc_wdt: 1; /*RTC WDT interrupt raw*/
uint32_t rtc_time_valid: 1; /*RTC time valid interrupt raw*/
uint32_t reserved4: 1;
uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt raw*/
uint32_t rtc_touch_done: 1; /*touch interrupt raw*/
uint32_t rtc_touch_active: 1; /*touch active interrupt raw*/
@ -236,7 +236,7 @@ typedef volatile struct {
uint32_t slp_reject: 1; /*sleep reject interrupt state*/
uint32_t sdio_idle: 1; /*SDIO idle interrupt state*/
uint32_t rtc_wdt: 1; /*RTC WDT interrupt state*/
uint32_t rtc_time_valid: 1; /*RTC time valid interrupt state*/
uint32_t reserved4: 1;
uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt state*/
uint32_t rtc_touch_done: 1; /*touch done interrupt state*/
uint32_t rtc_touch_active: 1; /*touch active interrupt state*/
@ -260,7 +260,7 @@ typedef volatile struct {
uint32_t slp_reject: 1; /*Clear sleep reject interrupt state*/
uint32_t sdio_idle: 1; /*Clear SDIO idle interrupt state*/
uint32_t rtc_wdt: 1; /*Clear RTC WDT interrupt state*/
uint32_t rtc_time_valid: 1; /*Clear RTC time valid interrupt state*/
uint32_t reserved4: 1;
uint32_t rtc_ulp_cp: 1; /*Clear ULP-coprocessor interrupt state*/
uint32_t rtc_touch_done: 1; /*Clear touch done interrupt state*/
uint32_t rtc_touch_active: 1; /*Clear touch active interrupt state*/
@ -818,10 +818,21 @@ typedef volatile struct {
uint32_t usb_txp: 1;
uint32_t usb_tx_en: 1;
uint32_t usb_tx_en_override: 1;
uint32_t reserved17: 15;
uint32_t usb_reset_disable: 1;
uint32_t io_mux_reset_disable: 1;
uint32_t reserved19: 13;
};
uint32_t val;
} usb_conf;
uint32_t reserved_124;
uint32_t reserved_128;
union {
struct {
uint32_t force_download_boot: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} option1;
union {
struct {
uint32_t date: 28;

8
components/soc/esp32s2beta/include/soc/rtc_i2c_reg.h
View File

@ -50,6 +50,12 @@ extern "C" {
#define RTC_I2C_RESET_M (BIT(30))
#define RTC_I2C_RESET_V 0x1
#define RTC_I2C_RESET_S 30
/* RTC_I2C_CTRL_CLK_GATE_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
#define RTC_I2C_CTRL_CLK_GATE_EN (BIT(29))
#define RTC_I2C_CTRL_CLK_GATE_EN_M (BIT(29))
#define RTC_I2C_CTRL_CLK_GATE_EN_V 0x1
#define RTC_I2C_CTRL_CLK_GATE_EN_S 29
/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: receive lsb first*/
#define RTC_I2C_RX_LSB_FIRST (BIT(5))
@ -672,7 +678,7 @@ extern "C" {
#define RTC_I2C_COMMAND15_S 0
#define RTC_I2C_DATE_REG (DR_REG_RTC_I2C_BASE + 0x00FC)
/* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1711170 ; */
/* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905310 ; */
/*description: */
#define RTC_I2C_DATE 0x0FFFFFFF
#define RTC_I2C_DATE_M ((RTC_I2C_DATE_V)<<(RTC_I2C_DATE_S))

8
components/soc/esp32s2beta/include/soc/rtc_i2c_struct.h
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@ -171,9 +171,13 @@ typedef volatile struct {
} fifo_data;
union {
struct {
uint32_t command: 14; /*command*/
uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/
uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/
uint32_t reserved14: 17;
uint32_t done: 1; /*command_done*/
uint32_t done: 1; /*command0_done*/
};
uint32_t val;
} command[16];

14
components/soc/esp32s2beta/include/soc/rtc_io_reg.h
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@ -2265,6 +2265,20 @@ extern "C" {
#define RTC_IO_SAR_DEBUG_BIT_SEL_V 0x1F
#define RTC_IO_SAR_DEBUG_BIT_SEL_S 23
#define RTC_IO_TOUCH_CTRL_REG (DR_REG_RTCIO_BASE + 0xE8)
/* RTC_IO_IO_TOUCH_BUFMODE : R/W ;bitpos:[4] ;default: 1'd0 ; */
/*description: BUF_MODE when touch work without fsm*/
#define RTC_IO_IO_TOUCH_BUFMODE (BIT(4))
#define RTC_IO_IO_TOUCH_BUFMODE_M (BIT(4))
#define RTC_IO_IO_TOUCH_BUFMODE_V 0x1
#define RTC_IO_IO_TOUCH_BUFMODE_S 4
/* RTC_IO_IO_TOUCH_BUFSEL : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
/*description: BUF_SEL when touch work without fsm*/
#define RTC_IO_IO_TOUCH_BUFSEL 0x0000000F
#define RTC_IO_IO_TOUCH_BUFSEL_M ((RTC_IO_IO_TOUCH_BUFSEL_V)<<(RTC_IO_IO_TOUCH_BUFSEL_S))
#define RTC_IO_IO_TOUCH_BUFSEL_V 0xF
#define RTC_IO_IO_TOUCH_BUFSEL_S 0
#define RTC_IO_DATE_REG (DR_REG_RTCIO_BASE + 0x1FC)
/* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1903170 ; */
/*description: */

82
components/soc/esp32s2beta/include/soc/sensitive_reg.h
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@ -1193,7 +1193,85 @@ extern "C" {
#define DPORT_PRO_I_TAG_RD_ACS_V 0x1
#define DPORT_PRO_I_TAG_RD_ACS_S 0
#define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x0EC)
#define DPORT_CACHE_MMU_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x0EC)
/* DPORT_CACHE_MMU_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_CACHE_MMU_ACCESS_LOCK (BIT(0))
#define DPORT_CACHE_MMU_ACCESS_LOCK_M (BIT(0))
#define DPORT_CACHE_MMU_ACCESS_LOCK_V 0x1
#define DPORT_CACHE_MMU_ACCESS_LOCK_S 0
#define DPORT_CACHE_MMU_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x0F0)
/* DPORT_PRO_MMU_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: */
#define DPORT_PRO_MMU_WR_ACS (BIT(1))
#define DPORT_PRO_MMU_WR_ACS_M (BIT(1))
#define DPORT_PRO_MMU_WR_ACS_V 0x1
#define DPORT_PRO_MMU_WR_ACS_S 1
/* DPORT_PRO_MMU_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define DPORT_PRO_MMU_RD_ACS (BIT(0))
#define DPORT_PRO_MMU_RD_ACS_M (BIT(0))
#define DPORT_PRO_MMU_RD_ACS_V 0x1
#define DPORT_PRO_MMU_RD_ACS_S 0
#define DPORT_APB_PERIPHERAL_INTR_REG (DR_REG_SENSITIVE_BASE + 0x0F4)
/* DPORT_APB_PERI_BYTE_ERROR_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define DPORT_APB_PERI_BYTE_ERROR_INTR (BIT(2))
#define DPORT_APB_PERI_BYTE_ERROR_INTR_M (BIT(2))
#define DPORT_APB_PERI_BYTE_ERROR_INTR_V 0x1
#define DPORT_APB_PERI_BYTE_ERROR_INTR_S 2
/* DPORT_APB_PERI_BYTE_ERROR_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define DPORT_APB_PERI_BYTE_ERROR_EN (BIT(1))
#define DPORT_APB_PERI_BYTE_ERROR_EN_M (BIT(1))
#define DPORT_APB_PERI_BYTE_ERROR_EN_V 0x1
#define DPORT_APB_PERI_BYTE_ERROR_EN_S 1
/* DPORT_APB_PERI_BYTE_ERROR_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_APB_PERI_BYTE_ERROR_CLR (BIT(0))
#define DPORT_APB_PERI_BYTE_ERROR_CLR_M (BIT(0))
#define DPORT_APB_PERI_BYTE_ERROR_CLR_V 0x1
#define DPORT_APB_PERI_BYTE_ERROR_CLR_S 0
#define DPORT_APB_PERIPHERAL_STATUS_REG (DR_REG_SENSITIVE_BASE + 0x0F8)
/* DPORT_APB_PERI_BYTE_ERROR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define DPORT_APB_PERI_BYTE_ERROR_ADDR 0xFFFFFFFF
#define DPORT_APB_PERI_BYTE_ERROR_ADDR_M ((DPORT_APB_PERI_BYTE_ERROR_ADDR_V)<<(DPORT_APB_PERI_BYTE_ERROR_ADDR_S))
#define DPORT_APB_PERI_BYTE_ERROR_ADDR_V 0xFFFFFFFF
#define DPORT_APB_PERI_BYTE_ERROR_ADDR_S 0
#define DPORT_CPU_PERIPHERAL_INTR_REG (DR_REG_SENSITIVE_BASE + 0x0FC)
/* DPORT_CPU_PERI_BYTE_ERROR_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define DPORT_CPU_PERI_BYTE_ERROR_INTR (BIT(2))
#define DPORT_CPU_PERI_BYTE_ERROR_INTR_M (BIT(2))
#define DPORT_CPU_PERI_BYTE_ERROR_INTR_V 0x1
#define DPORT_CPU_PERI_BYTE_ERROR_INTR_S 2
/* DPORT_CPU_PERI_BYTE_ERROR_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define DPORT_CPU_PERI_BYTE_ERROR_EN (BIT(1))
#define DPORT_CPU_PERI_BYTE_ERROR_EN_M (BIT(1))
#define DPORT_CPU_PERI_BYTE_ERROR_EN_V 0x1
#define DPORT_CPU_PERI_BYTE_ERROR_EN_S 1
/* DPORT_CPU_PERI_BYTE_ERROR_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define DPORT_CPU_PERI_BYTE_ERROR_CLR (BIT(0))
#define DPORT_CPU_PERI_BYTE_ERROR_CLR_M (BIT(0))
#define DPORT_CPU_PERI_BYTE_ERROR_CLR_V 0x1
#define DPORT_CPU_PERI_BYTE_ERROR_CLR_S 0
#define DPORT_CPU_PERIPHERAL_STATUS_REG (DR_REG_SENSITIVE_BASE + 0x100)
/* DPORT_CPU_PERI_BYTE_ERROR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define DPORT_CPU_PERI_BYTE_ERROR_ADDR 0xFFFFFFFF
#define DPORT_CPU_PERI_BYTE_ERROR_ADDR_M ((DPORT_CPU_PERI_BYTE_ERROR_ADDR_V)<<(DPORT_CPU_PERI_BYTE_ERROR_ADDR_S))
#define DPORT_CPU_PERI_BYTE_ERROR_ADDR_V 0xFFFFFFFF
#define DPORT_CPU_PERI_BYTE_ERROR_ADDR_S 0
#define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x104)
/* SENSITIVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define SENSITIVE_CLK_EN (BIT(0))
@ -1202,7 +1280,7 @@ extern "C" {
#define SENSITIVE_CLK_EN_S 0
#define SENSITIVE_DATE_REG (DR_REG_SENSITIVE_BASE + 0xFFC)
/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h1809042 ; */
/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905090 ; */
/*description: */
#define SENSITIVE_DATE 0x0FFFFFFF
#define SENSITIVE_DATE_M ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S))

232
components/soc/esp32s2beta/include/soc/soc.h
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@ -12,15 +12,15 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _ESP32_SOC_H_
#define _ESP32_SOC_H_
#ifndef __ASSEMBLER__
#include <stdint.h>
#include "esp_assert.h"
#include "esp_bit_defs.h"
#endif
#include <esp_bit_defs.h>
#define PRO_CPU_NUM (0)
#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
@ -29,16 +29,16 @@
#define DR_REG_SENSITIVE_BASE 0x3f4c1000
#define DR_REG_INTERRUPT_BASE 0x3f4c2000
#define DR_REG_DMA_COPY_BASE 0x3f4c3000
#define DR_REG_EXTMEM_BASE 0x3f4c4000
#define DR_REG_MMU_TABLE 0x3f4c5000
#define DR_REG_ITAG_TABLE 0x3f4c6000
#define DR_REG_DTAG_TABLE 0x3f4c7000
#define DR_REG_AES_BASE 0x3f4c8000
#define DR_REG_SHA_BASE 0x3f4c9000
#define DR_REG_RSA_BASE 0x3f4ca000
#define DR_REG_SECURE_BOOT_BASE 0x3f4cb000
#define DR_REG_HMAC_BASE 0x3f4cc000
#define DR_REG_DIGITAL_SINGNATURE_BASE 0x3f4cd000
#define DR_REG_EXTMEM_BASE 0x61800000
#define DR_REG_MMU_TABLE 0x61801000
#define DR_REG_ITAG_TABLE 0x61802000
#define DR_REG_DTAG_TABLE 0x61803000
#define DR_REG_AES_BASE 0x6003a000
#define DR_REG_SHA_BASE 0x6003b000
#define DR_REG_RSA_BASE 0x6003c000
#define DR_REG_HMAC_BASE 0x6003e000
#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000
#define DR_REG_CRYPTO_DMA_BASE 0x6003f000
#define DR_REG_ASSIST_DEBUG_BASE 0x3f4ce000
#define DR_REG_DEDICATED_GPIO_BASE 0x3f4cf000
#define DR_REG_INTRUSION_BASE 0x3f4d0000
@ -79,6 +79,7 @@
#define DR_REG_I2C1_EXT_BASE 0x3f427000
#define DR_REG_SPI4_BASE 0x3f437000
#define DR_REG_USB_WRAP_BASE 0x3f439000
#define DR_REG_APB_SARADC_BASE 0x3f440000
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE)
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 )
@ -94,30 +95,68 @@
#define ETS_CACHED_ADDR(addr) (addr)
#ifndef __ASSEMBLER__
#define BIT(nr) (1UL << (nr))
#else
#define BIT(nr) (1 << (nr))
#endif
#ifndef __ASSEMBLER__
#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END)
#if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_FREERTOS_UNICORE ) && defined( ESP_PLATFORM )
#define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP));
#else
#define ASSERT_IF_DPORT_REG(_r, OP)
#endif
//write value to register
#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
#define REG_WRITE(_r, _v) ({ \
ASSERT_IF_DPORT_REG((_r), REG_WRITE); \
(*(volatile uint32_t *)(_r)) = (_v); \
})
//read value from register
#define REG_READ(_r) (*(volatile uint32_t *)(_r))
#define REG_READ(_r) ({ \
ASSERT_IF_DPORT_REG((_r), REG_READ); \
(*(volatile uint32_t *)(_r)); \
})
//get bit or get bits from register
#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b))
#define REG_GET_BIT(_r, _b) ({ \
ASSERT_IF_DPORT_REG((_r), REG_GET_BIT); \
(*(volatile uint32_t*)(_r) & (_b)); \
})
//set bit or set bits to register
#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b))
#define REG_SET_BIT(_r, _b) ({ \
ASSERT_IF_DPORT_REG((_r), REG_SET_BIT); \
(*(volatile uint32_t*)(_r) |= (_b)); \
})
//clear bit or clear bits of register
#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b))
#define REG_CLR_BIT(_r, _b) ({ \
ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT); \
(*(volatile uint32_t*)(_r) &= ~(_b)); \
})
//set bits of register controlled by mask
#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)))
#define REG_SET_BITS(_r, _b, _m) ({ \
ASSERT_IF_DPORT_REG((_r), REG_SET_BITS); \
(*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); \
})
//get field from register, uses field _S & _V to determine mask
#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f##_V))
#define REG_GET_FIELD(_r, _f) ({ \
ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD); \
((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \
})
//set field of a register from variable, uses field _S & _V to determine mask
#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))))
#define REG_SET_FIELD(_r, _f, _v) ({ \
ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD); \
(REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); \
})
//get field value from a variable, used when _f is not left shifted by _f##_S
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
@ -138,28 +177,52 @@
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
//read value from register
#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)))
#define READ_PERI_REG(addr) ({ \
ASSERT_IF_DPORT_REG((addr), READ_PERI_REG); \
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \
})
//write value to register
#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)
#define WRITE_PERI_REG(addr, val) ({ \
ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); \
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
})
//clear bits of register controlled by mask
#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))))
#define CLEAR_PERI_REG_MASK(reg, mask) ({ \
ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK); \
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \
})
//set bits of register controlled by mask
#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)))
#define SET_PERI_REG_MASK(reg, mask) ({ \
ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK); \
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \
})
//get bits of register controlled by mask
#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask))
#define GET_PERI_REG_MASK(reg, mask) ({ \
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK); \
(READ_PERI_REG(reg) & (mask)); \
})
//get bits of register controlled by highest bit and lowest bit
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS); \
((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \
})
//set bits of register controlled by mask and shift
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ))
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({ \
ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS); \
(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); \
})
//get field of register
#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask))
#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2); \
((READ_PERI_REG(reg)>>(shift))&(mask)); \
})
#endif /* !__ASSEMBLER__ */
//}}
@ -168,8 +231,8 @@
#define APB_CLK_FREQ_ROM ( 40*1000000 )
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define UART_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define CPU_CLK_FREQ APB_CLK_FREQ //this may be incorrect, please refer to ESP32_DEFAULT_CPU_FREQ_MHZ
#define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz
#define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ ( 40*1000000 ) //unit: Hz
#define REF_CLK_FREQ ( 1000000 )
#define UART_CLK_FREQ APB_CLK_FREQ
#define WDT_CLK_FREQ APB_CLK_FREQ
@ -180,10 +243,10 @@
//}}
/* Overall memory map */
#define SOC_DROM_LOW 0x3F000000
#define SOC_DROM_HIGH 0x3F400000
#define SOC_DROM_LOW 0x3F000000/*drom0 low address for icache*/
#define SOC_DROM_HIGH 0x3FF80000/*dram0 high address for dcache*/
#define SOC_IROM_LOW 0x40080000
#define SOC_IROM_HIGH 0x40c00000
#define SOC_IROM_HIGH 0x40800000
#define SOC_IROM_MASK_LOW 0x40000000
#define SOC_IROM_MASK_HIGH 0x4001A100
#define SOC_IRAM_LOW 0x40020000
@ -197,9 +260,7 @@
#define SOC_RTC_DATA_LOW 0x50000000
#define SOC_RTC_DATA_HIGH 0x50002000
#define SOC_EXTRAM_DATA_LOW 0x3F500000
#define SOC_EXTRAM_DATA_HIGH 0x3FF90000
#define SOC_SLOW_EXTRAM_DATA_LOW 0x61800000
#define SOC_SLOW_EXTRAM_DATA_HIGH 0x61c00000
#define SOC_EXTRAM_DATA_HIGH 0x3FF80000
//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
#define SOC_DIRAM_IRAM_LOW 0x40020000
@ -220,97 +281,6 @@
#define SOC_MEM_INTERNAL_LOW 0x3FF9E000
#define SOC_MEM_INTERNAL_HIGH 0x40072000
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
#define ETS_WIFI_MAC_INTR_SOURCE 0/**< interrupt of WiFi MAC, level*/
#define ETS_WIFI_MAC_NMI_SOURCE 1/**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
#define ETS_WIFI_PWR_INTR_SOURCE 2/**< */
#define ETS_WIFI_BB_INTR_SOURCE 3/**< interrupt of WiFi BB, level, we can do some calibartion*/
#define ETS_BT_MAC_INTR_SOURCE 4/**< will be cancelled*/
#define ETS_BT_BB_INTR_SOURCE 5/**< interrupt of BT BB, level*/
#define ETS_BT_BB_NMI_SOURCE 6/**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
#define ETS_RWBT_INTR_SOURCE 7/**< interrupt of RWBT, level*/
#define ETS_RWBLE_INTR_SOURCE 8/**< interrupt of RWBLE, level*/
#define ETS_RWBT_NMI_SOURCE 9/**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
#define ETS_RWBLE_NMI_SOURCE 10/**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
#define ETS_SLC0_INTR_SOURCE 11/**< interrupt of SLC0, level*/
#define ETS_SLC1_INTR_SOURCE 12/**< interrupt of SLC1, level*/
#define ETS_UHCI0_INTR_SOURCE 13/**< interrupt of UHCI0, level*/
#define ETS_UHCI1_INTR_SOURCE 14/**< interrupt of UHCI1, level*/
#define ETS_TG0_T0_LEVEL_INTR_SOURCE 15/**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/
#define ETS_TG0_T1_LEVEL_INTR_SOURCE 16/**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/
#define ETS_TG0_WDT_LEVEL_INTR_SOURCE 17/**< interrupt of TIMER_GROUP0, WATCHDOG, level*/
#define ETS_TG0_LACT_LEVEL_INTR_SOURCE 18/**< interrupt of TIMER_GROUP0, LACT, level*/
#define ETS_TG1_T0_LEVEL_INTR_SOURCE 19/**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/
#define ETS_TG1_T1_LEVEL_INTR_SOURCE 20/**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/
#define ETS_TG1_WDT_LEVEL_INTR_SOURCE 21/**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
#define ETS_TG1_LACT_LEVEL_INTR_SOURCE 22/**< interrupt of TIMER_GROUP1, LACT, level*/
#define ETS_GPIO_INTR_SOURCE 23/**< interrupt of GPIO, level*/
#define ETS_GPIO_NMI_SOURCE 24/**< interrupt of GPIO, NMI*/
#define ETS_GPIO_INTR_SOURCE2 25/**< interrupt of GPIO, level*/
#define ETS_GPIO_NMI_SOURCE2 26/**< interrupt of GPIO, NMI*/
#define ETS_DEDICATED_GPIO_INTR_SOURCE 27/**< interrupt of dedicated GPIO, level*/
#define ETS_FROM_CPU_INTR0_SOURCE 28/**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
#define ETS_FROM_CPU_INTR1_SOURCE 29/**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
#define ETS_FROM_CPU_INTR2_SOURCE 30/**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
#define ETS_FROM_CPU_INTR3_SOURCE 31/**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
#define ETS_SPI1_INTR_SOURCE 32/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
#define ETS_SPI2_INTR_SOURCE 33/**< interrupt of SPI2, level*/
#define ETS_SPI3_INTR_SOURCE 34/**< interrupt of SPI3, level*/
#define ETS_I2S0_INTR_SOURCE 35/**< interrupt of I2S0, level*/
#define ETS_I2S1_INTR_SOURCE 36/**< interrupt of I2S1, level*/
#define ETS_UART0_INTR_SOURCE 37/**< interrupt of UART0, level*/
#define ETS_UART1_INTR_SOURCE 38/**< interrupt of UART1, level*/
#define ETS_UART2_INTR_SOURCE 39/**< interrupt of UART2, level*/
#define ETS_SDIO_HOST_INTR_SOURCE 40/**< interrupt of SD/SDIO/MMC HOST, level*/
#define ETS_PWM0_INTR_SOURCE 41/**< interrupt of PWM0, level, Reserved*/
#define ETS_PWM1_INTR_SOURCE 42/**< interrupt of PWM1, level, Reserved*/
#define ETS_PWM2_INTR_SOURCE 43/**< interrupt of PWM2, level*/
#define ETS_PWM3_INTR_SOURCE 44/**< interruot of PWM3, level*/
#define ETS_LEDC_INTR_SOURCE 45/**< interrupt of LED PWM, level*/
#define ETS_EFUSE_INTR_SOURCE 46/**< interrupt of efuse, level, not likely to use*/
#define ETS_CAN_INTR_SOURCE 47/**< interrupt of can, level*/
#define ETS_USB_INTR_SOURCE 48/**< interrupt of USB, level*/
#define ETS_RTC_CORE_INTR_SOURCE 49/**< interrupt of rtc core, level, include rtc watchdog*/
#define ETS_RMT_INTR_SOURCE 50/**< interrupt of remote controller, level*/
#define ETS_PCNT_INTR_SOURCE 51/**< interrupt of pluse count, level*/
#define ETS_I2C_EXT0_INTR_SOURCE 52/**< interrupt of I2C controller1, level*/
#define ETS_I2C_EXT1_INTR_SOURCE 53/**< interrupt of I2C controller0, level*/
#define ETS_RSA_INTR_SOURCE 54/**< interrupt of RSA accelerator, level*/
#define ETS_SPI1_DMA_INTR_SOURCE 55/**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/
#define ETS_SPI2_DMA_INTR_SOURCE 56/**< interrupt of SPI2 DMA, level*/
#define ETS_SPI3_DMA_INTR_SOURCE 57/**< interrupt of SPI3 DMA, level*/
#define ETS_WDT_INTR_SOURCE 58/**< will be cancelled*/
#define ETS_TIMER1_INTR_SOURCE 59/**< will be cancelled*/
#define ETS_TIMER2_INTR_SOURCE 60/**< will be cancelled*/
#define ETS_TG0_T0_EDGE_INTR_SOURCE 61/**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/
#define ETS_TG0_T1_EDGE_INTR_SOURCE 62/**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/
#define ETS_TG0_WDT_EDGE_INTR_SOURCE 63/**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/
#define ETS_TG0_LACT_EDGE_INTR_SOURCE 64/**< interrupt of TIMER_GROUP0, LACT, EDGE*/
#define ETS_TG1_T0_EDGE_INTR_SOURCE 65/**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/
#define ETS_TG1_T1_EDGE_INTR_SOURCE 66/**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/
#define ETS_TG1_WDT_EDGE_INTR_SOURCE 67/**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/
#define ETS_TG1_LACT_EDGE_INTR_SOURCE 68/**< interrupt of TIMER_GROUP0, LACT, EDGE*/
#define ETS_CACHE_IA_INTR_SOURCE 69/**< interrupt of Cache Invalied Access, LEVEL*/
#define ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE 70/**< interrupt of system timer 0, EDGE*/
#define ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE 71/**< interrupt of system timer 1, EDGE*/
#define ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE 72/**< interrupt of system timer 2, EDGE*/
#define ETS_ASSIST_DEBUG_INTR_SOURCE 73/**< interrupt of Assist debug module, LEVEL*/
#define ETS_PMS_PRO_IRAM0_ILG_INTR_SOURCE 74/**< interrupt of illegal IRAM1 access, LEVEL*/
#define ETS_PMS_PRO_DRAM0_ILG_INTR_SOURCE 75/**< interrupt of illegal DRAM0 access, LEVEL*/
#define ETS_PMS_PRO_DPORT_ILG_INTR_SOURCE 76/**< interrupt of illegal DPORT access, LEVEL*/
#define ETS_PMS_PRO_AHB_ILG_INTR_SOURCE 77/**< interrupt of illegal AHB access, LEVEL*/
#define ETS_PMS_PRO_CACHE_ILG_INTR_SOURCE 78/**< interrupt of illegal CACHE access, LEVEL*/
#define ETS_PMS_DMA_APB_I_ILG_INTR_SOURCE 79/**< interrupt of illegal APB access, LEVEL*/
#define ETS_PMS_DMA_RX_I_ILG_INTR_SOURCE 80/**< interrupt of illegal DMA RX access, LEVEL*/
#define ETS_PMS_DMA_TX_I_ILG_INTR_SOURCE 81/**< interrupt of illegal DMA TX access, LEVEL*/
#define ETS_SPI0_REJECT_CACHE_INTR_SOURCE 82/**< interrupt of SPI0 Cache access rejected, LEVEL*/
#define ETS_SPI1_REJECT_CPU_INTR_SOURCE 83/**< interrupt of SPI1 access rejected, LEVEL*/
#define ETS_DMA_COPY_INTR_SOURCE 84/**< interrupt of DMA copy, LEVEL*/
#define ETS_SPI4_DMA_INTR_SOURCE 85/**< interrupt of SPI4 DMA, LEVEL*/
#define ETS_SPI4_INTR_SOURCE 86/**< interrupt of SPI4, LEVEL*/
#define ETS_MAX_INTR_SOURCE 87/**< number of interrupt sources */
//interrupt cpu using table, Please see the core-isa.h
/*************************************************************************************************************
* Intr num Level Type PRO CPU usage APP CPU uasge
@ -342,7 +312,7 @@
* 25 4 extern level CACHEERR
* 26 5 extern level
* 27 3 extern level Reserved Reserved
* 28 4 extern edge
* 28 4 extern edge DPORT ACCESS DPORT ACCESS
* 29 3 software Reserved Reserved
* 30 4 extern edge Reserved Reserved
* 31 5 extern level
@ -357,11 +327,13 @@
#define ETS_FRC1_INUM 22
#define ETS_T1_WDT_INUM 24
#define ETS_CACHEERR_INUM 25
#define ETS_DPORT_INUM 28
//CPU0 Interrupt number used in ROM, should be cancelled in SDK
#define ETS_SLC_INUM 1
#define ETS_UART0_INUM 5
#define ETS_UART1_INUM 5
#define ETS_SPI2_INUM 1
//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here.
#define ETS_FRC_TIMER2_INUM 10 /* use edge*/
#define ETS_GPIO_INUM 4
@ -370,3 +342,5 @@
//Invalid interrupt for number interrupt matrix
#define ETS_INVALID_INUM 6
#endif /* _ESP32_SOC_H_ */

3
components/soc/esp32s2beta/include/soc/spi_caps.h
View File

@ -45,5 +45,4 @@
#define SOC_SPI_SUPPORT_CD_SIG 1
// Peripheral supports DIO, DOUT, QIO, or QOUT
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_dev) (!((void*)spi_dev == (void*)&GPSPI3 \
|| (void*)spi_dev == (void*)&GPSPI4))
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_dev) (!((void*)spi_dev == (void*)&GPSPI3))

1300
components/soc/esp32s2beta/include/soc/spi_mem_reg.h
View File

File diff suppressed because it is too large Load Diff

421
components/soc/esp32s2beta/include/soc/spi_mem_struct.h
View File

@ -43,19 +43,20 @@ typedef volatile struct {
union {
struct {
uint32_t reserved0: 3; /*reserved*/
uint32_t dummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/
uint32_t reserved4: 3; /*reserved*/
uint32_t fdummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/
uint32_t fdout_oct: 1; /*Apply 8 signals during write-data phase 1:enable 0: disable*/
uint32_t fdin_oct: 1; /*Apply 8 signals during read-data phase 1:enable 0: disable*/
uint32_t faddr_oct: 1; /*Apply 8 signals during address phase 1:enable 0: disable*/
uint32_t fcmd_dual: 1; /*Apply 2 signals during command phase 1:enable 0: disable*/
uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable*/
uint32_t reserved9: 1; /*reserved*/
uint32_t fcmd_oct: 1; /*Apply 8 signals during command phase 1:enable 0: disable*/
uint32_t fcs_crc_en: 1; /*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/
uint32_t tx_crc_en: 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
uint32_t reserved12: 1; /*reserved*/
uint32_t fastrd_mode: 1; /*This bit enable the bits: spi_mem_fread_qio spi_mem_fread_dio spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/
uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/
uint32_t resandres: 1; /*The Device ID is read out to SPI_MEM_RD_STATUS register this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.*/
uint32_t reserved16: 1; /*reserved*/
uint32_t flash_suspending: 1; /*The status of flash suspend only used in SPI1.*/
uint32_t reserved16: 2; /*reserved*/
uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high 0 low*/
uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low*/
uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
@ -70,27 +71,28 @@ typedef volatile struct {
union {
struct {
uint32_t clk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
uint32_t cs_hold_delay_res:12; /*Delay cycles of resume Flash when resume Flash is enable by spi clock.*/
uint32_t cs_hold_delay: 6; /*SPI cs signal is delayed by spi clock cycles.*/
uint32_t reserved20: 12; /*reserved*/
uint32_t cs_hold_dly_res:12; /*Delay cycles of resume Flash when resume Flash from standby mode is enable by spi clock.*/
uint32_t cs_hold_dly: 12; /*SPI fsm is delayed to idle by spi clock cycles.*/
uint32_t cs_dly_num: 2; /*spi_mem_cs signal is delayed by system clock cycles*/
uint32_t cs_dly_mode: 2; /*The cs signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk*/
uint32_t reserved30: 1;
uint32_t cs_dly_edge: 1; /*The bit is used to select the spi clock edge to modify CS line timing.*/
};
uint32_t val;
} ctrl1;
union {
struct {
uint32_t cs_setup_time:13; /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
uint32_t cs_hold_time: 13; /*delay cycles of cs pin by spi clock this bits are combined with spi_mem_cs_hold bit.*/
uint32_t cs_delay_mode: 2; /*spi_mem_cs signal is delayed by spi_mem_clk . 0: zero 1: if spi_mem_ck_out_edge or spi_mem_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_mem_ck_out_edge or spi_mem_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
uint32_t cs_delay_num: 2; /*spi_mem_cs signal is delayed by system clock cycles*/
uint32_t cs_delay_edge: 1; /*The bit is used to select the spi clock edge to modify CS line timing.*/
uint32_t cs_hold_time: 13; /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
uint32_t reserved26: 5; /*reserved*/
uint32_t sync_reset: 1; /*The FSM will be reset.*/
};
uint32_t val;
} ctrl2;
union {
struct {
uint32_t clkcnt_l: 8; /*In the master mode it must be equal to spi_mem_clkcnt_N. In the slave mode it must be 0.*/
uint32_t clkcnt_h: 8; /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/
uint32_t clkcnt_l: 8; /*In the master mode it must be equal to spi_mem_clkcnt_N.*/
uint32_t clkcnt_h: 8; /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
uint32_t clkcnt_n: 8; /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
uint32_t reserved24: 7; /*In the master mode it is pre-divider of spi_mem_clk.*/
uint32_t clk_equ_sysclk: 1; /*reserved*/
@ -102,7 +104,7 @@ typedef volatile struct {
uint32_t reserved0: 6; /*reserved*/
uint32_t cs_hold: 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable.*/
uint32_t cs_setup: 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/
uint32_t ck_i_edge: 1; /*In the slave mode the bit is same as spi_mem_ck_out_edge in master mode. It is combined with spi_mem_miso_delay_mode bits.*/
uint32_t reserved8: 1; /*reserved*/
uint32_t ck_out_edge: 1; /*the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.*/
uint32_t reserved10: 2; /*reserved*/
uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals*/
@ -204,7 +206,7 @@ typedef volatile struct {
uint32_t sram_rdummy_cyclelen: 8; /*For SPI0 In the sram mode it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/
uint32_t sram_addr_bitlen: 6; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/
uint32_t cache_sram_usr_wcmd: 1; /*For SPI0 In the spi sram mode cache write sram for user define command*/
uint32_t reserved21: 1; /*reserved*/
uint32_t sram_oct: 1; /*reserved*/
uint32_t sram_wdummy_cyclelen: 8; /*For SPI0 In the sram mode it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/
uint32_t reserved30: 2; /*reserved*/
};
@ -222,7 +224,12 @@ typedef volatile struct {
uint32_t sdout_quad: 1; /*For SPI0 sram dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
uint32_t saddr_quad: 1; /*For SPI0 sram address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
uint32_t scmd_quad: 1; /*For SPI0 sram cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
uint32_t reserved18:14; /*reserved*/
uint32_t sdin_oct: 1; /*For SPI0 sram din phase apply 8 signals. 1: enable 0: disable.*/
uint32_t sdout_oct: 1; /*For SPI0 sram dout phase apply 8 signals. 1: enable 0: disable.*/
uint32_t saddr_oct: 1; /*For SPI0 sram address phase apply 4 signals. 1: enable 0: disable.*/
uint32_t scmd_oct: 1; /*For SPI0 sram cmd phase apply 8 signals. 1: enable 0: disable.*/
uint32_t sdummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/
uint32_t reserved23: 9; /*reserved*/
};
uint32_t val;
} sram_cmd;
@ -244,8 +251,8 @@ typedef volatile struct {
} sram_dwr_cmd;
union {
struct {
uint32_t cnt_l: 8; /*For SPI0 sram interface it must be equal to spi_mem_clkcnt_N. In the slave mode it must be 0.*/
uint32_t cnt_h: 8; /*For SPI0 sram interface it must be floor((spi_mem_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/
uint32_t cnt_l: 8; /*For SPI0 sram interface it must be equal to spi_mem_clkcnt_N.*/
uint32_t cnt_h: 8; /*For SPI0 sram interface it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
uint32_t cnt_n: 8; /*For SPI0 sram interface it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
uint32_t reserved24: 7; /*reserved*/
uint32_t equ_sysclk: 1; /*For SPI0 sram interface 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/
@ -259,152 +266,7 @@ typedef volatile struct {
};
uint32_t val;
} fsm;
union {
struct {
uint32_t hold_ena: 2; /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at idle phase 2: hold at prepare phase.*/
uint32_t reserved2: 30; /*reserved*/
};
uint32_t val;
} hold;
union {
struct {
uint32_t dma_rx_ena: 1; /*spi dma rx data enable.*/
uint32_t dma_tx_ena: 1; /*spi dma tx data enable.*/
uint32_t in_rst: 1; /*The bit is used to reset in dma fsm and in data fifo pointer.*/
uint32_t out_rst: 1; /*The bit is used to reset out dma fsm and out data fifo pointer.*/
uint32_t ahbm_fifo_rst: 1; /*Reset spi dma ahb master fifo pointer.*/
uint32_t ahbm_rst: 1; /*Reset spi dma ahb master.*/
uint32_t in_loop_test: 1; /*Set bit to test in link.*/
uint32_t out_loop_test: 1; /*Set bit to test out link.*/
uint32_t out_auto_wrback: 1; /*when the bit is set DMA continue to use the next inlink node when the length of inlink is 0.*/
uint32_t out_eof_mode: 1; /*out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo.*/
uint32_t outdscr_burst_en: 1; /*read descriptor use burst mode when read data for memory.*/
uint32_t indscr_burst_en: 1; /*read descriptor use burst mode when write data to memory.*/
uint32_t out_data_burst_en: 1; /*spi dma read data from memory in burst mode.*/
uint32_t dma_mem_trans_ena: 1; /*reserved*/
uint32_t dma_rx_stop: 1; /*spi dma read data stop when in continue tx/rx mode.*/
uint32_t dma_tx_stop: 1; /*spi dma write data stop when in continue tx/rx mode.*/
uint32_t dma_continue: 1; /*spi dma continue tx/rx data.*/
uint32_t reserved17: 15; /*reserved*/
};
uint32_t val;
} dma_conf;
union {
struct {
uint32_t addr: 20; /*The address of the first outlink descriptor.*/
uint32_t reserved20: 8; /*reserved*/
uint32_t stop: 1; /*Set the bit to stop to use outlink descriptor.*/
uint32_t start: 1; /*Set the bit to start to use outlink descriptor.*/
uint32_t restart: 1; /*Set the bit to mount on new outlink descriptors.*/
uint32_t reserved31: 1; /*reserved*/
};
uint32_t val;
} dma_out_link;
union {
struct {
uint32_t addr: 20; /*The address of the first inlink descriptor.*/
uint32_t auto_ret: 1; /*when the bit is set the inlink descriptor returns to the first link node when a packet is error.*/
uint32_t reserved21: 7; /*reserved*/
uint32_t stop: 1; /*Set the bit to stop to use inlink descriptor.*/
uint32_t start: 1; /*Set the bit to start to use inlink descriptor.*/
uint32_t restart: 1; /*Set the bit to mount on new inlink descriptors.*/
uint32_t reserved31: 1; /*reserved*/
};
uint32_t val;
} dma_in_link;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The enable bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The enable bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The enable bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The enable bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The enable bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The enable bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The enable bit for completing usage of a outlink descriptor .*/
uint32_t out_eof: 1; /*The enable bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The enable bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} dma_int_ena;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The raw bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The raw bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The raw bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The raw bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The raw bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The raw bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The raw bit for completing usage of a outlink descriptor.*/
uint32_t out_eof: 1; /*The raw bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The raw bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} dma_int_raw;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The status bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The status bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The status bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The status bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The status bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The status bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The status bit for completing usage of a outlink descriptor.*/
uint32_t out_eof: 1; /*The status bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The status bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} dma_int_st;
union {
struct {
uint32_t inlink_dscr_empty: 1; /*The clear bit for lack of enough inlink descriptors.*/
uint32_t outlink_dscr_error: 1; /*The clear bit for outlink descriptor error.*/
uint32_t inlink_dscr_error: 1; /*The clear bit for inlink descriptor error.*/
uint32_t in_done: 1; /*The clear bit for completing usage of a inlink descriptor.*/
uint32_t in_err_eof: 1; /*The clear bit for receiving error.*/
uint32_t in_suc_eof: 1; /*The clear bit for completing receiving all the packets from host.*/
uint32_t out_done: 1; /*The clear bit for completing usage of a outlink descriptor.*/
uint32_t out_eof: 1; /*The clear bit for sending a packet to host done.*/
uint32_t out_total_eof: 1; /*The clear bit for sending all the packets to host done.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
} dma_int_clr;
uint32_t dma_in_err_eof_des_addr; /*The inlink descriptor address when spi dma produce receiving error.*/
uint32_t dma_in_suc_eof_des_addr; /*The last inlink descriptor address when spi dma produce from_suc_eof.*/
uint32_t dma_inlink_dscr; /*The content of current in descriptor pointer.*/
uint32_t dma_inlink_dscr_bf0; /*The content of next in descriptor pointer.*/
uint32_t dma_inlink_dscr_bf1; /*The content of current in descriptor data buffer pointer.*/
uint32_t dma_out_eof_bfr_des_addr; /*The address of buffer relative to the outlink descriptor that produce eof.*/
uint32_t dma_out_eof_des_addr; /*The last outlink descriptor address when spi dma produce to_eof.*/
uint32_t dma_outlink_dscr; /*The content of current out descriptor pointer.*/
uint32_t dma_outlink_dscr_bf0; /*The content of next out descriptor pointer.*/
uint32_t dma_outlink_dscr_bf1; /*The content of current out descriptor data buffer pointer.*/
union {
struct {
uint32_t out_dscr_addr: 18; /*SPI dma out descriptor address.*/
uint32_t out_dscr_state: 2; /*SPI dma out descriptor state.*/
uint32_t out_state: 3; /*SPI dma out data state.*/
uint32_t out_fifo_cnt: 7; /*The remains of SPI dma outfifo data.*/
uint32_t out_fifo_full: 1; /*SPI dma outfifo is full.*/
uint32_t out_fifo_empty: 1; /*SPI dma outfifo is empty.*/
};
uint32_t val;
} dma_out_status;
union {
struct {
uint32_t in_dscr_addr: 18; /*SPI dma in descriptor address.*/
uint32_t in_dscr_state: 2; /*SPI dma in descriptor state.*/
uint32_t in_state: 3; /*SPI dma in data state.*/
uint32_t in_fifo_cnt: 7; /*The remains of SPI dma infifo data.*/
uint32_t in_fifo_full: 1; /*SPI dma infifo is full.*/
uint32_t in_fifo_empty: 1; /*SPI dma infifo is empty.*/
};
uint32_t val;
} dma_in_status;
uint32_t data_buf[16]; /*data buffer*/
uint32_t data_buf[18]; /*data buffer*/
union {
struct {
uint32_t waiti_en: 1; /*auto-waiting flash idle operation when program flash or erase flash. 1: enable 0: disable.*/
@ -434,41 +296,62 @@ typedef volatile struct {
} flash_sus_ctrl;
union {
struct {
uint32_t din0_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din1_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din2_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din3_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t reserved8: 10; /*reserved*/
uint32_t din0_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t din1_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t din2_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t din3_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t reserved22: 10; /*reserved*/
uint32_t flash_sus: 1; /*The status of flash suspend only used in SPI1.*/
uint32_t reserved1: 31;
};
uint32_t val;
} sus_status;
union {
struct {
uint32_t timing_clk_ena: 1; /*The bit is used to enable timing adjust clock for all reading operations.*/
uint32_t timing_cali: 1; /*The bit is used to enable timing auto-calibration for all reading operations.*/
uint32_t extra_dummy_cyclelen: 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/
uint32_t reserved5: 27;
};
uint32_t val;
} timing_cali;
union {
struct {
uint32_t din0_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t din1_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t din2_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t din3_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t din4_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din5_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din6_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din7_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t dins_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t reserved18:14; /*reserved*/
};
uint32_t val;
} din_mode;
union {
struct {
uint32_t din0_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din1_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din2_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din3_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t reserved8: 24; /*reserved*/
uint32_t din0_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din1_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din2_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din3_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din4_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din5_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din6_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din7_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dins_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t reserved27: 5; /*reserved*/
};
uint32_t val;
} din_num;
union {
struct {
uint32_t dout0_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout1_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout2_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout3_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t reserved8: 10; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout0_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t dout1_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t dout2_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t dout3_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t reserved22: 10; /*reserved*/
uint32_t dout0_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t dout1_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t dout2_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t dout3_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t dout4_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout5_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout6_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout7_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t douts_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t reserved18:14; /*reserved*/
};
uint32_t val;
} dout_mode;
@ -478,67 +361,151 @@ typedef volatile struct {
uint32_t dout1_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout2_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout3_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t reserved8: 24; /*reserved*/
uint32_t dout4_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout5_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout6_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout7_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t douts_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t reserved18:14; /*reserved*/
};
uint32_t val;
} dout_num;
union {
struct {
uint32_t sdin0_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t sdin1_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t sdin2_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t sdin3_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t reserved8: 10;
uint32_t sdin0_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t sdin1_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t sdin2_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t sdin3_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t reserved22: 10; /*reserved*/
uint32_t spi_smem_timing_clk_ena: 1; /*For sram the bit is used to enable timing adjust clock for all reading operations.*/
uint32_t spi_smem_timing_cali: 1; /*For sram the bit is used to enable timing auto-calibration for all reading operations.*/
uint32_t spi_smem_extra_dummy_cyclelen: 3; /*For sram add extra dummy spi clock cycle length for spi clock calibration.*/
uint32_t reserved5: 27;
};
uint32_t val;
} sdin_mode;
} spi_smem_timing_cali;
union {
struct {
uint32_t sdin0_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t sdin1_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t sdin2_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t sdin3_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t reserved8: 24; /*reserved*/
uint32_t spi_smem_din0_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_din1_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_din2_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_din3_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_din4_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_din5_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_din6_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_din7_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_dins_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t reserved18: 14; /*reserved*/
};
uint32_t val;
} sdin_num;
} spi_smem_din_mode;
union {
struct {
uint32_t sdout0_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t sdout1_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t sdout2_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t sdout3_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t reserved8: 10; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t sdout0_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t sdout1_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t sdout2_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t sdout3_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t reserved22: 10; /*reserved*/
uint32_t spi_smem_din0_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din1_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din2_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din3_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din4_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din5_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din6_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din7_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_dins_num: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t reserved27: 5; /*reserved*/
};
uint32_t val;
} sdout_mode;
} spi_smem_din_num;
union {
struct {
uint32_t sdout0_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t sdout1_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t sdout2_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t sdout3_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t reserved8: 24; /*reserved*/
uint32_t spi_smem_dout0_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout1_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout2_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout3_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout4_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout5_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout6_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout7_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_douts_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t reserved18: 14; /*reserved*/
};
uint32_t val;
} sdout_num;
} spi_smem_dout_mode;
union {
struct {
uint32_t clk_en: 1;
uint32_t reserved1: 31;
uint32_t spi_smem_dout0_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_dout1_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_dout2_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_dout3_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_dout4_num: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout5_num: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout6_num: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout7_num: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_douts_num: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t reserved18: 14; /*reserved*/
};
uint32_t val;
} spi_smem_dout_num;
union {
struct {
uint32_t spi_smem_cs_setup: 1; /*For spi0 spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/
uint32_t spi_smem_cs_hold: 1; /*For spi0 spi cs keep low when spi is in done phase. 1: enable 0: disable.*/
uint32_t spi_smem_cs_setup_time:13; /*For spi0 (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
uint32_t spi_smem_cs_hold_time: 13; /*For spi0 spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
uint32_t reserved28: 4;
};
uint32_t val;
} spi_smem_ac;
union {
struct {
uint32_t spi_fmem_ddr_en: 1; /*1: in ddr mode 0 in sdr mode*/
uint32_t spi_fmem_var_dummy: 1; /*Set the bit to enable variable dummy cycle in spi ddr mode.*/
uint32_t spi_fmem_ddr_rdat_swp: 1; /*Set the bit to reorder rx data of the word in spi ddr mode.*/
uint32_t spi_fmem_ddr_wdat_swp: 1; /*Set the bit to reorder tx data of the word in spi ddr mode.*/
uint32_t spi_fmem_ddr_cmd_dis: 1; /*the bit is used to disable dual edge in command phase when ddr mode.*/
uint32_t spi_fmem_outminbytelen: 8; /*It is the minimum output data length in the panda device.*/
uint32_t spi_fmem_usr_ddr_dqs_thd: 8; /*The delay number of data strobe which from memory based on SPI clock.*/
uint32_t spi_fmem_ddr_dqs_loop: 1; /*the data strobe is generated by SPI.*/
uint32_t spi_fmem_ddr_dqs_loop_mode: 2; /*the bits are combined with the bit spi_fmem_ddr_fdqs_loop which used to select data strobe generating mode in ddr mode.*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
} ddr;
union {
struct {
uint32_t spi_smem_ddr_en: 1; /*1: in ddr mode 0 in sdr mode*/
uint32_t spi_smem_var_dummy: 1; /*Set the bit to enable variable dummy cycle in spi ddr mode.*/
uint32_t spi_smem_ddr_rdat_swp: 1; /*Set the bit to reorder rx data of the word in spi ddr mode.*/
uint32_t spi_smem_ddr_wdat_swp: 1; /*Set the bit to reorder tx data of the word in spi ddr mode.*/
uint32_t spi_smem_ddr_cmd_dis: 1; /*the bit is used to disable dual edge in command phase when ddr mode.*/
uint32_t spi_smem_outminbytelen: 8; /*It is the minimum output data length in the ddr psram.*/
uint32_t spi_smem_usr_ddr_dqs_thd: 8; /*The delay number of data strobe which from memory based on SPI clock.*/
uint32_t spi_smem_ddr_dqs_loop: 1; /*the data strobe is generated by SPI.*/
uint32_t spi_smem_ddr_dqs_loop_mode: 2; /*the bits are combined with the bit spi_smem_ddr_fdqs_loop which used to select data strobe generating mode in ddr mode.*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
} spi_smem_ddr;
union {
struct {
uint32_t clk_en: 1; /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
uint32_t reserved1: 31; /*reserved*/
};
uint32_t val;
} clock_gate;
union {
struct {
uint32_t spi01_clk_sel: 2; /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/
uint32_t reserved2: 30; /*reserved*/
};
uint32_t val;
} spi_core_clk_sel;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t reserved_fc;
uint32_t reserved_100;
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
uint32_t reserved_110;
uint32_t reserved_114;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;

40
components/soc/esp32s2beta/include/soc/spi_pins.h Normal file
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@ -0,0 +1,40 @@
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SPI_PINS_H_
#define _SOC_SPI_PINS_H_
#define SPI_PERIPH_NUM 3
#define SPI_FUNC_NUM 2
#define SPI_IOMUX_PIN_NUM_HD 27
#define SPI_IOMUX_PIN_NUM_CS 29
#define SPI_IOMUX_PIN_NUM_MOSI 32
#define SPI_IOMUX_PIN_NUM_CLK 30
#define SPI_IOMUX_PIN_NUM_MISO 31
#define SPI_IOMUX_PIN_NUM_WP 28
//TODO: add the next slot
#define FSPI_FUNC_NUM 0
#define FSPI_IOMUX_PIN_NUM_HD 9
#define FSPI_IOMUX_PIN_NUM_CS 10
#define FSPI_IOMUX_PIN_NUM_MOSI 11
#define FSPI_IOMUX_PIN_NUM_CLK 12
#define FSPI_IOMUX_PIN_NUM_MISO 13
#define FSPI_IOMUX_PIN_NUM_WP 14
//TODO: add the next slot
//HSPI and VSPI have no iomux pins
#endif

1292
components/soc/esp32s2beta/include/soc/spi_reg.h
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228
components/soc/esp32s2beta/include/soc/spi_struct.h
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@ -20,9 +20,10 @@ extern "C" {
typedef volatile struct {
union {
struct {
uint32_t reserved0: 18; /*reserved*/
uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t reserved19:13;
uint32_t conf_bitlen:23; /*Define the spi_clk cycles of SPI_CONF state.*/
uint32_t reserved23: 1; /*reserved*/
uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/
uint32_t reserved25: 7; /*reserved*/
};
uint32_t val;
} cmd;
@ -35,33 +36,35 @@ typedef volatile struct {
uint32_t reserved4: 1; /*reserved*/
uint32_t faddr_dual: 1; /*Apply 2 signals during addr phase 1:enable 0: disable*/
uint32_t faddr_quad: 1; /*Apply 4 signals during addr phase 1:enable 0: disable*/
uint32_t faddr_oct: 1; /*Apply 8 signals during addr phase 1:enable 0: disable*/
uint32_t fcmd_dual: 1; /*Apply 2 signals during command phase 1:enable 0: disable*/
uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable*/
uint32_t reserved9: 4;
uint32_t fast_rd_mode: 1; /*Enable 2/4 lines addr command including read and write command.*/
uint32_t fcmd_oct: 1; /*Apply 8 signals during command phase 1:enable 0: disable*/
uint32_t reserved11: 3; /*reserved*/
uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/
uint32_t reserved15: 3;
uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
uint32_t fread_oct: 1; /*In the read operations read-data phase apply 8 signals. 1: enable 0: disable.*/
uint32_t reserved17: 1; /*reserved*/
uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high 0 low*/
uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low*/
uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
uint32_t reserved20: 1; /*reserved*/
uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/
uint32_t reserved22: 3; /*reserved*/
uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first*/
uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/
uint32_t define_addr: 1; /*set spi_usr_addr and spi_usr_addr_value in spi defined slave mode. 1: disable 0:enable.*/
uint32_t reserved28: 4; /*reserved*/
uint32_t reserved27: 5; /*reserved*/
};
uint32_t val;
} ctrl;
union {
struct {
uint32_t clk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
uint32_t clk_mode_13: 1; /*{CPOL CPHA} 1: support spi clk mode 1 and 3 first edge output data B[0]/B[7]*/
uint32_t clk_mode_13: 1; /*{CPOL CPHA} 1: support spi clk mode 1 and 3 first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2 first edge output data B[1]/B[6].*/
uint32_t rsck_data_out: 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge*/
uint32_t w16_17_wr_ena: 1; /*1:reg_buf[16] [17] can be written 0:reg_buf[16] [17] can not be written.*/
uint32_t reserved5: 9; /*reserved*/
uint32_t cs_hold_delay: 6; /*SPI cs signal is delayed by spi clock cycles.*/
uint32_t reserved20: 12;
uint32_t reserved20: 12; /*reserved*/
};
uint32_t val;
} ctrl1;
@ -69,10 +72,9 @@ typedef volatile struct {
struct {
uint32_t cs_setup_time:13; /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit.*/
uint32_t cs_hold_time: 13; /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.*/
uint32_t cs_delay_mode: 2; /*spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
uint32_t cs_delay_mode: 3; /*spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/
uint32_t cs_delay_num: 2; /*spi_cs signal is delayed by system clock cycles*/
uint32_t reserved30: 1; /*reserved*/
uint32_t cs_delay_edge: 1;
uint32_t reserved31: 1; /*reserved*/
};
uint32_t val;
} ctrl2;
@ -100,8 +102,8 @@ typedef volatile struct {
uint32_t wr_byte_order: 1; /*In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/
uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals*/
uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals*/
uint32_t reserved14: 1; /*reserved*/
uint32_t reserved15: 1; /*reserved*/
uint32_t fwrite_oct: 1; /*In the write operations read-data phase apply 8 signals*/
uint32_t usr_conf_nxt: 1; /*1: Enable the DMA CONF phase of next seg-trans operation which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode.*/
uint32_t sio: 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable.*/
uint32_t usr_hold_pol: 1; /*It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/
uint32_t usr_dout_hold: 1; /*spi is hold at data out state the bit are combined with spi_usr_hold_pol bit.*/
@ -124,8 +126,8 @@ typedef volatile struct {
union {
struct {
uint32_t usr_dummy_cyclelen: 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
uint32_t reserved8: 18; /*reserved*/
uint32_t usr_addr_bitlen: 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/
uint32_t reserved8: 19; /*reserved*/
uint32_t usr_addr_bitlen: 5; /*The length in bits of address phase. The register value shall be (bit_num-1).*/
};
uint32_t val;
} user1;
@ -139,15 +141,15 @@ typedef volatile struct {
} user2;
union {
struct {
uint32_t usr_mosi_bit_len:24; /*The length in bits of write-data. The register value shall be (bit_num-1).*/
uint32_t reserved24: 8; /*reserved*/
uint32_t usr_mosi_bit_len:23; /*The length in bits of write-data. The register value shall be (bit_num-1).*/
uint32_t reserved23: 9; /*reserved*/
};
uint32_t val;
} mosi_dlen;
union {
struct {
uint32_t usr_miso_bit_len:24; /*The length in bits of read-data. The register value shall be (bit_num-1).*/
uint32_t reserved24: 8; /*reserved*/
uint32_t usr_miso_bit_len:23; /*The length in bits of read-data. The register value shall be (bit_num-1).*/
uint32_t reserved23: 9; /*reserved*/
};
uint32_t val;
} miso_dlen;
@ -157,14 +159,20 @@ typedef volatile struct {
uint32_t cs0_dis: 1; /*SPI CS0 pin enable 1: disable CS0 0: spi_cs0 signal is from/to CS0 pin*/
uint32_t cs1_dis: 1; /*SPI CS1 pin enable 1: disable CS1 0: spi_cs1 signal is from/to CS1 pin*/
uint32_t cs2_dis: 1; /*SPI CS2 pin enable 1: disable CS2 0: spi_cs2 signal is from/to CS2 pin*/
uint32_t reserved3: 2; /*reserved*/
uint32_t cs3_dis: 1; /*reserved*/
uint32_t cs4_dis: 1; /*SPI CS4 pin enable 1: disable CS4 0: spi_cs4 signal is from/to CS4 pin*/
uint32_t cs5_dis: 1; /*SPI CS5 pin enable 1: disable CS5 0: spi_cs5 signal is from/to CS5 pin*/
uint32_t ck_dis: 1; /*1: spi clk out disable 0: spi clk out enable*/
uint32_t master_cs_pol: 3; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol.*/
uint32_t reserved9: 14; /*reserved*/
uint32_t master_cs_pol: 6; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol.*/
uint32_t reserved13: 7; /*reserved*/
uint32_t cd_data_set: 1; /*1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DOUT or SPI_DIN state. 0: spi_cd = spi_cd_idle_edge.*/
uint32_t cd_dummy_set: 1; /*1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DUMMY state. 0: spi_cd = spi_cd_idle_edge.*/
uint32_t cd_addr_set: 1; /*1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_ADDR state. 0: spi_cd = spi_cd_idle_edge.*/
uint32_t slave_cs_pol: 1; /*spi slave input cs polarity select. 1: inv 0: not change*/
uint32_t reserved24: 3; /*reserved*/
uint32_t q_idle_out: 1; /*The idle output value of spi_q.*/
uint32_t reserved28: 1; /*reserved*/
uint32_t dqs_idle_edge: 1; /*The default value of spi_dqs.*/
uint32_t cd_cmd_set: 1; /*1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_CMD state. 0: spi_cd = spi_cd_idle_edge.*/
uint32_t cd_idle_edge: 1; /*The default value of spi_cd.*/
uint32_t reserved27: 2; /*reserved*/
uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/
uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/
uint32_t quad_din_pin_swap: 1; /*1: spi quad input swap enable 0: spi quad input swap disable*/
@ -175,11 +183,11 @@ typedef volatile struct {
struct {
uint32_t reserved0: 4; /*reserved*/
uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/
uint32_t int_rd_buf_done_en: 1; /*spi_slv_rd_buf Interrupt enable. 1: enable 0: disable*/
uint32_t int_wr_buf_done_en: 1; /*spi_slv_wr_buf Interrupt enable. 1: enable 0: disable*/
uint32_t int_rd_dma_done_en: 1; /*spi_slv_rd_dma Interrupt enable. 1: enable 0: disable*/
uint32_t int_wr_dma_done_en: 1; /*spi_slv_wr_dma Interrupt enable. 1: enable 0: disable*/
uint32_t int_trans_done_en: 1; /*spi_trans_done Interrupt enable. 1: enable 0: disable*/
uint32_t rd_buf_inten: 1; /*The interrupt enable bit for the completion of read-buffer operation in the slave mode.*/
uint32_t wr_buf_inten: 1; /*The interrupt enable bit for the completion of write-buffer operation in the slave mode.*/
uint32_t rd_dma_inten: 1; /*The interrupt enable bit for the completion of read-status operation in the slave mode.*/
uint32_t wr_dma_inten: 1; /*The interrupt enable bit for the completion of write-status operation in the slave mode.*/
uint32_t trans_inten: 1; /*The interrupt enable bit for the completion of any operation in both the master mode and the slave mode.*/
uint32_t reserved10:13; /*reserved*/
uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode.*/
uint32_t reserved27: 1; /*reserved*/
@ -192,21 +200,19 @@ typedef volatile struct {
} slave;
union {
struct {
uint32_t rd_addr_bytelen: 4; /*In the slave mode it is the address length in bytes for read-buffer operation. The register value shall be byte_num.*/
uint32_t wr_addr_bytelen: 4; /*In the slave mode it is the address length in bytes for write-buffer operation. The register value shall be byte_num.*/
uint32_t reserved8: 3; /*reserved*/
uint32_t wr_dma_done: 1; /*The interrupt raw bit for the completion of dma write operation in the slave mode.*/
uint32_t last_command: 3; /*In the slave mode it is the value of command.*/
uint32_t last_addr: 7; /*In the slave mode it is the value of address.*/
uint32_t reserved22: 10; /*reserved*/
uint32_t reserved0: 13; /*reserved*/
uint32_t addr_err: 1; /*1: The address value of the last SPI transfer is not supported by SPI slave. 0: The address value is supported or no address value is received.*/
uint32_t cmd_err: 1; /*1: The command value of the last SPI transfer is not supported by SPI slave. 0: The command value is supported or no command value is received.*/
uint32_t wr_dma_done: 1; /*The interrupt raw bit for the completion of dma write operation in the slave mode. Can not be changed by CONF_buf.*/
uint32_t last_command: 8; /*In the slave mode it is the value of command.*/
uint32_t last_addr: 8; /*In the slave mode it is the value of address.*/
};
uint32_t val;
} slave1;
union {
struct {
uint32_t rd_dummy_bytelen: 4; /*In the slave mode it is the length in spi_clk byte cycles of dummy phase for read operations.*/
uint32_t wr_dummy_bytelen: 4; /*In the slave mode it is the length in spi_clk byte cycles of dummy phase for write operations.*/
uint32_t rd_dma_done: 1; /*The interrupt raw bit for the completion of dma read operation in the slave mode.*/
uint32_t reserved0: 8;
uint32_t rd_dma_done: 1; /*The interrupt raw bit for the completion of Rd-DMA operation in the slave mode. Can not be changed by CONF_buf.*/
uint32_t reserved9: 23; /*reserved*/
};
uint32_t val;
@ -237,8 +243,9 @@ typedef volatile struct {
uint32_t reserved_4c;
union {
struct {
uint32_t st: 3; /*The status of spi state machine. 0: idle state 1: preparation state 2: send command state 3: send data state 4: red data state 5:write data state 6: wait state 7: done state.*/
uint32_t reserved3: 29; /*reserved*/
uint32_t st: 4; /*The status of spi state machine. 0: idle state 1: preparation state 2: send command state 3: send data state 4: red data state 5:write data state 6: wait state 7: done state.*/
uint32_t reserved4: 8; /*reserved*/
uint32_t mst_dma_rd_bytelen:20; /*Define the master DMA read byte length in non seg-trans or seg-trans mode. Invalid when spi_rx_eof_en is 0.*/
};
uint32_t val;
} fsm;
@ -248,7 +255,8 @@ typedef volatile struct {
uint32_t hold_val: 1; /*spi hold output value which should be used with spi_hold_out_en.*/
uint32_t hold_out_en: 1; /*Enable set spi output hold value to spi_hold_reg. It can be used to hold spi state machine with spi_ext_hold_en and other usr hold signals.*/
uint32_t hold_out_time: 3; /*set the hold cycles of output spi_hold signal when spi_hold_out_en is enable.*/
uint32_t reserved7: 25; /*reserved*/
uint32_t dma_seg_trans_done: 1; /*1: spi master DMA full-duplex/half-duplex seg-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-trans is not ended or not occurred. Can not be changed by CONF_buf.*/
uint32_t reserved8: 24; /*reserved*/
};
uint32_t val;
} hold;
@ -270,12 +278,17 @@ typedef volatile struct {
uint32_t dma_rx_stop: 1; /*spi dma read data stop when in continue tx/rx mode.*/
uint32_t dma_tx_stop: 1; /*spi dma write data stop when in continue tx/rx mode.*/
uint32_t dma_continue: 1; /*spi dma continue tx/rx data.*/
uint32_t continue_pop_data_clr: 1; /*Disable spi slave dma to pop data continuously in next transmission in dma half duplex slave mode. 1: disable continue transmit. 0: enable continue transmit.*/
uint32_t slv_rx_seg_trans_en: 1; /*enable DMA segment transfer in slave mode*/
uint32_t reserved19: 3; /*reserved*/
uint32_t infifo_full_clr: 1;
uint32_t outfifo_empty_clr: 1;
uint32_t reserved24: 8;
uint32_t last_seg_pop_clr: 1; /*1: Clear spi_slv_seg_frt_pop_mask. 0 : others*/
uint32_t dma_seg_trans_en: 1; /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/
uint32_t rx_seg_trans_clr_en: 1; /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/
uint32_t tx_seg_trans_clr_en: 1; /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/
uint32_t rx_eof_en: 1; /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/
uint32_t infifo_full_clr: 1; /*1:Clear spi_dma_infifo_full_vld. 0: Do not control it.*/
uint32_t outfifo_empty_clr: 1; /*1:Clear spi_dma_outfifo_empty_vld. 0: Do not control it.*/
uint32_t infifo_full_err: 1; /*1:spi_dma_infifo_full and spi_push_data_prep are valid which means that DMA Rx buffer is full but push is valid. 0: Others. Can not be changed by CONF_buf.*/
uint32_t outfifo_empty_err: 1; /*1:spi_dma_outfifo_empty and spi_pop_data_prep are valid which means that there is no data to pop but pop is valid. 0: Others. Can not be changed by CONF_buf.*/
uint32_t ext_mem_bk_size: 2; /*Select the external memory block size.*/
uint32_t reserved28: 4; /*reserved*/
};
uint32_t val;
} dma_conf;
@ -397,16 +410,16 @@ typedef volatile struct {
uint32_t data_buf[18]; /*data buffer*/
union {
struct {
uint32_t din0_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din1_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din2_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din3_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t reserved8: 10;
uint32_t din0_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t din1_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t din2_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t din3_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/
uint32_t reserved22: 10; /*reserved*/
uint32_t din0_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din1_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din2_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din3_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din4_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din5_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din6_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din7_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t timing_clk_ena: 1; /*1:enable hclk in spi_timing.v. 0: disable it.*/
uint32_t reserved25: 7; /*reserved*/
};
uint32_t val;
} din_mode;
@ -416,24 +429,25 @@ typedef volatile struct {
uint32_t din1_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din2_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din3_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t reserved8: 24; /*reserved*/
uint32_t din4_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din5_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din6_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din7_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t reserved16:16; /*reserved*/
};
uint32_t val;
} din_num;
union {
struct {
uint32_t dout0_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout1_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout2_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout3_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout4_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t reserved10: 8; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout0_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t dout1_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t dout2_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t dout3_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t dout4_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/
uint32_t reserved23: 9; /*reserved*/
uint32_t dout0_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout1_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout2_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout3_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout4_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout5_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout6_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout7_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t reserved24: 8; /*reserved*/
};
uint32_t val;
} dout_mode;
@ -444,34 +458,63 @@ typedef volatile struct {
uint32_t dout2_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout3_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout4_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t reserved10:22; /*reserved*/
uint32_t dout5_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout6_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dout7_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t reserved16:16; /*reserved*/
};
uint32_t val;
} dout_num;
union {
struct {
uint32_t sop_en: 1;
uint32_t sop_mode: 4;
uint32_t sop_rcmd: 8;
uint32_t sop_wcmd: 8;
uint32_t sop_dqs_edge: 1;
uint32_t reserved22: 10;
uint32_t lcd_hb_front: 11; /*It is the horizontal blank front porch of a frame.*/
uint32_t lcd_va_height: 10; /*It is the vertical active height of a frame.*/
uint32_t lcd_vt_height: 10; /*It is the vertical total height of a frame.*/
uint32_t lcd_srgb_mode_en: 1; /*1: Enable LCD mode output vsync hsync de. 0: Disable.*/
};
uint32_t val;
} spr_cfg0;
} lcd_ctrl;
union {
struct {
uint32_t sop_itl: 12;
uint32_t sop_len: 6;
uint32_t sop_dlen: 6;
uint32_t sop_dc_mode: 1;
uint32_t reserved25: 7;
uint32_t lcd_vb_front: 8; /*It is the vertical blank front porch of a frame.*/
uint32_t lcd_ha_width:12; /*It is the horizontal active width of a frame.*/
uint32_t lcd_ht_width:12; /*It is the horizontal total width of a frame.*/
};
uint32_t val;
} spr_cfg1;
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
} lcd_ctrl1;
union {
struct {
uint32_t lcd_vsync_width: 7; /*It is the position of spi_vsync_out active pulse in a line.*/
uint32_t vsync_idle_pol: 1; /*It is the idle value of spi_vsync_out.*/
uint32_t lcd_vsync_position: 8; /*It is the position of spi_vsync_out active pulse in a line.*/
uint32_t lcd_hsync_width: 7; /*It is the position of spi_hsync_out active pulse in a line.*/
uint32_t hsync_idle_pol: 1; /*It is the idle value of spi_hsync_out.*/
uint32_t lcd_hsync_position: 8; /*It is the position of spi_hsync_out active pulse in a line.*/
};
uint32_t val;
} lcd_ctrl2;
union {
struct {
uint32_t d_dqs_mode: 3; /*the output spi_dqs is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t d_cd_mode: 3; /*the output spi_cd is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t d_de_mode: 3; /*the output spi_de is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t d_hsync_mode: 3; /*the output spi_hsync is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t d_vsync_mode: 3; /*the output spi_vsync is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t reserved15: 17; /*reserved*/
};
uint32_t val;
} lcd_d_mode;
union {
struct {
uint32_t d_dqs_num: 2; /*the output spi_dqs is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t d_cd_num: 2; /*the output spi_cd is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t d_de_num: 2; /*the output spi_de is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t d_hsync_num: 2; /*the output spi_hsync is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t d_vsync_num: 2; /*the output spi_vsync is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t reserved10: 22; /*reserved*/
};
uint32_t val;
} lcd_d_num;
uint32_t reserved_110;
uint32_t reserved_114;
uint32_t reserved_118;
@ -669,7 +712,6 @@ typedef volatile struct {
} spi_dev_t;
extern spi_dev_t GPSPI2; //FSPI
extern spi_dev_t GPSPI3; //HSPI
extern spi_dev_t GPSPI4; //VSPI
_Static_assert(sizeof(spi_dev_t)==0x400, "***invalid spi");

474
components/soc/esp32s2beta/include/soc/syscon_reg.h
View File

@ -20,16 +20,6 @@ extern "C" {
#endif
#include "soc.h"
#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x000)
/* SYSCON_SOC_CLK_SEL : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
/*description: */
#define SYSCON_SOC_CLK_SEL 0x00000003
#define SYSCON_SOC_CLK_SEL_M ((SYSCON_SOC_CLK_SEL_V)<<(SYSCON_SOC_CLK_SEL_S))
#define SYSCON_SOC_CLK_SEL_V 0x3
#define SYSCON_SOC_CLK_SEL_S 14
#define SYSCON_SOC_CLK_SEL_XTL 0
#define SYSCON_SOC_CLK_SEL_PLL 1
#define SYSCON_SOC_CLK_SEL_8M 2
#define SYSCON_SOC_CLK_SEL_APLL 3
/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: */
#define SYSCON_RST_TICK_CNT (BIT(12))
@ -48,12 +38,6 @@ extern "C" {
#define SYSCON_CLK_320M_EN_M (BIT(10))
#define SYSCON_CLK_320M_EN_V 0x1
#define SYSCON_CLK_320M_EN_S 10
/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
/*description: */
#define SYSCON_PRE_DIV_CNT 0x000003FF
#define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S))
#define SYSCON_PRE_DIV_CNT_V 0x3FF
#define SYSCON_PRE_DIV_CNT_S 0
#define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x004)
/* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
@ -75,297 +59,7 @@ extern "C" {
#define SYSCON_XTAL_TICK_NUM_V 0xFF
#define SYSCON_XTAL_TICK_NUM_S 0
#define SYSCON_SARADC_CTRL_REG (DR_REG_SYSCON_BASE + 0x008)
/* SYSCON_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
/*description: force option to xpd sar blocks*/
#define SYSCON_SARADC_XPD_SAR_FORCE 0x00000003
#define SYSCON_SARADC_XPD_SAR_FORCE_M ((SYSCON_SARADC_XPD_SAR_FORCE_V)<<(SYSCON_SARADC_XPD_SAR_FORCE_S))
#define SYSCON_SARADC_XPD_SAR_FORCE_V 0x3
#define SYSCON_SARADC_XPD_SAR_FORCE_S 27
/* SYSCON_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data
is from GPIO matrix*/
#define SYSCON_SARADC_DATA_TO_I2S (BIT(26))
#define SYSCON_SARADC_DATA_TO_I2S_M (BIT(26))
#define SYSCON_SARADC_DATA_TO_I2S_V 0x1
#define SYSCON_SARADC_DATA_TO_I2S_S 26
/* SYSCON_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data
in this case the resolution should not be larger than 11 bits.*/
#define SYSCON_SARADC_DATA_SAR_SEL (BIT(25))
#define SYSCON_SARADC_DATA_SAR_SEL_M (BIT(25))
#define SYSCON_SARADC_DATA_SAR_SEL_V 0x1
#define SYSCON_SARADC_DATA_SAR_SEL_S 25
/* SYSCON_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */
/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/
#define SYSCON_SARADC_SAR2_PATT_P_CLEAR (BIT(24))
#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24))
#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_V 0x1
#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_S 24
/* SYSCON_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/
#define SYSCON_SARADC_SAR1_PATT_P_CLEAR (BIT(23))
#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23))
#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_V 0x1
#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_S 23
/* SYSCON_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */
/*description: 0 ~ 15 means length 1 ~ 16*/
#define SYSCON_SARADC_SAR2_PATT_LEN 0x0000000F
#define SYSCON_SARADC_SAR2_PATT_LEN_M ((SYSCON_SARADC_SAR2_PATT_LEN_V)<<(SYSCON_SARADC_SAR2_PATT_LEN_S))
#define SYSCON_SARADC_SAR2_PATT_LEN_V 0xF
#define SYSCON_SARADC_SAR2_PATT_LEN_S 19
/* SYSCON_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */
/*description: 0 ~ 15 means length 1 ~ 16*/
#define SYSCON_SARADC_SAR1_PATT_LEN 0x0000000F
#define SYSCON_SARADC_SAR1_PATT_LEN_M ((SYSCON_SARADC_SAR1_PATT_LEN_V)<<(SYSCON_SARADC_SAR1_PATT_LEN_S))
#define SYSCON_SARADC_SAR1_PATT_LEN_V 0xF
#define SYSCON_SARADC_SAR1_PATT_LEN_S 15
/* SYSCON_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
/*description: SAR clock divider*/
#define SYSCON_SARADC_SAR_CLK_DIV 0x000000FF
#define SYSCON_SARADC_SAR_CLK_DIV_M ((SYSCON_SARADC_SAR_CLK_DIV_V)<<(SYSCON_SARADC_SAR_CLK_DIV_S))
#define SYSCON_SARADC_SAR_CLK_DIV_V 0xFF
#define SYSCON_SARADC_SAR_CLK_DIV_S 7
/* SYSCON_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
#define SYSCON_SARADC_SAR_CLK_GATED (BIT(6))
#define SYSCON_SARADC_SAR_CLK_GATED_M (BIT(6))
#define SYSCON_SARADC_SAR_CLK_GATED_V 0x1
#define SYSCON_SARADC_SAR_CLK_GATED_S 6
/* SYSCON_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */
/*description: 0: SAR1 1: SAR2 only work for single SAR mode*/
#define SYSCON_SARADC_SAR_SEL (BIT(5))
#define SYSCON_SARADC_SAR_SEL_M (BIT(5))
#define SYSCON_SARADC_SAR_SEL_V 0x1
#define SYSCON_SARADC_SAR_SEL_S 5
/* SYSCON_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
/*description: 0: single mode 1: double mode 2: alternate mode*/
#define SYSCON_SARADC_WORK_MODE 0x00000003
#define SYSCON_SARADC_WORK_MODE_M ((SYSCON_SARADC_WORK_MODE_V)<<(SYSCON_SARADC_WORK_MODE_S))
#define SYSCON_SARADC_WORK_MODE_V 0x3
#define SYSCON_SARADC_WORK_MODE_S 3
/* SYSCON_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
/*description: */
#define SYSCON_SARADC_START (BIT(1))
#define SYSCON_SARADC_START_M (BIT(1))
#define SYSCON_SARADC_START_V 0x1
#define SYSCON_SARADC_START_S 1
/* SYSCON_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
#define SYSCON_SARADC_START_FORCE (BIT(0))
#define SYSCON_SARADC_START_FORCE_M (BIT(0))
#define SYSCON_SARADC_START_FORCE_V 0x1
#define SYSCON_SARADC_START_FORCE_S 0
#define SYSCON_SARADC_CTRL2_REG (DR_REG_SYSCON_BASE + 0x00C)
/* SYSCON_SARADC_TIMER_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
/*description: to enable saradc timer trigger*/
#define SYSCON_SARADC_TIMER_EN (BIT(20))
#define SYSCON_SARADC_TIMER_EN_M (BIT(20))
#define SYSCON_SARADC_TIMER_EN_V 0x1
#define SYSCON_SARADC_TIMER_EN_S 20
/* SYSCON_SARADC_TIMER_TARGET : R/W ;bitpos:[19:12] ;default: 8'd10 ; */
/*description: to set saradc timer target*/
#define SYSCON_SARADC_TIMER_TARGET 0x000000FF
#define SYSCON_SARADC_TIMER_TARGET_M ((SYSCON_SARADC_TIMER_TARGET_V)<<(SYSCON_SARADC_TIMER_TARGET_S))
#define SYSCON_SARADC_TIMER_TARGET_V 0xFF
#define SYSCON_SARADC_TIMER_TARGET_S 12
/* SYSCON_SARADC_TIMER_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
/*description: 1: select saradc timer 0: i2s_ws trigger*/
#define SYSCON_SARADC_TIMER_SEL (BIT(11))
#define SYSCON_SARADC_TIMER_SEL_M (BIT(11))
#define SYSCON_SARADC_TIMER_SEL_V 0x1
#define SYSCON_SARADC_TIMER_SEL_S 11
/* SYSCON_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/
#define SYSCON_SARADC_SAR2_INV (BIT(10))
#define SYSCON_SARADC_SAR2_INV_M (BIT(10))
#define SYSCON_SARADC_SAR2_INV_V 0x1
#define SYSCON_SARADC_SAR2_INV_S 10
/* SYSCON_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/
#define SYSCON_SARADC_SAR1_INV (BIT(9))
#define SYSCON_SARADC_SAR1_INV_M (BIT(9))
#define SYSCON_SARADC_SAR1_INV_V 0x1
#define SYSCON_SARADC_SAR1_INV_S 9
/* SYSCON_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
/*description: max conversion number*/
#define SYSCON_SARADC_MAX_MEAS_NUM 0x000000FF
#define SYSCON_SARADC_MAX_MEAS_NUM_M ((SYSCON_SARADC_MAX_MEAS_NUM_V)<<(SYSCON_SARADC_MAX_MEAS_NUM_S))
#define SYSCON_SARADC_MAX_MEAS_NUM_V 0xFF
#define SYSCON_SARADC_MAX_MEAS_NUM_S 1
/* SYSCON_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
#define SYSCON_SARADC_MEAS_NUM_LIMIT (BIT(0))
#define SYSCON_SARADC_MEAS_NUM_LIMIT_M (BIT(0))
#define SYSCON_SARADC_MEAS_NUM_LIMIT_V 0x1
#define SYSCON_SARADC_MEAS_NUM_LIMIT_S 0
#define SYSCON_SARADC_FSM_REG (DR_REG_SYSCON_BASE + 0x010)
/* SYSCON_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */
/*description: sample cycles*/
#define SYSCON_SARADC_SAMPLE_CYCLE 0x000000FF
#define SYSCON_SARADC_SAMPLE_CYCLE_M ((SYSCON_SARADC_SAMPLE_CYCLE_V)<<(SYSCON_SARADC_SAMPLE_CYCLE_S))
#define SYSCON_SARADC_SAMPLE_CYCLE_V 0xFF
#define SYSCON_SARADC_SAMPLE_CYCLE_S 24
/* SYSCON_SARADC_SAMPLE_NUM : R/W ;bitpos:[23:16] ;default: 8'd0 ; */
/*description: sample number*/
#define SYSCON_SARADC_SAMPLE_NUM 0x000000FF
#define SYSCON_SARADC_SAMPLE_NUM_M ((SYSCON_SARADC_SAMPLE_NUM_V)<<(SYSCON_SARADC_SAMPLE_NUM_S))
#define SYSCON_SARADC_SAMPLE_NUM_V 0xFF
#define SYSCON_SARADC_SAMPLE_NUM_S 16
#define SYSCON_SARADC_FSM_WAIT_REG (DR_REG_SYSCON_BASE + 0x014)
/* SYSCON_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
/*description: */
#define SYSCON_SARADC_STANDBY_WAIT 0x000000FF
#define SYSCON_SARADC_STANDBY_WAIT_M ((SYSCON_SARADC_STANDBY_WAIT_V)<<(SYSCON_SARADC_STANDBY_WAIT_S))
#define SYSCON_SARADC_STANDBY_WAIT_V 0xFF
#define SYSCON_SARADC_STANDBY_WAIT_S 16
/* SYSCON_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
/*description: */
#define SYSCON_SARADC_RSTB_WAIT 0x000000FF
#define SYSCON_SARADC_RSTB_WAIT_M ((SYSCON_SARADC_RSTB_WAIT_V)<<(SYSCON_SARADC_RSTB_WAIT_S))
#define SYSCON_SARADC_RSTB_WAIT_V 0xFF
#define SYSCON_SARADC_RSTB_WAIT_S 8
/* SYSCON_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
/*description: */
#define SYSCON_SARADC_XPD_WAIT 0x000000FF
#define SYSCON_SARADC_XPD_WAIT_M ((SYSCON_SARADC_XPD_WAIT_V)<<(SYSCON_SARADC_XPD_WAIT_S))
#define SYSCON_SARADC_XPD_WAIT_V 0xFF
#define SYSCON_SARADC_XPD_WAIT_S 0
#define SYSCON_SARADC_SAR1_STATUS_REG (DR_REG_SYSCON_BASE + 0x018)
/* SYSCON_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define SYSCON_SARADC_SAR1_STATUS 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_STATUS_M ((SYSCON_SARADC_SAR1_STATUS_V)<<(SYSCON_SARADC_SAR1_STATUS_S))
#define SYSCON_SARADC_SAR1_STATUS_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_STATUS_S 0
#define SYSCON_SARADC_SAR2_STATUS_REG (DR_REG_SYSCON_BASE + 0x01C)
/* SYSCON_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define SYSCON_SARADC_SAR2_STATUS 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_STATUS_M ((SYSCON_SARADC_SAR2_STATUS_V)<<(SYSCON_SARADC_SAR2_STATUS_S))
#define SYSCON_SARADC_SAR2_STATUS_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_STATUS_S 0
#define SYSCON_SARADC_SAR1_PATT_TAB1_REG (DR_REG_SYSCON_BASE + 0x020)
/* SYSCON_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/
#define SYSCON_SARADC_SAR1_PATT_TAB1 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB1_M ((SYSCON_SARADC_SAR1_PATT_TAB1_V)<<(SYSCON_SARADC_SAR1_PATT_TAB1_S))
#define SYSCON_SARADC_SAR1_PATT_TAB1_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB1_S 0
#define SYSCON_SARADC_SAR1_PATT_TAB2_REG (DR_REG_SYSCON_BASE + 0x024)
/* SYSCON_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/
#define SYSCON_SARADC_SAR1_PATT_TAB2 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB2_M ((SYSCON_SARADC_SAR1_PATT_TAB2_V)<<(SYSCON_SARADC_SAR1_PATT_TAB2_S))
#define SYSCON_SARADC_SAR1_PATT_TAB2_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB2_S 0
#define SYSCON_SARADC_SAR1_PATT_TAB3_REG (DR_REG_SYSCON_BASE + 0x028)
/* SYSCON_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/
#define SYSCON_SARADC_SAR1_PATT_TAB3 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB3_M ((SYSCON_SARADC_SAR1_PATT_TAB3_V)<<(SYSCON_SARADC_SAR1_PATT_TAB3_S))
#define SYSCON_SARADC_SAR1_PATT_TAB3_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB3_S 0
#define SYSCON_SARADC_SAR1_PATT_TAB4_REG (DR_REG_SYSCON_BASE + 0x02C)
/* SYSCON_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/
#define SYSCON_SARADC_SAR1_PATT_TAB4 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB4_M ((SYSCON_SARADC_SAR1_PATT_TAB4_V)<<(SYSCON_SARADC_SAR1_PATT_TAB4_S))
#define SYSCON_SARADC_SAR1_PATT_TAB4_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR1_PATT_TAB4_S 0
#define SYSCON_SARADC_SAR2_PATT_TAB1_REG (DR_REG_SYSCON_BASE + 0x030)
/* SYSCON_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/
#define SYSCON_SARADC_SAR2_PATT_TAB1 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB1_M ((SYSCON_SARADC_SAR2_PATT_TAB1_V)<<(SYSCON_SARADC_SAR2_PATT_TAB1_S))
#define SYSCON_SARADC_SAR2_PATT_TAB1_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB1_S 0
#define SYSCON_SARADC_SAR2_PATT_TAB2_REG (DR_REG_SYSCON_BASE + 0x034)
/* SYSCON_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/
#define SYSCON_SARADC_SAR2_PATT_TAB2 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB2_M ((SYSCON_SARADC_SAR2_PATT_TAB2_V)<<(SYSCON_SARADC_SAR2_PATT_TAB2_S))
#define SYSCON_SARADC_SAR2_PATT_TAB2_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB2_S 0
#define SYSCON_SARADC_SAR2_PATT_TAB3_REG (DR_REG_SYSCON_BASE + 0x038)
/* SYSCON_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/
#define SYSCON_SARADC_SAR2_PATT_TAB3 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB3_M ((SYSCON_SARADC_SAR2_PATT_TAB3_V)<<(SYSCON_SARADC_SAR2_PATT_TAB3_S))
#define SYSCON_SARADC_SAR2_PATT_TAB3_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB3_S 0
#define SYSCON_SARADC_SAR2_PATT_TAB4_REG (DR_REG_SYSCON_BASE + 0x03C)
/* SYSCON_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/
#define SYSCON_SARADC_SAR2_PATT_TAB4 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB4_M ((SYSCON_SARADC_SAR2_PATT_TAB4_V)<<(SYSCON_SARADC_SAR2_PATT_TAB4_S))
#define SYSCON_SARADC_SAR2_PATT_TAB4_V 0xFFFFFFFF
#define SYSCON_SARADC_SAR2_PATT_TAB4_S 0
#define SYSCON_ADC_ARB_CTRL_REG (DR_REG_SYSCON_BASE + 0x040)
/* SYSCON_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: adc2 arbiter uses fixed priority*/
#define SYSCON_ADC_ARB_FIX_PRIORITY (BIT(12))
#define SYSCON_ADC_ARB_FIX_PRIORITY_M (BIT(12))
#define SYSCON_ADC_ARB_FIX_PRIORITY_V 0x1
#define SYSCON_ADC_ARB_FIX_PRIORITY_S 12
/* SYSCON_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */
/*description: Set adc2 arbiter wifi priority*/
#define SYSCON_ADC_ARB_WIFI_PRIORITY 0x00000003
#define SYSCON_ADC_ARB_WIFI_PRIORITY_M ((SYSCON_ADC_ARB_WIFI_PRIORITY_V)<<(SYSCON_ADC_ARB_WIFI_PRIORITY_S))
#define SYSCON_ADC_ARB_WIFI_PRIORITY_V 0x3
#define SYSCON_ADC_ARB_WIFI_PRIORITY_S 10
/* SYSCON_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */
/*description: Set adc2 arbiter rtc priority*/
#define SYSCON_ADC_ARB_RTC_PRIORITY 0x00000003
#define SYSCON_ADC_ARB_RTC_PRIORITY_M ((SYSCON_ADC_ARB_RTC_PRIORITY_V)<<(SYSCON_ADC_ARB_RTC_PRIORITY_S))
#define SYSCON_ADC_ARB_RTC_PRIORITY_V 0x3
#define SYSCON_ADC_ARB_RTC_PRIORITY_S 8
/* SYSCON_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
/*description: Set adc2 arbiter apb priority*/
#define SYSCON_ADC_ARB_APB_PRIORITY 0x00000003
#define SYSCON_ADC_ARB_APB_PRIORITY_M ((SYSCON_ADC_ARB_APB_PRIORITY_V)<<(SYSCON_ADC_ARB_APB_PRIORITY_S))
#define SYSCON_ADC_ARB_APB_PRIORITY_V 0x3
#define SYSCON_ADC_ARB_APB_PRIORITY_S 6
/* SYSCON_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: adc2 arbiter force grant*/
#define SYSCON_ADC_ARB_GRANT_FORCE (BIT(5))
#define SYSCON_ADC_ARB_GRANT_FORCE_M (BIT(5))
#define SYSCON_ADC_ARB_GRANT_FORCE_V 0x1
#define SYSCON_ADC_ARB_GRANT_FORCE_S 5
/* SYSCON_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enable wifi controller*/
#define SYSCON_ADC_ARB_WIFI_FORCE (BIT(4))
#define SYSCON_ADC_ARB_WIFI_FORCE_M (BIT(4))
#define SYSCON_ADC_ARB_WIFI_FORCE_V 0x1
#define SYSCON_ADC_ARB_WIFI_FORCE_S 4
/* SYSCON_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enable rtc controller*/
#define SYSCON_ADC_ARB_RTC_FORCE (BIT(3))
#define SYSCON_ADC_ARB_RTC_FORCE_M (BIT(3))
#define SYSCON_ADC_ARB_RTC_FORCE_V 0x1
#define SYSCON_ADC_ARB_RTC_FORCE_S 3
/* SYSCON_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enableapb controller*/
#define SYSCON_ADC_ARB_APB_FORCE (BIT(2))
#define SYSCON_ADC_ARB_APB_FORCE_M (BIT(2))
#define SYSCON_ADC_ARB_APB_FORCE_V 0x1
#define SYSCON_ADC_ARB_APB_FORCE_S 2
#define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x044)
#define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x008)
/* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK_XTAL_OEN (BIT(10))
@ -433,25 +127,7 @@ extern "C" {
#define SYSCON_CLK20_OEN_V 0x1
#define SYSCON_CLK20_OEN_S 0
#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x048)
/* SYSCON_SPI_PRIOR : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: */
#define SYSCON_SPI_PRIOR (BIT(13))
#define SYSCON_SPI_PRIOR_M (BIT(13))
#define SYSCON_SPI_PRIOR_V 0x1
#define SYSCON_SPI_PRIOR_S 13
/* SYSCON_SPI1_HOLD : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: */
#define SYSCON_SPI1_HOLD (BIT(9))
#define SYSCON_SPI1_HOLD_M (BIT(9))
#define SYSCON_SPI1_HOLD_V 0x1
#define SYSCON_SPI1_HOLD_S 9
/* SYSCON_SPI0_HOLD : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
#define SYSCON_SPI0_HOLD (BIT(8))
#define SYSCON_SPI0_HOLD_M (BIT(8))
#define SYSCON_SPI0_HOLD_V 0x1
#define SYSCON_SPI0_HOLD_S 8
#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x00C)
/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
#define SYSCON_PERI_IO_SWAP 0x000000FF
@ -459,7 +135,7 @@ extern "C" {
#define SYSCON_PERI_IO_SWAP_V 0xFF
#define SYSCON_PERI_IO_SWAP_S 0
#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x04C)
#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x010)
/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define SYSCON_EXT_MEM_PMS_LOCK (BIT(0))
@ -467,7 +143,7 @@ extern "C" {
#define SYSCON_EXT_MEM_PMS_LOCK_V 0x1
#define SYSCON_EXT_MEM_PMS_LOCK_S 0
#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x050)
#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x014)
/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define SYSCON_FLASH_ACE0_ATTR 0x00000007
@ -475,7 +151,7 @@ extern "C" {
#define SYSCON_FLASH_ACE0_ATTR_V 0x7
#define SYSCON_FLASH_ACE0_ATTR_S 0
#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x054)
#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x018)
/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define SYSCON_FLASH_ACE1_ATTR 0x00000007
@ -483,7 +159,7 @@ extern "C" {
#define SYSCON_FLASH_ACE1_ATTR_V 0x7
#define SYSCON_FLASH_ACE1_ATTR_S 0
#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x058)
#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x01C)
/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define SYSCON_FLASH_ACE2_ATTR 0x00000007
@ -491,7 +167,7 @@ extern "C" {
#define SYSCON_FLASH_ACE2_ATTR_V 0x7
#define SYSCON_FLASH_ACE2_ATTR_S 0
#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x05C)
#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x020)
/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define SYSCON_FLASH_ACE3_ATTR 0x00000007
@ -499,7 +175,7 @@ extern "C" {
#define SYSCON_FLASH_ACE3_ATTR_V 0x7
#define SYSCON_FLASH_ACE3_ATTR_S 0
#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x060)
#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x024)
/* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF
@ -507,7 +183,7 @@ extern "C" {
#define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE0_ADDR_S_S 0
#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x064)
#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x028)
/* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
/*description: */
#define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFF
@ -515,7 +191,7 @@ extern "C" {
#define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE1_ADDR_S_S 0
#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x068)
#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x02C)
/* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
/*description: */
#define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF
@ -523,7 +199,7 @@ extern "C" {
#define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE2_ADDR_S_S 0
#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x06C)
#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x030)
/* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
/*description: */
#define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF
@ -531,7 +207,7 @@ extern "C" {
#define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE3_ADDR_S_S 0
#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x070)
#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x034)
/* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_FLASH_ACE0_SIZE 0x0000FFFF
@ -539,7 +215,7 @@ extern "C" {
#define SYSCON_FLASH_ACE0_SIZE_V 0xFFFF
#define SYSCON_FLASH_ACE0_SIZE_S 0
#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x074)
#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x038)
/* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_FLASH_ACE1_SIZE 0x0000FFFF
@ -547,7 +223,7 @@ extern "C" {
#define SYSCON_FLASH_ACE1_SIZE_V 0xFFFF
#define SYSCON_FLASH_ACE1_SIZE_S 0
#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x078)
#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x03C)
/* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_FLASH_ACE2_SIZE 0x0000FFFF
@ -555,7 +231,7 @@ extern "C" {
#define SYSCON_FLASH_ACE2_SIZE_V 0xFFFF
#define SYSCON_FLASH_ACE2_SIZE_S 0
#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x07C)
#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x040)
/* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_FLASH_ACE3_SIZE 0x0000FFFF
@ -563,7 +239,7 @@ extern "C" {
#define SYSCON_FLASH_ACE3_SIZE_V 0xFFFF
#define SYSCON_FLASH_ACE3_SIZE_S 0
#define SYSCON_SRAM_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x080)
#define SYSCON_SRAM_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x044)
/* SYSCON_SRAM_ACE0_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define SYSCON_SRAM_ACE0_ATTR 0x00000007
@ -571,7 +247,7 @@ extern "C" {
#define SYSCON_SRAM_ACE0_ATTR_V 0x7
#define SYSCON_SRAM_ACE0_ATTR_S 0
#define SYSCON_SRAM_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x084)
#define SYSCON_SRAM_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x048)
/* SYSCON_SRAM_ACE1_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define SYSCON_SRAM_ACE1_ATTR 0x00000007
@ -579,7 +255,7 @@ extern "C" {
#define SYSCON_SRAM_ACE1_ATTR_V 0x7
#define SYSCON_SRAM_ACE1_ATTR_S 0
#define SYSCON_SRAM_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x088)
#define SYSCON_SRAM_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x04C)
/* SYSCON_SRAM_ACE2_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define SYSCON_SRAM_ACE2_ATTR 0x00000007
@ -587,7 +263,7 @@ extern "C" {
#define SYSCON_SRAM_ACE2_ATTR_V 0x7
#define SYSCON_SRAM_ACE2_ATTR_S 0
#define SYSCON_SRAM_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x08C)
#define SYSCON_SRAM_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x050)
/* SYSCON_SRAM_ACE3_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
/*description: */
#define SYSCON_SRAM_ACE3_ATTR 0x00000007
@ -595,7 +271,7 @@ extern "C" {
#define SYSCON_SRAM_ACE3_ATTR_V 0x7
#define SYSCON_SRAM_ACE3_ATTR_S 0
#define SYSCON_SRAM_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x090)
#define SYSCON_SRAM_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x054)
/* SYSCON_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_SRAM_ACE0_ADDR_S 0xFFFFFFFF
@ -603,7 +279,7 @@ extern "C" {
#define SYSCON_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF
#define SYSCON_SRAM_ACE0_ADDR_S_S 0
#define SYSCON_SRAM_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x094)
#define SYSCON_SRAM_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x058)
/* SYSCON_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
/*description: */
#define SYSCON_SRAM_ACE1_ADDR_S 0xFFFFFFFF
@ -611,7 +287,7 @@ extern "C" {
#define SYSCON_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF
#define SYSCON_SRAM_ACE1_ADDR_S_S 0
#define SYSCON_SRAM_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x098)
#define SYSCON_SRAM_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x05C)
/* SYSCON_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
/*description: */
#define SYSCON_SRAM_ACE2_ADDR_S 0xFFFFFFFF
@ -619,7 +295,7 @@ extern "C" {
#define SYSCON_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF
#define SYSCON_SRAM_ACE2_ADDR_S_S 0
#define SYSCON_SRAM_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x09C)
#define SYSCON_SRAM_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x060)
/* SYSCON_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
/*description: */
#define SYSCON_SRAM_ACE3_ADDR_S 0xFFFFFFFF
@ -627,7 +303,7 @@ extern "C" {
#define SYSCON_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF
#define SYSCON_SRAM_ACE3_ADDR_S_S 0
#define SYSCON_SRAM_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x0A0)
#define SYSCON_SRAM_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x064)
/* SYSCON_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_SRAM_ACE0_SIZE 0x0000FFFF
@ -635,7 +311,7 @@ extern "C" {
#define SYSCON_SRAM_ACE0_SIZE_V 0xFFFF
#define SYSCON_SRAM_ACE0_SIZE_S 0
#define SYSCON_SRAM_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x0A4)
#define SYSCON_SRAM_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x068)
/* SYSCON_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_SRAM_ACE1_SIZE 0x0000FFFF
@ -643,7 +319,7 @@ extern "C" {
#define SYSCON_SRAM_ACE1_SIZE_V 0xFFFF
#define SYSCON_SRAM_ACE1_SIZE_S 0
#define SYSCON_SRAM_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x0A8)
#define SYSCON_SRAM_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x06C)
/* SYSCON_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_SRAM_ACE2_SIZE 0x0000FFFF
@ -651,7 +327,7 @@ extern "C" {
#define SYSCON_SRAM_ACE2_SIZE_V 0xFFFF
#define SYSCON_SRAM_ACE2_SIZE_S 0
#define SYSCON_SRAM_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x0AC)
#define SYSCON_SRAM_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x070)
/* SYSCON_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_SRAM_ACE3_SIZE 0x0000FFFF
@ -659,63 +335,35 @@ extern "C" {
#define SYSCON_SRAM_ACE3_SIZE_V 0xFFFF
#define SYSCON_SRAM_ACE3_SIZE_S 0
#define SYSCON_SPI0_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x0B0)
/* SYSCON_SPI0_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
#define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x074)
/* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
/*description: */
#define SYSCON_SPI0_REJECT_CDE 0x0000001F
#define SYSCON_SPI0_REJECT_CDE_M ((SYSCON_SPI0_REJECT_CDE_V)<<(SYSCON_SPI0_REJECT_CDE_S))
#define SYSCON_SPI0_REJECT_CDE_V 0x1F
#define SYSCON_SPI0_REJECT_CDE_S 2
/* SYSCON_SPI0_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
#define SYSCON_SPI_MEM_REJECT_CDE 0x0000001F
#define SYSCON_SPI_MEM_REJECT_CDE_M ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S))
#define SYSCON_SPI_MEM_REJECT_CDE_V 0x1F
#define SYSCON_SPI_MEM_REJECT_CDE_S 2
/* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define SYSCON_SPI0_REJECT_CLR (BIT(1))
#define SYSCON_SPI0_REJECT_CLR_M (BIT(1))
#define SYSCON_SPI0_REJECT_CLR_V 0x1
#define SYSCON_SPI0_REJECT_CLR_S 1
/* SYSCON_SPI0_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
#define SYSCON_SPI_MEM_REJECT_CLR (BIT(1))
#define SYSCON_SPI_MEM_REJECT_CLR_M (BIT(1))
#define SYSCON_SPI_MEM_REJECT_CLR_V 0x1
#define SYSCON_SPI_MEM_REJECT_CLR_S 1
/* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define SYSCON_SPI0_REJECT_INT (BIT(0))
#define SYSCON_SPI0_REJECT_INT_M (BIT(0))
#define SYSCON_SPI0_REJECT_INT_V 0x1
#define SYSCON_SPI0_REJECT_INT_S 0
#define SYSCON_SPI_MEM_REJECT_INT (BIT(0))
#define SYSCON_SPI_MEM_REJECT_INT_M (BIT(0))
#define SYSCON_SPI_MEM_REJECT_INT_V 0x1
#define SYSCON_SPI_MEM_REJECT_INT_S 0
#define SYSCON_SPI0_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x0B4)
/* SYSCON_SPI0_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
#define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x078)
/* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_SPI0_REJECT_ADDR 0xFFFFFFFF
#define SYSCON_SPI0_REJECT_ADDR_M ((SYSCON_SPI0_REJECT_ADDR_V)<<(SYSCON_SPI0_REJECT_ADDR_S))
#define SYSCON_SPI0_REJECT_ADDR_V 0xFFFFFFFF
#define SYSCON_SPI0_REJECT_ADDR_S 0
#define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFF
#define SYSCON_SPI_MEM_REJECT_ADDR_M ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S))
#define SYSCON_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF
#define SYSCON_SPI_MEM_REJECT_ADDR_S 0
#define SYSCON_SPI1_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x0B8)
/* SYSCON_SPI1_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
/*description: */
#define SYSCON_SPI1_REJECT_CDE 0x0000001F
#define SYSCON_SPI1_REJECT_CDE_M ((SYSCON_SPI1_REJECT_CDE_V)<<(SYSCON_SPI1_REJECT_CDE_S))
#define SYSCON_SPI1_REJECT_CDE_V 0x1F
#define SYSCON_SPI1_REJECT_CDE_S 2
/* SYSCON_SPI1_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define SYSCON_SPI1_REJECT_CLR (BIT(1))
#define SYSCON_SPI1_REJECT_CLR_M (BIT(1))
#define SYSCON_SPI1_REJECT_CLR_V 0x1
#define SYSCON_SPI1_REJECT_CLR_S 1
/* SYSCON_SPI1_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define SYSCON_SPI1_REJECT_INT (BIT(0))
#define SYSCON_SPI1_REJECT_INT_M (BIT(0))
#define SYSCON_SPI1_REJECT_INT_V 0x1
#define SYSCON_SPI1_REJECT_INT_S 0
#define SYSCON_SPI1_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x0BC)
/* SYSCON_SPI1_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_SPI1_REJECT_ADDR 0xFFFFFFFF
#define SYSCON_SPI1_REJECT_ADDR_M ((SYSCON_SPI1_REJECT_ADDR_V)<<(SYSCON_SPI1_REJECT_ADDR_S))
#define SYSCON_SPI1_REJECT_ADDR_V 0xFFFFFFFF
#define SYSCON_SPI1_REJECT_ADDR_S 0
#define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x0C0)
#define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x07C)
/* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0))
@ -723,7 +371,7 @@ extern "C" {
#define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1
#define SYSCON_SDIO_WIN_ACCESS_EN_S 0
#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x0C4)
#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x080)
/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define SYSCON_REDCY_ANDOR (BIT(31))
@ -737,7 +385,7 @@ extern "C" {
#define SYSCON_REDCY_SIG0_V 0x7FFFFFFF
#define SYSCON_REDCY_SIG0_S 0
#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x0C8)
#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x084)
/* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define SYSCON_REDCY_NANDOR (BIT(31))
@ -751,7 +399,7 @@ extern "C" {
#define SYSCON_REDCY_SIG1_V 0x7FFFFFFF
#define SYSCON_REDCY_SIG1_S 0
#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0x0CC)
#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0x088)
/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_WIFI_BB_CFG 0xFFFFFFFF
@ -759,7 +407,7 @@ extern "C" {
#define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF
#define SYSCON_WIFI_BB_CFG_S 0
#define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x0D0)
#define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x08C)
/* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFF
@ -767,7 +415,7 @@ extern "C" {
#define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFF
#define SYSCON_WIFI_BB_CFG_2_S 0
#define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x0D4)
#define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x090)
/* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
/*description: */
#define SYSCON_WIFI_CLK_EN 0xFFFFFFFF
@ -775,7 +423,7 @@ extern "C" {
#define SYSCON_WIFI_CLK_EN_V 0xFFFFFFFF
#define SYSCON_WIFI_CLK_EN_S 0
#define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x0D8)
#define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x094)
/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_WIFI_RST 0xFFFFFFFF
@ -793,9 +441,9 @@ extern "C" {
/* Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15, 19, 20, 21
Bit15 not included here because of the bit now can't be cleared */
#define DPORT_WIFI_CLK_WIFI_EN 0x00008040
#define DPORT_WIFI_CLK_WIFI_EN 0x003807cf
#define DPORT_WIFI_CLK_WIFI_EN_M ((DPORT_WIFI_CLK_WIFI_EN_V)<<(DPORT_WIFI_CLK_WIFI_EN_S))
#define DPORT_WIFI_CLK_WIFI_EN_V 0x0804
#define DPORT_WIFI_CLK_WIFI_EN_V 0x7cf
#define DPORT_WIFI_CLK_WIFI_EN_S 0
/* Mask for all Bluetooth clock bits - 11, 16, 17 */
#define DPORT_WIFI_CLK_BT_EN 0x61
@ -803,7 +451,7 @@ extern "C" {
#define DPORT_WIFI_CLK_BT_EN_V 0x61
#define DPORT_WIFI_CLK_BT_EN_S 11
/* Mask for clock bits used by both WIFI and Bluetooth, bit 0, 3, 6, 7, 8, 9 */
#define DPORT_WIFI_CLK_WIFI_BT_COMMON_M 0x0038078f
#define DPORT_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9
/* Digital team to check */
//bluetooth baseband bit11
@ -839,7 +487,7 @@ extern "C" {
#define DPORT_FE_RST (BIT(1))
#define DPORT_BB_RST (BIT(0))
#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x0DC)
#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x098)
/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define SYSCON_DC_MEM_FORCE_PD (BIT(5))
@ -878,7 +526,7 @@ extern "C" {
#define SYSCON_AGC_MEM_FORCE_PU_S 0
#define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC)
/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h18102500 ; */
/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h1907010 ; */
/*description: */
#define SYSCON_DATE 0xFFFFFFFF
#define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S))

127
components/soc/esp32s2beta/include/soc/syscon_struct.h
View File

@ -1,9 +1,9 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
@ -13,7 +13,6 @@
// limitations under the License.
#ifndef _SOC_SYSCON_STRUCT_H_
#define _SOC_SYSCON_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
@ -30,7 +29,7 @@ typedef volatile struct {
uint32_t reserved16: 16;
};
uint32_t val;
} clk_conf;
} apb_ctrl_sysclk_conf;
union {
struct {
uint32_t xtal_tick: 8;
@ -39,76 +38,7 @@ typedef volatile struct {
uint32_t reserved17: 15;
};
uint32_t val;
} tick_conf;
union {
struct {
uint32_t start_force: 1;
uint32_t start: 1;
uint32_t reserved2: 1;
uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/
uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/
uint32_t sar_clk_gated: 1;
uint32_t sar_clk_div: 8; /*SAR clock divider*/
uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/
uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/
uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/
uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/
uint32_t xpd_sar_force: 2; /*force option to xpd sar blocks*/
uint32_t reserved29: 3;
};
uint32_t val;
} saradc_ctrl;
union {
struct {
uint32_t meas_num_limit: 1;
uint32_t max_meas_num: 8; /*max conversion number*/
uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/
uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/
uint32_t timer_sel: 1; /*1: select saradc timer 0: i2s_ws trigger*/
uint32_t timer_target: 8; /*to set saradc timer target*/
uint32_t timer_en: 1; /*to enable saradc timer trigger*/
uint32_t reserved21: 11;
};
uint32_t val;
} saradc_ctrl2;
union {
struct {
uint32_t reserved0: 16;
uint32_t sample_num: 8; /*sample number*/
uint32_t sample_cycle: 8; /*sample cycles*/
};
uint32_t val;
} saradc_fsm;
union {
struct {
uint32_t xpd_wait: 8;
uint32_t rstb_wait: 8;
uint32_t standby_wait: 8;
uint32_t reserved24: 8;
};
uint32_t val;
} saradc_fsm_wait;
uint32_t saradc_sar1_status; /**/
uint32_t saradc_sar2_status; /**/
uint32_t saradc_sar1_patt_tab[4]; /*item 0 ~ 15 for pattern table 1 (each item one byte)*/
uint32_t saradc_sar2_patt_tab[4]; /*item 0 ~ 15 for pattern table 2 (each item one byte)*/
union {
struct {
uint32_t reserved0: 2;
uint32_t adc_arb_apb_force: 1; /*adc2 arbiter force to enableapb controller*/
uint32_t adc_arb_rtc_force: 1; /*adc2 arbiter force to enable rtc controller*/
uint32_t adc_arb_wifi_force: 1; /*adc2 arbiter force to enable wifi controller*/
uint32_t adc_arb_grant_force: 1; /*adc2 arbiter force grant*/
uint32_t adc_arb_apb_priority: 2; /*Set adc2 arbiterapb priority*/
uint32_t adc_arb_rtc_priority: 2; /*Set adc2 arbiter rtc priority*/
uint32_t adc_arb_wifi_priority: 2; /*Set adc2 arbiter wifi priority*/
uint32_t adc_arb_fix_priority: 1; /*adc2 arbiter uses fixed priority*/
uint32_t reserved13: 19;
};
uint32_t val;
} adc_arb_ctrl;
} apb_ctrl_tick_conf;
union {
struct {
uint32_t clk20_oen: 1;
@ -125,15 +55,11 @@ typedef volatile struct {
uint32_t reserved11: 21;
};
uint32_t val;
} clk_out_en;
} apb_ctrl_clk_out_en;
union {
struct {
uint32_t peri_io_swap: 8;
uint32_t spi0_hold: 1;
uint32_t spi1_hold: 1;
uint32_t reserved10: 3;
uint32_t spi_prior: 1;
uint32_t reserved14: 18;
uint32_t reserved8: 24;
};
uint32_t val;
} host_inf_sel;
@ -266,24 +192,14 @@ typedef volatile struct {
} sram_ace3_size;
union {
struct {
uint32_t spi0_reject_int: 1;
uint32_t spi0_reject_clr: 1;
uint32_t spi0_reject_cde: 5;
uint32_t spi_mem_reject_int: 1;
uint32_t spi_mem_reject_clr: 1;
uint32_t spi_mem_reject_cde: 5;
uint32_t reserved7: 25;
};
uint32_t val;
} spi0_pms_ctrl;
uint32_t spi0_reject_addr; /**/
union {
struct {
uint32_t spi1_reject_int: 1;
uint32_t spi1_reject_clr: 1;
uint32_t spi1_reject_cde: 5;
uint32_t reserved7: 25;
};
uint32_t val;
} spi1_pms_ctrl;
uint32_t spi1_reject_addr; /**/
} spi_mem_pms_ctrl;
uint32_t spi_mem_reject_addr; /**/
union {
struct {
uint32_t sdio_win_access_en: 1;
@ -321,6 +237,23 @@ typedef volatile struct {
};
uint32_t val;
} front_end_mem_pd;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
@ -522,9 +455,9 @@ typedef volatile struct {
uint32_t reserved_3f8;
uint32_t date; /**/
} syscon_dev_t;
extern syscon_dev_t SYSCON;
#ifdef __cplusplus
}
#endif
extern syscon_dev_t SYSCON;
#endif /* _SOC_SYSCON_STRUCT_H_ */

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