From fc61e60948e22e5e866e7a3e12e0dc6959dc09a1 Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Tue, 9 Mar 2021 17:35:14 +0800 Subject: [PATCH 1/2] uart: fixed incorrect baudrate on C3 and S3 when target is too slow The integer part of the divider is only 12-bit now. We used prescaler to get low frequency instead. --- components/hal/esp32c3/include/hal/uart_ll.h | 14 +++++++++----- components/hal/esp32s3/include/hal/uart_ll.h | 14 +++++++++----- 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/components/hal/esp32c3/include/hal/uart_ll.h b/components/hal/esp32c3/include/hal/uart_ll.h index a06cc72d70..931134f71f 100644 --- a/components/hal/esp32c3/include/hal/uart_ll.h +++ b/components/hal/esp32c3/include/hal/uart_ll.h @@ -145,20 +145,24 @@ static inline uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw) * @brief Configure the baud-rate. * * @param hw Beginning address of the peripheral registers. - * @param baud The baud rate to be set. When the source clock is APB, the max baud rate is `UART_LL_BITRATE_MAX` + * @param baud The baud rate to be set. * * @return None */ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud) { - const int sclk_div = 1; +#define DIV_UP(a, b) (((a) + (b) - 1) / (b)) uint32_t sclk_freq = uart_ll_get_sclk_freq(hw); - uint32_t clk_div = ((sclk_freq) << 4) / baud; + const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits + int sclk_div = DIV_UP(sclk_freq, max_div * baud); + + uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); // The baud rate configuration register is divided into // an integer part and a fractional part. hw->clk_div.div_int = clk_div >> 4; hw->clk_div.div_frag = clk_div & 0xf; - hw->clk_conf.sclk_div_num = sclk_div - 1;//7;//255; + hw->clk_conf.sclk_div_num = sclk_div - 1; +#undef DIV_UP } /** @@ -172,7 +176,7 @@ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw) { uint32_t sclk_freq = uart_ll_get_sclk_freq(hw); typeof(hw->clk_div) div_reg = hw->clk_div; - return ((sclk_freq << 4)) / ((div_reg.div_int << 4) | div_reg.div_frag); + return ((sclk_freq << 4)) / (((div_reg.div_int << 4) | div_reg.div_frag) * (hw->clk_conf.sclk_div_num + 1)); } /** diff --git a/components/hal/esp32s3/include/hal/uart_ll.h b/components/hal/esp32s3/include/hal/uart_ll.h index c5a167b298..7e5baeef2c 100644 --- a/components/hal/esp32s3/include/hal/uart_ll.h +++ b/components/hal/esp32s3/include/hal/uart_ll.h @@ -129,20 +129,24 @@ static inline uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw) * @brief Configure the baud-rate. * * @param hw Beginning address of the peripheral registers. - * @param baud The baud rate to be set. When the source clock is APB, the max baud rate is `UART_LL_BITRATE_MAX` + * @param baud The baud rate to be set. * * @return None */ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud) { - uint32_t sclk_freq, clk_div; +#define DIV_UP(a, b) (((a) + (b) - 1) / (b)) + uint32_t sclk_freq = uart_ll_get_sclk_freq(hw); + const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits + int sclk_div = DIV_UP(sclk_freq, max_div * baud); - sclk_freq = uart_ll_get_sclk_freq(hw); - clk_div = ((sclk_freq) << 4) / baud; + uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div); // The baud rate configuration register is divided into // an integer part and a fractional part. hw->clk_div.div_int = clk_div >> 4; hw->clk_div.div_frag = clk_div & 0xf; + hw->clk_conf.sclk_div_num = sclk_div - 1; +#undef DIV_UP } /** @@ -156,7 +160,7 @@ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw) { uint32_t sclk_freq = uart_ll_get_sclk_freq(hw); typeof(hw->clk_div) div_reg = hw->clk_div; - return ((sclk_freq << 4)) / ((div_reg.div_int << 4) | div_reg.div_frag); + return ((sclk_freq << 4)) / (((div_reg.div_int << 4) | div_reg.div_frag) * (hw->clk_conf.sclk_div_num + 1)); } /** From bd7cdf8f7cde47a310b419e0857ec9116fba5c12 Mon Sep 17 00:00:00 2001 From: aleks Date: Tue, 23 Feb 2021 14:18:51 +0100 Subject: [PATCH 2/2] driver: esp32s3 fix UART driver Fix set UART2 instance to correct base address (esp32s3 has non standard base periph address) --- components/esp32s3/ld/esp32s3.peripherals.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp32s3/ld/esp32s3.peripherals.ld b/components/esp32s3/ld/esp32s3.peripherals.ld index cba926397a..cc82d08140 100644 --- a/components/esp32s3/ld/esp32s3.peripherals.ld +++ b/components/esp32s3/ld/esp32s3.peripherals.ld @@ -31,7 +31,7 @@ PROVIDE ( I2C1 = 0x60027000 ); PROVIDE ( TWAI = 0x6002B000 ); PROVIDE ( GPSPI4 = 0x60037000 ); PROVIDE ( GDMA = 0x6003F000 ); -PROVIDE ( UART2 = 0x60010000 ); +PROVIDE ( UART2 = 0x6001e000 ); PROVIDE ( DMA = 0x6003F000 ); PROVIDE ( APB_SARADC = 0x60040000 ); PROVIDE ( LCD_CAM = 0x60041000 );