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feat(uhci): add reset and clock control functions

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This commit is contained in:
morris 2024-03-28 17:00:14 +08:00
parent 5d6c56c20d
commit 1b8e1df648
8 changed files with 143 additions and 29 deletions
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65
components/hal/esp32/include/hal/uhci_ll.h Normal file
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@ -0,0 +1,65 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for UHCI register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include <stdio.h>
#include "hal/uhci_types.h"
#include "soc/uhci_struct.h"
#include "soc/dport_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enable the bus clock for UHCI module
*
* @param group_id Group ID
* @param enable true to enable, false to disable
*/
static inline void _uhci_ll_enable_bus_clock(int group_id, bool enable)
{
uint32_t reg_val = DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
if (group_id == 0) {
reg_val &= ~DPORT_UHCI0_CLK_EN;
reg_val |= enable << 8;
} else {
reg_val &= ~DPORT_UHCI1_CLK_EN;
reg_val |= enable << 12;
}
DPORT_WRITE_PERI_REG(DPORT_PERIP_CLK_EN_REG, reg_val);
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define uhci_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uhci_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the UHCI module
*
* @param group_id Group ID
*/
static inline void _uhci_ll_reset_register(int group_id)
{
if (group_id == 0) {
DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, DPORT_UHCI0_RST);
DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, 0);
} else {
DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, DPORT_UHCI1_RST);
DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, 0);
}
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define uhci_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uhci_ll_reset_register(__VA_ARGS__)
#ifdef __cplusplus
}
#endif

41
components/hal/esp32c3/include/hal/uhci_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,11 +7,11 @@
// The LL layer for UHCI register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include <stdio.h>
#include "hal/uhci_types.h"
#include "soc/uhci_struct.h"
#include "soc/system_struct.h"
#ifdef __cplusplus
extern "C" {
@ -26,6 +26,38 @@ typedef enum {
UHCI_RX_EOF_MAX = 0x7,
} uhci_rxeof_cfg_t;
/**
* @brief Enable the bus clock for UHCI module
*
* @param group_id Group ID
* @param enable true to enable, false to disable
*/
static inline void _uhci_ll_enable_bus_clock(int group_id, bool enable)
{
(void)group_id;
SYSTEM.perip_clk_en0.reg_uhci0_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define uhci_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uhci_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the UHCI module
*
* @param group_id Group ID
*/
static inline void _uhci_ll_reset_register(int group_id)
{
(void)group_id;
SYSTEM.perip_rst_en0.reg_uhci0_rst = 1;
SYSTEM.perip_rst_en0.reg_uhci0_rst = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define uhci_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uhci_ll_reset_register(__VA_ARGS__)
static inline void uhci_ll_init(uhci_dev_t *hw)
{
typeof(hw->conf0) conf0_reg;
@ -38,8 +70,8 @@ static inline void uhci_ll_init(uhci_dev_t *hw)
static inline void uhci_ll_attach_uart_port(uhci_dev_t *hw, int uart_num)
{
hw->conf0.uart0_ce = (uart_num == 0)? 1: 0;
hw->conf0.uart1_ce = (uart_num == 1)? 1: 0;
hw->conf0.uart0_ce = (uart_num == 0) ? 1 : 0;
hw->conf0.uart1_ce = (uart_num == 1) ? 1 : 0;
}
static inline void uhci_ll_set_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_char)
@ -118,7 +150,6 @@ static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw)
return hw->int_st.val;
}
static inline void uhci_ll_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode)
{
if (eof_mode & UHCI_RX_BREAK_CHR_EOF) {

43
components/hal/esp32s3/include/hal/uhci_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,11 +7,11 @@
// The LL layer for UHCI register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include <stdio.h>
#include "hal/uhci_types.h"
#include "soc/uhci_struct.h"
#include "soc/system_struct.h"
#ifdef __cplusplus
extern "C" {
@ -26,6 +26,38 @@ typedef enum {
UHCI_RX_EOF_MAX = 0x7,
} uhci_rxeof_cfg_t;
/**
* @brief Enable the bus clock for UHCI module
*
* @param group_id Group ID
* @param enable true to enable, false to disable
*/
static inline void _uhci_ll_enable_bus_clock(int group_id, bool enable)
{
(void)group_id;
SYSTEM.perip_clk_en0.uhci0_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define uhci_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uhci_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the UHCI module
*
* @param group_id Group ID
*/
static inline void _uhci_ll_reset_register(int group_id)
{
(void)group_id;
SYSTEM.perip_rst_en0.uhci0_rst = 1;
SYSTEM.perip_rst_en0.uhci0_rst = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define uhci_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uhci_ll_reset_register(__VA_ARGS__)
static inline void uhci_ll_init(uhci_dev_t *hw)
{
typeof(hw->conf0) conf0_reg;
@ -38,9 +70,9 @@ static inline void uhci_ll_init(uhci_dev_t *hw)
static inline void uhci_ll_attach_uart_port(uhci_dev_t *hw, int uart_num)
{
hw->conf0.uart0_ce = (uart_num == 0)? 1: 0;
hw->conf0.uart1_ce = (uart_num == 1)? 1: 0;
hw->conf0.uart2_ce = (uart_num == 2)? 1: 0;
hw->conf0.uart0_ce = (uart_num == 0) ? 1 : 0;
hw->conf0.uart1_ce = (uart_num == 1) ? 1 : 0;
hw->conf0.uart2_ce = (uart_num == 2) ? 1 : 0;
}
static inline void uhci_ll_set_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_char)
@ -119,7 +151,6 @@ static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw)
return hw->int_st.val;
}
static inline void uhci_ll_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode)
{
if (eof_mode & UHCI_RX_BREAK_CHR_EOF) {

1
components/soc/esp32c3/include/soc/uhci_struct.h
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@ -215,7 +215,6 @@ typedef volatile struct uhci_dev_s {
uint32_t date; /*a*/
} uhci_dev_t;
extern uhci_dev_t UHCI0;
extern uhci_dev_t UHCI1;
#ifdef __cplusplus
}
#endif

1
components/soc/esp32c3/ld/esp32c3.peripherals.ld
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@ -16,7 +16,6 @@ PROVIDE ( HINF = 0x6000B000 );
PROVIDE ( I2S0 = 0x6002d000 );
PROVIDE ( I2C0 = 0x60013000 );
PROVIDE ( UHCI0 = 0x60014000 );
PROVIDE ( UHCI1 = 0x6000c000 );
PROVIDE ( HOST = 0x60015000 );
PROVIDE ( RMT = 0x60016000 );
PROVIDE ( RMTMEM = 0x60016400 );

19
components/soc/esp32s3/include/soc/uhci_struct.h
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@ -1,16 +1,8 @@
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_UHCI_STRUCT_H_
#define _SOC_UHCI_STRUCT_H_
@ -233,7 +225,6 @@ typedef volatile struct uhci_dev_s {
uint32_t date;
} uhci_dev_t;
extern uhci_dev_t UHCI0;
extern uhci_dev_t UHCI1;
#ifdef __cplusplus
}
#endif

1
components/soc/esp32s3/ld/esp32s3.peripherals.ld
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@ -19,7 +19,6 @@ PROVIDE ( I2S1 = 0x6002D000 );
PROVIDE ( UART1 = 0x60010000 );
PROVIDE ( I2C0 = 0x60013000 );
PROVIDE ( UHCI0 = 0x60014000 );
PROVIDE ( UHCI1 = 0x60014000 );
PROVIDE ( HOST = 0x60015000 );
PROVIDE ( RMT = 0x60016000 );
PROVIDE ( RMTMEM = 0x60016800 );

1
tools/ci/check_copyright_ignore.txt
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@ -714,7 +714,6 @@ components/soc/esp32s3/include/soc/uart_pins.h
components/soc/esp32s3/include/soc/uart_reg.h
components/soc/esp32s3/include/soc/uart_struct.h
components/soc/esp32s3/include/soc/uhci_reg.h
components/soc/esp32s3/include/soc/uhci_struct.h
components/soc/esp32s3/include/soc/usb_serial_jtag_struct.h
components/soc/esp32s3/include/soc/usb_wrap_reg.h
components/soc/esp32s3/include/soc/usb_wrap_struct.h