diff --git a/components/driver/dac/esp32/dac_dma.c b/components/driver/dac/esp32/dac_dma.c
index b11ee0a391..cc2b5706a2 100644
--- a/components/driver/dac/esp32/dac_dma.c
+++ b/components/driver/dac/esp32/dac_dma.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,7 +15,7 @@
 #include "freertos/FreeRTOS.h"
 #include "sdkconfig.h"
 #include "hal/adc_ll.h"
-#include "hal/i2s_ll.h"
+#include "hal/i2s_hal.h"
 #include "hal/i2s_types.h"
 #include "soc/i2s_periph.h"
 #include "../dac_priv_dma.h"
@@ -97,7 +97,9 @@ static esp_err_t s_dac_dma_periph_set_clock(uint32_t freq_hz, bool is_apll)
     ESP_LOGD(TAG, "[sclk] %"PRIu32" [mclk] %"PRIu32" [mclk_div] %"PRIu32" [bclk] %"PRIu32" [bclk_div] %"PRIu32, sclk, mclk, mclk_div, bclk, bclk_div);
 
     i2s_ll_tx_clk_set_src(s_ddp->periph_dev, is_apll ? I2S_CLK_SRC_APLL : I2S_CLK_SRC_DEFAULT);
-    i2s_ll_tx_set_mclk(s_ddp->periph_dev, sclk, mclk, mclk_div);
+    i2s_ll_mclk_div_t mclk_div_coeff = {};
+    i2s_hal_calc_mclk_precise_division(sclk, mclk, &mclk_div_coeff);
+    i2s_ll_tx_set_mclk(s_ddp->periph_dev, &mclk_div_coeff);
     i2s_ll_tx_set_bck_div_num(s_ddp->periph_dev, bclk_div);
 
     return ESP_OK;
diff --git a/components/driver/i2s/i2s_pdm.c b/components/driver/i2s/i2s_pdm.c
index 2f939c674e..e8d2f43dc2 100644
--- a/components/driver/i2s/i2s_pdm.c
+++ b/components/driver/i2s/i2s_pdm.c
@@ -71,7 +71,7 @@ static esp_err_t i2s_pdm_tx_set_clock(i2s_chan_handle_t handle, const i2s_pdm_tx
 #if SOC_I2S_HW_VERSION_2
     /* Work around for PDM TX clock, overwrite the raw division directly to reduce the noise
      * This set of coefficients is a special division to reduce the background noise in PDM TX mode */
-    i2s_ll_tx_set_raw_clk_div(handle->controller->hal.dev, 1, 1, 0, 0);
+    i2s_ll_tx_set_raw_clk_div(handle->controller->hal.dev, clk_info.mclk_div, 1, 1, 0, 0);
 #endif
     portEXIT_CRITICAL(&g_i2s.spinlock);
 
diff --git a/components/hal/adc_hal.c b/components/hal/adc_hal.c
index 5041a10eb5..053cc5f712 100644
--- a/components/hal/adc_hal.c
+++ b/components/hal/adc_hal.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,7 +13,7 @@
 
 #if CONFIG_IDF_TARGET_ESP32
 //ADC utilises I2S0 DMA on ESP32
-#include "hal/i2s_ll.h"
+#include "hal/i2s_hal.h"
 #include "hal/i2s_types.h"
 #include "soc/i2s_struct.h"
 #endif
@@ -180,8 +180,9 @@ static void adc_hal_digi_sample_freq_config(adc_hal_dma_ctx_t *hal, adc_continuo
     uint32_t bclk_div = 16;
     uint32_t bclk = sample_freq_hz * 2;
     uint32_t mclk = bclk * bclk_div;
-    uint32_t mclk_div = I2S_BASE_CLK / mclk;
-    i2s_ll_rx_set_mclk(hal->dev, I2S_BASE_CLK, mclk, mclk_div);
+    i2s_ll_mclk_div_t mclk_div = {};
+    i2s_hal_calc_mclk_precise_division(I2S_BASE_CLK, mclk, &mclk_div);
+    i2s_ll_rx_set_mclk(hal->dev, &mclk_div);
     i2s_ll_rx_set_bck_div_num(hal->dev, bclk_div);
 #endif
 }
diff --git a/components/hal/esp32/include/hal/i2s_ll.h b/components/hal/esp32/include/hal/i2s_ll.h
index 05f7ebd0fe..5f33bf4277 100644
--- a/components/hal/esp32/include/hal/i2s_ll.h
+++ b/components/hal/esp32/include/hal/i2s_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -48,11 +48,14 @@ extern "C" {
 #define I2S_LL_PLL_F160M_CLK_FREQ   (160 * 1000000) // PLL_F160M_CLK: 160MHz
 #define I2S_LL_DEFAULT_PLL_CLK_FREQ     I2S_LL_PLL_F160M_CLK_FREQ    // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
 
-/* I2S clock configuration structure */
+/**
+ * @brief I2S clock configuration structure
+ * @note Fmclk = Fsclk /(integ+numer/denom)
+ */
 typedef struct {
-    uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a)
-    uint16_t a;
-    uint16_t b;        // The decimal part of module clock divider, the decimal is: b/a
+    uint16_t integ;     // Integer part of I2S module clock divider
+    uint16_t denom;     // Denominator part of I2S module clock divider
+    uint16_t numer;     // Numerator part of I2S module clock divider
 } i2s_ll_mclk_div_t;
 
 /**
@@ -307,50 +310,16 @@ static inline void i2s_ll_set_raw_mclk_div(i2s_dev_t *hw, uint32_t mclk_div, uin
  * @note mclk on ESP32 is shared by both TX and RX channel
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param sclk system clock
- * @param mclk module clock
- * @param mclk_div integer part of the division from sclk to mclk
+ * @param mclk_div The mclk division coefficients
  */
-static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
+static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
 {
-    int ma = 0;
-    int mb = 0;
-    int denominator = 1;
-    int numerator = 0;
-
-    uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div));
-    if (!freq_diff) {
-        goto finish;
-    }
-    float decimal = freq_diff / (float)mclk;
-    // Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
-    if (decimal > 125.0 / 126.0) {
-        mclk_div++;
-        goto finish;
-    }
-    uint32_t min = ~0;
-    for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
-        int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
-        ma = freq_diff * a;
-        mb = mclk * b;
-        if (ma == mb) {
-            denominator = a;
-            numerator = b;
-            goto finish;
-        }
-        if (abs((mb - ma)) < min) {
-            denominator = a;
-            numerator = b;
-            min = abs(mb - ma);
-        }
-    }
-finish:
     /* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
      * Set to particular coefficients first then update to the target coefficients,
      * otherwise the clock division might be inaccurate.
-     * The particular coefficients here is calculated from 44100 Hz with 2 slots & 16-bit width @ 160MHz sclk */
-    i2s_ll_set_raw_mclk_div(hw, 13, 48, 1);
-    i2s_ll_set_raw_mclk_div(hw, mclk_div, denominator, numerator);
+     * the general idea is to set a value that unlike to calculate from the regular decimal */
+    i2s_ll_set_raw_mclk_div(hw, 7, 47, 3);
+    i2s_ll_set_raw_mclk_div(hw, mclk_div->integ, mclk_div->denom, mclk_div->numer);
 }
 
 /**
@@ -369,13 +338,12 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
  * @note mclk on ESP32 is shared by both TX and RX channel
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param sclk system clock
- * @param mclk module clock
- * @param mclk_div integer part of the division from sclk to mclk
+ * @param mclk_div The mclk division coefficients
  */
-static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
+static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
 {
-    i2s_ll_tx_set_mclk(hw, sclk, mclk, mclk_div);
+    // TX and RX channel on ESP32 shares a same mclk
+    i2s_ll_tx_set_mclk(hw, mclk_div);
 }
 
 /**
@@ -387,11 +355,13 @@ static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mcl
  */
 static inline void i2s_ll_enable_intr(i2s_dev_t *hw, uint32_t mask, bool en)
 {
+    uint32_t int_ena_mask = hw->int_ena.val;
     if (en) {
-        hw->int_ena.val |= mask;
+        int_ena_mask |= mask;
     } else {
-        hw->int_ena.val &= ~mask;
+        int_ena_mask &= ~mask;
     }
+    hw->int_ena.val = int_ena_mask;
 }
 
 /**
diff --git a/components/hal/esp32c3/include/hal/i2s_ll.h b/components/hal/esp32c3/include/hal/i2s_ll.h
index fd30cd6315..e007248f49 100644
--- a/components/hal/esp32c3/include/hal/i2s_ll.h
+++ b/components/hal/esp32c3/include/hal/i2s_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -35,11 +35,14 @@ extern "C" {
 #define I2S_LL_PLL_F160M_CLK_FREQ      (160 * 1000000) // PLL_F160M_CLK: 160MHz
 #define I2S_LL_DEFAULT_PLL_CLK_FREQ     I2S_LL_PLL_F160M_CLK_FREQ    // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
 
-/* I2S clock configuration structure */
+/**
+ * @brief I2S clock configuration structure
+ * @note Fmclk = Fsclk /(integ+numer/denom)
+ */
 typedef struct {
-    uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a)
-    uint16_t a;
-    uint16_t b;        // The decimal part of module clock divider, the decimal is: b/a
+    uint16_t integ;     // Integer part of I2S module clock divider
+    uint16_t denom;     // Denominator part of I2S module clock divider
+    uint16_t numer;     // Numerator part of I2S module clock divider
 } i2s_ll_mclk_div_t;
 
 /**
@@ -247,13 +250,17 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
  * @brief Set I2S tx raw clock division
  *
  * @param hw Peripheral I2S hardware instance address.
+ * @param div_int  Integer part of division
  * @param x  div x
  * @param y  div y
  * @param z  div z
  * @param yn1 yn1
  */
-static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
+static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
 {
+    /* Set the integer part of mclk division */
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, div_int);
+    /* Set the decimal part of the mclk division */
     typeof(hw->tx_clkm_div_conf) div = {};
     div.tx_clkm_div_x = x;
     div.tx_clkm_div_y = y;
@@ -266,13 +273,17 @@ static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t
  * @brief Set I2S rx raw clock division
  *
  * @param hw Peripheral I2S hardware instance address.
+ * @param div_int  Integer part of division
  * @param x  div x
  * @param y  div y
  * @param z  div z
  * @param yn1 yn1
  */
-static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
+static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
 {
+    /* Set the integer part of mclk division */
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, div_int);
+    /* Set the decimal part of the mclk division */
     typeof(hw->rx_clkm_div_conf) div = {};
     div.rx_clkm_div_x = x;
     div.rx_clkm_div_y = y;
@@ -285,64 +296,28 @@ static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t
  * @brief Configure I2S TX module clock divider
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param sclk system clock
- * @param mclk module clock
- * @param mclk_div integer part of the division from sclk to mclk
+ * @param mclk_div The mclk division coefficients
  */
-static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
+static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
 {
-    int ma = 0;
-    int mb = 0;
-    int denominator = 1;
-    int numerator = 0;
-
-    uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div));
-    if (!freq_diff) {
-        goto finish;
-    }
-    float decimal = freq_diff / (float)mclk;
-    // Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
-    if (decimal > 125.0 / 126.0) {
-        mclk_div++;
-        goto finish;
-    }
-    uint32_t min = ~0;
-    for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
-        int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
-        ma = freq_diff * a;
-        mb = mclk * b;
-        if (ma == mb) {
-            denominator = a;
-            numerator = b;
-            goto finish;
-        }
-        if (abs((mb - ma)) < min) {
-            denominator = a;
-            numerator = b;
-            min = abs(mb - ma);
-        }
-    }
-finish:
     /* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
      * Set to particular coefficients first then update to the target coefficients,
      * otherwise the clock division might be inaccurate.
-     * The particular coefficients here is calculated from 44100 Hz with 2 slots & 16-bit width @ 160MHz sclk */
-    i2s_ll_tx_set_raw_clk_div(hw, 47, 0, 1, 0);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, 13);
+     * the general idea is to set a value that impossible to calculate from the regular decimal */
+    i2s_ll_tx_set_raw_clk_div(hw, 7, 317, 7, 3, 0);
 
     uint32_t div_x = 0;
     uint32_t div_y = 0;
     uint32_t div_z = 0;
     uint32_t div_yn1 = 0;
     /* If any of denominator and numerator is 0, set all the coefficients to 0 */
-    if (denominator && numerator) {
-        div_yn1 = numerator * 2 > denominator;
-        div_z = div_yn1 ? denominator - numerator : numerator;
-        div_x = denominator / div_z - 1;
-        div_y = denominator % div_z;
+    if (mclk_div->denom && mclk_div->numer) {
+        div_yn1 = mclk_div->numer * 2 > mclk_div->denom;
+        div_z = div_yn1 ? mclk_div->denom - mclk_div->numer : mclk_div->numer;
+        div_x = mclk_div->denom / div_z - 1;
+        div_y = mclk_div->denom % div_z;
     }
-    i2s_ll_tx_set_raw_clk_div(hw, div_x, div_y, div_z, div_yn1);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, mclk_div);
+    i2s_ll_tx_set_raw_clk_div(hw, mclk_div->integ, div_x, div_y, div_z, div_yn1);
 }
 
 /**
@@ -361,64 +336,28 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
  * @note mclk on ESP32 is shared by both TX and RX channel
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param sclk system clock, 0 means use apll
- * @param mclk module clock
- * @param mclk_div integer part of the division from sclk to mclk
+ * @param mclk_div The mclk division coefficients
  */
-static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
+static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
 {
-    int ma = 0;
-    int mb = 0;
-    int denominator = 1;
-    int numerator = 0;
-
-    uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div));
-    if (!freq_diff) {
-        goto finish;
-    }
-    float decimal = freq_diff / (float)mclk;
-    // Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
-    if (decimal > 125.0 / 126.0) {
-        mclk_div++;
-        goto finish;
-    }
-    uint32_t min = ~0;
-    for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
-        int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
-        ma = freq_diff * a;
-        mb = mclk * b;
-        if (ma == mb) {
-            denominator = a;
-            numerator = b;
-            goto finish;
-        }
-        if (abs((mb - ma)) < min) {
-            denominator = a;
-            numerator = b;
-            min = abs(mb - ma);
-        }
-    }
-finish:
     /* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
      * Set to particular coefficients first then update to the target coefficients,
      * otherwise the clock division might be inaccurate.
-     * The particular coefficients here is calculated from 44100 Hz with 2 slots & 16-bit width @ 160MHz sclk */
-    i2s_ll_rx_set_raw_clk_div(hw, 47, 0, 1, 0);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, 13);
+     * the general idea is to set a value that impossible to calculate from the regular decimal */
+    i2s_ll_rx_set_raw_clk_div(hw, 7, 317, 7, 3, 0);
 
     uint32_t div_x = 0;
     uint32_t div_y = 0;
     uint32_t div_z = 0;
     uint32_t div_yn1 = 0;
     /* If any of denominator and numerator is 0, set all the coefficients to 0 */
-    if (denominator && numerator) {
-        div_yn1 = numerator * 2 > denominator;
-        div_z = div_yn1 ? denominator - numerator : numerator;
-        div_x = denominator / div_z - 1;
-        div_y = denominator % div_z;
+    if (mclk_div->denom && mclk_div->numer) {
+        div_yn1 = mclk_div->numer * 2 > mclk_div->denom;
+        div_z = div_yn1 ? mclk_div->denom - mclk_div->numer : mclk_div->numer;
+        div_x = mclk_div->denom / div_z - 1;
+        div_y = mclk_div->denom % div_z;
     }
-    i2s_ll_rx_set_raw_clk_div(hw, div_x, div_y, div_z, div_yn1);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, mclk_div);
+    i2s_ll_rx_set_raw_clk_div(hw, mclk_div->integ, div_x, div_y, div_z, div_yn1);
 }
 
 /**
@@ -600,10 +539,10 @@ static inline void i2s_ll_rx_set_chan_num(i2s_dev_t *hw, int total_num)
  */
 static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
 {
-    typeof(hw->tx_tdm_ctrl) tdm_ctrl_reg = hw->tx_tdm_ctrl;
-    tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK;
-    tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK;
-    hw->tx_tdm_ctrl.val = tdm_ctrl_reg.val;
+    uint32_t tdm_ctrl = hw->tx_tdm_ctrl.val;
+    tdm_ctrl &= 0xFFFF0000;
+    tdm_ctrl |= chan_mask;
+    hw->tx_tdm_ctrl.val = tdm_ctrl;
 }
 
 /**
@@ -614,10 +553,10 @@ static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_m
  */
 static inline void i2s_ll_rx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
 {
-    typeof(hw->rx_tdm_ctrl) tdm_ctrl_reg = hw->rx_tdm_ctrl;
-    tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK;
-    tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK;
-    hw->rx_tdm_ctrl.val = tdm_ctrl_reg.val;
+    uint32_t tdm_ctrl = hw->rx_tdm_ctrl.val;
+    tdm_ctrl &= 0xFFFF0000;
+    tdm_ctrl |= chan_mask;
+    hw->rx_tdm_ctrl.val = tdm_ctrl;
 }
 
 /**
@@ -631,21 +570,22 @@ static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
     /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
      * Otherwise always enable the first two slots */
     hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1;  // tx_tdm_tot_chan_num = 2 slots - 1 = 1
-    hw->tx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK;
+    uint32_t chan_mask = 0;
     switch (slot_mask)
     {
     case I2S_STD_SLOT_LEFT:
-        hw->tx_tdm_ctrl.val |= 0x01;
+        chan_mask |= 0x01;
         break;
     case I2S_STD_SLOT_RIGHT:
-        hw->tx_tdm_ctrl.val |= 0x02;
+        chan_mask |= 0x02;
         break;
     case I2S_STD_SLOT_BOTH:
-        hw->tx_tdm_ctrl.val |= 0x03;
+        chan_mask |= 0x03;
         break;
     default:
         break;
     }
+    i2s_ll_tx_set_active_chan_mask(hw, chan_mask);
 }
 
 /**
@@ -659,21 +599,22 @@ static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
     /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
      * Otherwise always enable the first two slots */
     hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1;  // rx_tdm_tot_chan_num = 2 slots - 1 = 1
-    hw->rx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK;
+    uint32_t chan_mask = 0;
     switch (slot_mask)
     {
     case I2S_STD_SLOT_LEFT:
-        hw->rx_tdm_ctrl.val |= 0x01;
+        chan_mask |= 0x01;
         break;
     case I2S_STD_SLOT_RIGHT:
-        hw->rx_tdm_ctrl.val |= 0x02;
+        chan_mask |= 0x02;
         break;
     case I2S_STD_SLOT_BOTH:
-        hw->rx_tdm_ctrl.val |= 0x03;
+        chan_mask |= 0x03;
         break;
     default:
         break;
     }
+    i2s_ll_rx_set_active_chan_mask(hw, chan_mask);
 }
 
 /**
diff --git a/components/hal/esp32c6/include/hal/i2s_ll.h b/components/hal/esp32c6/include/hal/i2s_ll.h
index 6cc7d9a266..c36e5d7ea6 100644
--- a/components/hal/esp32c6/include/hal/i2s_ll.h
+++ b/components/hal/esp32c6/include/hal/i2s_ll.h
@@ -36,11 +36,14 @@ extern "C" {
 #define I2S_LL_PLL_F160M_CLK_FREQ      (160 * 1000000) // PLL_F160M_CLK: 160MHz
 #define I2S_LL_DEFAULT_PLL_CLK_FREQ     I2S_LL_PLL_F160M_CLK_FREQ    // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
 
-/* I2S clock configuration structure */
+/**
+ * @brief I2S clock configuration structure
+ * @note Fmclk = Fsclk /(integ+numer/denom)
+ */
 typedef struct {
-    uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a)
-    uint16_t a;
-    uint16_t b;        // The decimal part of module clock divider, the decimal is: b/a
+    uint16_t integ;     // Integer part of I2S module clock divider
+    uint16_t denom;     // Denominator part of I2S module clock divider
+    uint16_t numer;     // Numerator part of I2S module clock divider
 } i2s_ll_mclk_div_t;
 
 /**
@@ -258,14 +261,16 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
  * @brief Set I2S tx raw clock division
  *
  * @param hw Peripheral I2S hardware instance address.
+ * @param div_int  Integer part of division
  * @param x  div x
  * @param y  div y
  * @param z  div z
  * @param yn1 yn1
  */
-static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
+static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
 {
     (void)hw;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_tx_clkm_conf, i2s_tx_clkm_div_num, div_int);
     typeof(PCR.i2s_tx_clkm_div_conf) div = {};
     div.i2s_tx_clkm_div_x = x;
     div.i2s_tx_clkm_div_y = y;
@@ -278,14 +283,16 @@ static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t
  * @brief Set I2S rx raw clock division
  *
  * @param hw Peripheral I2S hardware instance address.
+ * @param div_int  Integer part of division
  * @param x  div x
  * @param y  div y
  * @param z  div z
  * @param yn1 yn1
  */
-static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
+static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
 {
     (void)hw;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_rx_clkm_conf, i2s_rx_clkm_div_num, div_int);
     typeof(PCR.i2s_rx_clkm_div_conf) div = {};
     div.i2s_rx_clkm_div_x = x;
     div.i2s_rx_clkm_div_y = y;
@@ -298,65 +305,28 @@ static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t
  * @brief Configure I2S TX module clock divider
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param sclk system clock
- * @param mclk module clock
- * @param mclk_div integer part of the division from sclk to mclk
+ * @param mclk_div The mclk division coefficients
  */
-static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
+static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
 {
-    (void)hw;
-    int ma = 0;
-    int mb = 0;
-    int denominator = 1;
-    int numerator = 0;
-
-    uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div));
-    if (!freq_diff) {
-        goto finish;
-    }
-    float decimal = freq_diff / (float)mclk;
-    // Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
-    if (decimal > 125.0 / 126.0) {
-        mclk_div++;
-        goto finish;
-    }
-    uint32_t min = ~0;
-    for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
-        int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
-        ma = freq_diff * a;
-        mb = mclk * b;
-        if (ma == mb) {
-            denominator = a;
-            numerator = b;
-            goto finish;
-        }
-        if (abs((mb - ma)) < min) {
-            denominator = a;
-            numerator = b;
-            min = abs(mb - ma);
-        }
-    }
-finish:
     /* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
      * Set to particular coefficients first then update to the target coefficients,
      * otherwise the clock division might be inaccurate.
-     * The particular coefficients here is calculated from 44100 Hz with 2 slots & 16-bit width @ 160MHz sclk */
-    i2s_ll_tx_set_raw_clk_div(hw, 47, 0, 1, 0);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_tx_clkm_conf, i2s_tx_clkm_div_num, 13);
+     * the general idea is to set a value that impossible to calculate from the regular decimal */
+    i2s_ll_tx_set_raw_clk_div(hw, 7, 317, 7, 3, 0);
 
     uint32_t div_x = 0;
     uint32_t div_y = 0;
     uint32_t div_z = 0;
     uint32_t div_yn1 = 0;
     /* If any of denominator and numerator is 0, set all the coefficients to 0 */
-    if (denominator && numerator) {
-        div_yn1 = numerator * 2 > denominator;
-        div_z = div_yn1 ? denominator - numerator : numerator;
-        div_x = denominator / div_z - 1;
-        div_y = denominator % div_z;
+    if (mclk_div->denom && mclk_div->numer) {
+        div_yn1 = mclk_div->numer * 2 > mclk_div->denom;
+        div_z = div_yn1 ? mclk_div->denom - mclk_div->numer : mclk_div->numer;
+        div_x = mclk_div->denom / div_z - 1;
+        div_y = mclk_div->denom % div_z;
     }
-    i2s_ll_tx_set_raw_clk_div(hw, div_x, div_y, div_z, div_yn1);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_tx_clkm_conf, i2s_tx_clkm_div_num, mclk_div);
+    i2s_ll_tx_set_raw_clk_div(hw, mclk_div->integ, div_x, div_y, div_z, div_yn1);
 }
 
 /**
@@ -375,65 +345,28 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
  * @note mclk on ESP32 is shared by both TX and RX channel
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param sclk system clock, 0 means use apll
- * @param mclk module clock
- * @param mclk_div integer part of the division from sclk to mclk
+ * @param mclk_div The mclk division coefficients
  */
-static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
+static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
 {
-    (void)hw;
-    int ma = 0;
-    int mb = 0;
-    int denominator = 1;
-    int numerator = 0;
-
-    uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div));
-    if (!freq_diff) {
-        goto finish;
-    }
-    float decimal = freq_diff / (float)mclk;
-    // Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
-    if (decimal > 125.0 / 126.0) {
-        mclk_div++;
-        goto finish;
-    }
-    uint32_t min = ~0;
-    for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
-        int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
-        ma = freq_diff * a;
-        mb = mclk * b;
-        if (ma == mb) {
-            denominator = a;
-            numerator = b;
-            goto finish;
-        }
-        if (abs((mb - ma)) < min) {
-            denominator = a;
-            numerator = b;
-            min = abs(mb - ma);
-        }
-    }
-finish:
     /* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
      * Set to particular coefficients first then update to the target coefficients,
      * otherwise the clock division might be inaccurate.
-     * The particular coefficients here is calculated from 44100 Hz with 2 slots & 16-bit width @ 160MHz sclk */
-    i2s_ll_rx_set_raw_clk_div(hw, 47, 0, 1, 0);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_rx_clkm_conf, i2s_rx_clkm_div_num, 13);
+     * the general idea is to set a value that impossible to calculate from the regular decimal */
+    i2s_ll_rx_set_raw_clk_div(hw, 7, 317, 7, 3, 0);
 
     uint32_t div_x = 0;
     uint32_t div_y = 0;
     uint32_t div_z = 0;
     uint32_t div_yn1 = 0;
     /* If any of denominator and numerator is 0, set all the coefficients to 0 */
-    if (denominator && numerator) {
-        div_yn1 = numerator * 2 > denominator;
-        div_z = div_yn1 ? denominator - numerator : numerator;
-        div_x = denominator / div_z - 1;
-        div_y = denominator % div_z;
+    if (mclk_div->denom && mclk_div->numer) {
+        div_yn1 = mclk_div->numer * 2 > mclk_div->denom;
+        div_z = div_yn1 ? mclk_div->denom - mclk_div->numer : mclk_div->numer;
+        div_x = mclk_div->denom / div_z - 1;
+        div_y = mclk_div->denom % div_z;
     }
-    i2s_ll_rx_set_raw_clk_div(hw, div_x, div_y, div_z, div_yn1);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_rx_clkm_conf, i2s_rx_clkm_div_num, mclk_div);
+    i2s_ll_rx_set_raw_clk_div(hw, mclk_div->integ, div_x, div_y, div_z, div_yn1);
 }
 
 /**
@@ -615,10 +548,10 @@ static inline void i2s_ll_rx_set_chan_num(i2s_dev_t *hw, int total_num)
  */
 static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
 {
-    typeof(hw->tx_tdm_ctrl) tdm_ctrl_reg = hw->tx_tdm_ctrl;
-    tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK;
-    tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK;
-    hw->tx_tdm_ctrl.val = tdm_ctrl_reg.val;
+    uint32_t tdm_ctrl = hw->tx_tdm_ctrl.val;
+    tdm_ctrl &= 0xFFFF0000;
+    tdm_ctrl |= chan_mask;
+    hw->tx_tdm_ctrl.val = tdm_ctrl;
 }
 
 /**
@@ -629,10 +562,10 @@ static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_m
  */
 static inline void i2s_ll_rx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
 {
-    typeof(hw->rx_tdm_ctrl) tdm_ctrl_reg = hw->rx_tdm_ctrl;
-    tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK;
-    tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK;
-    hw->rx_tdm_ctrl.val = tdm_ctrl_reg.val;
+    uint32_t tdm_ctrl = hw->rx_tdm_ctrl.val;
+    tdm_ctrl &= 0xFFFF0000;
+    tdm_ctrl |= chan_mask;
+    hw->rx_tdm_ctrl.val = tdm_ctrl;
 }
 
 /**
@@ -646,21 +579,22 @@ static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
     /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
      * Otherwise always enable the first two slots */
     hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1;  // tx_tdm_tot_chan_num = 2 slots - 1 = 1
-    hw->tx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK;
+    uint32_t chan_mask = 0;
     switch (slot_mask)
     {
     case I2S_STD_SLOT_LEFT:
-        hw->tx_tdm_ctrl.val |= 0x01;
+        chan_mask |= 0x01;
         break;
     case I2S_STD_SLOT_RIGHT:
-        hw->tx_tdm_ctrl.val |= 0x02;
+        chan_mask |= 0x02;
         break;
     case I2S_STD_SLOT_BOTH:
-        hw->tx_tdm_ctrl.val |= 0x03;
+        chan_mask |= 0x03;
         break;
     default:
         break;
     }
+    i2s_ll_tx_set_active_chan_mask(hw, chan_mask);
 }
 
 /**
@@ -674,21 +608,22 @@ static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
     /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
      * Otherwise always enable the first two slots */
     hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1;  // rx_tdm_tot_chan_num = 2 slots - 1 = 1
-    hw->rx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK;
+    uint32_t chan_mask = 0;
     switch (slot_mask)
     {
     case I2S_STD_SLOT_LEFT:
-        hw->rx_tdm_ctrl.val |= 0x01;
+        chan_mask |= 0x01;
         break;
     case I2S_STD_SLOT_RIGHT:
-        hw->rx_tdm_ctrl.val |= 0x02;
+        chan_mask |= 0x02;
         break;
     case I2S_STD_SLOT_BOTH:
-        hw->rx_tdm_ctrl.val |= 0x03;
+        chan_mask |= 0x03;
         break;
     default:
         break;
     }
+    i2s_ll_rx_set_active_chan_mask(hw, chan_mask);
 }
 
 /**
diff --git a/components/hal/esp32h2/include/hal/i2s_ll.h b/components/hal/esp32h2/include/hal/i2s_ll.h
index 172562781d..2d7b4fce29 100644
--- a/components/hal/esp32h2/include/hal/i2s_ll.h
+++ b/components/hal/esp32h2/include/hal/i2s_ll.h
@@ -37,11 +37,14 @@ extern "C" {
 #define I2S_LL_PLL_F64M_CLK_FREQ      (64 * 1000000) // PLL_F64M_CLK: 64MHz
 #define I2S_LL_DEFAULT_PLL_CLK_FREQ   I2S_LL_PLL_F96M_CLK_FREQ  // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
 
-/* I2S clock configuration structure */
+/**
+ * @brief I2S clock configuration structure
+ * @note Fmclk = Fsclk /(integ+numer/denom)
+ */
 typedef struct {
-    uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a)
-    uint16_t a;
-    uint16_t b;        // The decimal part of module clock divider, the decimal is: b/a
+    uint16_t integ;     // Integer part of I2S module clock divider
+    uint16_t denom;     // Denominator part of I2S module clock divider
+    uint16_t numer;     // Numerator part of I2S module clock divider
 } i2s_ll_mclk_div_t;
 
 /**
@@ -265,14 +268,16 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
  * @brief Set I2S tx raw clock division
  *
  * @param hw Peripheral I2S hardware instance address.
+ * @param div_int  Integer part of division
  * @param x  div x
  * @param y  div y
  * @param z  div z
  * @param yn1 yn1
  */
-static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
+static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
 {
     (void)hw;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_tx_clkm_conf, i2s_tx_clkm_div_num, div_int);
     typeof(PCR.i2s_tx_clkm_div_conf) div = {};
     div.i2s_tx_clkm_div_x = x;
     div.i2s_tx_clkm_div_y = y;
@@ -285,14 +290,16 @@ static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t
  * @brief Set I2S rx raw clock division
  *
  * @param hw Peripheral I2S hardware instance address.
+ * @param div_int  Integer part of division
  * @param x  div x
  * @param y  div y
  * @param z  div z
  * @param yn1 yn1
  */
-static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
+static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
 {
     (void)hw;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_rx_clkm_conf, i2s_rx_clkm_div_num, div_int);
     typeof(PCR.i2s_rx_clkm_div_conf) div = {};
     div.i2s_rx_clkm_div_x = x;
     div.i2s_rx_clkm_div_y = y;
@@ -305,65 +312,28 @@ static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t
  * @brief Configure I2S TX module clock divider
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param sclk system clock
- * @param mclk module clock
- * @param mclk_div integer part of the division from sclk to mclk
+ * @param mclk_div The mclk division coefficients
  */
-static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
+static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
 {
-    (void)hw;
-    int ma = 0;
-    int mb = 0;
-    int denominator = 1;
-    int numerator = 0;
-
-    uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div));
-    if (!freq_diff) {
-        goto finish;
-    }
-    float decimal = freq_diff / (float)mclk;
-    // Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
-    if (decimal > 125.0 / 126.0) {
-        mclk_div++;
-        goto finish;
-    }
-    uint32_t min = ~0;
-    for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
-        int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
-        ma = freq_diff * a;
-        mb = mclk * b;
-        if (ma == mb) {
-            denominator = a;
-            numerator = b;
-            goto finish;
-        }
-        if (abs((mb - ma)) < min) {
-            denominator = a;
-            numerator = b;
-            min = abs(mb - ma);
-        }
-    }
-finish:
     /* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
      * Set to particular coefficients first then update to the target coefficients,
      * otherwise the clock division might be inaccurate.
-     * The particular coefficients here is calculated from 44100 Hz with 2 slots & 16-bit width @96MHz sclk */
-    i2s_ll_tx_set_raw_clk_div(hw, 1, 1, 73, 1);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_tx_clkm_conf, i2s_tx_clkm_div_num, 8);
+     * the general idea is to set a value that impossible to calculate from the regular decimal */
+    i2s_ll_tx_set_raw_clk_div(hw, 8, 1, 1, 73, 1);
 
     uint32_t div_x = 0;
     uint32_t div_y = 0;
     uint32_t div_z = 0;
     uint32_t div_yn1 = 0;
     /* If any of denominator and numerator is 0, set all the coefficients to 0 */
-    if (denominator && numerator) {
-        div_yn1 = numerator * 2 > denominator;
-        div_z = div_yn1 ? denominator - numerator : numerator;
-        div_x = denominator / div_z - 1;
-        div_y = denominator % div_z;
+    if (mclk_div->denom && mclk_div->numer) {
+        div_yn1 = mclk_div->numer * 2 > mclk_div->denom;
+        div_z = div_yn1 ? mclk_div->denom - mclk_div->numer : mclk_div->numer;
+        div_x = mclk_div->denom / div_z - 1;
+        div_y = mclk_div->denom % div_z;
     }
-    i2s_ll_tx_set_raw_clk_div(hw, div_x, div_y, div_z, div_yn1);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_tx_clkm_conf, i2s_tx_clkm_div_num, mclk_div);
+    i2s_ll_tx_set_raw_clk_div(hw, mclk_div->integ, div_x, div_y, div_z, div_yn1);
 }
 
 /**
@@ -382,65 +352,28 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
  * @note mclk on ESP32 is shared by both TX and RX channel
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param sclk system clock, 0 means use apll
- * @param mclk module clock
- * @param mclk_div integer part of the division from sclk to mclk
+ * @param mclk_div The mclk division coefficients
  */
-static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
+static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
 {
-    (void)hw;
-    int ma = 0;
-    int mb = 0;
-    int denominator = 1;
-    int numerator = 0;
-
-    uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div));
-    if (!freq_diff) {
-        goto finish;
-    }
-    float decimal = freq_diff / (float)mclk;
-    // Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
-    if (decimal > 125.0 / 126.0) {
-        mclk_div++;
-        goto finish;
-    }
-    uint32_t min = ~0;
-    for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
-        int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
-        ma = freq_diff * a;
-        mb = mclk * b;
-        if (ma == mb) {
-            denominator = a;
-            numerator = b;
-            goto finish;
-        }
-        if (abs((mb - ma)) < min) {
-            denominator = a;
-            numerator = b;
-            min = abs(mb - ma);
-        }
-    }
-finish:
     /* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
      * Set to particular coefficients first then update to the target coefficients,
      * otherwise the clock division might be inaccurate.
-     * The particular coefficients here is calculated from 44100 Hz with 2 slots & 16-bit width @96MHz sclk */
-    i2s_ll_rx_set_raw_clk_div(hw, 1, 1, 73, 1);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_rx_clkm_conf, i2s_rx_clkm_div_num, 8);
+     * the general idea is to set a value that impossible to calculate from the regular decimal */
+    i2s_ll_rx_set_raw_clk_div(hw, 8, 1, 1, 73, 1);
 
     uint32_t div_x = 0;
     uint32_t div_y = 0;
     uint32_t div_z = 0;
     uint32_t div_yn1 = 0;
     /* If any of denominator and numerator is 0, set all the coefficients to 0 */
-    if (denominator && numerator) {
-        div_yn1 = numerator * 2 > denominator;
-        div_z = div_yn1 ? denominator - numerator : numerator;
-        div_x = denominator / div_z - 1;
-        div_y = denominator % div_z;
+    if (mclk_div->denom && mclk_div->numer) {
+        div_yn1 = mclk_div->numer * 2 > mclk_div->denom;
+        div_z = div_yn1 ? mclk_div->denom - mclk_div->numer : mclk_div->numer;
+        div_x = mclk_div->denom / div_z - 1;
+        div_y = mclk_div->denom % div_z;
     }
-    i2s_ll_rx_set_raw_clk_div(hw, div_x, div_y, div_z, div_yn1);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_rx_clkm_conf, i2s_rx_clkm_div_num, mclk_div);
+    i2s_ll_rx_set_raw_clk_div(hw, mclk_div->integ, div_x, div_y, div_z, div_yn1);
 }
 
 /**
@@ -622,10 +555,10 @@ static inline void i2s_ll_rx_set_chan_num(i2s_dev_t *hw, int total_num)
  */
 static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
 {
-    typeof(hw->tx_tdm_ctrl) tdm_ctrl_reg = hw->tx_tdm_ctrl;
-    tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK;
-    tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK;
-    hw->tx_tdm_ctrl.val = tdm_ctrl_reg.val;
+    uint32_t tdm_ctrl = hw->tx_tdm_ctrl.val;
+    tdm_ctrl &= 0xFFFF0000;
+    tdm_ctrl |= chan_mask;
+    hw->tx_tdm_ctrl.val = tdm_ctrl;
 }
 
 /**
@@ -636,10 +569,10 @@ static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_m
  */
 static inline void i2s_ll_rx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
 {
-    typeof(hw->rx_tdm_ctrl) tdm_ctrl_reg = hw->rx_tdm_ctrl;
-    tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK;
-    tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK;
-    hw->rx_tdm_ctrl.val = tdm_ctrl_reg.val;
+    uint32_t tdm_ctrl = hw->rx_tdm_ctrl.val;
+    tdm_ctrl &= 0xFFFF0000;
+    tdm_ctrl |= chan_mask;
+    hw->rx_tdm_ctrl.val = tdm_ctrl;
 }
 
 /**
@@ -653,21 +586,22 @@ static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
     /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
      * Otherwise always enable the first two slots */
     hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1;  // tx_tdm_tot_chan_num = 2 slots - 1 = 1
-    hw->tx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK;
+    uint32_t chan_mask = 0;
     switch (slot_mask)
     {
     case I2S_STD_SLOT_LEFT:
-        hw->tx_tdm_ctrl.val |= 0x01;
+        chan_mask |= 0x01;
         break;
     case I2S_STD_SLOT_RIGHT:
-        hw->tx_tdm_ctrl.val |= 0x02;
+        chan_mask |= 0x02;
         break;
     case I2S_STD_SLOT_BOTH:
-        hw->tx_tdm_ctrl.val |= 0x03;
+        chan_mask |= 0x03;
         break;
     default:
         break;
     }
+    i2s_ll_tx_set_active_chan_mask(hw, chan_mask);
 }
 
 /**
@@ -681,21 +615,22 @@ static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
     /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
      * Otherwise always enable the first two slots */
     hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1;  // rx_tdm_tot_chan_num = 2 slots - 1 = 1
-    hw->rx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK;
+    uint32_t chan_mask = 0;
     switch (slot_mask)
     {
     case I2S_STD_SLOT_LEFT:
-        hw->rx_tdm_ctrl.val |= 0x01;
+        chan_mask |= 0x01;
         break;
     case I2S_STD_SLOT_RIGHT:
-        hw->rx_tdm_ctrl.val |= 0x02;
+        chan_mask |= 0x02;
         break;
     case I2S_STD_SLOT_BOTH:
-        hw->rx_tdm_ctrl.val |= 0x03;
+        chan_mask |= 0x03;
         break;
     default:
         break;
     }
+    i2s_ll_rx_set_active_chan_mask(hw, chan_mask);
 }
 
 /**
diff --git a/components/hal/esp32s2/include/hal/i2s_ll.h b/components/hal/esp32s2/include/hal/i2s_ll.h
index 54bce163e0..aaed7ac505 100644
--- a/components/hal/esp32s2/include/hal/i2s_ll.h
+++ b/components/hal/esp32s2/include/hal/i2s_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -45,11 +45,14 @@ extern "C" {
 #define I2S_LL_PLL_F160M_CLK_FREQ   (160 * 1000000) // PLL_F160M_CLK: 160MHz
 #define I2S_LL_DEFAULT_PLL_CLK_FREQ     I2S_LL_PLL_F160M_CLK_FREQ    // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
 
-/* I2S clock configuration structure */
+/**
+ * @brief I2S clock configuration structure
+ * @note Fmclk = Fsclk /(integ+numer/denom)
+ */
 typedef struct {
-    uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a)
-    uint16_t a;
-    uint16_t b;        // The decimal part of module clock divider, the decimal is: b/a
+    uint16_t integ;     // Integer part of I2S module clock divider
+    uint16_t denom;     // Denominator part of I2S module clock divider
+    uint16_t numer;     // Numerator part of I2S module clock divider
 } i2s_ll_mclk_div_t;
 
 /**
@@ -295,53 +298,19 @@ static inline void i2s_ll_set_raw_mclk_div(i2s_dev_t *hw, uint32_t mclk_div, uin
 
 /**
  * @brief Configure I2S TX module clock divider
- * @note mclk on ESP32S2 is shared by both TX and RX channel
+ * @note mclk on ESP32 is shared by both TX and RX channel
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param sclk system clock
- * @param mclk module clock
- * @param mclk_div integer part of the division from sclk to mclk
+ * @param mclk_div The mclk division coefficients
  */
-static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
+static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
 {
-    int ma = 0;
-    int mb = 0;
-    int denominator = 1;
-    int numerator = 0;
-
-    uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div));
-    if (!freq_diff) {
-        goto finish;
-    }
-    float decimal = freq_diff / (float)mclk;
-    // Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
-    if (decimal > 125.0 / 126.0) {
-        mclk_div++;
-        goto finish;
-    }
-    uint32_t min = ~0;
-    for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
-        int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
-        ma = freq_diff * a;
-        mb = mclk * b;
-        if (ma == mb) {
-            denominator = a;
-            numerator = b;
-            goto finish;
-        }
-        if (abs((mb - ma)) < min) {
-            denominator = a;
-            numerator = b;
-            min = abs(mb - ma);
-        }
-    }
-finish:
     /* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
      * Set to particular coefficients first then update to the target coefficients,
      * otherwise the clock division might be inaccurate.
-     * The particular coefficients here is calculated from 44100 Hz with 2 slots & 16-bit width @ 160MHz sclk */
-    i2s_ll_set_raw_mclk_div(hw, 13, 48, 1);
-    i2s_ll_set_raw_mclk_div(hw, mclk_div, denominator, numerator);
+     * the general idea is to set a value that unlike to calculate from the regular decimal */
+    i2s_ll_set_raw_mclk_div(hw, 7, 47, 3);
+    i2s_ll_set_raw_mclk_div(hw, mclk_div->integ, mclk_div->denom, mclk_div->numer);
 }
 
 /**
@@ -357,16 +326,15 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
 
 /**
  * @brief Configure I2S RX module clock divider
- * @note mclk on ESP32S2 is shared by both TX and RX channel
+ * @note mclk on ESP32 is shared by both TX and RX channel
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param sclk system clock
- * @param mclk module clock
- * @param mclk_div integer part of the division from sclk to mclk
+ * @param mclk_div The mclk division coefficients
  */
-static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
+static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
 {
-    i2s_ll_tx_set_mclk(hw, sclk, mclk, mclk_div);
+    // TX and RX channel on ESP32 shares a same mclk
+    i2s_ll_tx_set_mclk(hw, mclk_div);
 }
 
 /**
@@ -378,11 +346,13 @@ static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mcl
  */
 static inline void i2s_ll_enable_intr(i2s_dev_t *hw, uint32_t mask, bool en)
 {
+    uint32_t int_ena_mask = hw->int_ena.val;
     if (en) {
-        hw->int_ena.val |= mask;
+        int_ena_mask |= mask;
     } else {
-        hw->int_ena.val &= ~mask;
+        int_ena_mask &= ~mask;
     }
+    hw->int_ena.val = int_ena_mask;
 }
 
 /**
diff --git a/components/hal/esp32s3/include/hal/i2s_ll.h b/components/hal/esp32s3/include/hal/i2s_ll.h
index 16a5d8b683..02de004fbe 100644
--- a/components/hal/esp32s3/include/hal/i2s_ll.h
+++ b/components/hal/esp32s3/include/hal/i2s_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -36,11 +36,14 @@ extern "C" {
 #define I2S_LL_PLL_F160M_CLK_FREQ      (160 * 1000000) // PLL_F160M_CLK: 160MHz
 #define I2S_LL_DEFAULT_PLL_CLK_FREQ     I2S_LL_PLL_F160M_CLK_FREQ    // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
 
-/* I2S clock configuration structure */
+/**
+ * @brief I2S clock configuration structure
+ * @note Fmclk = Fsclk /(integ+numer/denom)
+ */
 typedef struct {
-    uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a)
-    uint16_t a;
-    uint16_t b;        // The decimal part of module clock divider, the decimal is: b/a
+    uint16_t integ;     // Integer part of I2S module clock divider
+    uint16_t denom;     // Denominator part of I2S module clock divider
+    uint16_t numer;     // Numerator part of I2S module clock divider
 } i2s_ll_mclk_div_t;
 
 /**
@@ -247,13 +250,17 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
  * @brief Set I2S tx raw clock division
  *
  * @param hw Peripheral I2S hardware instance address.
+ * @param div_int  Integer part of division
  * @param x  div x
  * @param y  div y
  * @param z  div z
  * @param yn1 yn1
  */
-static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
+static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
 {
+    /* Set the integer part of mclk division */
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, div_int);
+    /* Set the decimal part of the mclk division */
     typeof(hw->tx_clkm_div_conf) div = {};
     div.tx_clkm_div_x = x;
     div.tx_clkm_div_y = y;
@@ -266,13 +273,17 @@ static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t
  * @brief Set I2S rx raw clock division
  *
  * @param hw Peripheral I2S hardware instance address.
+ * @param div_int  Integer part of division
  * @param x  div x
  * @param y  div y
  * @param z  div z
  * @param yn1 yn1
  */
-static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
+static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
 {
+    /* Set the integer part of mclk division */
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, div_int);
+    /* Set the decimal part of the mclk division */
     typeof(hw->rx_clkm_div_conf) div = {};
     div.rx_clkm_div_x = x;
     div.rx_clkm_div_y = y;
@@ -285,64 +296,28 @@ static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t
  * @brief Configure I2S TX module clock divider
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param sclk system clock
- * @param mclk module clock
- * @param mclk_div integer part of the division from sclk to mclk
+ * @param mclk_div The mclk division coefficients
  */
-static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
+static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
 {
-    int ma = 0;
-    int mb = 0;
-    int denominator = 1;
-    int numerator = 0;
-
-    uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div));
-    if (!freq_diff) {
-        goto finish;
-    }
-    float decimal = freq_diff / (float)mclk;
-    // Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
-    if (decimal > 125.0 / 126.0) {
-        mclk_div++;
-        goto finish;
-    }
-    uint32_t min = ~0;
-    for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
-        int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
-        ma = freq_diff * a;
-        mb = mclk * b;
-        if (ma == mb) {
-            denominator = a;
-            numerator = b;
-            goto finish;
-        }
-        if (abs((mb - ma)) < min) {
-            denominator = a;
-            numerator = b;
-            min = abs(mb - ma);
-        }
-    }
-finish:
     /* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
      * Set to particular coefficients first then update to the target coefficients,
      * otherwise the clock division might be inaccurate.
-     * The particular coefficients here is calculated from 44100 Hz with 2 slots & 16-bit width @ 160MHz sclk */
-    i2s_ll_tx_set_raw_clk_div(hw, 47, 0, 1, 0);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, 13);
+     * the general idea is to set a value that impossible to calculate from the regular decimal */
+    i2s_ll_tx_set_raw_clk_div(hw, 7, 317, 7, 3, 0);
 
     uint32_t div_x = 0;
     uint32_t div_y = 0;
     uint32_t div_z = 0;
     uint32_t div_yn1 = 0;
     /* If any of denominator and numerator is 0, set all the coefficients to 0 */
-    if (denominator && numerator) {
-        div_yn1 = numerator * 2 > denominator;
-        div_z = div_yn1 ? denominator - numerator : numerator;
-        div_x = denominator / div_z - 1;
-        div_y = denominator % div_z;
+    if (mclk_div->denom && mclk_div->numer) {
+        div_yn1 = mclk_div->numer * 2 > mclk_div->denom;
+        div_z = div_yn1 ? mclk_div->denom - mclk_div->numer : mclk_div->numer;
+        div_x = mclk_div->denom / div_z - 1;
+        div_y = mclk_div->denom % div_z;
     }
-    i2s_ll_tx_set_raw_clk_div(hw, div_x, div_y, div_z, div_yn1);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, mclk_div);
+    i2s_ll_tx_set_raw_clk_div(hw, mclk_div->integ, div_x, div_y, div_z, div_yn1);
 }
 
 /**
@@ -361,66 +336,31 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
  * @note mclk on ESP32 is shared by both TX and RX channel
  *
  * @param hw Peripheral I2S hardware instance address.
- * @param sclk system clock, 0 means use apll
- * @param mclk module clock
- * @param mclk_div integer part of the division from sclk to mclk
+ * @param mclk_div The mclk division coefficients
  */
-static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
+static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
 {
-    int ma = 0;
-    int mb = 0;
-    int denominator = 1;
-    int numerator = 0;
-
-    uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div));
-    if (!freq_diff) {
-        goto finish;
-    }
-    float decimal = freq_diff / (float)mclk;
-    // Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
-    if (decimal > 125.0 / 126.0) {
-        mclk_div++;
-        goto finish;
-    }
-    uint32_t min = ~0;
-    for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
-        int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
-        ma = freq_diff * a;
-        mb = mclk * b;
-        if (ma == mb) {
-            denominator = a;
-            numerator = b;
-            goto finish;
-        }
-        if (abs((mb - ma)) < min) {
-            denominator = a;
-            numerator = b;
-            min = abs(mb - ma);
-        }
-    }
-finish:
     /* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
      * Set to particular coefficients first then update to the target coefficients,
      * otherwise the clock division might be inaccurate.
-     * The particular coefficients here is calculated from 44100 Hz with 2 slots & 16-bit width @ 160MHz sclk */
-    i2s_ll_rx_set_raw_clk_div(hw, 47, 0, 1, 0);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, 13);
+     * the general idea is to set a value that impossible to calculate from the regular decimal */
+    i2s_ll_rx_set_raw_clk_div(hw, 7, 317, 7, 3, 0);
 
     uint32_t div_x = 0;
     uint32_t div_y = 0;
     uint32_t div_z = 0;
     uint32_t div_yn1 = 0;
     /* If any of denominator and numerator is 0, set all the coefficients to 0 */
-    if (denominator && numerator) {
-        div_yn1 = numerator * 2 > denominator;
-        div_z = div_yn1 ? denominator - numerator : numerator;
-        div_x = denominator / div_z - 1;
-        div_y = denominator % div_z;
+    if (mclk_div->denom && mclk_div->numer) {
+        div_yn1 = mclk_div->numer * 2 > mclk_div->denom;
+        div_z = div_yn1 ? mclk_div->denom - mclk_div->numer : mclk_div->numer;
+        div_x = mclk_div->denom / div_z - 1;
+        div_y = mclk_div->denom % div_z;
     }
-    i2s_ll_rx_set_raw_clk_div(hw, div_x, div_y, div_z, div_yn1);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, mclk_div);
+    i2s_ll_rx_set_raw_clk_div(hw, mclk_div->integ, div_x, div_y, div_z, div_yn1);
 }
 
+
 /**
  * @brief Start I2S TX
  *
@@ -600,10 +540,10 @@ static inline void i2s_ll_rx_set_chan_num(i2s_dev_t *hw, int total_num)
  */
 static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
 {
-    typeof(hw->tx_tdm_ctrl) tdm_ctrl_reg = hw->tx_tdm_ctrl;
-    tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK;
-    tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK;
-    hw->tx_tdm_ctrl.val = tdm_ctrl_reg.val;
+    uint32_t tdm_ctrl = hw->tx_tdm_ctrl.val;
+    tdm_ctrl &= 0xFFFF0000;
+    tdm_ctrl |= chan_mask;
+    hw->tx_tdm_ctrl.val = tdm_ctrl;
 }
 
 /**
@@ -614,10 +554,10 @@ static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_m
  */
 static inline void i2s_ll_rx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
 {
-    typeof(hw->rx_tdm_ctrl) tdm_ctrl_reg = hw->rx_tdm_ctrl;
-    tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK;
-    tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK;
-    hw->rx_tdm_ctrl.val = tdm_ctrl_reg.val;
+    uint32_t tdm_ctrl = hw->rx_tdm_ctrl.val;
+    tdm_ctrl &= 0xFFFF0000;
+    tdm_ctrl |= chan_mask;
+    hw->rx_tdm_ctrl.val = tdm_ctrl;
 }
 
 /**
@@ -631,21 +571,22 @@ static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
     /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
      * Otherwise always enable the first two slots */
     hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1;  // tx_tdm_tot_chan_num = 2 slots - 1 = 1
-    hw->tx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK;
+    uint32_t chan_mask = 0;
     switch (slot_mask)
     {
     case I2S_STD_SLOT_LEFT:
-        hw->tx_tdm_ctrl.val |= 0x01;
+        chan_mask |= 0x01;
         break;
     case I2S_STD_SLOT_RIGHT:
-        hw->tx_tdm_ctrl.val |= 0x02;
+        chan_mask |= 0x02;
         break;
     case I2S_STD_SLOT_BOTH:
-        hw->tx_tdm_ctrl.val |= 0x03;
+        chan_mask |= 0x03;
         break;
     default:
         break;
     }
+    i2s_ll_tx_set_active_chan_mask(hw, chan_mask);
 }
 
 /**
@@ -659,21 +600,22 @@ static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
     /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
      * Otherwise always enable the first two slots */
     hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1;  // rx_tdm_tot_chan_num = 2 slots - 1 = 1
-    hw->rx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK;
+    uint32_t chan_mask = 0;
     switch (slot_mask)
     {
     case I2S_STD_SLOT_LEFT:
-        hw->rx_tdm_ctrl.val |= 0x01;
+        chan_mask |= 0x01;
         break;
     case I2S_STD_SLOT_RIGHT:
-        hw->rx_tdm_ctrl.val |= 0x02;
+        chan_mask |= 0x02;
         break;
     case I2S_STD_SLOT_BOTH:
-        hw->rx_tdm_ctrl.val |= 0x03;
+        chan_mask |= 0x03;
         break;
     default:
         break;
     }
+    i2s_ll_rx_set_active_chan_mask(hw, chan_mask);
 }
 
 /**
diff --git a/components/hal/i2s_hal.c b/components/hal/i2s_hal.c
index 5b3c3f53c6..2883b4084c 100644
--- a/components/hal/i2s_hal.c
+++ b/components/hal/i2s_hal.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,7 +11,7 @@
 #include "hal/i2s_hal.h"
 
 #if SOC_I2S_HW_VERSION_2 && SOC_I2S_SUPPORTS_PDM_TX
-/* PDM tx high pass filter cut-off frequency and coeffecients list
+/* PDM tx high pass filter cut-off frequency and coefficients list
  * [0]: cut-off frequency; [1]: param0; [2]: param5 */
 static const float cut_off_coef[21][3] = {
     {185, 0, 0}, {172,  0, 1}, {160,  1, 1},
@@ -24,6 +24,53 @@ static const float cut_off_coef[21][3] = {
 };
 #endif
 
+/**
+ * @brief Calculate the precise mclk division by sclk and mclk
+ *
+ * @param sclk      system clock
+ * @param mclk      module clock
+ * @param integer   output the integer part of the division
+ * @param denominator   output the denominator part of the division
+ * @param numerator     output the numerator part of the division
+ */
+void i2s_hal_calc_mclk_precise_division(uint32_t sclk, uint32_t mclk, i2s_ll_mclk_div_t *mclk_div)
+{
+    int ma = 0;
+    int mb = 0;
+    int min = INT32_MAX;
+    uint32_t div_denom = 1;
+    uint32_t div_numer = 0;
+    uint32_t div_inter = sclk / mclk;
+    uint32_t freq_diff = sclk % mclk;
+
+    if (freq_diff) {
+        float decimal = freq_diff / (float)mclk;
+        // Carry bit if the decimal is greater than 1.0 - 1.0 / (I2S_LL_MCLK_DIVIDER_MAX * 2)
+        if (decimal <= 1.0 - 1.0 / (float)(I2S_LL_MCLK_DIVIDER_MAX * 2)) {
+            for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
+                int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
+                ma = freq_diff * a;
+                mb = mclk * b;
+                if (ma == mb) {
+                    div_denom = (uint32_t)a;
+                    div_numer = (uint32_t)b;
+                    break;
+                }
+                if (abs(mb - ma) < min) {
+                    div_denom = (uint32_t)a;
+                    div_numer = (uint32_t)b;
+                    min = abs(mb - ma);
+                }
+            }
+        } else {
+            div_inter++;
+        }
+    }
+    mclk_div->integ = div_inter;
+    mclk_div->denom = div_denom;
+    mclk_div->numer = div_numer;
+}
+
 void i2s_hal_init(i2s_hal_context_t *hal, int port_id)
 {
     /* Get hardware instance */
@@ -32,23 +79,27 @@ void i2s_hal_init(i2s_hal_context_t *hal, int port_id)
 
 void i2s_hal_set_tx_clock(i2s_hal_context_t *hal, const i2s_hal_clock_info_t *clk_info, i2s_clock_src_t clk_src)
 {
+    i2s_ll_mclk_div_t mclk_div = {};
 #if SOC_I2S_HW_VERSION_2
     i2s_ll_tx_enable_clock(hal->dev);
     i2s_ll_mclk_bind_to_tx_clk(hal->dev);
 #endif
     i2s_ll_tx_clk_set_src(hal->dev, clk_src);
-    i2s_ll_tx_set_mclk(hal->dev, clk_info->sclk, clk_info->mclk, clk_info->mclk_div);
+    i2s_hal_calc_mclk_precise_division(clk_info->sclk, clk_info->mclk, &mclk_div);
+    i2s_ll_tx_set_mclk(hal->dev, &mclk_div);
     i2s_ll_tx_set_bck_div_num(hal->dev, clk_info->bclk_div);
 }
 
 void i2s_hal_set_rx_clock(i2s_hal_context_t *hal, const i2s_hal_clock_info_t *clk_info, i2s_clock_src_t clk_src)
 {
+    i2s_ll_mclk_div_t mclk_div = {};
 #if SOC_I2S_HW_VERSION_2
     i2s_ll_rx_enable_clock(hal->dev);
     i2s_ll_mclk_bind_to_rx_clk(hal->dev);
 #endif
     i2s_ll_rx_clk_set_src(hal->dev, clk_src);
-    i2s_ll_rx_set_mclk(hal->dev, clk_info->sclk, clk_info->mclk, clk_info->mclk_div);
+    i2s_hal_calc_mclk_precise_division(clk_info->sclk, clk_info->mclk, &mclk_div);
+    i2s_ll_rx_set_mclk(hal->dev, &mclk_div);
     i2s_ll_rx_set_bck_div_num(hal->dev, clk_info->bclk_div);
 }
 
@@ -200,7 +251,7 @@ void i2s_hal_pdm_set_rx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_ha
     i2s_ll_rx_enable_msb_right(hal->dev, false);
     i2s_ll_rx_enable_right_first(hal->dev, false);
 #elif SOC_I2S_HW_VERSION_2
-    i2s_ll_tx_set_half_sample_bit(hal->dev, 16);
+    i2s_ll_rx_set_half_sample_bit(hal->dev, 16);
     i2s_ll_rx_enable_mono_mode(hal->dev, false);
 #if SOC_I2S_PDM_MAX_RX_LINES > 1
     uint32_t slot_mask = (slot_cfg->slot_mode == I2S_SLOT_MODE_STEREO && slot_cfg->pdm_rx.slot_mask <= I2S_PDM_SLOT_BOTH) ?
diff --git a/components/hal/include/hal/i2s_hal.h b/components/hal/include/hal/i2s_hal.h
index 573d1f770f..7a76741f9f 100644
--- a/components/hal/include/hal/i2s_hal.h
+++ b/components/hal/include/hal/i2s_hal.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -120,6 +120,15 @@ typedef struct {
  */
 void i2s_hal_init(i2s_hal_context_t *hal, int port_id);
 
+/**
+ * @brief Helper function for calculating the precise mclk division by sclk and mclk
+ *
+ * @param sclk      system clock
+ * @param mclk      module clock
+ * @param mclk_div  mclk division coefficients, including integer part and decimal part
+ */
+void i2s_hal_calc_mclk_precise_division(uint32_t sclk, uint32_t mclk, i2s_ll_mclk_div_t *mclk_div);
+
 /**
  * @brief Set tx channel clock
  *
diff --git a/components/soc/esp32c3/include/soc/i2s_struct.h b/components/soc/esp32c3/include/soc/i2s_struct.h
index 8e27e2b702..e0c10e91e9 100644
--- a/components/soc/esp32c3/include/soc/i2s_struct.h
+++ b/components/soc/esp32c3/include/soc/i2s_struct.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
diff --git a/components/soc/esp32c6/include/soc/i2s_struct.h b/components/soc/esp32c6/include/soc/i2s_struct.h
index 4b019c334a..e2e4de298c 100644
--- a/components/soc/esp32c6/include/soc/i2s_struct.h
+++ b/components/soc/esp32c6/include/soc/i2s_struct.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
diff --git a/components/soc/esp32s3/include/soc/i2s_struct.h b/components/soc/esp32s3/include/soc/i2s_struct.h
index b048961085..2ad9b84d51 100644
--- a/components/soc/esp32s3/include/soc/i2s_struct.h
+++ b/components/soc/esp32s3/include/soc/i2s_struct.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */