diff --git a/components/bootloader_support/src/bootloader_efuse_esp32.c b/components/bootloader_support/src/bootloader_efuse_esp32.c
index 646ba3e9c7..3704e16c3a 100644
--- a/components/bootloader_support/src/bootloader_efuse_esp32.c
+++ b/components/bootloader_support/src/bootloader_efuse_esp32.c
@@ -27,6 +27,11 @@ uint8_t bootloader_common_get_chip_revision(void)
     case 3:
         chip_ver = 2;
         break;
+#if CONFIG_IDF_ENV_FPGA
+    case 4: /* Empty efuses, but APB_CTRL_DATE_REG bit is set */
+        chip_ver = 3;
+        break;
+#endif
     case 7:
         chip_ver = 3;
         break;
diff --git a/components/esp32/Kconfig b/components/esp32/Kconfig
index 2d7cdbdae0..3f43c7e72b 100644
--- a/components/esp32/Kconfig
+++ b/components/esp32/Kconfig
@@ -40,10 +40,14 @@ menu "ESP32-specific"
 
     choice ESP32_DEFAULT_CPU_FREQ_MHZ
         prompt "CPU frequency"
+        default ESP32_DEFAULT_CPU_FREQ_40 if IDF_ENV_FPGA
         default ESP32_DEFAULT_CPU_FREQ_160
         help
             CPU frequency to be set on application startup.
 
+        config ESP32_DEFAULT_CPU_FREQ_40
+            bool "40 MHz"
+            depends on IDF_ENV_FPGA
         config ESP32_DEFAULT_CPU_FREQ_80
             bool "80 MHz"
         config ESP32_DEFAULT_CPU_FREQ_160
@@ -54,6 +58,7 @@ menu "ESP32-specific"
 
     config ESP32_DEFAULT_CPU_FREQ_MHZ
         int
+        default 40 if ESP32_DEFAULT_CPU_FREQ_40
         default 80 if ESP32_DEFAULT_CPU_FREQ_80
         default 160 if ESP32_DEFAULT_CPU_FREQ_160
         default 240 if ESP32_DEFAULT_CPU_FREQ_240
diff --git a/components/esp_hw_support/port/esp32/rtc_clk.c b/components/esp_hw_support/port/esp32/rtc_clk.c
index b10eb6c518..79365bb181 100644
--- a/components/esp_hw_support/port/esp32/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32/rtc_clk.c
@@ -768,6 +768,9 @@ void rtc_clk_apb_freq_update(uint32_t apb_freq)
 
 uint32_t rtc_clk_apb_freq_get(void)
 {
+#if CONFIG_IDF_ENV_FPGA
+    return CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ * MHZ;
+#endif // CONFIG_IDF_ENV_FPGA
     uint32_t freq_hz = reg_val_to_clk_val(READ_PERI_REG(RTC_APB_FREQ_REG)) << 12;
     // round to the nearest MHz
     freq_hz += MHZ / 2;
diff --git a/components/esp_hw_support/port/esp32/rtc_clk_init.c b/components/esp_hw_support/port/esp32/rtc_clk_init.c
index 04c93c2fa6..c058c7c63e 100644
--- a/components/esp_hw_support/port/esp32/rtc_clk_init.c
+++ b/components/esp_hw_support/port/esp32/rtc_clk_init.c
@@ -140,7 +140,9 @@ void rtc_clk_init(rtc_clk_config_t cfg)
 
 static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void)
 {
-#ifndef CONFIG_IDF_ENV_FPGA
+#if CONFIG_IDF_ENV_FPGA
+    return RTC_XTAL_FREQ_40M;
+#endif // CONFIG_IDF_ENV_FPGA
     /* Enable 8M/256 clock if needed */
     const bool clk_8m_enabled = rtc_clk_8m_enabled();
     const bool clk_8md256_enabled = rtc_clk_8md256_enabled();
@@ -173,8 +175,4 @@ static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void)
     }
     /* Restore 8M and 8md256 clocks to original state */
     rtc_clk_8m_enable(clk_8m_enabled, clk_8md256_enabled);
-
-#else // CONFIG_IDF_ENV_FPGA
-    return RTC_XTAL_FREQ_40M;
-#endif // CONFIG_IDF_ENV_FPGA
 }
diff --git a/components/esp_system/fpga_overrides.c b/components/esp_system/fpga_overrides.c
index acb1fb38e4..407ab09634 100644
--- a/components/esp_system/fpga_overrides.c
+++ b/components/esp_system/fpga_overrides.c
@@ -13,6 +13,9 @@
 // limitations under the License.
 #include "sdkconfig.h"
 #include "soc/soc.h"
+#ifndef CONFIG_IDF_TARGET_ESP32
+#include "soc/system_reg.h"
+#endif // not CONFIG_IDF_TARGET_ESP32
 #include "soc/rtc.h"
 #include "soc/rtc_cntl_reg.h"
 #include "esp_log.h"