diff --git a/Kconfig b/Kconfig index f480355275..3ed5600cb8 100644 --- a/Kconfig +++ b/Kconfig @@ -45,19 +45,6 @@ mainmenu "Espressif IoT Development Framework Configuration" default "y" if IDF_TARGET="esp32s3" select IDF_TARGET_ARCH_XTENSA - choice IDF_TARGET_ESP32S3_BETA_VERSION - prompt "ESP32-S3 beta version" - depends on IDF_TARGET_ESP32S3 - default IDF_TARGET_ESP32S3_BETA_VERSION_3 - help - Currently ESP32-S3 has several beta versions for internal use only. - Select the one that matches your chip model. - - config IDF_TARGET_ESP32S3_BETA_VERSION_3 - bool - prompt "ESP32-S3 beta3" - endchoice - config IDF_TARGET_ESP32C3 bool default "y" if IDF_TARGET="esp32c3" @@ -73,7 +60,7 @@ mainmenu "Espressif IoT Development Framework Configuration" default 0x0000 if IDF_TARGET_ESP32 default 0x0002 if IDF_TARGET_ESP32S2 default 0x0005 if IDF_TARGET_ESP32C3 - default 0x0006 if IDF_TARGET_ESP32S3 + default 0x0009 if IDF_TARGET_ESP32S3 default 0xFFFF menu "SDK tool configuration" diff --git a/components/bootloader_support/include/esp_app_format.h b/components/bootloader_support/include/esp_app_format.h index 9be8784d3b..6390855b56 100644 --- a/components/bootloader_support/include/esp_app_format.h +++ b/components/bootloader_support/include/esp_app_format.h @@ -15,7 +15,7 @@ typedef enum { ESP_CHIP_ID_ESP32 = 0x0000, /*!< chip ID: ESP32 */ ESP_CHIP_ID_ESP32S2 = 0x0002, /*!< chip ID: ESP32-S2 */ ESP_CHIP_ID_ESP32C3 = 0x0005, /*!< chip ID: ESP32-C3 */ - ESP_CHIP_ID_ESP32S3 = 0x0006, /*!< chip ID: ESP32-S3 */ + ESP_CHIP_ID_ESP32S3 = 0x0009, /*!< chip ID: ESP32-S3 */ ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */ } __attribute__((packed)) esp_chip_id_t; diff --git a/components/esp_hw_support/port/esp32s3/rtc_init.c b/components/esp_hw_support/port/esp32s3/rtc_init.c index d2ff24f8bb..2aa7a3fd0a 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_init.c +++ b/components/esp_hw_support/port/esp32s3/rtc_init.c @@ -86,9 +86,6 @@ void rtc_init(rtc_config_t cfg) } else { SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU); } - // CLEAR APLL close - CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); - SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); //open sar_i2c protect function to avoid sar_i2c reset when rtc_ldo is low. CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD); diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld index 1c64375cab..4be3d3559f 100644 --- a/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld +++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld @@ -30,11 +30,9 @@ PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch ); PROVIDE ( esp_rom_uart_usb_acm_init = Uart_Init_USB ); PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); -/* wpa_supplicant re-implements the MD5 functions: MD5Init, MD5Update, MD5Final */ -/* so here we directly assign the symbols with the ROM API address */ -PROVIDE ( esp_rom_md5_init = 0x40001ac4 ); -PROVIDE ( esp_rom_md5_update = 0x40001ad0 ); -PROVIDE ( esp_rom_md5_final = 0x40001adc ); +PROVIDE ( esp_rom_md5_init = MD5Init ); +PROVIDE ( esp_rom_md5_update = MD5Update ); +PROVIDE ( esp_rom_md5_final = MD5Final ); PROVIDE ( esp_rom_printf = ets_printf ); PROVIDE ( esp_rom_delay_us = ets_delay_us ); diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld index 8dc27077e2..229c794885 100644 --- a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld +++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld @@ -1,7 +1,7 @@ /* ROM function interface esp32s3.rom.ld for esp32s3 * * - * Generated from ./interface-esp32s3.yml md5sum 36d43c36b9d0f4f082f71c819ad53470 + * Generated from ./interface-esp32s3.yml md5sum 39c4ce259b11323b9404c192b01b712b * * Compatible with ROM where ECO version equal or greater to 0. * @@ -58,7 +58,7 @@ UartDwnLdProc = 0x40000768; Uart_Init = 0x40000774; ets_set_user_start = 0x40000780; /* Data (.data, .bss, .rodata) */ -ets_rom_layout_p = 0x3ff0fffc; +ets_rom_layout_p = 0x3ff1fffc; ets_ops_table_ptr = 0x3fcefffc; @@ -95,6 +95,14 @@ jd_prepare = 0x40000858; jd_decomp = 0x40000864; +/*************************************** + Group esp-dsp + ***************************************/ + +/* Data (.data, .bss, .rodata) */ +dsps_fft2r_w_table_fc32_1024 = 0x3fcefff8; + + /*************************************** Group opi_flash ***************************************/ @@ -111,17 +119,18 @@ PROVIDE( esp_rom_opiflash_soft_reset = 0x400008c4 ); PROVIDE( esp_rom_opiflash_read_id = 0x400008d0 ); PROVIDE( esp_rom_opiflash_rdsr = 0x400008dc ); PROVIDE( esp_rom_opiflash_wait_idle = 0x400008e8 ); -PROVIDE( esp_rom_opiflash_rdcr2 = 0x400008f4 ); -PROVIDE( esp_rom_opiflash_wrcr2 = 0x40000900 ); -PROVIDE( esp_rom_opiflash_erase_sector = 0x4000090c ); -PROVIDE( esp_rom_opiflash_erase_block_64k = 0x40000918 ); -PROVIDE( esp_rom_opiflash_erase_area = 0x40000924 ); -PROVIDE( esp_rom_opiflash_read = 0x40000930 ); -PROVIDE( esp_rom_opiflash_write = 0x4000093c ); -PROVIDE( esp_rom_opiflash_set_mode = 0x40000948 ); -PROVIDE( esp_rom_spi_set_dtr_swap_mode = 0x40000954 ); -PROVIDE( esp_rom_opiflash_exit_continuous_read_mode = 0x40000960 ); -PROVIDE( opi_flash_wren = 0x4000096c ); +PROVIDE( esp_rom_opiflash_wren = 0x400008f4 ); +PROVIDE( esp_rom_opiflash_erase_sector = 0x40000900 ); +PROVIDE( esp_rom_opiflash_erase_block_64k = 0x4000090c ); +PROVIDE( esp_rom_opiflash_erase_area = 0x40000918 ); +PROVIDE( esp_rom_opiflash_read = 0x40000924 ); +PROVIDE( esp_rom_opiflash_write = 0x40000930 ); +PROVIDE( esp_rom_spi_set_dtr_swap_mode = 0x4000093c ); +PROVIDE( esp_rom_opiflash_exit_continuous_read_mode = 0x40000948 ); +PROVIDE( esp_rom_opiflash_legacy_driver_init = 0x40000954 ); +/* Data (.data, .bss, .rodata) */ +PROVIDE( rom_opiflash_cmd_def = 0x3fcefff4 ); +PROVIDE( rom_spi_usr_cmd_legacy_funcs = 0x3fcefff0 ); /*************************************** @@ -129,103 +138,133 @@ PROVIDE( opi_flash_wren = 0x4000096c ); ***************************************/ /* Functions */ -PROVIDE( esp_rom_spiflash_wait_idle = 0x40000978 ); -PROVIDE( esp_rom_spiflash_write_encrypted = 0x40000984 ); -PROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000990 ); -PROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x4000099c ); -PROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x400009a8 ); -PROVIDE( esp_rom_spiflash_erase_chip = 0x400009b4 ); -PROVIDE( esp_rom_spiflash_erase_block = 0x400009c0 ); -PROVIDE( esp_rom_spiflash_erase_sector = 0x400009cc ); -PROVIDE( esp_rom_spiflash_write = 0x400009d8 ); -PROVIDE( esp_rom_spiflash_read = 0x400009e4 ); -PROVIDE( esp_rom_spiflash_config_param = 0x400009f0 ); -PROVIDE( esp_rom_spiflash_read_user_cmd = 0x400009fc ); -PROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000a08 ); -PROVIDE( esp_rom_spiflash_unlock = 0x40000a14 ); -PROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000a20 ); -PROVIDE( esp_rom_spi_flash_send_resume = 0x40000a2c ); -PROVIDE( esp_rom_spi_flash_update_id = 0x40000a38 ); -PROVIDE( esp_rom_spiflash_config_clk = 0x40000a44 ); -PROVIDE( esp_rom_spiflash_config_readmode = 0x40000a50 ); -PROVIDE( esp_rom_spiflash_read_status = 0x40000a5c ); -PROVIDE( esp_rom_spiflash_read_statushigh = 0x40000a68 ); -PROVIDE( esp_rom_spiflash_write_status = 0x40000a74 ); -PROVIDE( esp_rom_opiflash_cache_mode_config = 0x40000a80 ); -PROVIDE( esp_rom_spiflash_auto_wait_idle = 0x40000a8c ); -PROVIDE( esp_rom_spiflash_write_disable = 0x40000a98 ); -PROVIDE( spi_flash_attach = 0x40000aa4 ); -PROVIDE( spi_flash_get_chip_size = 0x40000ab0 ); -PROVIDE( spi_flash_guard_set = 0x40000abc ); -PROVIDE( spi_flash_guard_get = 0x40000ac8 ); -PROVIDE( spi_flash_write_config_set = 0x40000ad4 ); -PROVIDE( spi_flash_write_config_get = 0x40000ae0 ); -PROVIDE( spi_flash_safe_write_address_func_set = 0x40000aec ); -PROVIDE( spi_flash_unlock = 0x40000af8 ); -PROVIDE( spi_flash_erase_range = 0x40000b04 ); -PROVIDE( spi_flash_erase_sector = 0x40000b10 ); -PROVIDE( spi_flash_write = 0x40000b1c ); -PROVIDE( spi_flash_read = 0x40000b28 ); -PROVIDE( spi_flash_write_encrypted = 0x40000b34 ); -PROVIDE( spi_flash_read_encrypted = 0x40000b40 ); -PROVIDE( spi_flash_mmap_os_func_set = 0x40000b4c ); -PROVIDE( spi_flash_mmap_page_num_init = 0x40000b58 ); -PROVIDE( spi_flash_mmap = 0x40000b64 ); -PROVIDE( spi_flash_mmap_pages = 0x40000b70 ); -PROVIDE( spi_flash_munmap = 0x40000b7c ); -PROVIDE( spi_flash_mmap_dump = 0x40000b88 ); -PROVIDE( spi_flash_check_and_flush_cache = 0x40000b94 ); -PROVIDE( spi_flash_mmap_get_free_pages = 0x40000ba0 ); -PROVIDE( spi_flash_cache2phys = 0x40000bac ); -PROVIDE( spi_flash_phys2cache = 0x40000bb8 ); -PROVIDE( spi_flash_disable_cache = 0x40000bc4 ); -PROVIDE( spi_flash_restore_cache = 0x40000bd0 ); -PROVIDE( spi_flash_cache_enabled = 0x40000bdc ); -PROVIDE( spi_flash_enable_cache = 0x40000be8 ); -PROVIDE( spi_cache_mode_switch = 0x40000bf4 ); -PROVIDE( spi_common_set_dummy_output = 0x40000c00 ); -PROVIDE( spi_common_set_flash_cs_timing = 0x40000c0c ); -PROVIDE( esp_enable_cache_flash_wrap = 0x40000c18 ); -PROVIDE( SPIEraseArea = 0x40000c24 ); -PROVIDE( SPILock = 0x40000c30 ); -PROVIDE( SPIMasterReadModeCnfig = 0x40000c3c ); -PROVIDE( SPI_Common_Command = 0x40000c48 ); -PROVIDE( SPI_WakeUp = 0x40000c54 ); -PROVIDE( SPI_block_erase = 0x40000c60 ); -PROVIDE( SPI_chip_erase = 0x40000c6c ); -PROVIDE( SPI_init = 0x40000c78 ); -PROVIDE( SPI_page_program = 0x40000c84 ); -PROVIDE( SPI_read_data = 0x40000c90 ); -PROVIDE( SPI_sector_erase = 0x40000c9c ); -PROVIDE( SPI_write_enable = 0x40000ca8 ); -PROVIDE( SelectSpiFunction = 0x40000cb4 ); -PROVIDE( SetSpiDrvs = 0x40000cc0 ); -PROVIDE( Wait_SPI_Idle = 0x40000ccc ); -PROVIDE( spi_dummy_len_fix = 0x40000cd8 ); -PROVIDE( Disable_QMode = 0x40000ce4 ); -PROVIDE( Enable_QMode = 0x40000cf0 ); +PROVIDE( esp_rom_spiflash_wait_idle = 0x40000960 ); +PROVIDE( esp_rom_spiflash_write_encrypted = 0x4000096c ); +PROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000978 ); +PROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000984 ); +PROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x40000990 ); +PROVIDE( esp_rom_spiflash_erase_chip = 0x4000099c ); +PROVIDE( _esp_rom_spiflash_erase_sector = 0x400009a8 ); +PROVIDE( _esp_rom_spiflash_erase_block = 0x400009b4 ); +PROVIDE( _esp_rom_spiflash_write = 0x400009c0 ); +PROVIDE( _esp_rom_spiflash_read = 0x400009cc ); +PROVIDE( _esp_rom_spiflash_unlock = 0x400009d8 ); +PROVIDE( _SPIEraseArea = 0x400009e4 ); +PROVIDE( _SPI_write_enable = 0x400009f0 ); +PROVIDE( esp_rom_spiflash_erase_sector = 0x400009fc ); +PROVIDE( esp_rom_spiflash_erase_block = 0x40000a08 ); +PROVIDE( esp_rom_spiflash_write = 0x40000a14 ); +PROVIDE( esp_rom_spiflash_read = 0x40000a20 ); +PROVIDE( esp_rom_spiflash_unlock = 0x40000a2c ); +PROVIDE( SPIEraseArea = 0x40000a38 ); +PROVIDE( SPI_write_enable = 0x40000a44 ); +PROVIDE( esp_rom_spiflash_config_param = 0x40000a50 ); +PROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000a5c ); +PROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000a68 ); +PROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000a74 ); +PROVIDE( esp_rom_spi_flash_send_resume = 0x40000a80 ); +PROVIDE( esp_rom_spi_flash_update_id = 0x40000a8c ); +PROVIDE( esp_rom_spiflash_config_clk = 0x40000a98 ); +PROVIDE( esp_rom_spiflash_config_readmode = 0x40000aa4 ); +PROVIDE( esp_rom_spiflash_read_status = 0x40000ab0 ); +PROVIDE( esp_rom_spiflash_read_statushigh = 0x40000abc ); +PROVIDE( esp_rom_spiflash_write_status = 0x40000ac8 ); +PROVIDE( esp_rom_opiflash_cache_mode_config = 0x40000ad4 ); +PROVIDE( esp_rom_spiflash_auto_wait_idle = 0x40000ae0 ); +PROVIDE( spi_flash_attach = 0x40000aec ); +PROVIDE( spi_flash_get_chip_size = 0x40000af8 ); +PROVIDE( spi_flash_guard_set = 0x40000b04 ); +PROVIDE( spi_flash_guard_get = 0x40000b10 ); +PROVIDE( spi_flash_write_config_set = 0x40000b1c ); +PROVIDE( spi_flash_write_config_get = 0x40000b28 ); +PROVIDE( spi_flash_safe_write_address_func_set = 0x40000b34 ); +PROVIDE( spi_flash_unlock = 0x40000b40 ); +PROVIDE( spi_flash_erase_range = 0x40000b4c ); +PROVIDE( spi_flash_erase_sector = 0x40000b58 ); +PROVIDE( spi_flash_write = 0x40000b64 ); +PROVIDE( spi_flash_read = 0x40000b70 ); +PROVIDE( spi_flash_write_encrypted = 0x40000b7c ); +PROVIDE( spi_flash_read_encrypted = 0x40000b88 ); +PROVIDE( spi_flash_mmap_os_func_set = 0x40000b94 ); +PROVIDE( spi_flash_mmap_page_num_init = 0x40000ba0 ); +PROVIDE( spi_flash_mmap = 0x40000bac ); +PROVIDE( spi_flash_mmap_pages = 0x40000bb8 ); +PROVIDE( spi_flash_munmap = 0x40000bc4 ); +PROVIDE( spi_flash_mmap_dump = 0x40000bd0 ); +PROVIDE( spi_flash_check_and_flush_cache = 0x40000bdc ); +PROVIDE( spi_flash_mmap_get_free_pages = 0x40000be8 ); +PROVIDE( spi_flash_cache2phys = 0x40000bf4 ); +PROVIDE( spi_flash_phys2cache = 0x40000c00 ); +PROVIDE( spi_flash_disable_cache = 0x40000c0c ); +PROVIDE( spi_flash_restore_cache = 0x40000c18 ); +PROVIDE( spi_flash_cache_enabled = 0x40000c24 ); +PROVIDE( spi_flash_enable_cache = 0x40000c30 ); +PROVIDE( spi_cache_mode_switch = 0x40000c3c ); +PROVIDE( spi_common_set_dummy_output = 0x40000c48 ); +PROVIDE( spi_common_set_flash_cs_timing = 0x40000c54 ); +PROVIDE( esp_rom_spi_set_address_bit_len = 0x40000c60 ); +PROVIDE( esp_enable_cache_flash_wrap = 0x40000c6c ); +PROVIDE( SPILock = 0x40000c78 ); +PROVIDE( SPIMasterReadModeCnfig = 0x40000c84 ); +PROVIDE( SPI_Common_Command = 0x40000c90 ); +PROVIDE( SPI_WakeUp = 0x40000c9c ); +PROVIDE( SPI_block_erase = 0x40000ca8 ); +PROVIDE( SPI_chip_erase = 0x40000cb4 ); +PROVIDE( SPI_init = 0x40000cc0 ); +PROVIDE( SPI_page_program = 0x40000ccc ); +PROVIDE( SPI_read_data = 0x40000cd8 ); +PROVIDE( SPI_sector_erase = 0x40000ce4 ); +PROVIDE( SelectSpiFunction = 0x40000cf0 ); +PROVIDE( SetSpiDrvs = 0x40000cfc ); +PROVIDE( Wait_SPI_Idle = 0x40000d08 ); +PROVIDE( spi_dummy_len_fix = 0x40000d14 ); +PROVIDE( Disable_QMode = 0x40000d20 ); +PROVIDE( Enable_QMode = 0x40000d2c ); /* Data (.data, .bss, .rodata) */ -PROVIDE( rom_spiflash_legacy_funcs = 0x3fcefff4 ); -PROVIDE( rom_spiflash_legacy_data = 0x3fcefff0 ); -PROVIDE( g_flash_guard_ops = 0x3fcefff8 ); +PROVIDE( rom_spiflash_legacy_funcs = 0x3fceffe8 ); +PROVIDE( rom_spiflash_legacy_data = 0x3fceffe4 ); +PROVIDE( g_flash_guard_ops = 0x3fceffec ); /*************************************** - Group spi_flash_hal + Group hal_soc ***************************************/ /* Functions */ -PROVIDE( spi_flash_hal_poll_cmd_done = 0x40000cfc ); -PROVIDE( spi_flash_hal_device_config = 0x40000d08 ); -PROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000d14 ); -PROVIDE( spi_flash_hal_common_command = 0x40000d20 ); -PROVIDE( spi_flash_hal_read = 0x40000d2c ); -PROVIDE( spi_flash_hal_erase_chip = 0x40000d38 ); -PROVIDE( spi_flash_hal_erase_sector = 0x40000d44 ); -PROVIDE( spi_flash_hal_erase_block = 0x40000d50 ); -PROVIDE( spi_flash_hal_program_page = 0x40000d5c ); -PROVIDE( spi_flash_hal_set_write_protect = 0x40000d68 ); -PROVIDE( spi_flash_hal_host_idle = 0x40000d74 ); +PROVIDE( spi_flash_hal_poll_cmd_done = 0x40000d38 ); +PROVIDE( spi_flash_hal_device_config = 0x40000d44 ); +PROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000d50 ); +PROVIDE( spi_flash_hal_common_command = 0x40000d5c ); +PROVIDE( spi_flash_hal_read = 0x40000d68 ); +PROVIDE( spi_flash_hal_erase_chip = 0x40000d74 ); +PROVIDE( spi_flash_hal_erase_sector = 0x40000d80 ); +PROVIDE( spi_flash_hal_erase_block = 0x40000d8c ); +PROVIDE( spi_flash_hal_program_page = 0x40000d98 ); +PROVIDE( spi_flash_hal_set_write_protect = 0x40000da4 ); +PROVIDE( spi_flash_hal_host_idle = 0x40000db0 ); +PROVIDE( wdt_hal_init = 0x40000dbc ); +PROVIDE( wdt_hal_deinit = 0x40000dc8 ); +PROVIDE( wdt_hal_config_stage = 0x40000dd4 ); +PROVIDE( wdt_hal_write_protect_disable = 0x40000de0 ); +PROVIDE( wdt_hal_write_protect_enable = 0x40000dec ); +PROVIDE( wdt_hal_enable = 0x40000df8 ); +PROVIDE( wdt_hal_disable = 0x40000e04 ); +PROVIDE( wdt_hal_handle_intr = 0x40000e10 ); +PROVIDE( wdt_hal_feed = 0x40000e1c ); +PROVIDE( wdt_hal_set_flashboot_en = 0x40000e28 ); +PROVIDE( wdt_hal_is_enabled = 0x40000e34 ); +PROVIDE( systimer_hal_get_counter_value = 0x40000e40 ); +PROVIDE( systimer_hal_get_time = 0x40000e4c ); +PROVIDE( systimer_hal_set_alarm_target = 0x40000e58 ); +PROVIDE( systimer_hal_set_alarm_period = 0x40000e64 ); +PROVIDE( systimer_hal_get_alarm_value = 0x40000e70 ); +PROVIDE( systimer_hal_enable_alarm_int = 0x40000e7c ); +PROVIDE( systimer_hal_on_apb_freq_update = 0x40000e88 ); +PROVIDE( systimer_hal_counter_value_advance = 0x40000e94 ); +PROVIDE( systimer_hal_enable_counter = 0x40000ea0 ); +PROVIDE( systimer_hal_init = 0x40000eac ); +PROVIDE( systimer_hal_select_alarm_mode = 0x40000eb8 ); +PROVIDE( systimer_hal_connect_alarm_counter = 0x40000ec4 ); /*************************************** @@ -233,37 +272,37 @@ PROVIDE( spi_flash_hal_host_idle = 0x40000d74 ); ***************************************/ /* Functions */ -PROVIDE( spi_flash_chip_generic_probe = 0x40000d80 ); -PROVIDE( spi_flash_chip_generic_detect_size = 0x40000d8c ); -PROVIDE( spi_flash_chip_generic_write = 0x40000d98 ); -PROVIDE( spi_flash_chip_generic_write_encrypted = 0x40000da4 ); -PROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000db0 ); -PROVIDE( spi_flash_common_write_status_16b_wrsr = 0x40000dbc ); -PROVIDE( spi_flash_chip_generic_reset = 0x40000dc8 ); -PROVIDE( spi_flash_chip_generic_erase_chip = 0x40000dd4 ); -PROVIDE( spi_flash_chip_generic_erase_sector = 0x40000de0 ); -PROVIDE( spi_flash_chip_generic_erase_block = 0x40000dec ); -PROVIDE( spi_flash_chip_generic_page_program = 0x40000df8 ); -PROVIDE( spi_flash_chip_generic_get_write_protect = 0x40000e04 ); -PROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x40000e10 ); -PROVIDE( spi_flash_chip_generic_read_reg = 0x40000e1c ); -PROVIDE( spi_flash_chip_generic_yield = 0x40000e28 ); -PROVIDE( spi_flash_generic_wait_host_idle = 0x40000e34 ); -PROVIDE( spi_flash_chip_generic_wait_idle = 0x40000e40 ); -PROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x40000e4c ); -PROVIDE( spi_flash_chip_generic_read = 0x40000e58 ); -PROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x40000e64 ); -PROVIDE( spi_flash_chip_generic_get_io_mode = 0x40000e70 ); -PROVIDE( spi_flash_common_read_status_8b_rdsr = 0x40000e7c ); -PROVIDE( spi_flash_common_write_status_8b_wrsr = 0x40000e88 ); -PROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x40000e94 ); -PROVIDE( spi_flash_common_set_io_mode = 0x40000ea0 ); -PROVIDE( spi_flash_chip_generic_set_io_mode = 0x40000eac ); -PROVIDE( spi_flash_chip_gd_get_io_mode = 0x40000eb8 ); -PROVIDE( spi_flash_chip_gd_probe = 0x40000ec4 ); -PROVIDE( spi_flash_chip_gd_set_io_mode = 0x40000ed0 ); +PROVIDE( spi_flash_chip_generic_probe = 0x40000ed0 ); +PROVIDE( spi_flash_chip_generic_detect_size = 0x40000edc ); +PROVIDE( spi_flash_chip_generic_write = 0x40000ee8 ); +PROVIDE( spi_flash_chip_generic_write_encrypted = 0x40000ef4 ); +PROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000f00 ); +PROVIDE( spi_flash_common_write_status_16b_wrsr = 0x40000f0c ); +PROVIDE( spi_flash_chip_generic_reset = 0x40000f18 ); +PROVIDE( spi_flash_chip_generic_erase_chip = 0x40000f24 ); +PROVIDE( spi_flash_chip_generic_erase_sector = 0x40000f30 ); +PROVIDE( spi_flash_chip_generic_erase_block = 0x40000f3c ); +PROVIDE( spi_flash_chip_generic_page_program = 0x40000f48 ); +PROVIDE( spi_flash_chip_generic_get_write_protect = 0x40000f54 ); +PROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x40000f60 ); +PROVIDE( spi_flash_chip_generic_read_reg = 0x40000f6c ); +PROVIDE( spi_flash_chip_generic_yield = 0x40000f78 ); +PROVIDE( spi_flash_generic_wait_host_idle = 0x40000f84 ); +PROVIDE( spi_flash_chip_generic_wait_idle = 0x40000f90 ); +PROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x40000f9c ); +PROVIDE( spi_flash_chip_generic_read = 0x40000fa8 ); +PROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x40000fb4 ); +PROVIDE( spi_flash_chip_generic_get_io_mode = 0x40000fc0 ); +PROVIDE( spi_flash_common_read_status_8b_rdsr = 0x40000fcc ); +PROVIDE( spi_flash_common_write_status_8b_wrsr = 0x40000fd8 ); +PROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x40000fe4 ); +PROVIDE( spi_flash_common_set_io_mode = 0x40000ff0 ); +PROVIDE( spi_flash_chip_generic_set_io_mode = 0x40000ffc ); +PROVIDE( spi_flash_chip_gd_get_io_mode = 0x40001008 ); +PROVIDE( spi_flash_chip_gd_probe = 0x40001014 ); +PROVIDE( spi_flash_chip_gd_set_io_mode = 0x40001020 ); /* Data (.data, .bss, .rodata) */ -PROVIDE( spi_flash_chip_generic_config_data = 0x3fceffec ); +PROVIDE( spi_flash_chip_generic_config_data = 0x3fceffe0 ); /*************************************** @@ -271,18 +310,18 @@ PROVIDE( spi_flash_chip_generic_config_data = 0x3fceffec ); ***************************************/ /* Functions */ -PROVIDE( memspi_host_read_id_hs = 0x40000edc ); -PROVIDE( memspi_host_read_status_hs = 0x40000ee8 ); -PROVIDE( memspi_host_flush_cache = 0x40000ef4 ); -PROVIDE( memspi_host_erase_chip = 0x40000f00 ); -PROVIDE( memspi_host_erase_sector = 0x40000f0c ); -PROVIDE( memspi_host_erase_block = 0x40000f18 ); -PROVIDE( memspi_host_program_page = 0x40000f24 ); -PROVIDE( memspi_host_read = 0x40000f30 ); -PROVIDE( memspi_host_set_write_protect = 0x40000f3c ); -PROVIDE( memspi_host_set_max_read_len = 0x40000f48 ); -PROVIDE( memspi_host_read_data_slicer = 0x40000f54 ); -PROVIDE( memspi_host_write_data_slicer = 0x40000f60 ); +PROVIDE( memspi_host_read_id_hs = 0x4000102c ); +PROVIDE( memspi_host_read_status_hs = 0x40001038 ); +PROVIDE( memspi_host_flush_cache = 0x40001044 ); +PROVIDE( memspi_host_erase_chip = 0x40001050 ); +PROVIDE( memspi_host_erase_sector = 0x4000105c ); +PROVIDE( memspi_host_erase_block = 0x40001068 ); +PROVIDE( memspi_host_program_page = 0x40001074 ); +PROVIDE( memspi_host_read = 0x40001080 ); +PROVIDE( memspi_host_set_write_protect = 0x4000108c ); +PROVIDE( memspi_host_set_max_read_len = 0x40001098 ); +PROVIDE( memspi_host_read_data_slicer = 0x400010a4 ); +PROVIDE( memspi_host_write_data_slicer = 0x400010b0 ); /*************************************** @@ -290,30 +329,33 @@ PROVIDE( memspi_host_write_data_slicer = 0x40000f60 ); ***************************************/ /* Functions */ -PROVIDE( esp_flash_chip_driver_initialized = 0x40000f6c ); -PROVIDE( esp_flash_read_id = 0x40000f78 ); -PROVIDE( esp_flash_get_size = 0x40000f84 ); -PROVIDE( esp_flash_erase_chip = 0x40000f90 ); -PROVIDE( esp_flash_erase_region = 0x40000f9c ); -PROVIDE( esp_flash_get_chip_write_protect = 0x40000fa8 ); -PROVIDE( esp_flash_set_chip_write_protect = 0x40000fb4 ); -PROVIDE( esp_flash_get_protectable_regions = 0x40000fc0 ); -PROVIDE( esp_flash_get_protected_region = 0x40000fcc ); -PROVIDE( esp_flash_set_protected_region = 0x40000fd8 ); -PROVIDE( esp_flash_read = 0x40000fe4 ); -PROVIDE( esp_flash_write = 0x40000ff0 ); -PROVIDE( esp_flash_write_encrypted = 0x40000ffc ); -PROVIDE( esp_flash_read_encrypted = 0x40001008 ); -PROVIDE( esp_flash_get_io_mode = 0x40001014 ); -PROVIDE( esp_flash_set_io_mode = 0x40001020 ); -PROVIDE( spi_flash_boot_attach = 0x4000102c ); -PROVIDE( spi_flash_dump_counters = 0x40001038 ); -PROVIDE( spi_flash_get_counters = 0x40001044 ); -PROVIDE( spi_flash_op_counters_config = 0x40001050 ); -PROVIDE( spi_flash_reset_counters = 0x4000105c ); +PROVIDE( esp_flash_chip_driver_initialized = 0x400010bc ); +PROVIDE( esp_flash_read_id = 0x400010c8 ); +PROVIDE( esp_flash_get_size = 0x400010d4 ); +PROVIDE( esp_flash_erase_chip = 0x400010e0 ); +PROVIDE( esp_flash_erase_region = 0x400010ec ); +PROVIDE( esp_flash_get_chip_write_protect = 0x400010f8 ); +PROVIDE( esp_flash_set_chip_write_protect = 0x40001104 ); +PROVIDE( esp_flash_get_protectable_regions = 0x40001110 ); +PROVIDE( esp_flash_get_protected_region = 0x4000111c ); +PROVIDE( esp_flash_set_protected_region = 0x40001128 ); +PROVIDE( esp_flash_read = 0x40001134 ); +PROVIDE( esp_flash_write = 0x40001140 ); +PROVIDE( esp_flash_write_encrypted = 0x4000114c ); +PROVIDE( esp_flash_read_encrypted = 0x40001158 ); +PROVIDE( esp_flash_get_io_mode = 0x40001164 ); +PROVIDE( esp_flash_set_io_mode = 0x40001170 ); +PROVIDE( spi_flash_boot_attach = 0x4000117c ); +PROVIDE( spi_flash_dump_counters = 0x40001188 ); +PROVIDE( spi_flash_get_counters = 0x40001194 ); +PROVIDE( spi_flash_op_counters_config = 0x400011a0 ); +PROVIDE( spi_flash_reset_counters = 0x400011ac ); +PROVIDE( esp_flash_read_chip_id = 0x400011b8 ); +PROVIDE( detect_spi_flash_chip = 0x400011c4 ); +PROVIDE( esp_rom_spiflash_write_disable = 0x400011d0 ); /* Data (.data, .bss, .rodata) */ -PROVIDE( esp_flash_default_chip = 0x3fceffe8 ); -PROVIDE( esp_flash_api_funcs = 0x3fceffe4 ); +PROVIDE( esp_flash_default_chip = 0x3fceffdc ); +PROVIDE( esp_flash_api_funcs = 0x3fceffd8 ); /*************************************** @@ -321,96 +363,99 @@ PROVIDE( esp_flash_api_funcs = 0x3fceffe4 ); ***************************************/ /* Functions */ -PROVIDE( Cache_Get_ICache_Line_Size = 0x40001488 ); -PROVIDE( Cache_Get_DCache_Line_Size = 0x40001494 ); -PROVIDE( Cache_Get_Mode = 0x400014a0 ); -PROVIDE( Cache_Set_ICache_Mode = 0x400014ac ); -PROVIDE( Cache_Set_DCache_Mode = 0x400014b8 ); -PROVIDE( Cache_Address_Through_ICache = 0x400014c4 ); -PROVIDE( Cache_Address_Through_DCache = 0x400014d0 ); -PROVIDE( Cache_Set_Default_Mode = 0x400014dc ); -PROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400014e8 ); -PROVIDE( ROM_Boot_Cache_Init = 0x400014f4 ); -PROVIDE( Cache_Invalidate_ICache_Items = 0x40001500 ); -PROVIDE( Cache_Invalidate_DCache_Items = 0x4000150c ); -PROVIDE( Cache_Clean_Items = 0x40001518 ); -PROVIDE( Cache_WriteBack_Items = 0x40001524 ); -PROVIDE( Cache_Op_Addr = 0x40001530 ); -PROVIDE( Cache_Invalidate_Addr = 0x4000153c ); -PROVIDE( Cache_Clean_Addr = 0x40001548 ); -PROVIDE( Cache_WriteBack_Addr = 0x40001554 ); -PROVIDE( Cache_Invalidate_ICache_All = 0x40001560 ); -PROVIDE( Cache_Invalidate_DCache_All = 0x4000156c ); -PROVIDE( Cache_Clean_All = 0x40001578 ); -PROVIDE( Cache_WriteBack_All = 0x40001584 ); -PROVIDE( Cache_Mask_All = 0x40001590 ); -PROVIDE( Cache_UnMask_Dram0 = 0x4000159c ); -PROVIDE( Cache_Suspend_ICache_Autoload = 0x400015a8 ); -PROVIDE( Cache_Resume_ICache_Autoload = 0x400015b4 ); -PROVIDE( Cache_Suspend_DCache_Autoload = 0x400015c0 ); -PROVIDE( Cache_Resume_DCache_Autoload = 0x400015cc ); -PROVIDE( Cache_Start_ICache_Preload = 0x400015d8 ); -PROVIDE( Cache_ICache_Preload_Done = 0x400015e4 ); -PROVIDE( Cache_End_ICache_Preload = 0x400015f0 ); -PROVIDE( Cache_Start_DCache_Preload = 0x400015fc ); -PROVIDE( Cache_DCache_Preload_Done = 0x40001608 ); -PROVIDE( Cache_End_DCache_Preload = 0x40001614 ); -PROVIDE( Cache_Config_ICache_Autoload = 0x40001620 ); -PROVIDE( Cache_Enable_ICache_Autoload = 0x4000162c ); -PROVIDE( Cache_Disable_ICache_Autoload = 0x40001638 ); -PROVIDE( Cache_Config_DCache_Autoload = 0x40001644 ); -PROVIDE( Cache_Enable_DCache_Autoload = 0x40001650 ); -PROVIDE( Cache_Disable_DCache_Autoload = 0x4000165c ); -PROVIDE( Cache_Enable_ICache_PreLock = 0x40001668 ); -PROVIDE( Cache_Disable_ICache_PreLock = 0x40001674 ); -PROVIDE( Cache_Lock_ICache_Items = 0x40001680 ); -PROVIDE( Cache_Unlock_ICache_Items = 0x4000168c ); -PROVIDE( Cache_Enable_DCache_PreLock = 0x40001698 ); -PROVIDE( Cache_Disable_DCache_PreLock = 0x400016a4 ); -PROVIDE( Cache_Lock_DCache_Items = 0x400016b0 ); -PROVIDE( Cache_Unlock_DCache_Items = 0x400016bc ); -PROVIDE( Cache_Lock_Addr = 0x400016c8 ); -PROVIDE( Cache_Unlock_Addr = 0x400016d4 ); -PROVIDE( Cache_Disable_ICache = 0x400016e0 ); -PROVIDE( Cache_Enable_ICache = 0x400016ec ); -PROVIDE( Cache_Disable_DCache = 0x400016f8 ); -PROVIDE( Cache_Enable_DCache = 0x40001704 ); -PROVIDE( Cache_Suspend_ICache = 0x40001710 ); -PROVIDE( Cache_Resume_ICache = 0x4000171c ); -PROVIDE( Cache_Suspend_DCache = 0x40001728 ); -PROVIDE( Cache_Resume_DCache = 0x40001734 ); -PROVIDE( Cache_Occupy_Items = 0x40001740 ); -PROVIDE( Cache_Occupy_Addr = 0x4000174c ); -PROVIDE( Cache_Freeze_ICache_Enable = 0x40001758 ); -PROVIDE( Cache_Freeze_ICache_Disable = 0x40001764 ); -PROVIDE( Cache_Freeze_DCache_Enable = 0x40001770 ); -PROVIDE( Cache_Freeze_DCache_Disable = 0x4000177c ); -PROVIDE( Cache_Set_IDROM_MMU_Size = 0x40001788 ); -PROVIDE( flash2spiram_instruction_offset = 0x40001794 ); -PROVIDE( flash2spiram_rodata_offset = 0x400017a0 ); -PROVIDE( flash_instr_rodata_start_page = 0x400017ac ); -PROVIDE( flash_instr_rodata_end_page = 0x400017b8 ); -PROVIDE( Cache_Set_IDROM_MMU_Info = 0x400017c4 ); -PROVIDE( Cache_Get_IROM_MMU_End = 0x400017d0 ); -PROVIDE( Cache_Get_DROM_MMU_End = 0x400017dc ); -PROVIDE( Cache_Owner_Init = 0x400017e8 ); -PROVIDE( Cache_Occupy_ICache_MEMORY = 0x400017f4 ); -PROVIDE( Cache_Occupy_DCache_MEMORY = 0x40001800 ); -PROVIDE( Cache_MMU_Init = 0x4000180c ); -PROVIDE( Cache_Ibus_MMU_Set = 0x40001818 ); -PROVIDE( Cache_Dbus_MMU_Set = 0x40001824 ); -PROVIDE( Cache_Count_Flash_Pages = 0x40001830 ); -PROVIDE( Cache_Flash_To_SPIRAM_Copy = 0x4000183c ); -PROVIDE( Cache_Travel_Tag_Memory = 0x40001848 ); -PROVIDE( Cache_Get_Virtual_Addr = 0x40001854 ); -PROVIDE( Cache_Get_Memory_BaseAddr = 0x40001860 ); -PROVIDE( Cache_Get_Memory_Addr = 0x4000186c ); -PROVIDE( Cache_Get_Memory_value = 0x40001878 ); -PROVIDE( rom_config_instruction_cache_mode = 0x40001884 ); -PROVIDE( rom_config_data_cache_mode = 0x40001890 ); +PROVIDE( Cache_Get_ICache_Line_Size = 0x400015fc ); +PROVIDE( Cache_Get_DCache_Line_Size = 0x40001608 ); +PROVIDE( Cache_Get_Mode = 0x40001614 ); +PROVIDE( Cache_Set_ICache_Mode = 0x40001620 ); +PROVIDE( Cache_Set_DCache_Mode = 0x4000162c ); +PROVIDE( Cache_Address_Through_ICache = 0x40001638 ); +PROVIDE( Cache_Address_Through_DCache = 0x40001644 ); +PROVIDE( Cache_Set_Default_Mode = 0x40001650 ); +PROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x4000165c ); +PROVIDE( ROM_Boot_Cache_Init = 0x40001668 ); +PROVIDE( Cache_Invalidate_ICache_Items = 0x40001674 ); +PROVIDE( Cache_Invalidate_DCache_Items = 0x40001680 ); +PROVIDE( Cache_Clean_Items = 0x4000168c ); +PROVIDE( Cache_WriteBack_Items = 0x40001698 ); +PROVIDE( Cache_Op_Addr = 0x400016a4 ); +PROVIDE( Cache_Invalidate_Addr = 0x400016b0 ); +PROVIDE( Cache_Clean_Addr = 0x400016bc ); +PROVIDE( Cache_WriteBack_Addr = 0x400016c8 ); +PROVIDE( Cache_Invalidate_ICache_All = 0x400016d4 ); +PROVIDE( Cache_Invalidate_DCache_All = 0x400016e0 ); +PROVIDE( Cache_Clean_All = 0x400016ec ); +PROVIDE( Cache_WriteBack_All = 0x400016f8 ); +PROVIDE( Cache_Mask_All = 0x40001704 ); +PROVIDE( Cache_UnMask_Dram0 = 0x40001710 ); +PROVIDE( Cache_Suspend_ICache_Autoload = 0x4000171c ); +PROVIDE( Cache_Resume_ICache_Autoload = 0x40001728 ); +PROVIDE( Cache_Suspend_DCache_Autoload = 0x40001734 ); +PROVIDE( Cache_Resume_DCache_Autoload = 0x40001740 ); +PROVIDE( Cache_Start_ICache_Preload = 0x4000174c ); +PROVIDE( Cache_ICache_Preload_Done = 0x40001758 ); +PROVIDE( Cache_End_ICache_Preload = 0x40001764 ); +PROVIDE( Cache_Start_DCache_Preload = 0x40001770 ); +PROVIDE( Cache_DCache_Preload_Done = 0x4000177c ); +PROVIDE( Cache_End_DCache_Preload = 0x40001788 ); +PROVIDE( Cache_Config_ICache_Autoload = 0x40001794 ); +PROVIDE( Cache_Config_ICache_Region_Autoload = 0x400017a0 ); +PROVIDE( Cache_Enable_ICache_Autoload = 0x400017ac ); +PROVIDE( Cache_Disable_ICache_Autoload = 0x400017b8 ); +PROVIDE( Cache_Config_DCache_Autoload = 0x400017c4 ); +PROVIDE( Cache_Config_DCache_Region_Autoload = 0x400017d0 ); +PROVIDE( Cache_Enable_DCache_Autoload = 0x400017dc ); +PROVIDE( Cache_Disable_DCache_Autoload = 0x400017e8 ); +PROVIDE( Cache_Enable_ICache_PreLock = 0x400017f4 ); +PROVIDE( Cache_Disable_ICache_PreLock = 0x40001800 ); +PROVIDE( Cache_Lock_ICache_Items = 0x4000180c ); +PROVIDE( Cache_Unlock_ICache_Items = 0x40001818 ); +PROVIDE( Cache_Enable_DCache_PreLock = 0x40001824 ); +PROVIDE( Cache_Disable_DCache_PreLock = 0x40001830 ); +PROVIDE( Cache_Lock_DCache_Items = 0x4000183c ); +PROVIDE( Cache_Unlock_DCache_Items = 0x40001848 ); +PROVIDE( Cache_Lock_Addr = 0x40001854 ); +PROVIDE( Cache_Unlock_Addr = 0x40001860 ); +PROVIDE( Cache_Disable_ICache = 0x4000186c ); +PROVIDE( Cache_Enable_ICache = 0x40001878 ); +PROVIDE( Cache_Disable_DCache = 0x40001884 ); +PROVIDE( Cache_Enable_DCache = 0x40001890 ); +PROVIDE( Cache_Suspend_ICache = 0x4000189c ); +PROVIDE( Cache_Resume_ICache = 0x400018a8 ); +PROVIDE( Cache_Suspend_DCache = 0x400018b4 ); +PROVIDE( Cache_Resume_DCache = 0x400018c0 ); +PROVIDE( Cache_Occupy_Items = 0x400018cc ); +PROVIDE( Cache_Occupy_Addr = 0x400018d8 ); +PROVIDE( Cache_Freeze_ICache_Enable = 0x400018e4 ); +PROVIDE( Cache_Freeze_ICache_Disable = 0x400018f0 ); +PROVIDE( Cache_Freeze_DCache_Enable = 0x400018fc ); +PROVIDE( Cache_Freeze_DCache_Disable = 0x40001908 ); +PROVIDE( Cache_Set_IDROM_MMU_Size = 0x40001914 ); +PROVIDE( flash2spiram_instruction_offset = 0x40001920 ); +PROVIDE( flash2spiram_rodata_offset = 0x4000192c ); +PROVIDE( flash_instr_rodata_start_page = 0x40001938 ); +PROVIDE( flash_instr_rodata_end_page = 0x40001944 ); +PROVIDE( Cache_Set_IDROM_MMU_Info = 0x40001950 ); +PROVIDE( Cache_Get_IROM_MMU_End = 0x4000195c ); +PROVIDE( Cache_Get_DROM_MMU_End = 0x40001968 ); +PROVIDE( Cache_Owner_Init = 0x40001974 ); +PROVIDE( Cache_Occupy_ICache_MEMORY = 0x40001980 ); +PROVIDE( Cache_Occupy_DCache_MEMORY = 0x4000198c ); +PROVIDE( Cache_MMU_Init = 0x40001998 ); +PROVIDE( Cache_Ibus_MMU_Set = 0x400019a4 ); +PROVIDE( Cache_Dbus_MMU_Set = 0x400019b0 ); +PROVIDE( Cache_Count_Flash_Pages = 0x400019bc ); +PROVIDE( Cache_Flash_To_SPIRAM_Copy = 0x400019c8 ); +PROVIDE( Cache_Travel_Tag_Memory = 0x400019d4 ); +PROVIDE( Cache_Travel_Tag_Memory2 = 0x400019e0 ); +PROVIDE( Cache_Get_Virtual_Addr = 0x400019ec ); +PROVIDE( Cache_Get_Memory_BaseAddr = 0x400019f8 ); +PROVIDE( Cache_Get_Memory_Addr = 0x40001a04 ); +PROVIDE( Cache_Get_Memory_value = 0x40001a10 ); +PROVIDE( rom_config_instruction_cache_mode = 0x40001a1c ); +PROVIDE( rom_config_data_cache_mode = 0x40001a28 ); /* Data (.data, .bss, .rodata) */ -PROVIDE( rom_cache_op_cb = 0x3fceffd4 ); -PROVIDE( rom_cache_internal_table_ptr = 0x3fceffd0 ); +PROVIDE( rom_cache_op_cb = 0x3fceffc8 ); +PROVIDE( rom_cache_internal_table_ptr = 0x3fceffc4 ); /*************************************** @@ -418,13 +463,13 @@ PROVIDE( rom_cache_internal_table_ptr = 0x3fceffd0 ); ***************************************/ /* Functions */ -ets_get_apb_freq = 0x4000189c; -ets_get_cpu_frequency = 0x400018a8; -ets_update_cpu_frequency = 0x400018b4; -ets_get_printf_channel = 0x400018c0; -ets_get_xtal_div = 0x400018cc; -ets_set_xtal_div = 0x400018d8; -ets_get_xtal_freq = 0x400018e4; +ets_get_apb_freq = 0x40001a34; +ets_get_cpu_frequency = 0x40001a40; +ets_update_cpu_frequency = 0x40001a4c; +ets_get_printf_channel = 0x40001a58; +ets_get_xtal_div = 0x40001a64; +ets_set_xtal_div = 0x40001a70; +ets_get_xtal_freq = 0x40001a7c; /*************************************** @@ -432,23 +477,23 @@ ets_get_xtal_freq = 0x400018e4; ***************************************/ /* Functions */ -gpio_input_get = 0x400018f0; -gpio_matrix_in = 0x400018fc; -gpio_matrix_out = 0x40001908; -gpio_output_disable = 0x40001914; -gpio_output_enable = 0x40001920; -gpio_output_set = 0x4000192c; -gpio_pad_hold = 0x40001938; -gpio_pad_input_disable = 0x40001944; -gpio_pad_input_enable = 0x40001950; -gpio_pad_pulldown = 0x4000195c; -gpio_pad_pullup = 0x40001968; -gpio_pad_select_gpio = 0x40001974; -gpio_pad_set_drv = 0x40001980; -gpio_pad_unhold = 0x4000198c; -gpio_pin_wakeup_disable = 0x40001998; -gpio_pin_wakeup_enable = 0x400019a4; -gpio_bypass_matrix_in = 0x400019b0; +gpio_input_get = 0x40001a88; +gpio_matrix_in = 0x40001a94; +gpio_matrix_out = 0x40001aa0; +gpio_output_disable = 0x40001aac; +gpio_output_enable = 0x40001ab8; +gpio_output_set = 0x40001ac4; +gpio_pad_hold = 0x40001ad0; +gpio_pad_input_disable = 0x40001adc; +gpio_pad_input_enable = 0x40001ae8; +gpio_pad_pulldown = 0x40001af4; +gpio_pad_pullup = 0x40001b00; +gpio_pad_select_gpio = 0x40001b0c; +gpio_pad_set_drv = 0x40001b18; +gpio_pad_unhold = 0x40001b24; +gpio_pin_wakeup_disable = 0x40001b30; +gpio_pin_wakeup_enable = 0x40001b3c; +gpio_bypass_matrix_in = 0x40001b48; /*************************************** @@ -456,12 +501,12 @@ gpio_bypass_matrix_in = 0x400019b0; ***************************************/ /* Functions */ -intr_matrix_set = 0x400019bc; -ets_intr_lock = 0x400019c8; -ets_intr_unlock = 0x400019d4; -ets_isr_attach = 0x400019e0; -ets_isr_mask = 0x400019ec; -ets_isr_unmask = 0x400019f8; +intr_matrix_set = 0x40001b54; +ets_intr_lock = 0x40001b60; +ets_intr_unlock = 0x40001b6c; +ets_isr_attach = 0x40001b78; +ets_isr_mask = 0x40001b84; +ets_isr_unmask = 0x40001b90; /*************************************** @@ -469,21 +514,21 @@ ets_isr_unmask = 0x400019f8; ***************************************/ /* Functions */ -xthal_bcopy = 0x40001a04; -xthal_memcpy = 0x40001a10; -xthal_get_ccompare = 0x40001a1c; -xthal_set_ccompare = 0x40001a28; -xthal_get_ccount = 0x40001a34; -xthal_get_interrupt = 0x40001a40; -xthal_set_intclear = 0x40001a4c; -_xtos_ints_off = 0x40001a58; -_xtos_ints_on = 0x40001a64; -_xtos_restore_intlevel = 0x40001a70; -_xtos_set_exception_handler = 0x40001a7c; -_xtos_set_interrupt_handler = 0x40001a88; -_xtos_set_interrupt_handler_arg = 0x40001a94; -_xtos_set_intlevel = 0x40001aa0; -_xtos_set_vpri = 0x40001aac; +xthal_bcopy = 0x40001b9c; +xthal_memcpy = 0x40001ba8; +xthal_get_ccompare = 0x40001bb4; +xthal_set_ccompare = 0x40001bc0; +xthal_get_ccount = 0x40001bcc; +xthal_get_interrupt = 0x40001bd8; +xthal_set_intclear = 0x40001be4; +_xtos_ints_off = 0x40001bf0; +_xtos_ints_on = 0x40001bfc; +_xtos_restore_intlevel = 0x40001c08; +_xtos_set_exception_handler = 0x40001c14; +_xtos_set_interrupt_handler = 0x40001c20; +_xtos_set_interrupt_handler_arg = 0x40001c2c; +_xtos_set_intlevel = 0x40001c38; +_xtos_set_vpri = 0x40001c44; /*************************************** @@ -491,54 +536,54 @@ _xtos_set_vpri = 0x40001aac; ***************************************/ /* Functions */ -md5_vector = 0x40001ab8; -MD5Init = 0x40001ac4; -MD5Update = 0x40001ad0; -MD5Final = 0x40001adc; -hmac_md5_vector = 0x40001ae8; -hmac_md5 = 0x40001af4; -crc32_le = 0x40001b00; -crc32_be = 0x40001b0c; -crc16_le = 0x40001b18; -crc16_be = 0x40001b24; -crc8_le = 0x40001b30; -crc8_be = 0x40001b3c; -esp_crc8 = 0x40001b48; -ets_sha_enable = 0x40001b54; -ets_sha_disable = 0x40001b60; -ets_sha_get_state = 0x40001b6c; -ets_sha_init = 0x40001b78; -ets_sha_process = 0x40001b84; -ets_sha_starts = 0x40001b90; -ets_sha_update = 0x40001b9c; -ets_sha_finish = 0x40001ba8; -ets_sha_clone = 0x40001bb4; -ets_hmac_enable = 0x40001bc0; -ets_hmac_disable = 0x40001bcc; -ets_hmac_calculate_message = 0x40001bd8; -ets_hmac_calculate_downstream = 0x40001be4; -ets_hmac_invalidate_downstream = 0x40001bf0; -ets_jtag_enable_temporarily = 0x40001bfc; -ets_aes_enable = 0x40001c08; -ets_aes_disable = 0x40001c14; -ets_aes_setkey = 0x40001c20; -ets_aes_block = 0x40001c2c; -ets_bigint_enable = 0x40001c38; -ets_bigint_disable = 0x40001c44; -ets_bigint_multiply = 0x40001c50; -ets_bigint_modmult = 0x40001c5c; -ets_bigint_modexp = 0x40001c68; -ets_bigint_wait_finish = 0x40001c74; -ets_bigint_getz = 0x40001c80; -ets_ds_enable = 0x40001c8c; -ets_ds_disable = 0x40001c98; -ets_ds_start_sign = 0x40001ca4; -ets_ds_is_busy = 0x40001cb0; -ets_ds_finish_sign = 0x40001cbc; -ets_ds_encrypt_params = 0x40001cc8; -ets_aes_setkey_dec = 0x40001cd4; -ets_aes_setkey_enc = 0x40001ce0; -ets_mgf1_sha256 = 0x40001cec; +md5_vector = 0x40001c50; +MD5Init = 0x40001c5c; +MD5Update = 0x40001c68; +MD5Final = 0x40001c74; +hmac_md5_vector = 0x40001c80; +hmac_md5 = 0x40001c8c; +crc32_le = 0x40001c98; +crc32_be = 0x40001ca4; +crc16_le = 0x40001cb0; +crc16_be = 0x40001cbc; +crc8_le = 0x40001cc8; +crc8_be = 0x40001cd4; +esp_crc8 = 0x40001ce0; +ets_sha_enable = 0x40001cec; +ets_sha_disable = 0x40001cf8; +ets_sha_get_state = 0x40001d04; +ets_sha_init = 0x40001d10; +ets_sha_process = 0x40001d1c; +ets_sha_starts = 0x40001d28; +ets_sha_update = 0x40001d34; +ets_sha_finish = 0x40001d40; +ets_sha_clone = 0x40001d4c; +ets_hmac_enable = 0x40001d58; +ets_hmac_disable = 0x40001d64; +ets_hmac_calculate_message = 0x40001d70; +ets_hmac_calculate_downstream = 0x40001d7c; +ets_hmac_invalidate_downstream = 0x40001d88; +ets_jtag_enable_temporarily = 0x40001d94; +ets_aes_enable = 0x40001da0; +ets_aes_disable = 0x40001dac; +ets_aes_setkey = 0x40001db8; +ets_aes_block = 0x40001dc4; +ets_bigint_enable = 0x40001dd0; +ets_bigint_disable = 0x40001ddc; +ets_bigint_multiply = 0x40001de8; +ets_bigint_modmult = 0x40001df4; +ets_bigint_modexp = 0x40001e00; +ets_bigint_wait_finish = 0x40001e0c; +ets_bigint_getz = 0x40001e18; +ets_ds_enable = 0x40001e24; +ets_ds_disable = 0x40001e30; +ets_ds_start_sign = 0x40001e3c; +ets_ds_is_busy = 0x40001e48; +ets_ds_finish_sign = 0x40001e54; +ets_ds_encrypt_params = 0x40001e60; +ets_aes_setkey_dec = 0x40001e6c; +ets_aes_setkey_enc = 0x40001e78; +ets_mgf1_sha256 = 0x40001e84; /*************************************** @@ -546,41 +591,41 @@ ets_mgf1_sha256 = 0x40001cec; ***************************************/ /* Functions */ -ets_efuse_read = 0x40001cf8; -ets_efuse_program = 0x40001d04; -ets_efuse_clear_program_registers = 0x40001d10; -ets_efuse_write_key = 0x40001d1c; -ets_efuse_get_read_register_address = 0x40001d28; -ets_efuse_get_key_purpose = 0x40001d34; -ets_efuse_key_block_unused = 0x40001d40; -ets_efuse_find_unused_key_block = 0x40001d4c; -ets_efuse_rs_calculate = 0x40001d58; -ets_efuse_count_unused_key_blocks = 0x40001d64; -ets_efuse_secure_boot_enabled = 0x40001d70; -ets_efuse_secure_boot_aggressive_revoke_enabled = 0x40001d7c; -ets_efuse_cache_encryption_enabled = 0x40001d88; -ets_efuse_download_modes_disabled = 0x40001d94; -ets_efuse_find_purpose = 0x40001da0; -ets_efuse_flash_opi_5pads_power_sel_vddspi = 0x40001dac; -ets_efuse_force_send_resume = 0x40001db8; -ets_efuse_get_flash_delay_us = 0x40001dc4; -ets_efuse_get_mac = 0x40001dd0; -ets_efuse_get_spiconfig = 0x40001ddc; -ets_efuse_usb_print_is_disabled = 0x40001de8; -ets_efuse_get_uart_print_channel = 0x40001df4; -ets_efuse_get_uart_print_control = 0x40001e00; -ets_efuse_get_wp_pad = 0x40001e0c; -ets_efuse_legacy_spi_boot_mode_disabled = 0x40001e18; -ets_efuse_security_download_modes_enabled = 0x40001e24; -ets_efuse_set_timing = 0x40001e30; -ets_efuse_jtag_disabled = 0x40001e3c; -ets_efuse_usb_download_mode_disabled = 0x40001e48; -ets_efuse_usb_module_disabled = 0x40001e54; -ets_efuse_usb_device_disabled = 0x40001e60; -ets_efuse_flash_octal_mode = 0x40001e6c; -ets_efuse_ecc_en = 0x40001e78; -ets_efuse_ecc_flash_page_size = 0x40001e84; -ets_efuse_ecc_16to17_mode = 0x40001e90; +ets_efuse_read = 0x40001e90; +ets_efuse_program = 0x40001e9c; +ets_efuse_clear_program_registers = 0x40001ea8; +ets_efuse_write_key = 0x40001eb4; +ets_efuse_get_read_register_address = 0x40001ec0; +ets_efuse_get_key_purpose = 0x40001ecc; +ets_efuse_key_block_unused = 0x40001ed8; +ets_efuse_find_unused_key_block = 0x40001ee4; +ets_efuse_rs_calculate = 0x40001ef0; +ets_efuse_count_unused_key_blocks = 0x40001efc; +ets_efuse_secure_boot_enabled = 0x40001f08; +ets_efuse_secure_boot_aggressive_revoke_enabled = 0x40001f14; +ets_efuse_cache_encryption_enabled = 0x40001f20; +ets_efuse_download_modes_disabled = 0x40001f2c; +ets_efuse_find_purpose = 0x40001f38; +ets_efuse_flash_opi_5pads_power_sel_vddspi = 0x40001f44; +ets_efuse_force_send_resume = 0x40001f50; +ets_efuse_get_flash_delay_us = 0x40001f5c; +ets_efuse_get_mac = 0x40001f68; +ets_efuse_get_spiconfig = 0x40001f74; +ets_efuse_usb_print_is_disabled = 0x40001f80; +ets_efuse_get_uart_print_channel = 0x40001f8c; +ets_efuse_get_uart_print_control = 0x40001f98; +ets_efuse_get_wp_pad = 0x40001fa4; +ets_efuse_legacy_spi_boot_mode_disabled = 0x40001fb0; +ets_efuse_security_download_modes_enabled = 0x40001fbc; +ets_efuse_set_timing = 0x40001fc8; +ets_efuse_jtag_disabled = 0x40001fd4; +ets_efuse_usb_download_mode_disabled = 0x40001fe0; +ets_efuse_usb_module_disabled = 0x40001fec; +ets_efuse_usb_device_disabled = 0x40001ff8; +ets_efuse_flash_octal_mode = 0x40002004; +ets_efuse_ecc_en = 0x40002010; +ets_efuse_ecc_flash_page_size = 0x4000201c; +ets_efuse_ecc_16to17_mode = 0x40002028; /*************************************** @@ -588,28 +633,28 @@ ets_efuse_ecc_16to17_mode = 0x40001e90; ***************************************/ /* Functions */ -ets_ecc_flash_enable = 0x40001e9c; -ets_ecc_flash_enable_all = 0x40001ea8; -ets_ecc_flash_disable = 0x40001eb4; -ets_ecc_flash_disable_all = 0x40001ec0; -ets_ecc_get_flash_page_size = 0x40001ecc; -ets_ecc_set_flash_page_size = 0x40001ed8; -ets_ecc_set_flash_byte_mode = 0x40001ee4; -ets_ecc_get_flash_byte_mode = 0x40001ef0; -ets_ecc_set_flash_range = 0x40001efc; -ets_ecc_get_flash_range = 0x40001f08; -ets_ecc_sram_enable = 0x40001f14; -ets_ecc_sram_disable = 0x40001f20; -ets_ecc_sram_enable_all = 0x40001f2c; -ets_ecc_sram_disable_all = 0x40001f38; -ets_ecc_get_sram_page_size = 0x40001f44; -ets_ecc_set_sram_page_size = 0x40001f50; -ets_ecc_get_sram_byte_mode = 0x40001f5c; -ets_ecc_set_sram_byte_mode = 0x40001f68; -ets_ecc_set_sram_range = 0x40001f74; -ets_ecc_get_sram_range = 0x40001f80; +ets_ecc_flash_enable = 0x40002034; +ets_ecc_flash_enable_all = 0x40002040; +ets_ecc_flash_disable = 0x4000204c; +ets_ecc_flash_disable_all = 0x40002058; +ets_ecc_get_flash_page_size = 0x40002064; +ets_ecc_set_flash_page_size = 0x40002070; +ets_ecc_set_flash_byte_mode = 0x4000207c; +ets_ecc_get_flash_byte_mode = 0x40002088; +ets_ecc_set_flash_range = 0x40002094; +ets_ecc_get_flash_range = 0x400020a0; +ets_ecc_sram_enable = 0x400020ac; +ets_ecc_sram_disable = 0x400020b8; +ets_ecc_sram_enable_all = 0x400020c4; +ets_ecc_sram_disable_all = 0x400020d0; +ets_ecc_get_sram_page_size = 0x400020dc; +ets_ecc_set_sram_page_size = 0x400020e8; +ets_ecc_get_sram_byte_mode = 0x400020f4; +ets_ecc_set_sram_byte_mode = 0x40002100; +ets_ecc_set_sram_range = 0x4000210c; +ets_ecc_get_sram_range = 0x40002118; /* Data (.data, .bss, .rodata) */ -ets_ecc_table_ptr = 0x3fceffcc; +ets_ecc_table_ptr = 0x3fceffc0; /*************************************** @@ -617,12 +662,12 @@ ets_ecc_table_ptr = 0x3fceffcc; ***************************************/ /* Functions */ -ets_emsa_pss_verify = 0x40001f8c; -ets_rsa_pss_verify = 0x40001f98; -ets_secure_boot_verify_bootloader_with_keys = 0x40001fa4; -ets_secure_boot_verify_signature = 0x40001fb0; -ets_secure_boot_read_key_digests = 0x40001fbc; -ets_secure_boot_revoke_public_key_digest = 0x40001fc8; +ets_emsa_pss_verify = 0x40002124; +ets_rsa_pss_verify = 0x40002130; +ets_secure_boot_verify_bootloader_with_keys = 0x4000213c; +ets_secure_boot_verify_signature = 0x40002148; +ets_secure_boot_read_key_digests = 0x40002154; +ets_secure_boot_revoke_public_key_digest = 0x40002160; /*************************************** @@ -630,15 +675,19 @@ ets_secure_boot_revoke_public_key_digest = 0x40001fc8; ***************************************/ /* Functions */ -PROVIDE( usb_uart_rx_one_char = 0x4000240c ); -PROVIDE( usb_uart_rx_one_char_block = 0x40002418 ); -PROVIDE( usb_uart_tx_flush = 0x40002424 ); -PROVIDE( usb_uart_tx_one_char = 0x40002430 ); -PROVIDE( Uart_Init_USB = 0x4000243c ); +PROVIDE( usb_uart_otg_rx_one_char = 0x400025a4 ); +PROVIDE( usb_uart_otg_rx_one_char_block = 0x400025b0 ); +PROVIDE( usb_uart_otg_tx_flush = 0x400025bc ); +PROVIDE( usb_uart_otg_tx_one_char = 0x400025c8 ); +PROVIDE( usb_uart_device_rx_one_char = 0x400025d4 ); +PROVIDE( usb_uart_device_rx_one_char_block = 0x400025e0 ); +PROVIDE( usb_uart_device_tx_flush = 0x400025ec ); +PROVIDE( usb_uart_device_tx_one_char = 0x400025f8 ); +PROVIDE( Uart_Init_USB = 0x40002604 ); /* Data (.data, .bss, .rodata) */ -PROVIDE( uart_acm_dev = 0x3fceffc8 ); -PROVIDE( g_uart_print = 0x3fceffc5 ); -PROVIDE( g_usb_print = 0x3fceffc4 ); +PROVIDE( uart_acm_dev = 0x3fceffbc ); +PROVIDE( g_uart_print = 0x3fceffb9 ); +PROVIDE( g_usb_print = 0x3fceffb8 ); /*************************************** @@ -646,102 +695,102 @@ PROVIDE( g_usb_print = 0x3fceffc4 ); ***************************************/ /* Functions */ -cdc_acm_class_handle_req = 0x40002448; -cdc_acm_init = 0x40002454; -cdc_acm_fifo_fill = 0x40002460; -cdc_acm_rx_fifo_cnt = 0x4000246c; -cdc_acm_fifo_read = 0x40002478; -cdc_acm_irq_tx_enable = 0x40002484; -cdc_acm_irq_tx_disable = 0x40002490; -cdc_acm_irq_state_enable = 0x4000249c; -cdc_acm_irq_state_disable = 0x400024a8; -cdc_acm_irq_tx_ready = 0x400024b4; -cdc_acm_irq_rx_enable = 0x400024c0; -cdc_acm_irq_rx_disable = 0x400024cc; -cdc_acm_irq_rx_ready = 0x400024d8; -cdc_acm_irq_is_pending = 0x400024e4; -cdc_acm_irq_callback_set = 0x400024f0; -cdc_acm_line_ctrl_set = 0x400024fc; -cdc_acm_line_ctrl_get = 0x40002508; -cdc_acm_poll_out = 0x40002514; -chip_usb_dw_did_persist = 0x40002520; -chip_usb_dw_init = 0x4000252c; -chip_usb_detach = 0x40002538; -chip_usb_dw_prepare_persist = 0x40002544; -chip_usb_get_persist_flags = 0x40002550; -chip_usb_set_persist_flags = 0x4000255c; -cpio_start = 0x40002568; -cpio_feed = 0x40002574; -cpio_done = 0x40002580; -cpio_destroy = 0x4000258c; -dfu_flash_init = 0x40002598; -dfu_flash_erase = 0x400025a4; -dfu_flash_program = 0x400025b0; -dfu_flash_read = 0x400025bc; -dfu_flash_attach = 0x400025c8; -dfu_cpio_callback = 0x400025d4; -dfu_updater_get_err = 0x400025e0; -dfu_updater_clear_err = 0x400025ec; -dfu_updater_enable = 0x400025f8; -dfu_updater_begin = 0x40002604; -dfu_updater_feed = 0x40002610; -dfu_updater_end = 0x4000261c; -dfu_updater_set_raw_addr = 0x40002628; -dfu_updater_flash_read = 0x40002634; -usb_dc_prepare_persist = 0x40002640; -usb_dw_isr_handler = 0x4000264c; -usb_dc_attach = 0x40002658; -usb_dc_detach = 0x40002664; -usb_dc_reset = 0x40002670; -usb_dc_set_address = 0x4000267c; -usb_dc_ep_check_cap = 0x40002688; -usb_dc_ep_configure = 0x40002694; -usb_dc_ep_set_stall = 0x400026a0; -usb_dc_ep_clear_stall = 0x400026ac; -usb_dc_ep_halt = 0x400026b8; -usb_dc_ep_is_stalled = 0x400026c4; -usb_dc_ep_enable = 0x400026d0; -usb_dc_ep_disable = 0x400026dc; -usb_dc_ep_flush = 0x400026e8; -usb_dc_ep_write_would_block = 0x400026f4; -usb_dc_ep_write = 0x40002700; -usb_dc_ep_read_wait = 0x4000270c; -usb_dc_ep_read_continue = 0x40002718; -usb_dc_ep_read = 0x40002724; -usb_dc_ep_set_callback = 0x40002730; -usb_dc_set_status_callback = 0x4000273c; -usb_dc_ep_mps = 0x40002748; -usb_dc_check_poll_for_interrupts = 0x40002754; -mac_addr_to_serial_str_desc = 0x40002760; -usb_set_current_descriptor = 0x4000276c; -usb_get_descriptor = 0x40002778; -usb_dev_resume = 0x40002784; -usb_dev_get_configuration = 0x40002790; -usb_set_config = 0x4000279c; -usb_deconfig = 0x400027a8; -usb_enable = 0x400027b4; -usb_disable = 0x400027c0; -usb_write_would_block = 0x400027cc; -usb_write = 0x400027d8; -usb_read = 0x400027e4; -usb_ep_set_stall = 0x400027f0; -usb_ep_clear_stall = 0x400027fc; -usb_ep_read_wait = 0x40002808; -usb_ep_read_continue = 0x40002814; -usb_transfer_ep_callback = 0x40002820; -usb_transfer = 0x4000282c; -usb_cancel_transfer = 0x40002838; -usb_transfer_sync = 0x40002844; -usb_dfu_set_detach_cb = 0x40002850; -dfu_class_handle_req = 0x4000285c; -dfu_status_cb = 0x40002868; -dfu_custom_handle_req = 0x40002874; -usb_dfu_init = 0x40002880; -usb_dfu_force_detach = 0x4000288c; -usb_dev_deinit = 0x40002898; -usb_dw_ctrl_deinit = 0x400028a4; +cdc_acm_class_handle_req = 0x40002610; +cdc_acm_init = 0x4000261c; +cdc_acm_fifo_fill = 0x40002628; +cdc_acm_rx_fifo_cnt = 0x40002634; +cdc_acm_fifo_read = 0x40002640; +cdc_acm_irq_tx_enable = 0x4000264c; +cdc_acm_irq_tx_disable = 0x40002658; +cdc_acm_irq_state_enable = 0x40002664; +cdc_acm_irq_state_disable = 0x40002670; +cdc_acm_irq_tx_ready = 0x4000267c; +cdc_acm_irq_rx_enable = 0x40002688; +cdc_acm_irq_rx_disable = 0x40002694; +cdc_acm_irq_rx_ready = 0x400026a0; +cdc_acm_irq_is_pending = 0x400026ac; +cdc_acm_irq_callback_set = 0x400026b8; +cdc_acm_line_ctrl_set = 0x400026c4; +cdc_acm_line_ctrl_get = 0x400026d0; +cdc_acm_poll_out = 0x400026dc; +chip_usb_dw_did_persist = 0x400026e8; +chip_usb_dw_init = 0x400026f4; +chip_usb_detach = 0x40002700; +chip_usb_dw_prepare_persist = 0x4000270c; +chip_usb_get_persist_flags = 0x40002718; +chip_usb_set_persist_flags = 0x40002724; +cpio_start = 0x40002730; +cpio_feed = 0x4000273c; +cpio_done = 0x40002748; +cpio_destroy = 0x40002754; +dfu_flash_init = 0x40002760; +dfu_flash_erase = 0x4000276c; +dfu_flash_program = 0x40002778; +dfu_flash_read = 0x40002784; +dfu_flash_attach = 0x40002790; +dfu_cpio_callback = 0x4000279c; +dfu_updater_get_err = 0x400027a8; +dfu_updater_clear_err = 0x400027b4; +dfu_updater_enable = 0x400027c0; +dfu_updater_begin = 0x400027cc; +dfu_updater_feed = 0x400027d8; +dfu_updater_end = 0x400027e4; +dfu_updater_set_raw_addr = 0x400027f0; +dfu_updater_flash_read = 0x400027fc; +usb_dc_prepare_persist = 0x40002808; +usb_dw_isr_handler = 0x40002814; +usb_dc_attach = 0x40002820; +usb_dc_detach = 0x4000282c; +usb_dc_reset = 0x40002838; +usb_dc_set_address = 0x40002844; +usb_dc_ep_check_cap = 0x40002850; +usb_dc_ep_configure = 0x4000285c; +usb_dc_ep_set_stall = 0x40002868; +usb_dc_ep_clear_stall = 0x40002874; +usb_dc_ep_halt = 0x40002880; +usb_dc_ep_is_stalled = 0x4000288c; +usb_dc_ep_enable = 0x40002898; +usb_dc_ep_disable = 0x400028a4; +usb_dc_ep_flush = 0x400028b0; +usb_dc_ep_write_would_block = 0x400028bc; +usb_dc_ep_write = 0x400028c8; +usb_dc_ep_read_wait = 0x400028d4; +usb_dc_ep_read_continue = 0x400028e0; +usb_dc_ep_read = 0x400028ec; +usb_dc_ep_set_callback = 0x400028f8; +usb_dc_set_status_callback = 0x40002904; +usb_dc_ep_mps = 0x40002910; +usb_dc_check_poll_for_interrupts = 0x4000291c; +mac_addr_to_serial_str_desc = 0x40002928; +usb_set_current_descriptor = 0x40002934; +usb_get_descriptor = 0x40002940; +usb_dev_resume = 0x4000294c; +usb_dev_get_configuration = 0x40002958; +usb_set_config = 0x40002964; +usb_deconfig = 0x40002970; +usb_enable = 0x4000297c; +usb_disable = 0x40002988; +usb_write_would_block = 0x40002994; +usb_write = 0x400029a0; +usb_read = 0x400029ac; +usb_ep_set_stall = 0x400029b8; +usb_ep_clear_stall = 0x400029c4; +usb_ep_read_wait = 0x400029d0; +usb_ep_read_continue = 0x400029dc; +usb_transfer_ep_callback = 0x400029e8; +usb_transfer = 0x400029f4; +usb_cancel_transfer = 0x40002a00; +usb_transfer_sync = 0x40002a0c; +usb_dfu_set_detach_cb = 0x40002a18; +dfu_class_handle_req = 0x40002a24; +dfu_status_cb = 0x40002a30; +dfu_custom_handle_req = 0x40002a3c; +usb_dfu_init = 0x40002a48; +usb_dfu_force_detach = 0x40002a54; +usb_dev_deinit = 0x40002a60; +usb_dw_ctrl_deinit = 0x40002a6c; /* Data (.data, .bss, .rodata) */ -s_usb_osglue = 0x3fceffb8; +s_usb_osglue = 0x3fceffac; /*************************************** @@ -749,969 +798,998 @@ s_usb_osglue = 0x3fceffb8; ***************************************/ /* Functions */ -bt_rf_coex_get_dft_cfg = 0x400028b0; -bt_rf_coex_hooks_p_set = 0x400028bc; -btdm_con_maxevtime_cal_impl = 0x400028c8; -btdm_controller_get_compile_version_impl = 0x400028d4; -btdm_controller_rom_data_init = 0x400028e0; -btdm_dis_privacy_err_report_impl = 0x400028ec; -btdm_disable_adv_delay_impl = 0x400028f8; -btdm_enable_scan_continue_impl = 0x40002904; -btdm_enable_scan_forever_impl = 0x40002910; -btdm_get_power_state_impl = 0x4000291c; -btdm_get_prevent_sleep_flag_impl = 0x40002928; -btdm_power_state_active_impl = 0x40002934; -btdm_switch_phy_coded_impl = 0x40002940; -hci_acl_data_handler = 0x4000294c; -hci_disconnect_cmd_handler = 0x40002958; -hci_le_con_upd_cmd_handler = 0x40002964; -hci_le_ltk_req_neg_reply_cmd_handler = 0x40002970; -hci_le_ltk_req_reply_cmd_handler = 0x4000297c; -hci_le_rd_chnl_map_cmd_handler = 0x40002988; -hci_le_rd_phy_cmd_handler = 0x40002994; -hci_le_rd_rem_feats_cmd_handler = 0x400029a0; -hci_le_rem_con_param_req_neg_reply_cmd_handler = 0x400029ac; -hci_le_rem_con_param_req_reply_cmd_handler = 0x400029b8; -hci_le_set_data_len_cmd_handler = 0x400029c4; -hci_le_set_phy_cmd_handler = 0x400029d0; -hci_le_start_enc_cmd_handler = 0x400029dc; -hci_rd_auth_payl_to_cmd_handler = 0x400029e8; -hci_rd_rem_ver_info_cmd_handler = 0x400029f4; -hci_rd_rssi_cmd_handler = 0x40002a00; -hci_rd_tx_pwr_lvl_cmd_handler = 0x40002a0c; -hci_vs_set_pref_slave_evt_dur_cmd_handler = 0x40002a18; -hci_vs_set_pref_slave_latency_cmd_handler = 0x40002a24; -hci_wr_auth_payl_to_cmd_handler = 0x40002a30; -ll_channel_map_ind_handler = 0x40002a3c; -ll_connection_param_req_handler = 0x40002a48; -ll_connection_param_rsp_handler = 0x40002a54; -ll_connection_update_ind_handler = 0x40002a60; -ll_enc_req_handler = 0x40002a6c; -ll_enc_rsp_handler = 0x40002a78; -ll_feature_req_handler = 0x40002a84; -ll_feature_rsp_handler = 0x40002a90; -ll_length_req_handler = 0x40002a9c; -ll_length_rsp_handler = 0x40002aa8; -ll_min_used_channels_ind_handler = 0x40002ab4; -ll_pause_enc_req_handler = 0x40002ac0; -ll_pause_enc_rsp_handler = 0x40002acc; -ll_phy_req_handler = 0x40002ad8; -ll_phy_rsp_handler = 0x40002ae4; -ll_phy_update_ind_handler = 0x40002af0; -ll_ping_req_handler = 0x40002afc; -ll_ping_rsp_handler = 0x40002b08; -ll_slave_feature_req_handler = 0x40002b14; -ll_start_enc_req_handler = 0x40002b20; -ll_start_enc_rsp_handler = 0x40002b2c; -ll_terminate_ind_handler = 0x40002b38; -ll_version_ind_handler = 0x40002b44; -llc_auth_payl_nearly_to_handler = 0x40002b50; -llc_auth_payl_real_to_handler = 0x40002b5c; -llc_encrypt_ind_handler = 0x40002b68; -llc_hci_command_handler_wrapper = 0x40002b74; -llc_ll_connection_param_req_pdu_send = 0x40002b80; -llc_ll_connection_param_rsp_pdu_send = 0x40002b8c; -llc_ll_connection_update_ind_pdu_send = 0x40002b98; -llc_ll_enc_req_pdu_send = 0x40002ba4; -llc_ll_enc_rsp_pdu_send = 0x40002bb0; -llc_ll_feature_req_pdu_send = 0x40002bbc; -llc_ll_feature_rsp_pdu_send = 0x40002bc8; -llc_ll_length_req_pdu_send = 0x40002bd4; -llc_ll_length_rsp_pdu_send = 0x40002be0; -llc_ll_pause_enc_req_pdu_send = 0x40002bec; -llc_ll_pause_enc_rsp_pdu_send = 0x40002bf8; -llc_ll_phy_req_pdu_send = 0x40002c04; -llc_ll_phy_rsp_pdu_send = 0x40002c10; -llc_ll_ping_req_pdu_send = 0x40002c1c; -llc_ll_ping_rsp_pdu_send = 0x40002c28; -llc_ll_start_enc_req_pdu_send = 0x40002c34; -llc_ll_start_enc_rsp_pdu_send = 0x40002c40; -llc_ll_terminate_ind_pdu_send = 0x40002c4c; -llc_ll_unknown_rsp_pdu_send = 0x40002c58; -llc_llcp_ch_map_update_ind_pdu_send = 0x40002c64; -llc_llcp_phy_upd_ind_pdu_send = 0x40002c70; -llc_llcp_version_ind_pdu_send = 0x40002c7c; -llc_op_ch_map_upd_ind_handler = 0x40002c88; -llc_op_con_upd_ind_handler = 0x40002c94; -llc_op_disconnect_ind_handler = 0x40002ca0; -llc_op_dl_upd_ind_handler = 0x40002cac; -llc_op_encrypt_ind_handler = 0x40002cb8; -llc_op_feats_exch_ind_handler = 0x40002cc4; -llc_op_le_ping_ind_handler = 0x40002cd0; -llc_op_phy_upd_ind_handler = 0x40002cdc; -llc_op_ver_exch_ind_handler = 0x40002ce8; -llc_stopped_ind_handler = 0x40002cf4; -lld_acl_rx_ind_handler = 0x40002d00; -lld_acl_tx_cfm_handler = 0x40002d0c; -lld_adv_end_ind_handler = 0x40002d18; -lld_adv_rep_ind_handler = 0x40002d24; -lld_ch_map_upd_cfm_handler = 0x40002d30; -lld_con_estab_ind_handler = 0x40002d3c; -lld_con_evt_sd_evt_time_set = 0x40002d48; -lld_con_offset_upd_ind_handler = 0x40002d54; -lld_con_param_upd_cfm_handler = 0x40002d60; -lld_disc_ind_handler = 0x40002d6c; -lld_init_end_ind_handler = 0x40002d78; -lld_llcp_rx_ind_handler_wrapper = 0x40002d84; -lld_llcp_tx_cfm_handler = 0x40002d90; -lld_per_adv_end_ind_handler = 0x40002d9c; -lld_per_adv_rep_ind_handler = 0x40002da8; -lld_per_adv_rx_end_ind_handler = 0x40002db4; -lld_phy_coded_500k_get = 0x40002dc0; -lld_phy_upd_cfm_handler = 0x40002dcc; -lld_scan_end_ind_handler = 0x40002dd8; -lld_scan_req_ind_handler = 0x40002de4; -lld_sync_start_req_handler = 0x40002df0; -lld_test_end_ind_handler = 0x40002dfc; -lld_update_rxbuf_handler = 0x40002e08; -llm_ch_map_update_ind_handler = 0x40002e14; -llm_hci_command_handler_wrapper = 0x40002e20; -llm_scan_period_to_handler = 0x40002e2c; -r_Add2SelfBigHex256 = 0x40002e38; -r_AddBigHex256 = 0x40002e44; -r_AddBigHexModP256 = 0x40002e50; -r_AddP256 = 0x40002e5c; -r_AddPdiv2_256 = 0x40002e68; -r_GF_Jacobian_Point_Addition256 = 0x40002e74; -r_GF_Jacobian_Point_Double256 = 0x40002e80; -r_GF_Point_Jacobian_To_Affine256 = 0x40002e8c; -r_MultiplyBigHexByUint32_256 = 0x40002e98; -r_MultiplyBigHexModP256 = 0x40002ea4; -r_MultiplyByU16ModP256 = 0x40002eb0; -r_SubtractBigHex256 = 0x40002ebc; -r_SubtractBigHexMod256 = 0x40002ec8; -r_SubtractBigHexUint32_256 = 0x40002ed4; -r_SubtractFromSelfBigHex256 = 0x40002ee0; -r_SubtractFromSelfBigHexSign256 = 0x40002eec; -r_aes_alloc = 0x40002ef8; -r_aes_ccm_continue = 0x40002f04; -r_aes_ccm_process_e = 0x40002f10; -r_aes_ccm_xor_128_lsb = 0x40002f1c; -r_aes_ccm_xor_128_msb = 0x40002f28; -r_aes_cmac_continue = 0x40002f34; -r_aes_cmac_start = 0x40002f40; -r_aes_k1_continue = 0x40002f4c; -r_aes_k2_continue = 0x40002f58; -r_aes_k3_continue = 0x40002f64; -r_aes_k4_continue = 0x40002f70; -r_aes_shift_left_128 = 0x40002f7c; -r_aes_start = 0x40002f88; -r_aes_xor_128 = 0x40002f94; -r_assert_err = 0x40002fa0; -r_assert_param = 0x40002fac; -r_assert_warn = 0x40002fb8; -r_bigHexInversion256 = 0x40002fc4; -r_ble_sw_cca_check_isr = 0x40002fd0; -r_ble_util_buf_acl_tx_alloc = 0x40002fdc; -r_ble_util_buf_acl_tx_elt_get = 0x40002fe8; -r_ble_util_buf_acl_tx_free = 0x40002ff4; -r_ble_util_buf_acl_tx_free_in_isr = 0x40003000; -r_ble_util_buf_adv_tx_alloc = 0x4000300c; -r_ble_util_buf_adv_tx_free = 0x40003018; -r_ble_util_buf_adv_tx_free_in_isr = 0x40003024; -r_ble_util_buf_env_deinit = 0x40003030; -r_ble_util_buf_env_init = 0x4000303c; -r_ble_util_buf_get_rx_buf_nb = 0x40003048; -r_ble_util_buf_get_rx_buf_size = 0x40003054; -r_ble_util_buf_llcp_tx_alloc = 0x40003060; -r_ble_util_buf_llcp_tx_free = 0x4000306c; -r_ble_util_buf_rx_alloc = 0x40003078; -r_ble_util_buf_rx_alloc_in_isr = 0x40003084; -r_ble_util_buf_rx_free = 0x40003090; -r_ble_util_buf_rx_free_in_isr = 0x4000309c; -r_ble_util_buf_set_rx_buf_nb = 0x400030a8; -r_ble_util_buf_set_rx_buf_size = 0x400030b4; -r_ble_util_data_rx_buf_reset = 0x400030c0; -r_bt_bb_get_intr_mask = 0x400030cc; -r_bt_bb_intr_clear = 0x400030d8; -r_bt_bb_intr_mask_set = 0x400030e4; -r_bt_bb_isr = 0x400030f0; -r_bt_rf_coex_cfg_set = 0x400030fc; -r_bt_rf_coex_conn_dynamic_pti_en_get = 0x40003108; -r_bt_rf_coex_conn_phy_coded_data_time_limit_en_get = 0x40003114; -r_bt_rf_coex_ext_adv_dynamic_pti_en_get = 0x40003120; -r_bt_rf_coex_ext_scan_dynamic_pti_en_get = 0x4000312c; -r_bt_rf_coex_legacy_adv_dynamic_pti_en_get = 0x40003138; -r_bt_rf_coex_per_adv_dynamic_pti_en_get = 0x40003144; -r_bt_rf_coex_pti_table_get = 0x40003150; -r_bt_rf_coex_st_param_get = 0x4000315c; -r_bt_rf_coex_st_param_set = 0x40003168; -r_bt_rf_coex_sync_scan_dynamic_pti_en_get = 0x40003174; -r_bt_rma_apply_rule_cs_fmt = 0x40003180; -r_bt_rma_apply_rule_cs_idx = 0x4000318c; -r_bt_rma_configure = 0x40003198; -r_bt_rma_deregister_rule_cs_fmt = 0x400031a4; -r_bt_rma_deregister_rule_cs_idx = 0x400031b0; -r_bt_rma_get_ant_by_act = 0x400031bc; -r_bt_rma_init = 0x400031c8; -r_bt_rma_register_rule_cs_fmt = 0x400031d4; -r_bt_rma_register_rule_cs_idx = 0x400031e0; -r_bt_rtp_apply_rule_cs_fmt = 0x400031ec; -r_bt_rtp_apply_rule_cs_idx = 0x400031f8; -r_bt_rtp_deregister_rule_cs_fmt = 0x40003204; -r_bt_rtp_deregister_rule_cs_idx = 0x40003210; -r_bt_rtp_get_txpwr_idx_by_act = 0x4000321c; -r_bt_rtp_init = 0x40003228; -r_bt_rtp_register_rule_cs_fmt = 0x40003234; -r_bt_rtp_register_rule_cs_idx = 0x40003240; -r_btdm_isr = 0x4000324c; -r_btdm_task_post = 0x40003258; -r_btdm_task_post_from_isr = 0x40003264; -r_btdm_task_recycle = 0x40003270; -r_cali_phase_match_p = 0x4000327c; -r_cmp_abs_time = 0x40003288; -r_cmp_dest_id = 0x40003294; -r_cmp_timer_id = 0x400032a0; -r_co_bdaddr_compare = 0x400032ac; -r_co_ble_pkt_dur_in_us = 0x400032b8; -r_co_list_extract = 0x400032c4; -r_co_list_extract_after = 0x400032d0; -r_co_list_extract_sublist = 0x400032dc; -r_co_list_find = 0x400032e8; -r_co_list_init = 0x400032f4; -r_co_list_insert_after = 0x40003300; -r_co_list_insert_before = 0x4000330c; -r_co_list_merge = 0x40003318; -r_co_list_pool_init = 0x40003324; -r_co_list_pop_front = 0x40003330; -r_co_list_push_back = 0x4000333c; -r_co_list_push_back_sublist = 0x40003348; -r_co_list_push_front = 0x40003354; -r_co_list_size = 0x40003360; -r_co_nb_good_le_channels = 0x4000336c; -r_co_util_pack = 0x40003378; -r_co_util_read_array_size = 0x40003384; -r_co_util_unpack = 0x40003390; -r_dbg_env_deinit = 0x4000339c; -r_dbg_env_init = 0x400033a8; -r_dbg_platform_reset_complete = 0x400033b4; -r_dl_upd_proc_start = 0x400033c0; -r_dump_data = 0x400033cc; -r_ecc_abort_key256_generation = 0x400033d8; -r_ecc_gen_new_public_key = 0x400033e4; -r_ecc_gen_new_secret_key = 0x400033f0; -r_ecc_generate_key256 = 0x400033fc; -r_ecc_get_debug_Keys = 0x40003408; -r_ecc_init = 0x40003414; -r_ecc_is_valid_point = 0x40003420; -r_ecc_multiplication_event_handler = 0x4000342c; -r_ecc_point_multiplication_win_256 = 0x40003438; -r_emi_alloc_em_mapping_by_offset = 0x40003444; -r_emi_base_reg_lut_show = 0x40003450; -r_emi_em_base_reg_show = 0x4000345c; -r_emi_free_em_mapping_by_offset = 0x40003468; -r_emi_get_em_mapping_idx_by_offset = 0x40003474; -r_emi_get_mem_addr_by_offset = 0x40003480; -r_emi_overwrite_em_mapping_by_offset = 0x4000348c; -r_esp_vendor_hci_command_handler = 0x40003498; -r_get_stack_usage = 0x400034a4; -r_h4tl_acl_hdr_rx_evt_handler = 0x400034b0; -r_h4tl_cmd_hdr_rx_evt_handler = 0x400034bc; -r_h4tl_cmd_pld_rx_evt_handler = 0x400034c8; -r_h4tl_eif_io_event_post = 0x400034d4; -r_h4tl_eif_register = 0x400034e0; -r_h4tl_init = 0x400034ec; -r_h4tl_out_of_sync = 0x400034f8; -r_h4tl_out_of_sync_check = 0x40003504; -r_h4tl_read_hdr = 0x40003510; -r_h4tl_read_next_out_of_sync = 0x4000351c; -r_h4tl_read_payl = 0x40003528; -r_h4tl_read_start = 0x40003534; -r_h4tl_rx_acl_hdr_extract = 0x40003540; -r_h4tl_rx_cmd_hdr_extract = 0x4000354c; -r_h4tl_rx_done = 0x40003558; -r_h4tl_start = 0x40003564; -r_h4tl_stop = 0x40003570; -r_h4tl_tx_done = 0x4000357c; -r_h4tl_tx_evt_handler = 0x40003588; -r_h4tl_write = 0x40003594; -r_hci_acl_tx_data_alloc = 0x400035a0; -r_hci_acl_tx_data_received = 0x400035ac; -r_hci_basic_cmd_send_2_controller = 0x400035b8; -r_hci_ble_adv_report_filter_check = 0x400035c4; -r_hci_ble_adv_report_tx_check = 0x400035d0; -r_hci_ble_conhdl_register = 0x400035dc; -r_hci_ble_conhdl_unregister = 0x400035e8; -r_hci_build_acl_data = 0x400035f4; -r_hci_build_cc_evt = 0x40003600; -r_hci_build_cs_evt = 0x4000360c; -r_hci_build_evt = 0x40003618; -r_hci_build_le_evt = 0x40003624; -r_hci_cmd_get_max_param_size = 0x40003630; -r_hci_cmd_received = 0x4000363c; -r_hci_cmd_reject = 0x40003648; -r_hci_evt_mask_check = 0x40003654; -r_hci_evt_mask_set = 0x40003660; -r_hci_fc_acl_buf_size_set = 0x4000366c; -r_hci_fc_acl_en = 0x40003678; -r_hci_fc_acl_packet_sent = 0x40003684; -r_hci_fc_check_host_available_nb_acl_packets = 0x40003690; -r_hci_fc_host_nb_acl_pkts_complete = 0x4000369c; -r_hci_fc_init = 0x400036a8; -r_hci_look_for_cmd_desc = 0x400036b4; -r_hci_look_for_evt_desc = 0x400036c0; -r_hci_look_for_le_evt_desc = 0x400036cc; -r_hci_look_for_le_evt_desc_esp = 0x400036d8; -r_hci_pack_bytes = 0x400036e4; -r_hci_register_vendor_desc_tab = 0x400036f0; -r_hci_send_2_controller = 0x400036fc; -r_hci_send_2_host = 0x40003708; -r_hci_tl_c2h_data_flow_on = 0x40003714; -r_hci_tl_cmd_hdr_rx_evt_handler = 0x40003720; -r_hci_tl_cmd_pld_rx_evt_handler = 0x4000372c; -r_hci_tl_get_pkt = 0x40003738; -r_hci_tl_hci_pkt_handler = 0x40003744; -r_hci_tl_hci_tx_done_evt_handler = 0x40003750; -r_hci_tl_inc_nb_h2c_cmd_pkts = 0x4000375c; -r_hci_tl_save_pkt = 0x40003768; -r_hci_tl_send = 0x40003774; -r_hci_tx_done = 0x40003780; -r_hci_tx_start = 0x4000378c; -r_hci_tx_trigger = 0x40003798; -r_isValidSecretKey_256 = 0x400037a4; -r_ke_check_malloc = 0x400037b0; -r_ke_event_callback_set = 0x400037bc; -r_ke_event_clear = 0x400037c8; -r_ke_event_flush = 0x400037d4; -r_ke_event_get = 0x400037e0; -r_ke_event_get_all = 0x400037ec; -r_ke_event_init = 0x400037f8; -r_ke_event_schedule = 0x40003804; -r_ke_event_set = 0x40003810; -r_ke_flush = 0x4000381c; -r_ke_free = 0x40003828; -r_ke_handler_search = 0x40003834; -r_ke_init = 0x40003840; -r_ke_is_free = 0x4000384c; -r_ke_malloc = 0x40003858; -r_ke_mem_init = 0x40003864; -r_ke_mem_is_empty = 0x40003870; -r_ke_mem_is_in_heap = 0x4000387c; -r_ke_msg_alloc = 0x40003888; -r_ke_msg_dest_id_get = 0x40003894; -r_ke_msg_discard = 0x400038a0; -r_ke_msg_forward = 0x400038ac; -r_ke_msg_forward_new_id = 0x400038b8; -r_ke_msg_free = 0x400038c4; -r_ke_msg_in_queue = 0x400038d0; -r_ke_msg_save = 0x400038dc; -r_ke_msg_send = 0x400038e8; -r_ke_msg_send_basic = 0x400038f4; -r_ke_msg_src_id_get = 0x40003900; -r_ke_queue_extract = 0x4000390c; -r_ke_queue_insert = 0x40003918; -r_ke_sleep_check = 0x40003924; -r_ke_state_get = 0x40003930; -r_ke_state_set = 0x4000393c; -r_ke_task_check = 0x40003948; -r_ke_task_create = 0x40003954; -r_ke_task_delete = 0x40003960; -r_ke_task_handler_get = 0x4000396c; -r_ke_task_init = 0x40003978; -r_ke_task_msg_flush = 0x40003984; -r_ke_task_saved_update = 0x40003990; -r_ke_task_schedule = 0x4000399c; -r_ke_time = 0x400039a8; -r_ke_time_cmp = 0x400039b4; -r_ke_time_past = 0x400039c0; -r_ke_timer_active = 0x400039cc; -r_ke_timer_adjust_all = 0x400039d8; -r_ke_timer_clear = 0x400039e4; -r_ke_timer_init = 0x400039f0; -r_ke_timer_schedule = 0x400039fc; -r_ke_timer_set = 0x40003a08; -r_led_init = 0x40003a14; -r_led_set_all = 0x40003a20; -r_llc_aes_res_cb = 0x40003a2c; -r_llc_ch_map_up_proc_err_cb = 0x40003a38; -r_llc_cleanup = 0x40003a44; -r_llc_cmd_cmp_send = 0x40003a50; -r_llc_cmd_stat_send = 0x40003a5c; -r_llc_con_move_cbk = 0x40003a68; -r_llc_con_plan_set_update = 0x40003a74; -r_llc_con_upd_param_in_range = 0x40003a80; -r_llc_disconnect = 0x40003a8c; -r_llc_disconnect_end = 0x40003a98; -r_llc_disconnect_proc_continue = 0x40003aa4; -r_llc_disconnect_proc_err_cb = 0x40003ab0; -r_llc_dl_chg_check = 0x40003abc; -r_llc_dle_proc_err_cb = 0x40003ac8; -r_llc_feats_exch_proc_err_cb = 0x40003ad4; -r_llc_hci_cmd_handler_tab_p_get = 0x40003ae0; -r_llc_hci_command_handler = 0x40003aec; -r_llc_hci_con_param_req_evt_send = 0x40003af8; -r_llc_hci_con_upd_info_send = 0x40003b04; -r_llc_hci_disconnected_dis = 0x40003b10; -r_llc_hci_dl_upd_info_send = 0x40003b1c; -r_llc_hci_enc_evt_send = 0x40003b28; -r_llc_hci_feats_info_send = 0x40003b34; -r_llc_hci_le_phy_upd_cmp_evt_send = 0x40003b40; -r_llc_hci_ltk_request_evt_send = 0x40003b4c; -r_llc_hci_nb_cmp_pkts_evt_send = 0x40003b58; -r_llc_hci_version_info_send = 0x40003b64; -r_llc_init_term_proc = 0x40003b70; -r_llc_iv_skd_rand_gen = 0x40003b7c; -r_llc_le_ping_proc_continue = 0x40003b88; -r_llc_le_ping_proc_err_cb = 0x40003b94; -r_llc_le_ping_restart = 0x40003ba0; -r_llc_le_ping_set = 0x40003bac; -r_llc_ll_pause_enc_rsp_ack_handler = 0x40003bb8; -r_llc_ll_reject_ind_ack_handler = 0x40003bc4; -r_llc_ll_reject_ind_pdu_send = 0x40003bd0; -r_llc_ll_start_enc_rsp_ack_handler = 0x40003bdc; -r_llc_ll_terminate_ind_ack = 0x40003be8; -r_llc_ll_unknown_ind_handler = 0x40003bf4; -r_llc_llcp_send = 0x40003c00; -r_llc_llcp_state_set = 0x40003c0c; -r_llc_llcp_trans_timer_set = 0x40003c18; -r_llc_llcp_tx_check = 0x40003c24; -r_llc_loc_ch_map_proc_continue = 0x40003c30; -r_llc_loc_con_upd_proc_continue = 0x40003c3c; -r_llc_loc_con_upd_proc_err_cb = 0x40003c48; -r_llc_loc_dl_upd_proc_continue = 0x40003c54; -r_llc_loc_encrypt_proc_continue = 0x40003c60; -r_llc_loc_encrypt_proc_err_cb = 0x40003c6c; -r_llc_loc_feats_exch_proc_continue = 0x40003c78; -r_llc_loc_phy_upd_proc_continue = 0x40003c84; -r_llc_loc_phy_upd_proc_err_cb = 0x40003c90; -r_llc_msg_handler_tab_p_get = 0x40003c9c; -r_llc_pref_param_compute = 0x40003ca8; -r_llc_proc_collision_check = 0x40003cb4; -r_llc_proc_err_ind = 0x40003cc0; -r_llc_proc_get = 0x40003ccc; -r_llc_proc_id_get = 0x40003cd8; -r_llc_proc_reg = 0x40003ce4; -r_llc_proc_state_get = 0x40003cf0; -r_llc_proc_state_set = 0x40003cfc; -r_llc_proc_timer_pause_set = 0x40003d08; -r_llc_proc_timer_set = 0x40003d14; -r_llc_proc_unreg = 0x40003d20; -r_llc_rem_ch_map_proc_continue = 0x40003d2c; -r_llc_rem_con_upd_proc_continue = 0x40003d38; -r_llc_rem_con_upd_proc_err_cb = 0x40003d44; -r_llc_rem_dl_upd_proc = 0x40003d50; -r_llc_rem_encrypt_proc_continue = 0x40003d5c; -r_llc_rem_encrypt_proc_err_cb = 0x40003d68; -r_llc_rem_phy_upd_proc_continue = 0x40003d74; -r_llc_rem_phy_upd_proc_err_cb = 0x40003d80; -r_llc_role_get = 0x40003d8c; -r_llc_sk_gen = 0x40003d98; -r_llc_start = 0x40003da4; -r_llc_stop = 0x40003db0; -r_llc_ver_exch_loc_proc_continue = 0x40003dbc; -r_llc_ver_proc_err_cb = 0x40003dc8; -r_llcp_pdu_handler_tab_p_get = 0x40003dd4; -r_lld_aa_gen = 0x40003de0; -r_lld_adv_adv_data_set = 0x40003dec; -r_lld_adv_adv_data_update = 0x40003df8; -r_lld_adv_aux_ch_idx_set = 0x40003e04; -r_lld_adv_aux_evt_canceled_cbk = 0x40003e10; -r_lld_adv_aux_evt_start_cbk = 0x40003e1c; -r_lld_adv_coex_check_ext_adv_synced = 0x40003e28; -r_lld_adv_coex_env_reset = 0x40003e34; -r_lld_adv_duration_update = 0x40003e40; -r_lld_adv_dynamic_pti_process = 0x40003e4c; -r_lld_adv_end = 0x40003e58; -r_lld_adv_evt_canceled_cbk = 0x40003e64; -r_lld_adv_evt_start_cbk = 0x40003e70; -r_lld_adv_ext_chain_construct = 0x40003e7c; -r_lld_adv_ext_pkt_prepare = 0x40003e88; -r_lld_adv_frm_cbk = 0x40003e94; -r_lld_adv_frm_isr = 0x40003ea0; -r_lld_adv_frm_skip_isr = 0x40003eac; -r_lld_adv_init = 0x40003eb8; -r_lld_adv_pkt_rx = 0x40003ec4; -r_lld_adv_pkt_rx_connect_ind = 0x40003ed0; -r_lld_adv_pkt_rx_send_scan_req_evt = 0x40003edc; -r_lld_adv_rand_addr_update = 0x40003ee8; -r_lld_adv_restart = 0x40003ef4; -r_lld_adv_scan_rsp_data_set = 0x40003f00; -r_lld_adv_scan_rsp_data_update = 0x40003f0c; -r_lld_adv_set_tx_power = 0x40003f18; -r_lld_adv_start = 0x40003f24; -r_lld_adv_stop = 0x40003f30; -r_lld_adv_sync_info_set = 0x40003f3c; -r_lld_adv_sync_info_update = 0x40003f48; -r_lld_calc_aux_rx = 0x40003f54; -r_lld_cca_alloc = 0x40003f60; -r_lld_cca_data_reset = 0x40003f6c; -r_lld_cca_free = 0x40003f78; -r_lld_ch_assess_data_get = 0x40003f84; -r_lld_ch_idx_get = 0x40003f90; -r_lld_ch_map_set = 0x40003f9c; -r_lld_channel_assess = 0x40003fa8; -r_lld_con_activity_act_offset_compute = 0x40003fb4; -r_lld_con_activity_offset_compute = 0x40003fc0; -r_lld_con_ch_map_update = 0x40003fcc; -r_lld_con_cleanup = 0x40003fd8; -r_lld_con_current_tx_power_get = 0x40003fe4; -r_lld_con_data_flow_set = 0x40003ff0; -r_lld_con_data_len_update = 0x40003ffc; -r_lld_con_data_tx = 0x40004008; -r_lld_con_enc_key_load = 0x40004014; -r_lld_con_event_counter_get = 0x40004020; -r_lld_con_evt_canceled_cbk = 0x4000402c; -r_lld_con_evt_duration_min_get = 0x40004038; -r_lld_con_evt_max_eff_time_cal = 0x40004044; -r_lld_con_evt_sd_evt_time_get = 0x40004050; -r_lld_con_evt_start_cbk = 0x4000405c; -r_lld_con_evt_time_update = 0x40004068; -r_lld_con_free_all_tx_buf = 0x40004074; -r_lld_con_frm_cbk = 0x40004080; -r_lld_con_frm_isr = 0x4000408c; -r_lld_con_frm_skip_isr = 0x40004098; -r_lld_con_init = 0x400040a4; -r_lld_con_llcp_tx = 0x400040b0; -r_lld_con_max_lat_calc = 0x400040bc; -r_lld_con_offset_get = 0x400040c8; -r_lld_con_param_update = 0x400040d4; -r_lld_con_phys_update = 0x400040e0; -r_lld_con_pref_slave_evt_dur_set = 0x400040ec; -r_lld_con_pref_slave_latency_set = 0x400040f8; -r_lld_con_rssi_get = 0x40004104; -r_lld_con_rx = 0x40004110; -r_lld_con_rx_channel_assess = 0x4000411c; -r_lld_con_rx_enc = 0x40004128; -r_lld_con_rx_isr = 0x40004134; -r_lld_con_rx_link_info_check = 0x40004140; -r_lld_con_rx_llcp_check = 0x4000414c; -r_lld_con_rx_sync_time_update = 0x40004158; -r_lld_con_sched = 0x40004164; -r_lld_con_set_tx_power = 0x40004170; -r_lld_con_start = 0x4000417c; -r_lld_con_stop = 0x40004188; -r_lld_con_tx = 0x40004194; -r_lld_con_tx_enc = 0x400041a0; -r_lld_con_tx_isr = 0x400041ac; -r_lld_con_tx_len_update = 0x400041b8; -r_lld_con_tx_len_update_for_intv = 0x400041c4; -r_lld_con_tx_len_update_for_rate = 0x400041d0; -r_lld_con_tx_prog = 0x400041dc; -r_lld_conn_dynamic_pti_process = 0x400041e8; -r_lld_continue_scan_rx_isr_end_process = 0x400041f4; -r_lld_ext_scan_dynamic_pti_process = 0x40004200; -r_lld_hw_cca_end_isr = 0x4000420c; -r_lld_hw_cca_evt_handler = 0x40004218; -r_lld_hw_cca_isr = 0x40004224; -r_lld_init_cal_anchor_point = 0x40004230; -r_lld_init_compute_winoffset = 0x4000423c; -r_lld_init_connect_req_pack = 0x40004248; -r_lld_init_end = 0x40004254; -r_lld_init_evt_canceled_cbk = 0x40004260; -r_lld_init_evt_start_cbk = 0x4000426c; -r_lld_init_frm_cbk = 0x40004278; -r_lld_init_frm_eof_isr = 0x40004284; -r_lld_init_frm_skip_isr = 0x40004290; -r_lld_init_init = 0x4000429c; -r_lld_init_process_pkt_rx = 0x400042a8; -r_lld_init_process_pkt_rx_adv_ext_ind = 0x400042b4; -r_lld_init_process_pkt_rx_adv_ind_or_direct_ind = 0x400042c0; -r_lld_init_process_pkt_rx_aux_connect_rsp = 0x400042cc; -r_lld_init_process_pkt_tx = 0x400042d8; -r_lld_init_process_pkt_tx_cal_con_timestamp = 0x400042e4; -r_lld_init_sched = 0x400042f0; -r_lld_init_set_tx_power = 0x400042fc; -r_lld_init_start = 0x40004308; -r_lld_init_stop = 0x40004314; -r_lld_instant_proc_end = 0x40004320; -r_lld_llcp_rx_ind_handler = 0x4000432c; -r_lld_per_adv_ch_map_update = 0x40004338; -r_lld_per_adv_chain_construct = 0x40004344; -r_lld_per_adv_cleanup = 0x40004350; -r_lld_per_adv_coex_env_reset = 0x4000435c; -r_lld_per_adv_data_set = 0x40004368; -r_lld_per_adv_data_update = 0x40004374; -r_lld_per_adv_dynamic_pti_process = 0x40004380; -r_lld_per_adv_evt_canceled_cbk = 0x4000438c; -r_lld_per_adv_evt_start_cbk = 0x40004398; -r_lld_per_adv_ext_pkt_prepare = 0x400043a4; -r_lld_per_adv_frm_cbk = 0x400043b0; -r_lld_per_adv_frm_isr = 0x400043bc; -r_lld_per_adv_frm_skip_isr = 0x400043c8; -r_lld_per_adv_init = 0x400043d4; -r_lld_per_adv_init_info_get = 0x400043e0; -r_lld_per_adv_list_add = 0x400043ec; -r_lld_per_adv_list_rem = 0x400043f8; -r_lld_per_adv_sched = 0x40004404; -r_lld_per_adv_set_tx_power = 0x40004410; -r_lld_per_adv_start = 0x4000441c; -r_lld_per_adv_stop = 0x40004428; -r_lld_per_adv_sync_info_get = 0x40004434; -r_lld_process_cca_data = 0x40004440; -r_lld_ral_search = 0x4000444c; -r_lld_read_clock = 0x40004458; -r_lld_res_list_add = 0x40004464; -r_lld_res_list_clear = 0x40004470; -r_lld_res_list_is_empty = 0x4000447c; -r_lld_res_list_local_rpa_get = 0x40004488; -r_lld_res_list_peer_rpa_get = 0x40004494; -r_lld_res_list_peer_update = 0x400044a0; -r_lld_res_list_priv_mode_update = 0x400044ac; -r_lld_res_list_rem = 0x400044b8; -r_lld_reset_reg = 0x400044c4; -r_lld_rpa_renew = 0x400044d0; -r_lld_rpa_renew_evt_canceled_cbk = 0x400044dc; -r_lld_rpa_renew_evt_start_cbk = 0x400044e8; -r_lld_rpa_renew_instant_cbk = 0x400044f4; -r_lld_rxdesc_check = 0x40004500; -r_lld_rxdesc_free = 0x4000450c; -r_lld_scan_create_sync = 0x40004518; -r_lld_scan_create_sync_cancel = 0x40004524; -r_lld_scan_end = 0x40004530; -r_lld_scan_evt_canceled_cbk = 0x4000453c; -r_lld_scan_evt_start_cbk = 0x40004548; -r_lld_scan_frm_cbk = 0x40004554; -r_lld_scan_frm_eof_isr = 0x40004560; -r_lld_scan_frm_rx_isr = 0x4000456c; -r_lld_scan_frm_skip_isr = 0x40004578; -r_lld_scan_init = 0x40004584; -r_lld_scan_params_update = 0x40004590; -r_lld_scan_process_pkt_rx = 0x4000459c; -r_lld_scan_process_pkt_rx_adv_rep = 0x400045a8; -r_lld_scan_process_pkt_rx_aux_adv_ind = 0x400045b4; -r_lld_scan_process_pkt_rx_aux_chain_ind = 0x400045c0; -r_lld_scan_process_pkt_rx_aux_scan_rsp = 0x400045cc; -r_lld_scan_process_pkt_rx_ext_adv = 0x400045d8; -r_lld_scan_process_pkt_rx_ext_adv_ind = 0x400045e4; -r_lld_scan_process_pkt_rx_legacy_adv = 0x400045f0; -r_lld_scan_restart = 0x400045fc; -r_lld_scan_sched = 0x40004608; -r_lld_scan_set_tx_power = 0x40004614; -r_lld_scan_start = 0x40004620; -r_lld_scan_stop = 0x4000462c; -r_lld_scan_sync_accept = 0x40004638; -r_lld_scan_sync_info_unpack = 0x40004644; -r_lld_scan_trunc_ind = 0x40004650; -r_lld_sw_cca_evt_handler = 0x4000465c; -r_lld_sw_cca_isr = 0x40004668; -r_lld_sync_ch_map_update = 0x40004674; -r_lld_sync_cleanup = 0x40004680; -r_lld_sync_evt_canceled_cbk = 0x4000468c; -r_lld_sync_evt_start_cbk = 0x40004698; -r_lld_sync_frm_cbk = 0x400046a4; -r_lld_sync_frm_eof_isr = 0x400046b0; -r_lld_sync_frm_rx_isr = 0x400046bc; -r_lld_sync_frm_skip_isr = 0x400046c8; -r_lld_sync_init = 0x400046d4; -r_lld_sync_process_pkt_rx = 0x400046e0; -r_lld_sync_process_pkt_rx_aux_sync_ind = 0x400046ec; -r_lld_sync_process_pkt_rx_pkt_check = 0x400046f8; -r_lld_sync_scan_dynamic_pti_process = 0x40004704; -r_lld_sync_sched = 0x40004710; -r_lld_sync_start = 0x4000471c; -r_lld_sync_stop = 0x40004728; -r_lld_sync_trunc_ind = 0x40004734; -r_lld_test_cleanup = 0x40004740; -r_lld_test_evt_canceled_cbk = 0x4000474c; -r_lld_test_evt_start_cbk = 0x40004758; -r_lld_test_freq2chnl = 0x40004764; -r_lld_test_frm_cbk = 0x40004770; -r_lld_test_frm_isr = 0x4000477c; -r_lld_test_init = 0x40004788; -r_lld_test_rx_isr = 0x40004794; -r_lld_test_set_tx_power = 0x400047a0; -r_lld_test_start = 0x400047ac; -r_lld_test_stop = 0x400047b8; -r_lld_update_rxbuf = 0x400047c4; -r_lld_update_rxbuf_isr = 0x400047d0; -r_lld_white_list_add = 0x400047dc; -r_lld_white_list_rem = 0x400047e8; -r_llm_activity_free_get = 0x400047f4; -r_llm_activity_free_set = 0x40004800; -r_llm_activity_syncing_get = 0x4000480c; -r_llm_adv_con_len_check = 0x40004818; -r_llm_adv_hdl_to_id = 0x40004824; -r_llm_adv_rep_flow_control_check = 0x40004830; -r_llm_adv_rep_flow_control_update = 0x4000483c; -r_llm_adv_reports_list_check = 0x40004848; -r_llm_adv_set_all_release = 0x40004854; -r_llm_adv_set_dft_params = 0x40004860; -r_llm_adv_set_release = 0x4000486c; -r_llm_aes_res_cb = 0x40004878; -r_llm_ble_update_adv_flow_control = 0x40004884; -r_llm_ch_map_update = 0x40004890; -r_llm_cmd_cmp_send = 0x4000489c; -r_llm_cmd_stat_send = 0x400048a8; -r_llm_dev_list_empty_entry = 0x400048b4; -r_llm_dev_list_search = 0x400048c0; -r_llm_env_adv_dup_filt_deinit = 0x400048cc; -r_llm_env_adv_dup_filt_init = 0x400048d8; -r_llm_init_ble_adv_report_flow_contol = 0x400048e4; -r_llm_is_dev_connected = 0x400048f0; -r_llm_is_dev_synced = 0x400048fc; -r_llm_is_non_con_act_ongoing_check = 0x40004908; -r_llm_is_wl_accessible = 0x40004914; -r_llm_le_evt_mask_check = 0x40004920; -r_llm_le_features_get = 0x4000492c; -r_llm_link_disc = 0x40004938; -r_llm_master_ch_map_get = 0x40004944; -r_llm_msg_handler_tab_p_get = 0x40004950; -r_llm_no_activity = 0x4000495c; -r_llm_per_adv_slot_dur = 0x40004968; -r_llm_plan_elt_get = 0x40004974; -r_llm_rx_path_comp_get = 0x40004980; -r_llm_scan_start = 0x4000498c; -r_llm_scan_sync_acad_attach = 0x40004998; -r_llm_scan_sync_acad_detach = 0x400049a4; -r_llm_send_adv_lost_event_to_host = 0x400049b0; -r_llm_tx_path_comp_get = 0x400049bc; -r_misc_deinit = 0x400049c8; -r_misc_free_em_buf_in_isr = 0x400049d4; -r_misc_init = 0x400049e0; -r_misc_msg_handler_tab_p_get = 0x400049ec; -r_notEqual256 = 0x400049f8; -r_phy_upd_proc_start = 0x40004a04; -r_platform_reset = 0x40004a10; -r_register_esp_vendor_cmd_handler = 0x40004a1c; -r_rf_em_init = 0x40004a28; -r_rf_force_agc_enable = 0x40004a34; -r_rf_reg_rd = 0x40004a40; -r_rf_reg_wr = 0x40004a4c; -r_rf_reset = 0x40004a58; -r_rf_rssi_convert = 0x40004a64; -r_rf_rw_v9_le_disable = 0x40004a70; -r_rf_rw_v9_le_enable = 0x40004a7c; -r_rf_sleep = 0x40004a88; -r_rf_txpwr_cs_get = 0x40004a94; -r_rf_txpwr_dbm_get = 0x40004aa0; -r_rf_util_cs_fmt_convert = 0x40004aac; -r_rw_crypto_aes_ccm = 0x40004ab8; -r_rw_crypto_aes_encrypt = 0x40004ac4; -r_rw_crypto_aes_init = 0x40004ad0; -r_rw_crypto_aes_k1 = 0x40004adc; -r_rw_crypto_aes_k2 = 0x40004ae8; -r_rw_crypto_aes_k3 = 0x40004af4; -r_rw_crypto_aes_k4 = 0x40004b00; -r_rw_crypto_aes_rand = 0x40004b0c; -r_rw_crypto_aes_result_handler = 0x40004b18; -r_rw_crypto_aes_s1 = 0x40004b24; -r_rw_cryto_aes_cmac = 0x40004b30; -r_rw_v9_init_em_radio_table = 0x40004b3c; -r_rwble_isr = 0x40004b48; -r_rwble_sleep_enter = 0x40004b54; -r_rwble_sleep_wakeup_end = 0x40004b60; -r_rwbtdm_isr_wrapper = 0x40004b6c; -r_rwip_active_check = 0x40004b78; -r_rwip_aes_encrypt = 0x40004b84; -r_rwip_assert = 0x40004b90; -r_rwip_crypt_evt_handler = 0x40004b9c; -r_rwip_crypt_isr_handler = 0x40004ba8; -r_rwip_eif_get = 0x40004bb4; -r_rwip_half_slot_2_lpcycles = 0x40004bc0; -r_rwip_hus_2_lpcycles = 0x40004bcc; -r_rwip_isr = 0x40004bd8; -r_rwip_lpcycles_2_hus = 0x40004be4; -r_rwip_prevent_sleep_clear = 0x40004bf0; -r_rwip_prevent_sleep_set = 0x40004bfc; -r_rwip_schedule = 0x40004c08; -r_rwip_sleep = 0x40004c14; -r_rwip_sw_int_handler = 0x40004c20; -r_rwip_sw_int_req = 0x40004c2c; -r_rwip_time_get = 0x40004c38; -r_rwip_timer_10ms_handler = 0x40004c44; -r_rwip_timer_10ms_set = 0x40004c50; -r_rwip_timer_hs_handler = 0x40004c5c; -r_rwip_timer_hs_set = 0x40004c68; -r_rwip_timer_hus_handler = 0x40004c74; -r_rwip_timer_hus_set = 0x40004c80; -r_rwip_wakeup = 0x40004c8c; -r_rwip_wakeup_end = 0x40004c98; -r_rwip_wlcoex_set = 0x40004ca4; -r_sch_alarm_clear = 0x40004cb0; -r_sch_alarm_init = 0x40004cbc; -r_sch_alarm_prog = 0x40004cc8; -r_sch_alarm_set = 0x40004cd4; -r_sch_alarm_timer_isr = 0x40004ce0; -r_sch_arb_conflict_check = 0x40004cec; -r_sch_arb_elt_cancel = 0x40004cf8; -r_sch_arb_event_start_isr = 0x40004d04; -r_sch_arb_init = 0x40004d10; -r_sch_arb_insert = 0x40004d1c; -r_sch_arb_prog_timer = 0x40004d28; -r_sch_arb_remove = 0x40004d34; -r_sch_arb_sw_isr = 0x40004d40; -r_sch_plan_chk = 0x40004d4c; -r_sch_plan_clock_wrap_offset_update = 0x40004d58; -r_sch_plan_init = 0x40004d64; -r_sch_plan_interval_req = 0x40004d70; -r_sch_plan_offset_max_calc = 0x40004d7c; -r_sch_plan_offset_req = 0x40004d88; -r_sch_plan_position_range_compute = 0x40004d94; -r_sch_plan_rem = 0x40004da0; -r_sch_plan_req = 0x40004dac; -r_sch_plan_set = 0x40004db8; -r_sch_prog_end_isr = 0x40004dc4; -r_sch_prog_init = 0x40004dd0; -r_sch_prog_push = 0x40004ddc; -r_sch_prog_rx_isr = 0x40004de8; -r_sch_prog_skip_isr = 0x40004df4; -r_sch_prog_tx_isr = 0x40004e00; -r_sch_slice_bg_add = 0x40004e0c; -r_sch_slice_bg_remove = 0x40004e18; -r_sch_slice_compute = 0x40004e24; -r_sch_slice_fg_add = 0x40004e30; -r_sch_slice_fg_remove = 0x40004e3c; -r_sch_slice_init = 0x40004e48; -r_sch_slice_per_add = 0x40004e54; -r_sch_slice_per_remove = 0x40004e60; -r_sdk_config_get_bt_sleep_enable = 0x40004e6c; -r_sdk_config_get_hl_derived_opts = 0x40004e78; -r_sdk_config_get_opts = 0x40004e84; -r_sdk_config_get_priv_opts = 0x40004e90; -r_sdk_config_set_bt_sleep_enable = 0x40004e9c; -r_sdk_config_set_hl_derived_opts = 0x40004ea8; -r_sdk_config_set_opts = 0x40004eb4; -r_specialModP256 = 0x40004ec0; -r_unloaded_area_init = 0x40004ecc; -r_vhci_flow_off = 0x40004ed8; -r_vhci_flow_on = 0x40004ee4; -r_vhci_notify_host_send_available = 0x40004ef0; -r_vhci_send_to_host = 0x40004efc; -r_vnd_hci_command_handler = 0x40004f08; -r_vshci_init = 0x40004f14; -vnd_hci_command_handler_wrapper = 0x40004f20; +bt_rf_coex_get_dft_cfg = 0x40002a78; +bt_rf_coex_hooks_p_set = 0x40002a84; +btdm_con_maxevtime_cal_impl = 0x40002a90; +btdm_controller_get_compile_version_impl = 0x40002a9c; +btdm_controller_rom_data_init = 0x40002aa8; +btdm_dis_privacy_err_report_impl = 0x40002ab4; +btdm_disable_adv_delay_impl = 0x40002ac0; +btdm_enable_scan_continue_impl = 0x40002acc; +btdm_enable_scan_forever_impl = 0x40002ad8; +btdm_get_power_state_impl = 0x40002ae4; +btdm_get_prevent_sleep_flag_impl = 0x40002af0; +btdm_power_state_active_impl = 0x40002afc; +btdm_switch_phy_coded_impl = 0x40002b08; +hci_acl_data_handler = 0x40002b14; +hci_disconnect_cmd_handler = 0x40002b20; +hci_le_con_upd_cmd_handler = 0x40002b2c; +hci_le_ltk_req_neg_reply_cmd_handler = 0x40002b38; +hci_le_ltk_req_reply_cmd_handler = 0x40002b44; +hci_le_rd_chnl_map_cmd_handler = 0x40002b50; +hci_le_rd_phy_cmd_handler = 0x40002b5c; +hci_le_rd_rem_feats_cmd_handler = 0x40002b68; +hci_le_rem_con_param_req_neg_reply_cmd_handler = 0x40002b74; +hci_le_rem_con_param_req_reply_cmd_handler = 0x40002b80; +hci_le_set_data_len_cmd_handler = 0x40002b8c; +hci_le_set_phy_cmd_handler = 0x40002b98; +hci_le_start_enc_cmd_handler = 0x40002ba4; +hci_rd_auth_payl_to_cmd_handler = 0x40002bb0; +hci_rd_rem_ver_info_cmd_handler = 0x40002bbc; +hci_rd_rssi_cmd_handler = 0x40002bc8; +hci_rd_tx_pwr_lvl_cmd_handler = 0x40002bd4; +hci_vs_set_pref_slave_evt_dur_cmd_handler = 0x40002be0; +hci_vs_set_pref_slave_latency_cmd_handler = 0x40002bec; +hci_wr_auth_payl_to_cmd_handler = 0x40002bf8; +ll_channel_map_ind_handler = 0x40002c04; +ll_connection_param_req_handler = 0x40002c10; +ll_connection_param_rsp_handler = 0x40002c1c; +ll_connection_update_ind_handler = 0x40002c28; +ll_enc_req_handler = 0x40002c34; +ll_enc_rsp_handler = 0x40002c40; +ll_feature_req_handler = 0x40002c4c; +ll_feature_rsp_handler = 0x40002c58; +ll_length_req_handler = 0x40002c64; +ll_length_rsp_handler = 0x40002c70; +ll_min_used_channels_ind_handler = 0x40002c7c; +ll_pause_enc_req_handler = 0x40002c88; +ll_pause_enc_rsp_handler = 0x40002c94; +ll_phy_req_handler = 0x40002ca0; +ll_phy_rsp_handler = 0x40002cac; +ll_phy_update_ind_handler = 0x40002cb8; +ll_ping_req_handler = 0x40002cc4; +ll_ping_rsp_handler = 0x40002cd0; +ll_slave_feature_req_handler = 0x40002cdc; +ll_start_enc_req_handler = 0x40002ce8; +ll_start_enc_rsp_handler = 0x40002cf4; +ll_terminate_ind_handler = 0x40002d00; +ll_version_ind_handler = 0x40002d0c; +llc_auth_payl_nearly_to_handler = 0x40002d18; +llc_auth_payl_real_to_handler = 0x40002d24; +llc_encrypt_ind_handler = 0x40002d30; +llc_hci_command_handler_wrapper = 0x40002d3c; +llc_ll_connection_param_req_pdu_send = 0x40002d48; +llc_ll_connection_param_rsp_pdu_send = 0x40002d54; +llc_ll_connection_update_ind_pdu_send = 0x40002d60; +llc_ll_enc_req_pdu_send = 0x40002d6c; +llc_ll_enc_rsp_pdu_send = 0x40002d78; +llc_ll_feature_req_pdu_send = 0x40002d84; +llc_ll_feature_rsp_pdu_send = 0x40002d90; +llc_ll_length_req_pdu_send = 0x40002d9c; +llc_ll_length_rsp_pdu_send = 0x40002da8; +llc_ll_pause_enc_req_pdu_send = 0x40002db4; +llc_ll_pause_enc_rsp_pdu_send = 0x40002dc0; +llc_ll_phy_req_pdu_send = 0x40002dcc; +llc_ll_phy_rsp_pdu_send = 0x40002dd8; +llc_ll_ping_req_pdu_send = 0x40002de4; +llc_ll_ping_rsp_pdu_send = 0x40002df0; +llc_ll_start_enc_req_pdu_send = 0x40002dfc; +llc_ll_start_enc_rsp_pdu_send = 0x40002e08; +llc_ll_terminate_ind_pdu_send = 0x40002e14; +llc_ll_unknown_rsp_pdu_send = 0x40002e20; +llc_llcp_ch_map_update_ind_pdu_send = 0x40002e2c; +llc_llcp_phy_upd_ind_pdu_send = 0x40002e38; +llc_llcp_version_ind_pdu_send = 0x40002e44; +llc_op_ch_map_upd_ind_handler = 0x40002e50; +llc_op_con_upd_ind_handler = 0x40002e5c; +llc_op_disconnect_ind_handler = 0x40002e68; +llc_op_dl_upd_ind_handler = 0x40002e74; +llc_op_encrypt_ind_handler = 0x40002e80; +llc_op_feats_exch_ind_handler = 0x40002e8c; +llc_op_le_ping_ind_handler = 0x40002e98; +llc_op_phy_upd_ind_handler = 0x40002ea4; +llc_op_ver_exch_ind_handler = 0x40002eb0; +llc_stopped_ind_handler = 0x40002ebc; +lld_acl_rx_ind_handler = 0x40002ec8; +lld_acl_tx_cfm_handler = 0x40002ed4; +lld_adv_end_ind_handler = 0x40002ee0; +lld_adv_rep_ind_handler = 0x40002eec; +lld_ch_map_upd_cfm_handler = 0x40002ef8; +lld_con_estab_ind_handler = 0x40002f04; +lld_con_evt_sd_evt_time_set = 0x40002f10; +lld_con_offset_upd_ind_handler = 0x40002f1c; +lld_con_param_upd_cfm_handler = 0x40002f28; +lld_disc_ind_handler = 0x40002f34; +lld_init_end_ind_handler = 0x40002f40; +lld_llcp_rx_ind_handler_wrapper = 0x40002f4c; +lld_llcp_tx_cfm_handler = 0x40002f58; +lld_per_adv_end_ind_handler = 0x40002f64; +lld_per_adv_rep_ind_handler = 0x40002f70; +lld_per_adv_rx_end_ind_handler = 0x40002f7c; +lld_phy_coded_500k_get = 0x40002f88; +lld_phy_upd_cfm_handler = 0x40002f94; +lld_scan_end_ind_handler = 0x40002fa0; +lld_scan_req_ind_handler = 0x40002fac; +lld_sync_start_req_handler = 0x40002fb8; +lld_test_end_ind_handler = 0x40002fc4; +lld_update_rxbuf_handler = 0x40002fd0; +llm_ch_map_update_ind_handler = 0x40002fdc; +llm_hci_command_handler_wrapper = 0x40002fe8; +llm_scan_period_to_handler = 0x40002ff4; +r_Add2SelfBigHex256 = 0x40003000; +r_AddBigHex256 = 0x4000300c; +r_AddBigHexModP256 = 0x40003018; +r_AddP256 = 0x40003024; +r_AddPdiv2_256 = 0x40003030; +r_GF_Jacobian_Point_Addition256 = 0x4000303c; +r_GF_Jacobian_Point_Double256 = 0x40003048; +r_GF_Point_Jacobian_To_Affine256 = 0x40003054; +r_MultiplyBigHexByUint32_256 = 0x40003060; +r_MultiplyBigHexModP256 = 0x4000306c; +r_MultiplyByU16ModP256 = 0x40003078; +r_SubtractBigHex256 = 0x40003084; +r_SubtractBigHexMod256 = 0x40003090; +r_SubtractBigHexUint32_256 = 0x4000309c; +r_SubtractFromSelfBigHex256 = 0x400030a8; +r_SubtractFromSelfBigHexSign256 = 0x400030b4; +r_aes_alloc = 0x400030c0; +r_aes_ccm_continue = 0x400030cc; +r_aes_ccm_process_e = 0x400030d8; +r_aes_ccm_xor_128_lsb = 0x400030e4; +r_aes_ccm_xor_128_msb = 0x400030f0; +r_aes_cmac_continue = 0x400030fc; +r_aes_cmac_start = 0x40003108; +r_aes_k1_continue = 0x40003114; +r_aes_k2_continue = 0x40003120; +r_aes_k3_continue = 0x4000312c; +r_aes_k4_continue = 0x40003138; +r_aes_shift_left_128 = 0x40003144; +r_aes_start = 0x40003150; +r_aes_xor_128 = 0x4000315c; +r_assert_err = 0x40003168; +r_assert_param = 0x40003174; +r_assert_warn = 0x40003180; +r_bigHexInversion256 = 0x4000318c; +r_ble_sw_cca_check_isr = 0x40003198; +r_ble_util_buf_acl_tx_alloc = 0x400031a4; +r_ble_util_buf_acl_tx_elt_get = 0x400031b0; +r_ble_util_buf_acl_tx_free = 0x400031bc; +r_ble_util_buf_acl_tx_free_in_isr = 0x400031c8; +r_ble_util_buf_adv_tx_alloc = 0x400031d4; +r_ble_util_buf_adv_tx_free = 0x400031e0; +r_ble_util_buf_adv_tx_free_in_isr = 0x400031ec; +r_ble_util_buf_env_deinit = 0x400031f8; +r_ble_util_buf_env_init = 0x40003204; +r_ble_util_buf_get_rx_buf_nb = 0x40003210; +r_ble_util_buf_get_rx_buf_size = 0x4000321c; +r_ble_util_buf_llcp_tx_alloc = 0x40003228; +r_ble_util_buf_llcp_tx_free = 0x40003234; +r_ble_util_buf_rx_alloc = 0x40003240; +r_ble_util_buf_rx_alloc_in_isr = 0x4000324c; +r_ble_util_buf_rx_free = 0x40003258; +r_ble_util_buf_rx_free_in_isr = 0x40003264; +r_ble_util_buf_set_rx_buf_nb = 0x40003270; +r_ble_util_buf_set_rx_buf_size = 0x4000327c; +r_ble_util_data_rx_buf_reset = 0x40003288; +r_bt_bb_get_intr_mask = 0x40003294; +r_bt_bb_intr_clear = 0x400032a0; +r_bt_bb_intr_mask_set = 0x400032ac; +r_bt_bb_isr = 0x400032b8; +r_bt_rf_coex_cfg_set = 0x400032c4; +r_bt_rf_coex_conn_dynamic_pti_en_get = 0x400032d0; +r_bt_rf_coex_conn_phy_coded_data_time_limit_en_get = 0x400032dc; +r_bt_rf_coex_ext_adv_dynamic_pti_en_get = 0x400032e8; +r_bt_rf_coex_ext_scan_dynamic_pti_en_get = 0x400032f4; +r_bt_rf_coex_legacy_adv_dynamic_pti_en_get = 0x40003300; +r_bt_rf_coex_per_adv_dynamic_pti_en_get = 0x4000330c; +r_bt_rf_coex_pti_table_get = 0x40003318; +r_bt_rf_coex_st_param_get = 0x40003324; +r_bt_rf_coex_st_param_set = 0x40003330; +r_bt_rf_coex_sync_scan_dynamic_pti_en_get = 0x4000333c; +r_bt_rma_apply_rule_cs_fmt = 0x40003348; +r_bt_rma_apply_rule_cs_idx = 0x40003354; +r_bt_rma_configure = 0x40003360; +r_bt_rma_deregister_rule_cs_fmt = 0x4000336c; +r_bt_rma_deregister_rule_cs_idx = 0x40003378; +r_bt_rma_get_ant_by_act = 0x40003384; +r_bt_rma_init = 0x40003390; +r_bt_rma_register_rule_cs_fmt = 0x4000339c; +r_bt_rma_register_rule_cs_idx = 0x400033a8; +r_bt_rtp_apply_rule_cs_fmt = 0x400033b4; +r_bt_rtp_apply_rule_cs_idx = 0x400033c0; +r_bt_rtp_deregister_rule_cs_fmt = 0x400033cc; +r_bt_rtp_deregister_rule_cs_idx = 0x400033d8; +r_bt_rtp_get_txpwr_idx_by_act = 0x400033e4; +r_bt_rtp_init = 0x400033f0; +r_bt_rtp_register_rule_cs_fmt = 0x400033fc; +r_bt_rtp_register_rule_cs_idx = 0x40003408; +r_btdm_isr = 0x40003414; +r_btdm_task_post = 0x40003420; +r_btdm_task_post_from_isr = 0x4000342c; +r_btdm_task_recycle = 0x40003438; +r_cali_phase_match_p = 0x40003444; +r_cmp_abs_time = 0x40003450; +r_cmp_dest_id = 0x4000345c; +r_cmp_timer_id = 0x40003468; +r_co_bdaddr_compare = 0x40003474; +r_co_ble_pkt_dur_in_us = 0x40003480; +r_co_list_extract = 0x4000348c; +r_co_list_extract_after = 0x40003498; +r_co_list_extract_sublist = 0x400034a4; +r_co_list_find = 0x400034b0; +r_co_list_init = 0x400034bc; +r_co_list_insert_after = 0x400034c8; +r_co_list_insert_before = 0x400034d4; +r_co_list_merge = 0x400034e0; +r_co_list_pool_init = 0x400034ec; +r_co_list_pop_front = 0x400034f8; +r_co_list_push_back = 0x40003504; +r_co_list_push_back_sublist = 0x40003510; +r_co_list_push_front = 0x4000351c; +r_co_list_size = 0x40003528; +r_co_nb_good_le_channels = 0x40003534; +r_co_util_pack = 0x40003540; +r_co_util_read_array_size = 0x4000354c; +r_co_util_unpack = 0x40003558; +r_dbg_env_deinit = 0x40003564; +r_dbg_env_init = 0x40003570; +r_dbg_platform_reset_complete = 0x4000357c; +r_dl_upd_proc_start = 0x40003588; +r_dump_data = 0x40003594; +r_ecc_abort_key256_generation = 0x400035a0; +r_ecc_gen_new_public_key = 0x400035ac; +r_ecc_gen_new_secret_key = 0x400035b8; +r_ecc_generate_key256 = 0x400035c4; +r_ecc_get_debug_Keys = 0x400035d0; +r_ecc_init = 0x400035dc; +r_ecc_is_valid_point = 0x400035e8; +r_ecc_multiplication_event_handler = 0x400035f4; +r_ecc_point_multiplication_win_256 = 0x40003600; +r_emi_alloc_em_mapping_by_offset = 0x4000360c; +r_emi_base_reg_lut_show = 0x40003618; +r_emi_em_base_reg_show = 0x40003624; +r_emi_free_em_mapping_by_offset = 0x40003630; +r_emi_get_em_mapping_idx_by_offset = 0x4000363c; +r_emi_get_mem_addr_by_offset = 0x40003648; +r_emi_overwrite_em_mapping_by_offset = 0x40003654; +r_esp_vendor_hci_command_handler = 0x40003660; +r_get_stack_usage = 0x4000366c; +r_h4tl_acl_hdr_rx_evt_handler = 0x40003678; +r_h4tl_cmd_hdr_rx_evt_handler = 0x40003684; +r_h4tl_cmd_pld_rx_evt_handler = 0x40003690; +r_h4tl_eif_io_event_post = 0x4000369c; +r_h4tl_eif_register = 0x400036a8; +r_h4tl_init = 0x400036b4; +r_h4tl_out_of_sync = 0x400036c0; +r_h4tl_out_of_sync_check = 0x400036cc; +r_h4tl_read_hdr = 0x400036d8; +r_h4tl_read_next_out_of_sync = 0x400036e4; +r_h4tl_read_payl = 0x400036f0; +r_h4tl_read_start = 0x400036fc; +r_h4tl_rx_acl_hdr_extract = 0x40003708; +r_h4tl_rx_cmd_hdr_extract = 0x40003714; +r_h4tl_rx_done = 0x40003720; +r_h4tl_start = 0x4000372c; +r_h4tl_stop = 0x40003738; +r_h4tl_tx_done = 0x40003744; +r_h4tl_tx_evt_handler = 0x40003750; +r_h4tl_write = 0x4000375c; +r_hci_acl_tx_data_alloc = 0x40003768; +r_hci_acl_tx_data_received = 0x40003774; +r_hci_basic_cmd_send_2_controller = 0x40003780; +r_hci_ble_adv_report_filter_check = 0x4000378c; +r_hci_ble_adv_report_tx_check = 0x40003798; +r_hci_ble_conhdl_register = 0x400037a4; +r_hci_ble_conhdl_unregister = 0x400037b0; +r_hci_build_acl_data = 0x400037bc; +r_hci_build_cc_evt = 0x400037c8; +r_hci_build_cs_evt = 0x400037d4; +r_hci_build_evt = 0x400037e0; +r_hci_build_le_evt = 0x400037ec; +r_hci_cmd_get_max_param_size = 0x400037f8; +r_hci_cmd_received = 0x40003804; +r_hci_cmd_reject = 0x40003810; +r_hci_evt_mask_check = 0x4000381c; +r_hci_evt_mask_set = 0x40003828; +r_hci_fc_acl_buf_size_set = 0x40003834; +r_hci_fc_acl_en = 0x40003840; +r_hci_fc_acl_packet_sent = 0x4000384c; +r_hci_fc_check_host_available_nb_acl_packets = 0x40003858; +r_hci_fc_host_nb_acl_pkts_complete = 0x40003864; +r_hci_fc_init = 0x40003870; +r_hci_look_for_cmd_desc = 0x4000387c; +r_hci_look_for_evt_desc = 0x40003888; +r_hci_look_for_le_evt_desc = 0x40003894; +r_hci_look_for_le_evt_desc_esp = 0x400038a0; +r_hci_pack_bytes = 0x400038ac; +r_hci_register_vendor_desc_tab = 0x400038b8; +r_hci_send_2_controller = 0x400038c4; +r_hci_send_2_host = 0x400038d0; +r_hci_tl_c2h_data_flow_on = 0x400038dc; +r_hci_tl_cmd_hdr_rx_evt_handler = 0x400038e8; +r_hci_tl_cmd_pld_rx_evt_handler = 0x400038f4; +r_hci_tl_get_pkt = 0x40003900; +r_hci_tl_hci_pkt_handler = 0x4000390c; +r_hci_tl_hci_tx_done_evt_handler = 0x40003918; +r_hci_tl_inc_nb_h2c_cmd_pkts = 0x40003924; +r_hci_tl_save_pkt = 0x40003930; +r_hci_tl_send = 0x4000393c; +r_hci_tx_done = 0x40003948; +r_hci_tx_start = 0x40003954; +r_hci_tx_trigger = 0x40003960; +r_isValidSecretKey_256 = 0x4000396c; +r_ke_check_malloc = 0x40003978; +r_ke_event_callback_set = 0x40003984; +r_ke_event_clear = 0x40003990; +r_ke_event_flush = 0x4000399c; +r_ke_event_get = 0x400039a8; +r_ke_event_get_all = 0x400039b4; +r_ke_event_init = 0x400039c0; +r_ke_event_schedule = 0x400039cc; +r_ke_event_set = 0x400039d8; +r_ke_flush = 0x400039e4; +r_ke_free = 0x400039f0; +r_ke_handler_search = 0x400039fc; +r_ke_init = 0x40003a08; +r_ke_is_free = 0x40003a14; +r_ke_malloc = 0x40003a20; +r_ke_mem_init = 0x40003a2c; +r_ke_mem_is_empty = 0x40003a38; +r_ke_mem_is_in_heap = 0x40003a44; +r_ke_msg_alloc = 0x40003a50; +r_ke_msg_dest_id_get = 0x40003a5c; +r_ke_msg_discard = 0x40003a68; +r_ke_msg_forward = 0x40003a74; +r_ke_msg_forward_new_id = 0x40003a80; +r_ke_msg_free = 0x40003a8c; +r_ke_msg_in_queue = 0x40003a98; +r_ke_msg_save = 0x40003aa4; +r_ke_msg_send = 0x40003ab0; +r_ke_msg_send_basic = 0x40003abc; +r_ke_msg_src_id_get = 0x40003ac8; +r_ke_queue_extract = 0x40003ad4; +r_ke_queue_insert = 0x40003ae0; +r_ke_sleep_check = 0x40003aec; +r_ke_state_get = 0x40003af8; +r_ke_state_set = 0x40003b04; +r_ke_task_check = 0x40003b10; +r_ke_task_create = 0x40003b1c; +r_ke_task_delete = 0x40003b28; +r_ke_task_handler_get = 0x40003b34; +r_ke_task_init = 0x40003b40; +r_ke_task_msg_flush = 0x40003b4c; +r_ke_task_saved_update = 0x40003b58; +r_ke_task_schedule = 0x40003b64; +r_ke_time = 0x40003b70; +r_ke_time_cmp = 0x40003b7c; +r_ke_time_past = 0x40003b88; +r_ke_timer_active = 0x40003b94; +r_ke_timer_adjust_all = 0x40003ba0; +r_ke_timer_clear = 0x40003bac; +r_ke_timer_init = 0x40003bb8; +r_ke_timer_schedule = 0x40003bc4; +r_ke_timer_set = 0x40003bd0; +r_led_init = 0x40003bdc; +r_led_set_all = 0x40003be8; +r_llc_aes_res_cb = 0x40003bf4; +r_llc_ch_map_up_proc_err_cb = 0x40003c00; +r_llc_cleanup = 0x40003c0c; +r_llc_cmd_cmp_send = 0x40003c18; +r_llc_cmd_stat_send = 0x40003c24; +r_llc_con_move_cbk = 0x40003c30; +r_llc_con_plan_set_update = 0x40003c3c; +r_llc_con_upd_param_in_range = 0x40003c48; +r_llc_disconnect = 0x40003c54; +r_llc_disconnect_end = 0x40003c60; +r_llc_disconnect_proc_continue = 0x40003c6c; +r_llc_disconnect_proc_err_cb = 0x40003c78; +r_llc_dl_chg_check = 0x40003c84; +r_llc_dle_proc_err_cb = 0x40003c90; +r_llc_feats_exch_proc_err_cb = 0x40003c9c; +r_llc_hci_cmd_handler_tab_p_get = 0x40003ca8; +r_llc_hci_command_handler = 0x40003cb4; +r_llc_hci_con_param_req_evt_send = 0x40003cc0; +r_llc_hci_con_upd_info_send = 0x40003ccc; +r_llc_hci_disconnected_dis = 0x40003cd8; +r_llc_hci_dl_upd_info_send = 0x40003ce4; +r_llc_hci_enc_evt_send = 0x40003cf0; +r_llc_hci_feats_info_send = 0x40003cfc; +r_llc_hci_le_phy_upd_cmp_evt_send = 0x40003d08; +r_llc_hci_ltk_request_evt_send = 0x40003d14; +r_llc_hci_nb_cmp_pkts_evt_send = 0x40003d20; +r_llc_hci_version_info_send = 0x40003d2c; +r_llc_init_term_proc = 0x40003d38; +r_llc_iv_skd_rand_gen = 0x40003d44; +r_llc_le_ping_proc_continue = 0x40003d50; +r_llc_le_ping_proc_err_cb = 0x40003d5c; +r_llc_le_ping_restart = 0x40003d68; +r_llc_le_ping_set = 0x40003d74; +r_llc_ll_pause_enc_rsp_ack_handler = 0x40003d80; +r_llc_ll_reject_ind_ack_handler = 0x40003d8c; +r_llc_ll_reject_ind_pdu_send = 0x40003d98; +r_llc_ll_start_enc_rsp_ack_handler = 0x40003da4; +r_llc_ll_terminate_ind_ack = 0x40003db0; +r_llc_ll_unknown_ind_handler = 0x40003dbc; +r_llc_llcp_send = 0x40003dc8; +r_llc_llcp_state_set = 0x40003dd4; +r_llc_llcp_trans_timer_set = 0x40003de0; +r_llc_llcp_tx_check = 0x40003dec; +r_llc_loc_ch_map_proc_continue = 0x40003df8; +r_llc_loc_con_upd_proc_continue = 0x40003e04; +r_llc_loc_con_upd_proc_err_cb = 0x40003e10; +r_llc_loc_dl_upd_proc_continue = 0x40003e1c; +r_llc_loc_encrypt_proc_continue = 0x40003e28; +r_llc_loc_encrypt_proc_err_cb = 0x40003e34; +r_llc_loc_feats_exch_proc_continue = 0x40003e40; +r_llc_loc_phy_upd_proc_continue = 0x40003e4c; +r_llc_loc_phy_upd_proc_err_cb = 0x40003e58; +r_llc_msg_handler_tab_p_get = 0x40003e64; +r_llc_pref_param_compute = 0x40003e70; +r_llc_proc_collision_check = 0x40003e7c; +r_llc_proc_err_ind = 0x40003e88; +r_llc_proc_get = 0x40003e94; +r_llc_proc_id_get = 0x40003ea0; +r_llc_proc_reg = 0x40003eac; +r_llc_proc_state_get = 0x40003eb8; +r_llc_proc_state_set = 0x40003ec4; +r_llc_proc_timer_pause_set = 0x40003ed0; +r_llc_proc_timer_set = 0x40003edc; +r_llc_proc_unreg = 0x40003ee8; +r_llc_rem_ch_map_proc_continue = 0x40003ef4; +r_llc_rem_con_upd_proc_continue = 0x40003f00; +r_llc_rem_con_upd_proc_err_cb = 0x40003f0c; +r_llc_rem_dl_upd_proc = 0x40003f18; +r_llc_rem_encrypt_proc_continue = 0x40003f24; +r_llc_rem_encrypt_proc_err_cb = 0x40003f30; +r_llc_rem_phy_upd_proc_continue = 0x40003f3c; +r_llc_rem_phy_upd_proc_err_cb = 0x40003f48; +r_llc_role_get = 0x40003f54; +r_llc_sk_gen = 0x40003f60; +r_llc_start = 0x40003f6c; +r_llc_stop = 0x40003f78; +r_llc_ver_exch_loc_proc_continue = 0x40003f84; +r_llc_ver_proc_err_cb = 0x40003f90; +r_llcp_pdu_handler_tab_p_get = 0x40003f9c; +r_lld_aa_gen = 0x40003fa8; +r_lld_adv_adv_data_set = 0x40003fb4; +r_lld_adv_adv_data_update = 0x40003fc0; +r_lld_adv_aux_ch_idx_set = 0x40003fcc; +r_lld_adv_aux_evt_canceled_cbk = 0x40003fd8; +r_lld_adv_aux_evt_start_cbk = 0x40003fe4; +r_lld_adv_coex_check_ext_adv_synced = 0x40003ff0; +r_lld_adv_coex_env_reset = 0x40003ffc; +r_lld_adv_duration_update = 0x40004008; +r_lld_adv_dynamic_pti_process = 0x40004014; +r_lld_adv_end = 0x40004020; +r_lld_adv_evt_canceled_cbk = 0x4000402c; +r_lld_adv_evt_start_cbk = 0x40004038; +r_lld_adv_ext_chain_construct = 0x40004044; +r_lld_adv_ext_pkt_prepare = 0x40004050; +r_lld_adv_frm_cbk = 0x4000405c; +r_lld_adv_frm_isr = 0x40004068; +r_lld_adv_frm_skip_isr = 0x40004074; +r_lld_adv_init = 0x40004080; +r_lld_adv_pkt_rx = 0x4000408c; +r_lld_adv_pkt_rx_connect_ind = 0x40004098; +r_lld_adv_pkt_rx_send_scan_req_evt = 0x400040a4; +r_lld_adv_rand_addr_update = 0x400040b0; +r_lld_adv_restart = 0x400040bc; +r_lld_adv_scan_rsp_data_set = 0x400040c8; +r_lld_adv_scan_rsp_data_update = 0x400040d4; +r_lld_adv_set_tx_power = 0x400040e0; +r_lld_adv_start = 0x400040ec; +r_lld_adv_stop = 0x400040f8; +r_lld_adv_sync_info_set = 0x40004104; +r_lld_adv_sync_info_update = 0x40004110; +r_lld_calc_aux_rx = 0x4000411c; +r_lld_cca_alloc = 0x40004128; +r_lld_cca_data_reset = 0x40004134; +r_lld_cca_free = 0x40004140; +r_lld_ch_assess_data_get = 0x4000414c; +r_lld_ch_idx_get = 0x40004158; +r_lld_ch_map_set = 0x40004164; +r_lld_channel_assess = 0x40004170; +r_lld_con_activity_act_offset_compute = 0x4000417c; +r_lld_con_activity_offset_compute = 0x40004188; +r_lld_con_ch_map_update = 0x40004194; +r_lld_con_cleanup = 0x400041a0; +r_lld_con_current_tx_power_get = 0x400041ac; +r_lld_con_data_flow_set = 0x400041b8; +r_lld_con_data_len_update = 0x400041c4; +r_lld_con_data_tx = 0x400041d0; +r_lld_con_enc_key_load = 0x400041dc; +r_lld_con_event_counter_get = 0x400041e8; +r_lld_con_evt_canceled_cbk = 0x400041f4; +r_lld_con_evt_duration_min_get = 0x40004200; +r_lld_con_evt_max_eff_time_cal = 0x4000420c; +r_lld_con_evt_sd_evt_time_get = 0x40004218; +r_lld_con_evt_start_cbk = 0x40004224; +r_lld_con_evt_time_update = 0x40004230; +r_lld_con_free_all_tx_buf = 0x4000423c; +r_lld_con_frm_cbk = 0x40004248; +r_lld_con_frm_isr = 0x40004254; +r_lld_con_frm_skip_isr = 0x40004260; +r_lld_con_init = 0x4000426c; +r_lld_con_llcp_tx = 0x40004278; +r_lld_con_max_lat_calc = 0x40004284; +r_lld_con_offset_get = 0x40004290; +r_lld_con_param_update = 0x4000429c; +r_lld_con_phys_update = 0x400042a8; +r_lld_con_pref_slave_evt_dur_set = 0x400042b4; +r_lld_con_pref_slave_latency_set = 0x400042c0; +r_lld_con_rssi_get = 0x400042cc; +r_lld_con_rx = 0x400042d8; +r_lld_con_rx_channel_assess = 0x400042e4; +r_lld_con_rx_enc = 0x400042f0; +r_lld_con_rx_isr = 0x400042fc; +r_lld_con_rx_link_info_check = 0x40004308; +r_lld_con_rx_llcp_check = 0x40004314; +r_lld_con_rx_sync_time_update = 0x40004320; +r_lld_con_sched = 0x4000432c; +r_lld_con_set_tx_power = 0x40004338; +r_lld_con_start = 0x40004344; +r_lld_con_stop = 0x40004350; +r_lld_con_tx = 0x4000435c; +r_lld_con_tx_enc = 0x40004368; +r_lld_con_tx_isr = 0x40004374; +r_lld_con_tx_len_update = 0x40004380; +r_lld_con_tx_len_update_for_intv = 0x4000438c; +r_lld_con_tx_len_update_for_rate = 0x40004398; +r_lld_con_tx_prog = 0x400043a4; +r_lld_conn_dynamic_pti_process = 0x400043b0; +r_lld_continue_scan_rx_isr_end_process = 0x400043bc; +r_lld_ext_scan_dynamic_pti_process = 0x400043c8; +r_lld_hw_cca_end_isr = 0x400043d4; +r_lld_hw_cca_evt_handler = 0x400043e0; +r_lld_hw_cca_isr = 0x400043ec; +r_lld_init_cal_anchor_point = 0x400043f8; +r_lld_init_compute_winoffset = 0x40004404; +r_lld_init_connect_req_pack = 0x40004410; +r_lld_init_end = 0x4000441c; +r_lld_init_evt_canceled_cbk = 0x40004428; +r_lld_init_evt_start_cbk = 0x40004434; +r_lld_init_frm_cbk = 0x40004440; +r_lld_init_frm_eof_isr = 0x4000444c; +r_lld_init_frm_skip_isr = 0x40004458; +r_lld_init_init = 0x40004464; +r_lld_init_process_pkt_rx = 0x40004470; +r_lld_init_process_pkt_rx_adv_ext_ind = 0x4000447c; +r_lld_init_process_pkt_rx_adv_ind_or_direct_ind = 0x40004488; +r_lld_init_process_pkt_rx_aux_connect_rsp = 0x40004494; +r_lld_init_process_pkt_tx = 0x400044a0; +r_lld_init_process_pkt_tx_cal_con_timestamp = 0x400044ac; +r_lld_init_sched = 0x400044b8; +r_lld_init_set_tx_power = 0x400044c4; +r_lld_init_start = 0x400044d0; +r_lld_init_stop = 0x400044dc; +r_lld_instant_proc_end = 0x400044e8; +r_lld_llcp_rx_ind_handler = 0x400044f4; +r_lld_per_adv_ch_map_update = 0x40004500; +r_lld_per_adv_chain_construct = 0x4000450c; +r_lld_per_adv_cleanup = 0x40004518; +r_lld_per_adv_coex_env_reset = 0x40004524; +r_lld_per_adv_data_set = 0x40004530; +r_lld_per_adv_data_update = 0x4000453c; +r_lld_per_adv_dynamic_pti_process = 0x40004548; +r_lld_per_adv_evt_canceled_cbk = 0x40004554; +r_lld_per_adv_evt_start_cbk = 0x40004560; +r_lld_per_adv_ext_pkt_prepare = 0x4000456c; +r_lld_per_adv_frm_cbk = 0x40004578; +r_lld_per_adv_frm_isr = 0x40004584; +r_lld_per_adv_frm_skip_isr = 0x40004590; +r_lld_per_adv_init = 0x4000459c; +r_lld_per_adv_init_info_get = 0x400045a8; +r_lld_per_adv_list_add = 0x400045b4; +r_lld_per_adv_list_rem = 0x400045c0; +r_lld_per_adv_sched = 0x400045cc; +r_lld_per_adv_set_tx_power = 0x400045d8; +r_lld_per_adv_start = 0x400045e4; +r_lld_per_adv_stop = 0x400045f0; +r_lld_per_adv_sync_info_get = 0x400045fc; +r_lld_process_cca_data = 0x40004608; +r_lld_ral_search = 0x40004614; +r_lld_read_clock = 0x40004620; +r_lld_res_list_add = 0x4000462c; +r_lld_res_list_clear = 0x40004638; +r_lld_res_list_is_empty = 0x40004644; +r_lld_res_list_local_rpa_get = 0x40004650; +r_lld_res_list_peer_rpa_get = 0x4000465c; +r_lld_res_list_peer_update = 0x40004668; +r_lld_res_list_priv_mode_update = 0x40004674; +r_lld_res_list_rem = 0x40004680; +r_lld_reset_reg = 0x4000468c; +r_lld_rpa_renew = 0x40004698; +r_lld_rpa_renew_evt_canceled_cbk = 0x400046a4; +r_lld_rpa_renew_evt_start_cbk = 0x400046b0; +r_lld_rpa_renew_instant_cbk = 0x400046bc; +r_lld_rxdesc_check = 0x400046c8; +r_lld_rxdesc_free = 0x400046d4; +r_lld_scan_create_sync = 0x400046e0; +r_lld_scan_create_sync_cancel = 0x400046ec; +r_lld_scan_end = 0x400046f8; +r_lld_scan_evt_canceled_cbk = 0x40004704; +r_lld_scan_evt_start_cbk = 0x40004710; +r_lld_scan_frm_cbk = 0x4000471c; +r_lld_scan_frm_eof_isr = 0x40004728; +r_lld_scan_frm_rx_isr = 0x40004734; +r_lld_scan_frm_skip_isr = 0x40004740; +r_lld_scan_init = 0x4000474c; +r_lld_scan_params_update = 0x40004758; +r_lld_scan_process_pkt_rx = 0x40004764; +r_lld_scan_process_pkt_rx_adv_rep = 0x40004770; +r_lld_scan_process_pkt_rx_aux_adv_ind = 0x4000477c; +r_lld_scan_process_pkt_rx_aux_chain_ind = 0x40004788; +r_lld_scan_process_pkt_rx_aux_scan_rsp = 0x40004794; +r_lld_scan_process_pkt_rx_ext_adv = 0x400047a0; +r_lld_scan_process_pkt_rx_ext_adv_ind = 0x400047ac; +r_lld_scan_process_pkt_rx_legacy_adv = 0x400047b8; +r_lld_scan_restart = 0x400047c4; +r_lld_scan_sched = 0x400047d0; +r_lld_scan_set_tx_power = 0x400047dc; +r_lld_scan_start = 0x400047e8; +r_lld_scan_stop = 0x400047f4; +r_lld_scan_sync_accept = 0x40004800; +r_lld_scan_sync_info_unpack = 0x4000480c; +r_lld_scan_trunc_ind = 0x40004818; +r_lld_sw_cca_evt_handler = 0x40004824; +r_lld_sw_cca_isr = 0x40004830; +r_lld_sync_ch_map_update = 0x4000483c; +r_lld_sync_cleanup = 0x40004848; +r_lld_sync_evt_canceled_cbk = 0x40004854; +r_lld_sync_evt_start_cbk = 0x40004860; +r_lld_sync_frm_cbk = 0x4000486c; +r_lld_sync_frm_eof_isr = 0x40004878; +r_lld_sync_frm_rx_isr = 0x40004884; +r_lld_sync_frm_skip_isr = 0x40004890; +r_lld_sync_init = 0x4000489c; +r_lld_sync_process_pkt_rx = 0x400048a8; +r_lld_sync_process_pkt_rx_aux_sync_ind = 0x400048b4; +r_lld_sync_process_pkt_rx_pkt_check = 0x400048c0; +r_lld_sync_scan_dynamic_pti_process = 0x400048cc; +r_lld_sync_sched = 0x400048d8; +r_lld_sync_start = 0x400048e4; +r_lld_sync_stop = 0x400048f0; +r_lld_sync_trunc_ind = 0x400048fc; +r_lld_test_cleanup = 0x40004908; +r_lld_test_evt_canceled_cbk = 0x40004914; +r_lld_test_evt_start_cbk = 0x40004920; +r_lld_test_freq2chnl = 0x4000492c; +r_lld_test_frm_cbk = 0x40004938; +r_lld_test_frm_isr = 0x40004944; +r_lld_test_init = 0x40004950; +r_lld_test_rx_isr = 0x4000495c; +r_lld_test_set_tx_power = 0x40004968; +r_lld_test_start = 0x40004974; +r_lld_test_stop = 0x40004980; +r_lld_update_rxbuf = 0x4000498c; +r_lld_update_rxbuf_isr = 0x40004998; +r_lld_white_list_add = 0x400049a4; +r_lld_white_list_rem = 0x400049b0; +r_llm_activity_free_get = 0x400049bc; +r_llm_activity_free_set = 0x400049c8; +r_llm_activity_syncing_get = 0x400049d4; +r_llm_adv_con_len_check = 0x400049e0; +r_llm_adv_hdl_to_id = 0x400049ec; +r_llm_adv_rep_flow_control_check = 0x400049f8; +r_llm_adv_rep_flow_control_update = 0x40004a04; +r_llm_adv_reports_list_check = 0x40004a10; +r_llm_adv_set_all_release = 0x40004a1c; +r_llm_adv_set_dft_params = 0x40004a28; +r_llm_adv_set_release = 0x40004a34; +r_llm_aes_res_cb = 0x40004a40; +r_llm_ble_update_adv_flow_control = 0x40004a4c; +r_llm_ch_map_update = 0x40004a58; +r_llm_cmd_cmp_send = 0x40004a64; +r_llm_cmd_stat_send = 0x40004a70; +r_llm_dev_list_empty_entry = 0x40004a7c; +r_llm_dev_list_search = 0x40004a88; +r_llm_env_adv_dup_filt_deinit = 0x40004a94; +r_llm_env_adv_dup_filt_init = 0x40004aa0; +r_llm_init_ble_adv_report_flow_contol = 0x40004aac; +r_llm_is_dev_connected = 0x40004ab8; +r_llm_is_dev_synced = 0x40004ac4; +r_llm_is_non_con_act_ongoing_check = 0x40004ad0; +r_llm_is_wl_accessible = 0x40004adc; +r_llm_le_evt_mask_check = 0x40004ae8; +r_llm_le_features_get = 0x40004af4; +r_llm_link_disc = 0x40004b00; +r_llm_master_ch_map_get = 0x40004b0c; +r_llm_msg_handler_tab_p_get = 0x40004b18; +r_llm_no_activity = 0x40004b24; +r_llm_per_adv_slot_dur = 0x40004b30; +r_llm_plan_elt_get = 0x40004b3c; +r_llm_rx_path_comp_get = 0x40004b48; +r_llm_scan_start = 0x40004b54; +r_llm_scan_sync_acad_attach = 0x40004b60; +r_llm_scan_sync_acad_detach = 0x40004b6c; +r_llm_send_adv_lost_event_to_host = 0x40004b78; +r_llm_tx_path_comp_get = 0x40004b84; +r_misc_deinit = 0x40004b90; +r_misc_free_em_buf_in_isr = 0x40004b9c; +r_misc_init = 0x40004ba8; +r_misc_msg_handler_tab_p_get = 0x40004bb4; +r_notEqual256 = 0x40004bc0; +r_phy_upd_proc_start = 0x40004bcc; +r_platform_reset = 0x40004bd8; +r_register_esp_vendor_cmd_handler = 0x40004be4; +r_rf_em_init = 0x40004bf0; +r_rf_force_agc_enable = 0x40004bfc; +r_rf_reg_rd = 0x40004c08; +r_rf_reg_wr = 0x40004c14; +r_rf_reset = 0x40004c20; +r_rf_rssi_convert = 0x40004c2c; +r_rf_rw_v9_le_disable = 0x40004c38; +r_rf_rw_v9_le_enable = 0x40004c44; +r_rf_sleep = 0x40004c50; +r_rf_txpwr_cs_get = 0x40004c5c; +r_rf_txpwr_dbm_get = 0x40004c68; +r_rf_util_cs_fmt_convert = 0x40004c74; +r_rw_crypto_aes_ccm = 0x40004c80; +r_rw_crypto_aes_encrypt = 0x40004c8c; +r_rw_crypto_aes_init = 0x40004c98; +r_rw_crypto_aes_k1 = 0x40004ca4; +r_rw_crypto_aes_k2 = 0x40004cb0; +r_rw_crypto_aes_k3 = 0x40004cbc; +r_rw_crypto_aes_k4 = 0x40004cc8; +r_rw_crypto_aes_rand = 0x40004cd4; +r_rw_crypto_aes_result_handler = 0x40004ce0; +r_rw_crypto_aes_s1 = 0x40004cec; +r_rw_cryto_aes_cmac = 0x40004cf8; +r_rw_v9_init_em_radio_table = 0x40004d04; +r_rwble_isr = 0x40004d10; +r_rwble_sleep_enter = 0x40004d1c; +r_rwble_sleep_wakeup_end = 0x40004d28; +r_rwbtdm_isr_wrapper = 0x40004d34; +r_rwip_active_check = 0x40004d40; +r_rwip_aes_encrypt = 0x40004d4c; +r_rwip_assert = 0x40004d58; +r_rwip_crypt_evt_handler = 0x40004d64; +r_rwip_crypt_isr_handler = 0x40004d70; +r_rwip_eif_get = 0x40004d7c; +r_rwip_half_slot_2_lpcycles = 0x40004d88; +r_rwip_hus_2_lpcycles = 0x40004d94; +r_rwip_isr = 0x40004da0; +r_rwip_lpcycles_2_hus = 0x40004dac; +r_rwip_prevent_sleep_clear = 0x40004db8; +r_rwip_prevent_sleep_set = 0x40004dc4; +r_rwip_schedule = 0x40004dd0; +r_rwip_sleep = 0x40004ddc; +r_rwip_sw_int_handler = 0x40004de8; +r_rwip_sw_int_req = 0x40004df4; +r_rwip_time_get = 0x40004e00; +r_rwip_timer_10ms_handler = 0x40004e0c; +r_rwip_timer_10ms_set = 0x40004e18; +r_rwip_timer_hs_handler = 0x40004e24; +r_rwip_timer_hs_set = 0x40004e30; +r_rwip_timer_hus_handler = 0x40004e3c; +r_rwip_timer_hus_set = 0x40004e48; +r_rwip_wakeup = 0x40004e54; +r_rwip_wakeup_end = 0x40004e60; +r_rwip_wlcoex_set = 0x40004e6c; +r_sch_alarm_clear = 0x40004e78; +r_sch_alarm_init = 0x40004e84; +r_sch_alarm_prog = 0x40004e90; +r_sch_alarm_set = 0x40004e9c; +r_sch_alarm_timer_isr = 0x40004ea8; +r_sch_arb_conflict_check = 0x40004eb4; +r_sch_arb_elt_cancel = 0x40004ec0; +r_sch_arb_event_start_isr = 0x40004ecc; +r_sch_arb_init = 0x40004ed8; +r_sch_arb_insert = 0x40004ee4; +r_sch_arb_prog_timer = 0x40004ef0; +r_sch_arb_remove = 0x40004efc; +r_sch_arb_sw_isr = 0x40004f08; +r_sch_plan_chk = 0x40004f14; +r_sch_plan_clock_wrap_offset_update = 0x40004f20; +r_sch_plan_init = 0x40004f2c; +r_sch_plan_interval_req = 0x40004f38; +r_sch_plan_offset_max_calc = 0x40004f44; +r_sch_plan_offset_req = 0x40004f50; +r_sch_plan_position_range_compute = 0x40004f5c; +r_sch_plan_rem = 0x40004f68; +r_sch_plan_req = 0x40004f74; +r_sch_plan_set = 0x40004f80; +r_sch_prog_end_isr = 0x40004f8c; +r_sch_prog_init = 0x40004f98; +r_sch_prog_push = 0x40004fa4; +r_sch_prog_rx_isr = 0x40004fb0; +r_sch_prog_skip_isr = 0x40004fbc; +r_sch_prog_tx_isr = 0x40004fc8; +r_sch_slice_bg_add = 0x40004fd4; +r_sch_slice_bg_remove = 0x40004fe0; +r_sch_slice_compute = 0x40004fec; +r_sch_slice_fg_add = 0x40004ff8; +r_sch_slice_fg_remove = 0x40005004; +r_sch_slice_init = 0x40005010; +r_sch_slice_per_add = 0x4000501c; +r_sch_slice_per_remove = 0x40005028; +r_sdk_config_get_bt_sleep_enable = 0x40005034; +r_sdk_config_get_hl_derived_opts = 0x40005040; +r_sdk_config_get_opts = 0x4000504c; +r_sdk_config_get_priv_opts = 0x40005058; +r_sdk_config_set_bt_sleep_enable = 0x40005064; +r_sdk_config_set_hl_derived_opts = 0x40005070; +r_sdk_config_set_opts = 0x4000507c; +r_specialModP256 = 0x40005088; +r_unloaded_area_init = 0x40005094; +r_vhci_flow_off = 0x400050a0; +r_vhci_flow_on = 0x400050ac; +r_vhci_notify_host_send_available = 0x400050b8; +r_vhci_send_to_host = 0x400050c4; +r_vnd_hci_command_handler = 0x400050d0; +r_vshci_init = 0x400050dc; +vnd_hci_command_handler_wrapper = 0x400050e8; +r_lld_legacy_adv_dynamic_pti_get = 0x400050f4; +r_lld_legacy_adv_dynamic_pti_process = 0x40005100; +r_lld_ext_adv_dynamic_pti_get = 0x4000510c; +r_lld_ext_adv_dynamic_aux_pti_process = 0x40005118; +r_lld_ext_adv_dynamic_pti_process = 0x40005124; +r_lld_adv_ext_pkt_prepare_set = 0x40005130; +r_lld_adv_ext_chain_none_construct = 0x4000513c; +r_lld_adv_ext_chain_connectable_construct = 0x40005148; +r_lld_adv_ext_chain_scannable_construct = 0x40005154; +r_lld_adv_pkt_rx_connect_post = 0x40005160; +r_lld_adv_start_init_evt_param = 0x4000516c; +r_lld_adv_start_set_cs = 0x40005178; +r_lld_adv_start_update_filter_policy = 0x40005184; +r_lld_adv_start_schedule_asap = 0x40005190; +r_lld_con_tx_prog_new_packet_coex = 0x4000519c; +r_lld_con_tx_prog_new_packet = 0x400051a8; +r_lld_per_adv_dynamic_pti_get = 0x400051b4; +r_lld_per_adv_evt_start_chm_upd = 0x400051c0; +r_lld_ext_scan_dynamic_pti_get = 0x400051cc; +r_lld_scan_try_sched = 0x400051d8; +r_lld_sync_insert = 0x400051e4; +r_sch_prog_ble_push = 0x400051f0; +r_sch_prog_bt_push = 0x400051fc; +r_lld_init_evt_end_type_set = 0x40005208; +r_lld_init_evt_end_type_get = 0x40005214; +r_lld_adv_direct_adv_use_rpa_addr_state_set = 0x40005220; +r_lld_adv_direct_adv_use_rpa_addr_state_get = 0x4000522c; +r_lld_init_evt_end_type_check_state_set = 0x40005238; +r_lld_init_evt_end_type_check_state_get = 0x40005244; /* Data (.data, .bss, .rodata) */ -bt_rf_coex_cfg_p = 0x3fceffb4; -bt_rf_coex_hooks_p = 0x3fceffb0; -btdm_env_p = 0x3fceffac; -g_rw_controller_task_handle = 0x3fceffa8; -g_rw_init_sem = 0x3fceffa4; -g_rw_schd_queue = 0x3fceffa0; -lld_init_env = 0x3fceff9c; -lld_rpa_renew_env = 0x3fceff98; -lld_scan_env = 0x3fceff94; -lld_scan_sync_env = 0x3fceff90; -lld_test_env = 0x3fceff8c; -p_ble_util_buf_env = 0x3fceff88; -p_lld_env = 0x3fceff84; -p_llm_env = 0x3fceff80; -r_h4tl_eif_p = 0x3fceff7c; -r_hli_funcs_p = 0x3fceff78; -r_ip_funcs_p = 0x3fceff74; -r_modules_funcs_p = 0x3fceff70; -r_osi_funcs_p = 0x3fceff6c; -r_plf_funcs_p = 0x3fceff68; -vhci_env_p = 0x3fceff64; -aa_gen = 0x3fceff60; -aes_env = 0x3fceff54; -bt_rf_coex_cfg_cb = 0x3fceff04; -btdm_pwr_state = 0x3fceff00; -btdm_slp_err = 0x3fcefefc; -ecc_env = 0x3fcefef4; -esp_handler = 0x3fcefeec; -esp_vendor_cmd = 0x3fcefee4; -g_adv_delay_dis = 0x3fcefee0; -g_conflict_elt = 0x3fcefedc; -g_eif_api = 0x3fcefecc; -g_event_empty = 0x3fcefec0; -g_llc_state = 0x3fcefeb6; -g_llm_state = 0x3fcefeb5; -g_max_evt_env = 0x3fcefeb3; -g_misc_state = 0x3fcefeb2; -g_rma_rule_db = 0x3fcefe96; -g_rtp_rule_db = 0x3fcefe7a; -g_scan_forever = 0x3fcefe79; -g_time_msb = 0x3fcefe78; -h4tl_env = 0x3fcefe50; -hci_env = 0x3fcefe2d; -hci_ext_host = 0x3fcefe2c; -hci_fc_env = 0x3fcefe24; -hci_tl_env = 0x3fcefdf8; -ke_env = 0x3fcefdc8; -ke_event_env = 0x3fcefd88; -ke_task_env = 0x3fcefd0c; -llc_env = 0x3fcefce4; -lld_adv_env = 0x3fcefcbc; -lld_con_env = 0x3fcefc94; -lld_exp_sync_pos_tab = 0x3fcefc8c; -lld_per_adv_env = 0x3fcefc64; -lld_sync_env = 0x3fcefc3c; -llm_le_adv_flow_env = 0x3fcefc30; -rw_sleep_enable = 0x3fcefc2c; -rwble_env = 0x3fcefc24; -rwip_env = 0x3fcefc08; -rwip_param = 0x3fcefbfc; -rwip_prog_delay = 0x3fcefbf8; -rwip_rf = 0x3fcefbc0; -sch_alarm_env = 0x3fcefbb8; -sch_arb_env = 0x3fcefba4; -sch_plan_env = 0x3fcefb9c; -sch_prog_env = 0x3fcefa98; -sch_slice_env = 0x3fcefa38; -sch_slice_params = 0x3fcefa30; -timer_env = 0x3fcefa28; -unloaded_area = 0x3fcefa24; -vshci_state = 0x3fcefa20; -TASK_DESC_LLC = 0x3fcefa14; -TASK_DESC_LLM = 0x3fcefa08; -TASK_DESC_VSHCI = 0x3fcef9fc; -co_default_bdaddr = 0x3fcef9f4; -dbg_assert_block = 0x3fcef9f0; -g_bt_plf_log_level = 0x3fcef9ec; -hci_cmd_desc_tab_vs_esp = 0x3fcef9c8; -hci_command_handler_tab_esp = 0x3fcef9b0; -privacy_en = 0x3fcef9ac; -sdk_cfg_priv_opts = 0x3fcef964; -BasePoint_x_256 = 0x3ff0ffdc; -BasePoint_y_256 = 0x3ff0ffbc; -DebugE256PublicKey_x = 0x3ff0ff9c; -DebugE256PublicKey_y = 0x3ff0ff7c; -DebugE256SecretKey = 0x3ff0ff5c; -ECC_4Win_Look_up_table = 0x3ff0f7a0; -LLM_AA_CT1 = 0x3ff0f79a; -LLM_AA_CT2 = 0x3ff0f798; -RF_TX_PW_CONV_TBL = 0x3ff0f790; -TASK_DESC_MISC = 0x3ff0f784; -adv_evt_prop2type = 0x3ff0f766; -adv_evt_type2prop = 0x3ff0f761; -aes_cmac_zero = 0x3ff0f751; -aes_k2_salt = 0x3ff0f741; -aes_k3_id64 = 0x3ff0f73c; -aes_k3_salt = 0x3ff0f72c; -aes_k4_id6 = 0x3ff0f728; -aes_k4_salt = 0x3ff0f718; -bigHexP256 = 0x3ff0f6ec; -byte_tx_time = 0x3ff0f6e2; -co_null_bdaddr = 0x3ff0f6dc; -co_phy_mask_to_rate = 0x3ff0f6d7; -co_phy_mask_to_value = 0x3ff0f6d2; -co_phy_to_rate = 0x3ff0f6ce; -co_phy_value_to_mask = 0x3ff0f6ca; -co_rate_to_byte_dur_us = 0x3ff0f6c5; -co_rate_to_phy = 0x3ff0f6c0; -co_rate_to_phy_mask = 0x3ff0f6bc; -co_sca2ppm = 0x3ff0f6ac; -coef_B = 0x3ff0f680; -connect_req_dur_tab = 0x3ff0f678; -ecc_Jacobian_InfinityPoint256 = 0x3ff0f5f4; -em_base_reg_lut = 0x3ff0f526; -fixed_tx_time = 0x3ff0f51e; -h4tl_msgtype2hdrlen = 0x3ff0f518; -hci_cmd_desc_root_tab = 0x3ff0f4e8; -hci_cmd_desc_tab_ctrl_bb = 0x3ff0f47c; -hci_cmd_desc_tab_info_par = 0x3ff0f44c; -hci_cmd_desc_tab_le = 0x3ff0f0b0; -hci_cmd_desc_tab_lk_ctrl = 0x3ff0f098; -hci_cmd_desc_tab_stat_par = 0x3ff0f08c; -hci_cmd_desc_tab_vs = 0x3ff0f050; -hci_evt_desc_tab = 0x3ff0f008; -hci_evt_le_desc_tab = 0x3ff0ef68; -hci_evt_le_desc_tab_esp = 0x3ff0ef60; -hci_rsvd_evt_msk = 0x3ff0ef57; -lld_aux_phy_to_rate = 0x3ff0ef54; -lld_init_max_aux_dur_tab = 0x3ff0ef4c; -lld_scan_map_legacy_pdu_to_evt_type = 0x3ff0ef44; -lld_scan_max_aux_dur_tab = 0x3ff0ef3c; -lld_sync_max_aux_dur_tab = 0x3ff0ef34; -llm_local_le_feats = 0x3ff0ef2c; -llm_local_le_states = 0x3ff0ef24; -llm_local_supp_cmds = 0x3ff0eefc; -maxSecretKey_256 = 0x3ff0eedc; -max_data_tx_time = 0x3ff0eed4; -one_bits = 0x3ff0eec3; -rwip_coex_cfg = 0x3ff0eebe; -rwip_priority = 0x3ff0eea8; -veryBigHexP256 = 0x3ff0ee5c; +bt_rf_coex_cfg_p = 0x3fceffa8; +bt_rf_coex_hooks_p = 0x3fceffa4; +btdm_env_p = 0x3fceffa0; +g_rw_controller_task_handle = 0x3fceff9c; +g_rw_init_sem = 0x3fceff98; +g_rw_schd_queue = 0x3fceff94; +lld_init_env = 0x3fceff90; +lld_rpa_renew_env = 0x3fceff8c; +lld_scan_env = 0x3fceff88; +lld_scan_sync_env = 0x3fceff84; +lld_test_env = 0x3fceff80; +p_ble_util_buf_env = 0x3fceff7c; +p_lld_env = 0x3fceff78; +p_llm_env = 0x3fceff74; +r_h4tl_eif_p = 0x3fceff70; +r_hli_funcs_p = 0x3fceff6c; +r_ip_funcs_p = 0x3fceff68; +r_modules_funcs_p = 0x3fceff64; +r_osi_funcs_p = 0x3fceff60; +r_plf_funcs_p = 0x3fceff5c; +vhci_env_p = 0x3fceff58; +aa_gen = 0x3fceff54; +aes_env = 0x3fceff48; +bt_rf_coex_cfg_cb = 0x3fcefef8; +btdm_pwr_state = 0x3fcefef4; +btdm_slp_err = 0x3fcefef0; +ecc_env = 0x3fcefee8; +esp_handler = 0x3fcefee0; +esp_vendor_cmd = 0x3fcefed8; +g_adv_delay_dis = 0x3fcefed4; +g_conflict_elt = 0x3fcefed0; +g_eif_api = 0x3fcefec0; +g_event_empty = 0x3fcefeb4; +g_llc_state = 0x3fcefeaa; +g_llm_state = 0x3fcefea9; +g_max_evt_env = 0x3fcefea7; +g_misc_state = 0x3fcefea6; +g_rma_rule_db = 0x3fcefe8a; +g_rtp_rule_db = 0x3fcefe6e; +g_scan_forever = 0x3fcefe6d; +g_time_msb = 0x3fcefe6c; +h4tl_env = 0x3fcefe44; +hci_env = 0x3fcefe21; +hci_ext_host = 0x3fcefe20; +hci_fc_env = 0x3fcefe18; +hci_tl_env = 0x3fcefdec; +ke_env = 0x3fcefdbc; +ke_event_env = 0x3fcefd7c; +ke_task_env = 0x3fcefd00; +llc_env = 0x3fcefcd8; +lld_adv_env = 0x3fcefcb0; +lld_con_env = 0x3fcefc88; +lld_exp_sync_pos_tab = 0x3fcefc80; +lld_per_adv_env = 0x3fcefc58; +lld_sync_env = 0x3fcefc30; +llm_le_adv_flow_env = 0x3fcefc24; +rw_sleep_enable = 0x3fcefc20; +rwble_env = 0x3fcefc18; +rwip_env = 0x3fcefbfc; +rwip_param = 0x3fcefbf0; +rwip_prog_delay = 0x3fcefbec; +rwip_rf = 0x3fcefbb4; +sch_alarm_env = 0x3fcefbac; +sch_arb_env = 0x3fcefb98; +sch_plan_env = 0x3fcefb90; +sch_prog_env = 0x3fcefa8c; +sch_slice_env = 0x3fcefa2c; +sch_slice_params = 0x3fcefa24; +timer_env = 0x3fcefa1c; +unloaded_area = 0x3fcefa18; +vshci_state = 0x3fcefa14; +TASK_DESC_LLC = 0x3fcefa08; +TASK_DESC_LLM = 0x3fcef9fc; +TASK_DESC_VSHCI = 0x3fcef9f0; +co_default_bdaddr = 0x3fcef9e8; +dbg_assert_block = 0x3fcef9e4; +g_bt_plf_log_level = 0x3fcef9e0; +hci_cmd_desc_tab_vs_esp = 0x3fcef9bc; +hci_command_handler_tab_esp = 0x3fcef9a4; +privacy_en = 0x3fcef9a0; +sdk_cfg_priv_opts = 0x3fcef958; +BasePoint_x_256 = 0x3ff1ffdc; +BasePoint_y_256 = 0x3ff1ffbc; +DebugE256PublicKey_x = 0x3ff1ff9c; +DebugE256PublicKey_y = 0x3ff1ff7c; +DebugE256SecretKey = 0x3ff1ff5c; +ECC_4Win_Look_up_table = 0x3ff1f7a0; +LLM_AA_CT1 = 0x3ff1f79a; +LLM_AA_CT2 = 0x3ff1f798; +RF_TX_PW_CONV_TBL = 0x3ff1f790; +TASK_DESC_MISC = 0x3ff1f784; +adv_evt_prop2type = 0x3ff1f766; +adv_evt_type2prop = 0x3ff1f761; +aes_cmac_zero = 0x3ff1f751; +aes_k2_salt = 0x3ff1f741; +aes_k3_id64 = 0x3ff1f73c; +aes_k3_salt = 0x3ff1f72c; +aes_k4_id6 = 0x3ff1f728; +aes_k4_salt = 0x3ff1f718; +bigHexP256 = 0x3ff1f6ec; +byte_tx_time = 0x3ff1f6e2; +co_null_bdaddr = 0x3ff1f6dc; +co_phy_mask_to_rate = 0x3ff1f6d7; +co_phy_mask_to_value = 0x3ff1f6d2; +co_phy_to_rate = 0x3ff1f6ce; +co_phy_value_to_mask = 0x3ff1f6ca; +co_rate_to_byte_dur_us = 0x3ff1f6c5; +co_rate_to_phy = 0x3ff1f6c0; +co_rate_to_phy_mask = 0x3ff1f6bc; +co_sca2ppm = 0x3ff1f6ac; +coef_B = 0x3ff1f680; +connect_req_dur_tab = 0x3ff1f678; +ecc_Jacobian_InfinityPoint256 = 0x3ff1f5f4; +em_base_reg_lut = 0x3ff1f526; +fixed_tx_time = 0x3ff1f51e; +h4tl_msgtype2hdrlen = 0x3ff1f518; +hci_cmd_desc_root_tab = 0x3ff1f4e8; +hci_cmd_desc_tab_ctrl_bb = 0x3ff1f47c; +hci_cmd_desc_tab_info_par = 0x3ff1f44c; +hci_cmd_desc_tab_le = 0x3ff1f0b0; +hci_cmd_desc_tab_lk_ctrl = 0x3ff1f098; +hci_cmd_desc_tab_stat_par = 0x3ff1f08c; +hci_cmd_desc_tab_vs = 0x3ff1f050; +hci_evt_desc_tab = 0x3ff1f008; +hci_evt_le_desc_tab = 0x3ff1ef68; +hci_evt_le_desc_tab_esp = 0x3ff1ef60; +hci_rsvd_evt_msk = 0x3ff1ef57; +lld_aux_phy_to_rate = 0x3ff1ef54; +lld_init_max_aux_dur_tab = 0x3ff1ef4c; +lld_scan_map_legacy_pdu_to_evt_type = 0x3ff1ef44; +lld_scan_max_aux_dur_tab = 0x3ff1ef3c; +lld_sync_max_aux_dur_tab = 0x3ff1ef34; +llm_local_le_feats = 0x3ff1ef2c; +llm_local_le_states = 0x3ff1ef24; +llm_local_supp_cmds = 0x3ff1eefc; +maxSecretKey_256 = 0x3ff1eedc; +max_data_tx_time = 0x3ff1eed4; +one_bits = 0x3ff1eec3; +rwip_coex_cfg = 0x3ff1eebe; +rwip_priority = 0x3ff1eea8; +veryBigHexP256 = 0x3ff1ee5c; /*************************************** @@ -1719,208 +1797,213 @@ veryBigHexP256 = 0x3ff0ee5c; ***************************************/ /* Functions */ -esp_pp_rom_version_get = 0x40004f2c; -RC_GetBlockAckTime = 0x40004f38; -ebuf_list_remove = 0x40004f44; -esf_buf_alloc = 0x40004f50; -esf_buf_alloc_dynamic = 0x40004f5c; -esf_buf_recycle = 0x40004f68; -GetAccess = 0x40004f74; -hal_mac_is_low_rate_enabled = 0x40004f80; -hal_mac_tx_get_blockack = 0x40004f8c; -hal_mac_tx_set_ppdu = 0x40004f98; -ic_get_trc = 0x40004fa4; -ic_mac_deinit = 0x40004fb0; -ic_mac_init = 0x40004fbc; -ic_interface_enabled = 0x40004fc8; -is_lmac_idle = 0x40004fd4; -lmacAdjustTimestamp = 0x40004fe0; -lmacDiscardAgedMSDU = 0x40004fec; -lmacDiscardMSDU = 0x40004ff8; -lmacEndFrameExchangeSequence = 0x40005004; -lmacIsIdle = 0x40005010; -lmacIsLongFrame = 0x4000501c; -lmacMSDUAged = 0x40005028; -lmacPostTxComplete = 0x40005034; -lmacProcessAllTxTimeout = 0x40005040; -lmacProcessCollisions = 0x4000504c; -lmacProcessRxSucData = 0x40005058; -lmacReachLongLimit = 0x40005064; -lmacReachShortLimit = 0x40005070; -lmacRecycleMPDU = 0x4000507c; -lmacRxDone = 0x40005088; -lmacSetTxFrame = 0x40005094; -lmacTxFrame = 0x400050ac; -mac_tx_set_duration = 0x400050b8; -mac_tx_set_htsig = 0x400050c4; -mac_tx_set_plcp0 = 0x400050d0; -mac_tx_set_plcp1 = 0x400050dc; -mac_tx_set_plcp2 = 0x400050e8; -pm_check_state = 0x400050f4; -pm_disable_dream_timer = 0x40005100; -pm_disable_sleep_delay_timer = 0x4000510c; -pm_dream = 0x40005118; -pm_mac_wakeup = 0x40005124; -pm_mac_sleep = 0x40005130; -pm_enable_active_timer = 0x4000513c; -pm_enable_sleep_delay_timer = 0x40005148; -pm_local_tsf_process = 0x40005154; -pm_set_beacon_filter = 0x40005160; -pm_is_in_wifi_slice_threshold = 0x4000516c; -pm_is_waked = 0x40005178; -pm_keep_alive = 0x40005184; -pm_on_beacon_rx = 0x40005190; -pm_on_data_rx = 0x4000519c; -pm_on_tbtt = 0x400051a8; -pm_parse_beacon = 0x400051b4; -pm_process_tim = 0x400051c0; -pm_rx_beacon_process = 0x400051cc; -pm_rx_data_process = 0x400051d8; -pm_sleep = 0x400051e4; -pm_sleep_for = 0x400051f0; -pm_tbtt_process = 0x400051fc; -ppAMPDU2Normal = 0x40005208; -ppAssembleAMPDU = 0x40005214; -ppCalFrameTimes = 0x40005220; -ppCalSubFrameLength = 0x4000522c; -ppCalTxAMPDULength = 0x40005238; -ppCheckTxAMPDUlength = 0x40005244; -ppDequeueRxq_Locked = 0x40005250; -ppDequeueTxQ = 0x4000525c; -ppEmptyDelimiterLength = 0x40005268; -ppEnqueueRxq = 0x40005274; -ppEnqueueTxDone = 0x40005280; -ppGetTxQFirstAvail_Locked = 0x4000528c; -ppGetTxframe = 0x40005298; -ppProcTxSecFrame = 0x400052b0; -ppProcessRxPktHdr = 0x400052bc; -ppProcessTxQ = 0x400052c8; -ppRecordBarRRC = 0x400052d4; -lmacRequestTxopQueue = 0x400052e0; -lmacReleaseTxopQueue = 0x400052ec; -ppRecycleAmpdu = 0x400052f8; -ppRecycleRxPkt = 0x40005304; -ppResortTxAMPDU = 0x40005310; -ppResumeTxAMPDU = 0x4000531c; -ppRxFragmentProc = 0x40005328; -ppRxPkt = 0x40005334; -ppRxProtoProc = 0x40005340; -ppSearchTxQueue = 0x4000534c; -ppSearchTxframe = 0x40005358; -ppSelectNextQueue = 0x40005364; -ppSubFromAMPDU = 0x40005370; -ppTask = 0x4000537c; -ppTxPkt = 0x40005388; -ppTxProtoProc = 0x40005394; -ppTxqUpdateBitmap = 0x400053a0; -pp_coex_tx_request = 0x400053ac; -pp_hdrsize = 0x400053b8; -pp_post = 0x400053c4; -pp_process_hmac_waiting_txq = 0x400053d0; -rcGetAmpduSched = 0x400053dc; -rcUpdateRxDone = 0x400053e8; -rc_get_trc = 0x400053f4; -rc_get_trc_by_index = 0x40005400; -rcAmpduLowerRate = 0x4000540c; -rcampduuprate = 0x40005418; -rcClearCurAMPDUSched = 0x40005424; -rcClearCurSched = 0x40005430; -rcClearCurStat = 0x4000543c; -rcLowerSched = 0x40005454; -rcSetTxAmpduLimit = 0x40005460; -rcTxUpdatePer = 0x4000546c; -rcUpdateAckSnr = 0x40005478; -rcUpdateRate = 0x40005484; -rcUpdateTxDone = 0x40005490; -rcUpdateTxDoneAmpdu2 = 0x4000549c; -rcUpSched = 0x400054a8; -rssi_margin = 0x400054b4; -rx11NRate2AMPDULimit = 0x400054c0; -TRC_AMPDU_PER_DOWN_THRESHOLD = 0x400054cc; -TRC_AMPDU_PER_UP_THRESHOLD = 0x400054d8; -trc_calc_duration = 0x400054e4; -trc_isTxAmpduOperational = 0x400054f0; -trc_onAmpduOp = 0x400054fc; -TRC_PER_IS_GOOD = 0x40005508; -trc_SetTxAmpduState = 0x40005514; -trc_tid_isTxAmpduOperational = 0x40005520; -trcAmpduSetState = 0x4000552c; -wDevCheckBlockError = 0x40005538; -wDev_AppendRxBlocks = 0x40005544; -wDev_DiscardFrame = 0x40005550; -wDev_GetNoiseFloor = 0x4000555c; -wDev_IndicateAmpdu = 0x40005568; -wDev_IndicateFrame = 0x40005574; -wdev_bank_store = 0x40005580; -wdev_bank_load = 0x4000558c; -wdev_mac_reg_load = 0x40005598; -wdev_mac_reg_store = 0x400055a4; -wdev_mac_special_reg_load = 0x400055b0; -wdev_mac_special_reg_store = 0x400055bc; -wdev_mac_wakeup = 0x400055c8; -wdev_mac_sleep = 0x400055d4; -hal_mac_is_dma_enable = 0x400055e0; -wDev_ProcessFiq = 0x400055ec; -wDev_ProcessRxSucData = 0x400055f8; -wdevProcessRxSucDataAll = 0x40005604; -wdev_csi_len_align = 0x40005610; -ppDequeueTxDone_Locked = 0x4000561c; -ppProcTxDone = 0x40005628; -pm_tx_data_done_process = 0x40005634; -config_is_cache_tx_buf_enabled = 0x40005640; -ppMapWaitTxq = 0x4000564c; -ppProcessWaitingQueue = 0x40005658; -ppDisableQueue = 0x40005664; -pm_allow_tx = 0x40005670; +esp_pp_rom_version_get = 0x40005250; +RC_GetBlockAckTime = 0x4000525c; +ebuf_list_remove = 0x40005268; +esf_buf_alloc = 0x40005274; +esf_buf_alloc_dynamic = 0x40005280; +esf_buf_recycle = 0x4000528c; +GetAccess = 0x40005298; +hal_mac_is_low_rate_enabled = 0x400052a4; +hal_mac_tx_get_blockack = 0x400052b0; +hal_mac_tx_set_ppdu = 0x400052bc; +ic_get_trc = 0x400052c8; +ic_mac_deinit = 0x400052d4; +ic_mac_init = 0x400052e0; +ic_interface_enabled = 0x400052ec; +is_lmac_idle = 0x400052f8; +lmacAdjustTimestamp = 0x40005304; +lmacDiscardAgedMSDU = 0x40005310; +lmacDiscardMSDU = 0x4000531c; +lmacEndFrameExchangeSequence = 0x40005328; +lmacIsIdle = 0x40005334; +lmacIsLongFrame = 0x40005340; +lmacMSDUAged = 0x4000534c; +lmacPostTxComplete = 0x40005358; +lmacProcessAllTxTimeout = 0x40005364; +lmacProcessCollisions = 0x40005370; +lmacProcessRxSucData = 0x4000537c; +lmacReachLongLimit = 0x40005388; +lmacReachShortLimit = 0x40005394; +lmacRecycleMPDU = 0x400053a0; +lmacRxDone = 0x400053ac; +lmacSetTxFrame = 0x400053b8; +lmacTxDone = 0x400053c4; +lmacTxFrame = 0x400053d0; +mac_tx_set_duration = 0x400053dc; +mac_tx_set_htsig = 0x400053e8; +mac_tx_set_plcp0 = 0x400053f4; +mac_tx_set_plcp1 = 0x40005400; +mac_tx_set_plcp2 = 0x4000540c; +pm_check_state = 0x40005418; +pm_disable_dream_timer = 0x40005424; +pm_disable_sleep_delay_timer = 0x40005430; +pm_dream = 0x4000543c; +pm_mac_wakeup = 0x40005448; +pm_mac_sleep = 0x40005454; +pm_enable_active_timer = 0x40005460; +pm_enable_sleep_delay_timer = 0x4000546c; +pm_local_tsf_process = 0x40005478; +pm_set_beacon_filter = 0x40005484; +pm_is_in_wifi_slice_threshold = 0x40005490; +pm_is_waked = 0x4000549c; +pm_keep_alive = 0x400054a8; +pm_on_beacon_rx = 0x400054b4; +pm_on_data_rx = 0x400054c0; +pm_on_tbtt = 0x400054cc; +pm_parse_beacon = 0x400054d8; +pm_process_tim = 0x400054e4; +pm_rx_beacon_process = 0x400054f0; +pm_rx_data_process = 0x400054fc; +pm_sleep = 0x40005508; +pm_sleep_for = 0x40005514; +pm_tbtt_process = 0x40005520; +ppAMPDU2Normal = 0x4000552c; +ppAssembleAMPDU = 0x40005538; +ppCalFrameTimes = 0x40005544; +ppCalSubFrameLength = 0x40005550; +ppCalTxAMPDULength = 0x4000555c; +ppCheckTxAMPDUlength = 0x40005568; +ppDequeueRxq_Locked = 0x40005574; +ppDequeueTxQ = 0x40005580; +ppEmptyDelimiterLength = 0x4000558c; +ppEnqueueRxq = 0x40005598; +ppEnqueueTxDone = 0x400055a4; +ppGetTxQFirstAvail_Locked = 0x400055b0; +ppGetTxframe = 0x400055bc; +ppMapTxQueue = 0x400055c8; +ppProcTxSecFrame = 0x400055d4; +ppProcessRxPktHdr = 0x400055e0; +ppProcessTxQ = 0x400055ec; +ppRecordBarRRC = 0x400055f8; +lmacRequestTxopQueue = 0x40005604; +lmacReleaseTxopQueue = 0x40005610; +ppRecycleAmpdu = 0x4000561c; +ppRecycleRxPkt = 0x40005628; +ppResortTxAMPDU = 0x40005634; +ppResumeTxAMPDU = 0x40005640; +ppRxFragmentProc = 0x4000564c; +ppRxPkt = 0x40005658; +ppRxProtoProc = 0x40005664; +ppSearchTxQueue = 0x40005670; +ppSearchTxframe = 0x4000567c; +ppSelectNextQueue = 0x40005688; +ppSubFromAMPDU = 0x40005694; +ppTask = 0x400056a0; +ppTxPkt = 0x400056ac; +ppTxProtoProc = 0x400056b8; +ppTxqUpdateBitmap = 0x400056c4; +pp_coex_tx_request = 0x400056d0; +pp_hdrsize = 0x400056dc; +pp_post = 0x400056e8; +pp_process_hmac_waiting_txq = 0x400056f4; +rcGetAmpduSched = 0x40005700; +rcUpdateRxDone = 0x4000570c; +rc_get_trc = 0x40005718; +rc_get_trc_by_index = 0x40005724; +rcAmpduLowerRate = 0x40005730; +rcampduuprate = 0x4000573c; +rcClearCurAMPDUSched = 0x40005748; +rcClearCurSched = 0x40005754; +rcClearCurStat = 0x40005760; +rcGetSched = 0x4000576c; +rcLowerSched = 0x40005778; +rcSetTxAmpduLimit = 0x40005784; +rcTxUpdatePer = 0x40005790; +rcUpdateAckSnr = 0x4000579c; +rcUpdateRate = 0x400057a8; +rcUpdateTxDone = 0x400057b4; +rcUpdateTxDoneAmpdu2 = 0x400057c0; +rcUpSched = 0x400057cc; +rssi_margin = 0x400057d8; +rx11NRate2AMPDULimit = 0x400057e4; +TRC_AMPDU_PER_DOWN_THRESHOLD = 0x400057f0; +TRC_AMPDU_PER_UP_THRESHOLD = 0x400057fc; +trc_calc_duration = 0x40005808; +trc_isTxAmpduOperational = 0x40005814; +trc_onAmpduOp = 0x40005820; +TRC_PER_IS_GOOD = 0x4000582c; +trc_SetTxAmpduState = 0x40005838; +trc_tid_isTxAmpduOperational = 0x40005844; +trcAmpduSetState = 0x40005850; +wDevCheckBlockError = 0x4000585c; +wDev_AppendRxBlocks = 0x40005868; +wDev_DiscardFrame = 0x40005874; +wDev_GetNoiseFloor = 0x40005880; +wDev_IndicateAmpdu = 0x4000588c; +wDev_IndicateFrame = 0x40005898; +wdev_bank_store = 0x400058a4; +wdev_bank_load = 0x400058b0; +wdev_mac_reg_load = 0x400058bc; +wdev_mac_reg_store = 0x400058c8; +wdev_mac_special_reg_load = 0x400058d4; +wdev_mac_special_reg_store = 0x400058e0; +wdev_mac_wakeup = 0x400058ec; +wdev_mac_sleep = 0x400058f8; +hal_mac_is_dma_enable = 0x40005904; +wDev_ProcessFiq = 0x40005910; +wDev_ProcessRxSucData = 0x4000591c; +wdevProcessRxSucDataAll = 0x40005928; +wdev_csi_len_align = 0x40005934; +ppDequeueTxDone_Locked = 0x40005940; +ppProcTxDone = 0x4000594c; +pm_tx_data_done_process = 0x40005958; +config_is_cache_tx_buf_enabled = 0x40005964; +ppMapWaitTxq = 0x40005970; +ppProcessWaitingQueue = 0x4000597c; +ppDisableQueue = 0x40005988; +pm_allow_tx = 0x40005994; +wdev_is_data_in_rxlist = 0x400059a0; +ppProcTxCallback = 0x400059ac; /* Data (.data, .bss, .rodata) */ -our_instances_ptr = 0x3ff0ee58; -pTxRx = 0x3fcef960; -lmacConfMib_ptr = 0x3fcef95c; -our_wait_eb = 0x3fcef958; -our_tx_eb = 0x3fcef954; -pp_wdev_funcs = 0x3fcef950; -g_osi_funcs_p = 0x3fcef94c; -wDevCtrl_ptr = 0x3fcef948; -g_wdev_last_desc_reset_ptr = 0x3ff0ee54; -wDevMacSleep_ptr = 0x3fcef944; -g_lmac_cnt_ptr = 0x3fcef940; -our_controls_ptr = 0x3ff0ee50; -pp_sig_cnt_ptr = 0x3fcef93c; -g_eb_list_desc_ptr = 0x3fcef938; -s_fragment_ptr = 0x3fcef934; -if_ctrl_ptr = 0x3fcef930; -g_intr_lock_mux = 0x3fcef92c; -g_wifi_global_lock = 0x3fcef928; -s_wifi_queue = 0x3fcef924; -pp_task_hdl = 0x3fcef920; -s_pp_task_create_sem = 0x3fcef91c; -s_pp_task_del_sem = 0x3fcef918; -g_wifi_menuconfig_ptr = 0x3fcef914; -xphyQueue = 0x3fcef910; -ap_no_lr_ptr = 0x3fcef90c; -rc11BSchedTbl_ptr = 0x3fcef908; -rc11NSchedTbl_ptr = 0x3fcef904; -rcLoRaSchedTbl_ptr = 0x3fcef900; -BasicOFDMSched_ptr = 0x3fcef8fc; -trc_ctl_ptr = 0x3fcef8f8; -g_pm_cnt_ptr = 0x3fcef8f4; -g_pm_ptr = 0x3fcef8f0; -g_pm_cfg_ptr = 0x3fcef8ec; -g_esp_mesh_quick_funcs_ptr = 0x3fcef8e8; -g_txop_queue_status_ptr = 0x3fcef8e4; -g_mac_sleep_en_ptr = 0x3fcef8e0; -g_mesh_is_root_ptr = 0x3fcef8dc; -g_mesh_topology_ptr = 0x3fcef8d8; -g_mesh_init_ps_type_ptr = 0x3fcef8d4; -g_mesh_is_started_ptr = 0x3fcef8d0; -g_config_func = 0x3fcef8cc; -g_net80211_tx_func = 0x3fcef8c8; -g_timer_func = 0x3fcef8c4; -s_michael_mic_failure_cb = 0x3fcef8c0; -wifi_sta_rx_probe_req = 0x3fcef8bc; -g_tx_done_cb_func = 0x3fcef8b8; -g_per_conn_trc = 0x3fcef86c; -s_encap_amsdu_func = 0x3fcef868; +our_instances_ptr = 0x3ff1ee58; +pTxRx = 0x3fcef954; +lmacConfMib_ptr = 0x3fcef950; +our_wait_eb = 0x3fcef94c; +our_tx_eb = 0x3fcef948; +pp_wdev_funcs = 0x3fcef944; +g_osi_funcs_p = 0x3fcef940; +wDevCtrl_ptr = 0x3fcef93c; +g_wdev_last_desc_reset_ptr = 0x3ff1ee54; +wDevMacSleep_ptr = 0x3fcef938; +g_lmac_cnt_ptr = 0x3fcef934; +our_controls_ptr = 0x3ff1ee50; +pp_sig_cnt_ptr = 0x3fcef930; +g_eb_list_desc_ptr = 0x3fcef92c; +s_fragment_ptr = 0x3fcef928; +if_ctrl_ptr = 0x3fcef924; +g_intr_lock_mux = 0x3fcef920; +g_wifi_global_lock = 0x3fcef91c; +s_wifi_queue = 0x3fcef918; +pp_task_hdl = 0x3fcef914; +s_pp_task_create_sem = 0x3fcef910; +s_pp_task_del_sem = 0x3fcef90c; +g_wifi_menuconfig_ptr = 0x3fcef908; +xphyQueue = 0x3fcef904; +ap_no_lr_ptr = 0x3fcef900; +rc11BSchedTbl_ptr = 0x3fcef8fc; +rc11NSchedTbl_ptr = 0x3fcef8f8; +rcLoRaSchedTbl_ptr = 0x3fcef8f4; +BasicOFDMSched_ptr = 0x3fcef8f0; +trc_ctl_ptr = 0x3fcef8ec; +g_pm_cnt_ptr = 0x3fcef8e8; +g_pm_ptr = 0x3fcef8e4; +g_pm_cfg_ptr = 0x3fcef8e0; +g_esp_mesh_quick_funcs_ptr = 0x3fcef8dc; +g_txop_queue_status_ptr = 0x3fcef8d8; +g_mac_sleep_en_ptr = 0x3fcef8d4; +g_mesh_is_root_ptr = 0x3fcef8d0; +g_mesh_topology_ptr = 0x3fcef8cc; +g_mesh_init_ps_type_ptr = 0x3fcef8c8; +g_mesh_is_started_ptr = 0x3fcef8c4; +g_config_func = 0x3fcef8c0; +g_net80211_tx_func = 0x3fcef8bc; +g_timer_func = 0x3fcef8b8; +s_michael_mic_failure_cb = 0x3fcef8b4; +wifi_sta_rx_probe_req = 0x3fcef8b0; +g_tx_done_cb_func = 0x3fcef8ac; +g_per_conn_trc = 0x3fcef860; +s_encap_amsdu_func = 0x3fcef85c; /*************************************** @@ -1928,51 +2011,52 @@ s_encap_amsdu_func = 0x3fcef868; ***************************************/ /* Functions */ -esp_net80211_rom_version_get = 0x4000567c; -ampdu_dispatch = 0x40005688; -ampdu_dispatch_all = 0x40005694; -ampdu_dispatch_as_many_as_possible = 0x400056a0; -ampdu_dispatch_movement = 0x400056ac; -ampdu_dispatch_upto = 0x400056b8; -chm_is_at_home_channel = 0x400056c4; -cnx_node_is_existing = 0x400056d0; -cnx_node_search = 0x400056dc; -ic_ebuf_recycle_rx = 0x400056e8; -ic_ebuf_recycle_tx = 0x400056f4; -ic_reset_rx_ba = 0x40005700; -ieee80211_align_eb = 0x4000570c; -ieee80211_ampdu_reorder = 0x40005718; -ieee80211_ampdu_start_age_timer = 0x40005724; -ieee80211_encap_esfbuf = 0x40005730; -ieee80211_is_tx_allowed = 0x4000573c; -ieee80211_output_pending_eb = 0x40005748; -ieee80211_output_process = 0x40005754; -ieee80211_set_tx_desc = 0x40005760; -sta_input = 0x4000576c; -wifi_get_macaddr = 0x40005778; -wifi_rf_phy_disable = 0x40005784; -wifi_rf_phy_enable = 0x40005790; -ic_ebuf_alloc = 0x4000579c; -ieee80211_classify = 0x400057a8; -ieee80211_copy_eb_header = 0x400057b4; -ieee80211_recycle_cache_eb = 0x400057c0; -ieee80211_search_node = 0x400057cc; -roundup2 = 0x400057d8; -ieee80211_crypto_encap = 0x400057e4; -ieee80211_crypto_decap = 0x400057f0; -ieee80211_decap = 0x400057fc; -ieee80211_set_tx_pti = 0x40005808; -wifi_is_started = 0x40005814; +esp_net80211_rom_version_get = 0x400059b8; +ampdu_dispatch = 0x400059c4; +ampdu_dispatch_all = 0x400059d0; +ampdu_dispatch_as_many_as_possible = 0x400059dc; +ampdu_dispatch_movement = 0x400059e8; +ampdu_dispatch_upto = 0x400059f4; +chm_is_at_home_channel = 0x40005a00; +cnx_node_is_existing = 0x40005a0c; +cnx_node_search = 0x40005a18; +ic_ebuf_recycle_rx = 0x40005a24; +ic_ebuf_recycle_tx = 0x40005a30; +ic_reset_rx_ba = 0x40005a3c; +ieee80211_align_eb = 0x40005a48; +ieee80211_ampdu_reorder = 0x40005a54; +ieee80211_ampdu_start_age_timer = 0x40005a60; +ieee80211_encap_esfbuf = 0x40005a6c; +ieee80211_is_tx_allowed = 0x40005a78; +ieee80211_output_pending_eb = 0x40005a84; +ieee80211_output_process = 0x40005a90; +ieee80211_set_tx_desc = 0x40005a9c; +sta_input = 0x40005aa8; +wifi_get_macaddr = 0x40005ab4; +wifi_rf_phy_disable = 0x40005ac0; +wifi_rf_phy_enable = 0x40005acc; +ic_ebuf_alloc = 0x40005ad8; +ieee80211_classify = 0x40005ae4; +ieee80211_copy_eb_header = 0x40005af0; +ieee80211_recycle_cache_eb = 0x40005afc; +ieee80211_search_node = 0x40005b08; +roundup2 = 0x40005b14; +ieee80211_crypto_encap = 0x40005b20; +ieee80211_crypto_decap = 0x40005b2c; +ieee80211_decap = 0x40005b38; +ieee80211_set_tx_pti = 0x40005b44; +wifi_is_started = 0x40005b50; +ieee80211_gettid = 0x40005b5c; /* Data (.data, .bss, .rodata) */ -net80211_funcs = 0x3fcef864; -g_scan = 0x3fcef860; -g_chm = 0x3fcef85c; -g_ic_ptr = 0x3fcef858; -g_hmac_cnt_ptr = 0x3fcef854; -g_tx_cacheq_ptr = 0x3fcef850; -s_netstack_free = 0x3fcef84c; -mesh_rxcb = 0x3fcef848; -sta_rxcb = 0x3fcef844; +net80211_funcs = 0x3fcef858; +g_scan = 0x3fcef854; +g_chm = 0x3fcef850; +g_ic_ptr = 0x3fcef84c; +g_hmac_cnt_ptr = 0x3fcef848; +g_tx_cacheq_ptr = 0x3fcef844; +s_netstack_free = 0x3fcef840; +mesh_rxcb = 0x3fcef83c; +sta_rxcb = 0x3fcef838; /*************************************** @@ -1980,33 +2064,33 @@ sta_rxcb = 0x3fcef844; ***************************************/ /* Functions */ -esp_coex_rom_version_get = 0x40005820; -coex_bt_release = 0x4000582c; -coex_bt_request = 0x40005838; -coex_core_ble_conn_dyn_prio_get = 0x40005844; -coex_core_event_duration_get = 0x40005850; -coex_core_pti_get = 0x4000585c; -coex_core_release = 0x40005868; -coex_core_request = 0x40005874; -coex_core_status_get = 0x40005880; -coex_core_timer_idx_get = 0x4000588c; -coex_event_duration_get = 0x40005898; -coex_hw_timer_disable = 0x400058a4; -coex_hw_timer_enable = 0x400058b0; -coex_hw_timer_set = 0x400058bc; -coex_schm_interval_set = 0x400058c8; -coex_schm_lock = 0x400058d4; -coex_schm_unlock = 0x400058e0; -coex_status_get = 0x400058ec; -coex_wifi_release = 0x400058f8; -esp_coex_ble_conn_dynamic_prio_get = 0x40005904; +esp_coex_rom_version_get = 0x40005b68; +coex_bt_release = 0x40005b74; +coex_bt_request = 0x40005b80; +coex_core_ble_conn_dyn_prio_get = 0x40005b8c; +coex_core_event_duration_get = 0x40005b98; +coex_core_pti_get = 0x40005ba4; +coex_core_release = 0x40005bb0; +coex_core_request = 0x40005bbc; +coex_core_status_get = 0x40005bc8; +coex_core_timer_idx_get = 0x40005bd4; +coex_event_duration_get = 0x40005be0; +coex_hw_timer_disable = 0x40005bec; +coex_hw_timer_enable = 0x40005bf8; +coex_hw_timer_set = 0x40005c04; +coex_schm_interval_set = 0x40005c10; +coex_schm_lock = 0x40005c1c; +coex_schm_unlock = 0x40005c28; +coex_status_get = 0x40005c34; +coex_wifi_release = 0x40005c40; +esp_coex_ble_conn_dynamic_prio_get = 0x40005c4c; /* Data (.data, .bss, .rodata) */ -coex_env_ptr = 0x3fcef840; -coex_pti_tab_ptr = 0x3fcef83c; -coex_schm_env_ptr = 0x3fcef838; -coexist_funcs = 0x3fcef834; -g_coa_funcs_p = 0x3fcef830; -g_coex_param_ptr = 0x3fcef82c; +coex_env_ptr = 0x3fcef834; +coex_pti_tab_ptr = 0x3fcef830; +coex_schm_env_ptr = 0x3fcef82c; +coexist_funcs = 0x3fcef828; +g_coa_funcs_p = 0x3fcef824; +g_coex_param_ptr = 0x3fcef820; /*************************************** @@ -2014,145 +2098,173 @@ g_coex_param_ptr = 0x3fcef82c; ***************************************/ /* Functions */ -chip727_phyrom_version = 0x40005910; -phy_get_romfuncs = 0x4000591c; -rom_abs_temp = 0x40005928; -rom_agc_reg_init = 0x40005934; -rom_bb_bss_cbw40 = 0x40005940; -rom_bb_bss_cbw40_ana = 0x4000594c; -rom_bb_bss_cbw40_dig = 0x40005958; -rom_bb_reg_init = 0x40005964; -rom_bb_wdg_cfg = 0x40005970; -rom_bb_wdg_test_en = 0x4000597c; -rom_bb_wdt_get_status = 0x40005988; -rom_bb_wdt_int_enable = 0x40005994; -rom_bb_wdt_rst_enable = 0x400059a0; -rom_bb_wdt_timeout_clear = 0x400059ac; -rom_bt_bb_to_index = 0x400059b8; -rom_bt_correct_rf_ana_gain = 0x400059c4; -rom_bt_index_to_bb = 0x400059d0; -rom_cbw2040_cfg = 0x400059dc; -rom_chan_to_freq = 0x400059e8; -rom_check_noise_floor = 0x400059f4; -rom_chip_i2c_readReg = 0x40005a00; -rom_chip_i2c_readReg_org = 0x40005a0c; -rom_chip_i2c_writeReg = 0x40005a18; -rom_code_to_temp = 0x40005a24; -rom_correct_rf_ana_gain = 0x40005a30; -rom_dac_rate_set = 0x40005a3c; -rom_dc_iq_est = 0x40005a48; -rom_disable_agc = 0x40005a54; -rom_disable_wifi_agc = 0x40005a60; -rom_en_pwdet = 0x40005a6c; -rom_enable_agc = 0x40005a78; -rom_enable_wifi_agc = 0x40005a84; -rom_enter_critical_phy = 0x40005a90; -rom_exit_critical_phy = 0x40005a9c; -rom_fe_reg_init = 0x40005aa8; -rom_fe_txrx_reset = 0x40005ab4; -rom_force_txon = 0x40005ac0; -rom_get_bbgain_db = 0x40005acc; -rom_get_data_sat = 0x40005ad8; -rom_get_i2c_hostid = 0x40005ae4; -rom_get_i2c_mst0_mask = 0x40005af0; -rom_get_i2c_read_mask = 0x40005afc; -rom_get_phy_target_power = 0x40005b08; -rom_get_pll_vol = 0x40005b14; -rom_get_pwctrl_correct = 0x40005b20; -rom_get_rate_fcc_index = 0x40005b2c; -rom_get_rate_target_power = 0x40005b38; -rom_get_rf_gain_qdb = 0x40005b44; -rom_get_sar2_vol = 0x40005b50; -rom_get_target_power_offset = 0x40005b5c; -rom_i2c_paral_read = 0x40005b68; -rom_i2c_paral_set_mst0 = 0x40005b74; -rom_i2c_paral_set_read = 0x40005b80; -rom_i2c_paral_write = 0x40005b8c; -rom_i2c_paral_write_mask = 0x40005b98; -rom_i2c_paral_write_num = 0x40005ba4; -rom_i2c_readReg = 0x40005bb0; -rom_i2c_readReg_Mask = 0x40005bbc; -rom_i2c_writeReg = 0x40005bc8; -rom_i2c_writeReg_Mask = 0x40005bd4; -rom_i2cmst_reg_init = 0x40005be0; -rom_index_to_txbbgain = 0x40005bec; -rom_iq_corr_enable = 0x40005bf8; -rom_iq_est_disable = 0x40005c04; -rom_iq_est_enable = 0x40005c10; -rom_linear_to_db = 0x40005c1c; -rom_loopback_mode_en = 0x40005c28; -rom_mac_enable_bb = 0x40005c34; -rom_mac_tx_chan_offset = 0x40005c40; -rom_mhz2ieee = 0x40005c4c; -rom_noise_floor_auto_set = 0x40005c58; -rom_open_i2c_xpd = 0x40005c64; -rom_pbus_debugmode = 0x40005c70; -rom_pbus_force_mode = 0x40005c7c; -rom_pbus_force_test = 0x40005c88; -rom_pbus_rd = 0x40005c94; -rom_pbus_rd_addr = 0x40005ca0; -rom_pbus_rd_shift = 0x40005cac; -rom_pbus_set_dco = 0x40005cb8; -rom_pbus_set_rxgain = 0x40005cc4; -rom_pbus_workmode = 0x40005cd0; -rom_pbus_xpd_rx_off = 0x40005cdc; -rom_pbus_xpd_rx_on = 0x40005ce8; -rom_pbus_xpd_tx_off = 0x40005cf4; -rom_pbus_xpd_tx_on = 0x40005d00; -rom_phy_byte_to_word = 0x40005d0c; -rom_phy_dis_hw_set_freq = 0x40005d18; -rom_phy_disable_cca = 0x40005d24; -rom_phy_en_hw_set_freq = 0x40005d30; -rom_phy_enable_cca = 0x40005d3c; -rom_phy_get_noisefloor = 0x40005d48; -rom_phy_get_rx_freq = 0x40005d54; -rom_phy_pwdet_always_en = 0x40005d60; -rom_phy_pwdet_onetime_en = 0x40005d6c; -rom_phy_set_bbfreq_init = 0x40005d78; -rom_phy_track_pll_cap = 0x40005d84; -rom_phy_xpd_rf = 0x40005d90; -rom_pkdet_vol_start = 0x40005d9c; -rom_pll_correct_dcap = 0x40005da8; -rom_pll_vol_cal = 0x40005db4; -rom_pow_usr = 0x40005dc0; -rom_pwdet_sar2_init = 0x40005dcc; -rom_read_hw_noisefloor = 0x40005dd8; -rom_read_sar_dout = 0x40005de4; -rom_read_sar2_code = 0x40005df0; -rom_rtc_sar2_init = 0x40005dfc; -rom_rx_gain_force = 0x40005e08; -rom_set_cal_rxdc = 0x40005e14; -rom_set_cca = 0x40005e20; -rom_set_chan_cal_interp = 0x40005e2c; -rom_set_loopback_gain = 0x40005e38; -rom_set_noise_floor = 0x40005e44; -rom_set_pbus_reg = 0x40005e50; -rom_set_rx_comp = 0x40005e5c; -rom_set_rxclk_en = 0x40005e68; -rom_set_tx_dig_gain = 0x40005e74; -rom_set_tx_gain_table = 0x40005e80; -rom_set_txcap_reg = 0x40005e8c; -rom_set_txclk_en = 0x40005e98; -rom_set_xpd_sar = 0x40005ea4; -rom_spur_cal = 0x40005eb0; -rom_spur_coef_cfg = 0x40005ebc; -rom_spur_reg_write_one_tone = 0x40005ec8; -rom_target_power_add_backoff = 0x40005ed4; -rom_temp_to_power = 0x40005ee0; -rom_tsens_code_read = 0x40005eec; -rom_tsens_dac_cal = 0x40005ef8; -rom_tsens_index_to_dac = 0x40005f04; -rom_tsens_index_to_offset = 0x40005f10; -rom_tsens_read_init = 0x40005f1c; -rom_tx_paon_set = 0x40005f28; -rom_tx_pwctrl_bg_init = 0x40005f34; -rom_txbbgain_to_index = 0x40005f40; -rom_wifi_11g_rate_chg = 0x40005f4c; -rom_wr_bt_tx_atten = 0x40005f58; -rom_wr_bt_tx_gain_mem = 0x40005f64; -rom_write_chan_freq = 0x40005f70; -rom_write_dac_gain2 = 0x40005f7c; +phy_get_romfuncs = 0x40005c58; +rom_abs_temp = 0x40005c64; +rom_bb_bss_cbw40_dig = 0x40005c70; +rom_bb_wdg_test_en = 0x40005c7c; +rom_bb_wdt_get_status = 0x40005c88; +rom_bb_wdt_int_enable = 0x40005c94; +rom_bb_wdt_rst_enable = 0x40005ca0; +rom_bb_wdt_timeout_clear = 0x40005cac; +rom_cbw2040_cfg = 0x40005cb8; +rom_check_noise_floor = 0x40005cc4; +rom_chip_i2c_readReg = 0x40005cd0; +rom_chip_i2c_writeReg = 0x40005cdc; +rom_dc_iq_est = 0x40005ce8; +rom_disable_agc = 0x40005cf4; +rom_en_pwdet = 0x40005d00; +rom_enable_agc = 0x40005d0c; +rom_get_bbgain_db = 0x40005d18; +rom_get_data_sat = 0x40005d24; +rom_get_i2c_read_mask = 0x40005d30; +rom_get_pwctrl_correct = 0x40005d3c; +rom_i2c_readReg = 0x40005d48; +rom_i2c_readReg_Mask = 0x40005d54; +rom_i2c_writeReg = 0x40005d60; +rom_i2c_writeReg_Mask = 0x40005d6c; +rom_index_to_txbbgain = 0x40005d78; +rom_iq_est_disable = 0x40005d84; +rom_iq_est_enable = 0x40005d90; +rom_linear_to_db = 0x40005d9c; +rom_loopback_mode_en = 0x40005da8; +rom_mhz2ieee = 0x40005db4; +rom_noise_floor_auto_set = 0x40005dc0; +rom_pbus_debugmode = 0x40005dcc; +rom_pbus_force_mode = 0x40005dd8; +rom_pbus_force_test = 0x40005de4; +rom_pbus_rd = 0x40005df0; +rom_pbus_rd_addr = 0x40005dfc; +rom_pbus_rd_shift = 0x40005e08; +rom_pbus_set_dco = 0x40005e14; +rom_pbus_set_rxgain = 0x40005e20; +rom_pbus_workmode = 0x40005e2c; +rom_pbus_xpd_rx_off = 0x40005e38; +rom_pbus_xpd_rx_on = 0x40005e44; +rom_pbus_xpd_tx_off = 0x40005e50; +rom_pbus_xpd_tx_on = 0x40005e5c; +rom_phy_byte_to_word = 0x40005e68; +rom_phy_disable_cca = 0x40005e74; +rom_phy_enable_cca = 0x40005e80; +rom_phy_get_noisefloor = 0x40005e8c; +rom_phy_get_rx_freq = 0x40005e98; +rom_phy_set_bbfreq_init = 0x40005ea4; +rom_pow_usr = 0x40005eb0; +rom_pwdet_sar2_init = 0x40005ebc; +rom_read_hw_noisefloor = 0x40005ec8; +rom_read_sar_dout = 0x40005ed4; +rom_set_cal_rxdc = 0x40005ee0; +rom_set_chan_cal_interp = 0x40005eec; +rom_set_loopback_gain = 0x40005ef8; +rom_set_noise_floor = 0x40005f04; +rom_set_rxclk_en = 0x40005f10; +rom_set_tx_dig_gain = 0x40005f1c; +rom_set_txcap_reg = 0x40005f28; +rom_set_txclk_en = 0x40005f34; +rom_spur_cal = 0x40005f40; +rom_spur_reg_write_one_tone = 0x40005f4c; +rom_target_power_add_backoff = 0x40005f58; +rom_tx_pwctrl_bg_init = 0x40005f64; +rom_txbbgain_to_index = 0x40005f70; +rom_wifi_11g_rate_chg = 0x40005f7c; rom_write_gain_mem = 0x40005f88; -rom_write_pll_cap_mem = 0x40005f94; -rom_write_txrate_power_offset = 0x40005fa0; -rom_write_wifi_dig_gain = 0x40005fac; +chip728_phyrom_version = 0x40005f94; +rom_disable_wifi_agc = 0x40005fa0; +rom_enable_wifi_agc = 0x40005fac; +rom_bt_index_to_bb = 0x40005fb8; +rom_bt_bb_to_index = 0x40005fc4; +rom_spur_coef_cfg = 0x40005fd0; +rom_bb_bss_cbw40 = 0x40005fdc; +rom_set_cca = 0x40005fe8; +rom_tx_paon_set = 0x40005ff4; +rom_i2cmst_reg_init = 0x40006000; +rom_iq_corr_enable = 0x4000600c; +rom_fe_reg_init = 0x40006018; +rom_agc_reg_init = 0x40006024; +rom_bb_reg_init = 0x40006030; +rom_mac_enable_bb = 0x4000603c; +rom_bb_wdg_cfg = 0x40006048; +rom_force_txon = 0x40006054; +rom_fe_txrx_reset = 0x40006060; +rom_set_rx_comp = 0x4000606c; +rom_set_pbus_reg = 0x40006078; +rom_write_chan_freq = 0x40006084; +rom_phy_xpd_rf = 0x40006090; +rom_set_xpd_sar = 0x4000609c; +rom_get_target_power_offset = 0x400060a8; +rom_write_txrate_power_offset = 0x400060b4; +rom_get_rate_fcc_index = 0x400060c0; +rom_get_rate_target_power = 0x400060cc; +rom_pkdet_vol_start = 0x400060d8; +rom_read_sar2_code = 0x400060e4; +rom_get_sar2_vol = 0x400060f0; +rom_get_pll_vol = 0x400060fc; +rom_get_phy_target_power = 0x40006108; +rom_temp_to_power = 0x40006114; +rom_phy_track_pll_cap = 0x40006120; +rom_phy_pwdet_always_en = 0x4000612c; +rom_phy_pwdet_onetime_en = 0x40006138; +rom_get_i2c_mst0_mask = 0x40006144; +rom_get_i2c_hostid = 0x40006150; +rom_enter_critical_phy = 0x4000615c; +rom_exit_critical_phy = 0x40006168; +rom_chip_i2c_readReg_org = 0x40006174; +rom_i2c_paral_set_mst0 = 0x40006180; +rom_i2c_paral_set_read = 0x4000618c; +rom_i2c_paral_read = 0x40006198; +rom_i2c_paral_write = 0x400061a4; +rom_i2c_paral_write_num = 0x400061b0; +rom_i2c_paral_write_mask = 0x400061bc; +rom_bb_bss_cbw40_ana = 0x400061c8; +rom_chan_to_freq = 0x400061d4; +rom_open_i2c_xpd = 0x400061e0; +rom_dac_rate_set = 0x400061ec; +rom_tsens_read_init = 0x400061f8; +rom_tsens_code_read = 0x40006204; +rom_tsens_index_to_dac = 0x40006210; +rom_tsens_index_to_offset = 0x4000621c; +rom_tsens_dac_cal = 0x40006228; +rom_code_to_temp = 0x40006234; +rom_write_pll_cap_mem = 0x40006240; +rom_pll_correct_dcap = 0x4000624c; +rom_phy_en_hw_set_freq = 0x40006258; +rom_phy_dis_hw_set_freq = 0x40006264; +rom_pll_vol_cal = 0x40006270; +rom_wrtie_pll_cap = 0x4000627c; +rom_set_tx_gain_mem = 0x40006288; +rom_bt_tx_dig_gain = 0x40006294; +rom_bt_get_tx_gain = 0x400062a0; +rom_get_chan_target_power = 0x400062ac; +rom_get_tx_gain_value = 0x400062b8; +rom_wifi_tx_dig_gain = 0x400062c4; +rom_wifi_get_tx_gain = 0x400062d0; +rom_fe_i2c_reg_renew = 0x400062dc; +rom_wifi_agc_sat_gain = 0x400062e8; +rom_i2c_master_reset = 0x400062f4; +rom_bt_filter_reg = 0x40006300; +rom_phy_bbpll_cal = 0x4000630c; +rom_i2c_sar2_init_code = 0x40006318; +rom_phy_param_addr = 0x40006324; +rom_phy_reg_init = 0x40006330; +rom_set_chan_reg = 0x4000633c; +rom_phy_wakeup_init = 0x40006348; +rom_phy_i2c_init1 = 0x40006354; +rom_tsens_temp_read = 0x40006360; +rom_bt_track_pll_cap = 0x4000636c; +rom_wifi_track_pll_cap = 0x40006378; +rom_wifi_set_tx_gain = 0x40006384; +rom_txpwr_cal_track = 0x40006390; +rom_tx_pwctrl_background = 0x4000639c; +rom_bt_set_tx_gain = 0x400063a8; +rom_noise_check_loop = 0x400063b4; +rom_phy_close_rf = 0x400063c0; +rom_phy_xpd_tsens = 0x400063cc; +rom_phy_freq_mem_backup = 0x400063d8; +rom_phy_ant_init = 0x400063e4; +rom_bt_track_tx_power = 0x400063f0; +rom_wifi_track_tx_power = 0x400063fc; +rom_phy_dig_reg_backup = 0x40006408; +chip728_phyrom_version_num = 0x40006414; +rom_mac_tx_chan_offset = 0x40006420; +rom_rx_gain_force = 0x4000642c; +/* Data (.data, .bss, .rodata) */ +phy_param_rom = 0x3fcef81c; diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.libgcc.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.libgcc.ld index 36886182c3..3571b0380d 100644 --- a/components/esp_rom/esp32s3/ld/esp32s3.rom.libgcc.ld +++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.libgcc.ld @@ -1,7 +1,7 @@ /* ROM function interface esp32s3.rom.libgcc.ld for esp32s3 * * - * Generated from ./interface-esp32s3.yml md5sum 36d43c36b9d0f4f082f71c819ad53470 + * Generated from ./interface-esp32s3.yml md5sum 39c4ce259b11323b9404c192b01b712b * * Compatible with ROM where ECO version equal or greater to 0. * @@ -13,93 +13,93 @@ ***************************************/ /* Functions */ -__absvdi2 = 0x40001fd4; -__absvsi2 = 0x40001fe0; -__adddf3 = 0x40001fec; -__addsf3 = 0x40001ff8; -__addvdi3 = 0x40002004; -__addvsi3 = 0x40002010; -__ashldi3 = 0x4000201c; -__ashrdi3 = 0x40002028; -__bswapdi2 = 0x40002034; -__bswapsi2 = 0x40002040; -__clear_cache = 0x4000204c; -__clrsbdi2 = 0x40002058; -__clrsbsi2 = 0x40002064; -__clzdi2 = 0x40002070; -__clzsi2 = 0x4000207c; -__cmpdi2 = 0x40002088; -__ctzdi2 = 0x40002094; -__ctzsi2 = 0x400020a0; -__divdc3 = 0x400020ac; -__divdf3 = 0x400020b8; -__divdi3 = 0x400020c4; -__divsc3 = 0x400020d0; -__divsf3 = 0x400020dc; -__divsi3 = 0x400020e8; -__eqdf2 = 0x400020f4; -__eqsf2 = 0x40002100; -__extendsfdf2 = 0x4000210c; -__ffsdi2 = 0x40002118; -__ffssi2 = 0x40002124; -__fixdfdi = 0x40002130; -__fixdfsi = 0x4000213c; -__fixsfdi = 0x40002148; -__fixsfsi = 0x40002154; -__fixunsdfsi = 0x40002160; -__fixunssfdi = 0x4000216c; -__fixunssfsi = 0x40002178; -__floatdidf = 0x40002184; -__floatdisf = 0x40002190; -__floatsidf = 0x4000219c; -__floatsisf = 0x400021a8; -__floatundidf = 0x400021b4; -__floatundisf = 0x400021c0; -__floatunsidf = 0x400021cc; -__floatunsisf = 0x400021d8; -__gcc_bcmp = 0x400021e4; -__gedf2 = 0x400021f0; -__gesf2 = 0x400021fc; -__gtdf2 = 0x40002208; -__gtsf2 = 0x40002214; -__ledf2 = 0x40002220; -__lesf2 = 0x4000222c; -__lshrdi3 = 0x40002238; -__ltdf2 = 0x40002244; -__ltsf2 = 0x40002250; -__moddi3 = 0x4000225c; -__modsi3 = 0x40002268; -__muldc3 = 0x40002274; -__muldf3 = 0x40002280; -__muldi3 = 0x4000228c; -__mulsc3 = 0x40002298; -__mulsf3 = 0x400022a4; -__mulsi3 = 0x400022b0; -__mulvdi3 = 0x400022bc; -__mulvsi3 = 0x400022c8; -__nedf2 = 0x400022d4; -__negdf2 = 0x400022e0; -__negdi2 = 0x400022ec; -__negsf2 = 0x400022f8; -__negvdi2 = 0x40002304; -__negvsi2 = 0x40002310; -__nesf2 = 0x4000231c; -__paritysi2 = 0x40002328; -__popcountdi2 = 0x40002334; -__popcountsi2 = 0x40002340; -__powidf2 = 0x4000234c; -__powisf2 = 0x40002358; -__subdf3 = 0x40002364; -__subsf3 = 0x40002370; -__subvdi3 = 0x4000237c; -__subvsi3 = 0x40002388; -__truncdfsf2 = 0x40002394; -__ucmpdi2 = 0x400023a0; -__udivdi3 = 0x400023ac; -__udivmoddi4 = 0x400023b8; -__udivsi3 = 0x400023c4; -__udiv_w_sdiv = 0x400023d0; -__umoddi3 = 0x400023dc; -__umodsi3 = 0x400023e8; -__unorddf2 = 0x400023f4; -__unordsf2 = 0x40002400; +__absvdi2 = 0x4000216c; +__absvsi2 = 0x40002178; +__adddf3 = 0x40002184; +__addsf3 = 0x40002190; +__addvdi3 = 0x4000219c; +__addvsi3 = 0x400021a8; +__ashldi3 = 0x400021b4; +__ashrdi3 = 0x400021c0; +__bswapdi2 = 0x400021cc; +__bswapsi2 = 0x400021d8; +__clear_cache = 0x400021e4; +__clrsbdi2 = 0x400021f0; +__clrsbsi2 = 0x400021fc; +__clzdi2 = 0x40002208; +__clzsi2 = 0x40002214; +__cmpdi2 = 0x40002220; +__ctzdi2 = 0x4000222c; +__ctzsi2 = 0x40002238; +__divdc3 = 0x40002244; +__divdf3 = 0x40002250; +__divdi3 = 0x4000225c; +__divsc3 = 0x40002268; +__divsf3 = 0x40002274; +__divsi3 = 0x40002280; +__eqdf2 = 0x4000228c; +__eqsf2 = 0x40002298; +__extendsfdf2 = 0x400022a4; +__ffsdi2 = 0x400022b0; +__ffssi2 = 0x400022bc; +__fixdfdi = 0x400022c8; +__fixdfsi = 0x400022d4; +__fixsfdi = 0x400022e0; +__fixsfsi = 0x400022ec; +__fixunsdfsi = 0x400022f8; +__fixunssfdi = 0x40002304; +__fixunssfsi = 0x40002310; +__floatdidf = 0x4000231c; +__floatdisf = 0x40002328; +__floatsidf = 0x40002334; +__floatsisf = 0x40002340; +__floatundidf = 0x4000234c; +__floatundisf = 0x40002358; +__floatunsidf = 0x40002364; +__floatunsisf = 0x40002370; +__gcc_bcmp = 0x4000237c; +__gedf2 = 0x40002388; +__gesf2 = 0x40002394; +__gtdf2 = 0x400023a0; +__gtsf2 = 0x400023ac; +__ledf2 = 0x400023b8; +__lesf2 = 0x400023c4; +__lshrdi3 = 0x400023d0; +__ltdf2 = 0x400023dc; +__ltsf2 = 0x400023e8; +__moddi3 = 0x400023f4; +__modsi3 = 0x40002400; +__muldc3 = 0x4000240c; +__muldf3 = 0x40002418; +__muldi3 = 0x40002424; +__mulsc3 = 0x40002430; +__mulsf3 = 0x4000243c; +__mulsi3 = 0x40002448; +__mulvdi3 = 0x40002454; +__mulvsi3 = 0x40002460; +__nedf2 = 0x4000246c; +__negdf2 = 0x40002478; +__negdi2 = 0x40002484; +__negsf2 = 0x40002490; +__negvdi2 = 0x4000249c; +__negvsi2 = 0x400024a8; +__nesf2 = 0x400024b4; +__paritysi2 = 0x400024c0; +__popcountdi2 = 0x400024cc; +__popcountsi2 = 0x400024d8; +__powidf2 = 0x400024e4; +__powisf2 = 0x400024f0; +__subdf3 = 0x400024fc; +__subsf3 = 0x40002508; +__subvdi3 = 0x40002514; +__subvsi3 = 0x40002520; +__truncdfsf2 = 0x4000252c; +__ucmpdi2 = 0x40002538; +__udivdi3 = 0x40002544; +__udivmoddi4 = 0x40002550; +__udivsi3 = 0x4000255c; +__udiv_w_sdiv = 0x40002568; +__umoddi3 = 0x40002574; +__umodsi3 = 0x40002580; +__unorddf2 = 0x4000258c; +__unordsf2 = 0x40002598; diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.newlib-nano.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.newlib-nano.ld index 4c352abb84..1be53790e6 100644 --- a/components/esp_rom/esp32s3/ld/esp32s3.rom.newlib-nano.ld +++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.newlib-nano.ld @@ -1,7 +1,7 @@ /* ROM function interface esp32s3.rom.newlib-nano.ld for esp32s3 * * - * Generated from ./interface-esp32s3.yml md5sum 36d43c36b9d0f4f082f71c819ad53470 + * Generated from ./interface-esp32s3.yml md5sum 39c4ce259b11323b9404c192b01b712b * * Compatible with ROM where ECO version equal or greater to 0. * @@ -13,15 +13,15 @@ ***************************************/ /* Functions */ -__sprint_r = 0x400013f8; -_fiprintf_r = 0x40001404; -_fprintf_r = 0x40001410; -_printf_common = 0x4000141c; -_printf_i = 0x40001428; -_vfiprintf_r = 0x40001434; -_vfprintf_r = 0x40001440; -fiprintf = 0x4000144c; -fprintf = 0x40001458; -printf = 0x40001464; -vfiprintf = 0x40001470; -vfprintf = 0x4000147c; +__sprint_r = 0x4000156c; +_fiprintf_r = 0x40001578; +_fprintf_r = 0x40001584; +_printf_common = 0x40001590; +_printf_i = 0x4000159c; +_vfiprintf_r = 0x400015a8; +_vfprintf_r = 0x400015b4; +fiprintf = 0x400015c0; +fprintf = 0x400015cc; +printf = 0x400015d8; +vfiprintf = 0x400015e4; +vfprintf = 0x400015f0; diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.newlib.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.newlib.ld index 486154a2e2..bd33a20187 100644 --- a/components/esp_rom/esp32s3/ld/esp32s3.rom.newlib.ld +++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.newlib.ld @@ -1,7 +1,7 @@ /* ROM function interface esp32s3.rom.newlib.ld for esp32s3 * * - * Generated from ./interface-esp32s3.yml md5sum 36d43c36b9d0f4f082f71c819ad53470 + * Generated from ./interface-esp32s3.yml md5sum 39c4ce259b11323b9404c192b01b712b * * Compatible with ROM where ECO version equal or greater to 0. * @@ -13,82 +13,82 @@ ***************************************/ /* Functions */ -esp_rom_newlib_init_common_mutexes = 0x40001068; -memset = 0x40001074; -memcpy = 0x40001080; -memmove = 0x4000108c; -memcmp = 0x40001098; -strcpy = 0x400010a4; -strncpy = 0x400010b0; -strcmp = 0x400010bc; -strncmp = 0x400010c8; -strlen = 0x400010d4; -strstr = 0x400010e0; -bzero = 0x400010ec; -_isatty_r = 0x400010f8; -sbrk = 0x40001104; -isalnum = 0x40001110; -isalpha = 0x4000111c; -isascii = 0x40001128; -isblank = 0x40001134; -iscntrl = 0x40001140; -isdigit = 0x4000114c; -islower = 0x40001158; -isgraph = 0x40001164; -isprint = 0x40001170; -ispunct = 0x4000117c; -isspace = 0x40001188; -isupper = 0x40001194; -toupper = 0x400011a0; -tolower = 0x400011ac; -toascii = 0x400011b8; -memccpy = 0x400011c4; -memchr = 0x400011d0; -memrchr = 0x400011dc; -strcasecmp = 0x400011e8; -strcasestr = 0x400011f4; -strcat = 0x40001200; -strdup = 0x4000120c; -strchr = 0x40001218; -strcspn = 0x40001224; -strcoll = 0x40001230; -strlcat = 0x4000123c; -strlcpy = 0x40001248; -strlwr = 0x40001254; -strncasecmp = 0x40001260; -strncat = 0x4000126c; -strndup = 0x40001278; -strnlen = 0x40001284; -strrchr = 0x40001290; -strsep = 0x4000129c; -strspn = 0x400012a8; -strtok_r = 0x400012b4; -strupr = 0x400012c0; -longjmp = 0x400012cc; -setjmp = 0x400012d8; -abs = 0x400012e4; -div = 0x400012f0; -labs = 0x400012fc; -ldiv = 0x40001308; -qsort = 0x40001314; -rand_r = 0x40001320; -rand = 0x4000132c; -srand = 0x40001338; -utoa = 0x40001344; -itoa = 0x40001350; -atoi = 0x4000135c; -atol = 0x40001368; -strtol = 0x40001374; -strtoul = 0x40001380; -PROVIDE( fflush = 0x4000138c ); -PROVIDE( _fflush_r = 0x40001398 ); -PROVIDE( _fwalk = 0x400013a4 ); -PROVIDE( _fwalk_reent = 0x400013b0 ); -PROVIDE( __smakebuf_r = 0x400013bc ); -PROVIDE( __swhatbuf_r = 0x400013c8 ); -PROVIDE( __swbuf_r = 0x400013d4 ); -__swbuf = 0x400013e0; -PROVIDE( __swsetup_r = 0x400013ec ); +esp_rom_newlib_init_common_mutexes = 0x400011dc; +memset = 0x400011e8; +memcpy = 0x400011f4; +memmove = 0x40001200; +memcmp = 0x4000120c; +strcpy = 0x40001218; +strncpy = 0x40001224; +strcmp = 0x40001230; +strncmp = 0x4000123c; +strlen = 0x40001248; +strstr = 0x40001254; +bzero = 0x40001260; +_isatty_r = 0x4000126c; +sbrk = 0x40001278; +isalnum = 0x40001284; +isalpha = 0x40001290; +isascii = 0x4000129c; +isblank = 0x400012a8; +iscntrl = 0x400012b4; +isdigit = 0x400012c0; +islower = 0x400012cc; +isgraph = 0x400012d8; +isprint = 0x400012e4; +ispunct = 0x400012f0; +isspace = 0x400012fc; +isupper = 0x40001308; +toupper = 0x40001314; +tolower = 0x40001320; +toascii = 0x4000132c; +memccpy = 0x40001338; +memchr = 0x40001344; +memrchr = 0x40001350; +strcasecmp = 0x4000135c; +strcasestr = 0x40001368; +strcat = 0x40001374; +strdup = 0x40001380; +strchr = 0x4000138c; +strcspn = 0x40001398; +strcoll = 0x400013a4; +strlcat = 0x400013b0; +strlcpy = 0x400013bc; +strlwr = 0x400013c8; +strncasecmp = 0x400013d4; +strncat = 0x400013e0; +strndup = 0x400013ec; +strnlen = 0x400013f8; +strrchr = 0x40001404; +strsep = 0x40001410; +strspn = 0x4000141c; +strtok_r = 0x40001428; +strupr = 0x40001434; +longjmp = 0x40001440; +setjmp = 0x4000144c; +abs = 0x40001458; +div = 0x40001464; +labs = 0x40001470; +ldiv = 0x4000147c; +qsort = 0x40001488; +rand_r = 0x40001494; +rand = 0x400014a0; +srand = 0x400014ac; +utoa = 0x400014b8; +itoa = 0x400014c4; +atoi = 0x400014d0; +atol = 0x400014dc; +strtol = 0x400014e8; +strtoul = 0x400014f4; +PROVIDE( fflush = 0x40001500 ); +PROVIDE( _fflush_r = 0x4000150c ); +PROVIDE( _fwalk = 0x40001518 ); +PROVIDE( _fwalk_reent = 0x40001524 ); +PROVIDE( __smakebuf_r = 0x40001530 ); +PROVIDE( __swhatbuf_r = 0x4000153c ); +PROVIDE( __swbuf_r = 0x40001548 ); +__swbuf = 0x40001554; +PROVIDE( __swsetup_r = 0x40001560 ); /* Data (.data, .bss, .rodata) */ -syscall_table_ptr = 0x3fceffe0; -_global_impure_ptr = 0x3fceffdc; +syscall_table_ptr = 0x3fceffd4; +_global_impure_ptr = 0x3fceffd0; diff --git a/components/esp_rom/patches/esp_rom_sys.c b/components/esp_rom/patches/esp_rom_sys.c index b719fdd620..1ec7a15b86 100644 --- a/components/esp_rom/patches/esp_rom_sys.c +++ b/components/esp_rom/patches/esp_rom_sys.c @@ -18,12 +18,6 @@ #include "sdkconfig.h" -#ifdef CONFIG_IDF_TARGET_ESP32 -#include "esp32/rom/rtc.h" -#elif CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/rom/rtc.h" -#endif - IRAM_ATTR void esp_rom_install_channel_putc(int channel, void (*putc)(char c)) { extern void ets_install_putc1(void (*p)(char c)); diff --git a/components/esptool_py/esptool b/components/esptool_py/esptool index e5f94fa7ea..1c9fe70597 160000 --- a/components/esptool_py/esptool +++ b/components/esptool_py/esptool @@ -1 +1 @@ -Subproject commit e5f94fa7ea60403e804d782115f440385e8a5edd +Subproject commit 1c9fe7059738ecd8e2b77c66cf7e2be73e566c16 diff --git a/components/esptool_py/project_include.cmake b/components/esptool_py/project_include.cmake index 5948fe40c2..a1802d5f03 100644 --- a/components/esptool_py/project_include.cmake +++ b/components/esptool_py/project_include.cmake @@ -6,11 +6,6 @@ idf_build_get_property(python PYTHON) idf_build_get_property(idf_path IDF_PATH) set(chip_model ${target}) -if(target STREQUAL "esp32s3") - if(CONFIG_IDF_TARGET_ESP32S3_BETA_VERSION_3) - set(chip_model "esp32s3beta3") - endif() -endif() set(ESPTOOLPY ${python} "$ENV{ESPTOOL_WRAPPER}" "${CMAKE_CURRENT_LIST_DIR}/esptool/esptool.py" --chip ${chip_model}) set(ESPSECUREPY ${python} "${CMAKE_CURRENT_LIST_DIR}/esptool/espsecure.py") diff --git a/components/hal/esp32s3/include/hal/gdma_ll.h b/components/hal/esp32s3/include/hal/gdma_ll.h index 9483302132..7709cc1235 100644 --- a/components/hal/esp32s3/include/hal/gdma_ll.h +++ b/components/hal/esp32s3/include/hal/gdma_ll.h @@ -48,17 +48,21 @@ extern "C" { #define GDMA_LL_EVENT_RX_SUC_EOF (1<<1) #define GDMA_LL_EVENT_RX_DONE (1<<0) +/* Memory block size value supported by TX channel */ +#define GDMA_LL_OUT_EXT_MEM_BK_SIZE_16B (0) +#define GDMA_LL_OUT_EXT_MEM_BK_SIZE_32B (1) + ///////////////////////////////////// Common ///////////////////////////////////////// /** * @brief Enable DMA channel M2M mode (TX channel n forward data to RX channel n), disabled by default */ static inline void gdma_ll_enable_m2m_mode(gdma_dev_t *dev, uint32_t channel, bool enable) { - dev->in[channel].conf0.mem_trans_en = enable; + dev->channel[channel].in.conf0.mem_trans_en = enable; if (enable) { // to enable m2m mode, the tx chan has to be the same to rx chan, and set to a valid value - dev->in[channel].peri_sel.sel = 0; - dev->out[channel].peri_sel.sel = 0; + dev->channel[channel].in.peri_sel.sel = 0; + dev->channel[channel].out.peri_sel.sel = 0; } } @@ -76,7 +80,7 @@ static inline void gdma_ll_enable_clock(gdma_dev_t *dev, bool enable) */ static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) { - return dev->in[channel].int_st.val; + return dev->channel[channel].in.int_st.val; } /** @@ -85,9 +89,9 @@ static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable) { if (enable) { - dev->in[channel].int_ena.val |= mask; + dev->channel[channel].in.int_ena.val |= mask; } else { - dev->in[channel].int_ena.val &= ~mask; + dev->channel[channel].in.int_ena.val &= ~mask; } } @@ -96,7 +100,7 @@ static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel */ static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask) { - dev->in[channel].int_clr.val = mask; + dev->channel[channel].in.int_clr.val = mask; } /** @@ -104,7 +108,7 @@ static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t c */ static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel) { - return (volatile void *)(&dev->in[channel].int_st); + return (volatile void *)(&dev->channel[channel].in.int_st); } /** @@ -112,7 +116,7 @@ static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev */ static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) { - dev->in[channel].conf1.in_check_owner = enable; + dev->channel[channel].in.conf1.in_check_owner = enable; } /** @@ -120,7 +124,7 @@ static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t chann */ static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable) { - dev->in[channel].conf0.in_data_burst_en = enable; + dev->channel[channel].in.conf0.in_data_burst_en = enable; } /** @@ -128,7 +132,7 @@ static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channe */ static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable) { - dev->in[channel].conf0.indscr_burst_en = enable; + dev->channel[channel].in.conf0.indscr_burst_en = enable; } /** @@ -136,8 +140,8 @@ static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t */ static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel) { - dev->in[channel].conf0.in_rst = 1; - dev->in[channel].conf0.in_rst = 0; + dev->channel[channel].in.conf0.in_rst = 1; + dev->channel[channel].in.conf0.in_rst = 0; } /** @@ -146,7 +150,7 @@ static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel) */ static inline void gdma_ll_rx_set_block_size_psram(gdma_dev_t *dev, uint32_t channel, uint32_t size_index) { - dev->in[channel].conf1.in_ext_mem_bk_size = size_index; + dev->channel[channel].in.conf1.in_ext_mem_bk_size = size_index; } /** @@ -154,7 +158,7 @@ static inline void gdma_ll_rx_set_block_size_psram(gdma_dev_t *dev, uint32_t cha */ static inline void gdma_ll_rx_set_water_mark(gdma_dev_t *dev, uint32_t channel, uint32_t water_mark) { - dev->in[channel].conf1.dma_infifo_full_thrs = water_mark; + dev->channel[channel].in.conf1.dma_infifo_full_thrs = water_mark; } /** @@ -163,7 +167,7 @@ static inline void gdma_ll_rx_set_water_mark(gdma_dev_t *dev, uint32_t channel, */ static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) { - return dev->in[channel].infifo_status.val & (1 << 2 * (fifo_level - 1)); + return dev->channel[channel].in.infifo_status.val & (1 << 2 * (fifo_level - 1)); } /** @@ -172,7 +176,7 @@ static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, ui */ static inline bool gdma_ll_rx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) { - return dev->in[channel].infifo_status.val & (1 << (2 * (fifo_level - 1) + 1)); + return dev->channel[channel].in.infifo_status.val & (1 << (2 * (fifo_level - 1) + 1)); } /** @@ -183,11 +187,11 @@ static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t chann { switch (fifo_level) { case 1: - return dev->in[channel].infifo_status.infifo_cnt_l1; + return dev->channel[channel].in.infifo_status.infifo_cnt_l1; case 2: - return dev->in[channel].infifo_status.infifo_cnt_l2; + return dev->channel[channel].in.infifo_status.infifo_cnt_l2; case 3: - return dev->in[channel].infifo_status.infifo_cnt_l3; + return dev->channel[channel].in.infifo_status.infifo_cnt_l3; } } @@ -196,8 +200,8 @@ static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t chann */ static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel) { - dev->in[channel].pop.infifo_pop = 1; - return dev->in[channel].pop.infifo_rdata; + dev->channel[channel].in.pop.infifo_pop = 1; + return dev->channel[channel].in.pop.infifo_rdata; } /** @@ -205,7 +209,7 @@ static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel) */ static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr) { - dev->in[channel].link.addr = addr; + dev->channel[channel].in.link.addr = addr; } /** @@ -213,7 +217,7 @@ static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, u */ static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel) { - dev->in[channel].link.start = 1; + dev->channel[channel].in.link.start = 1; } /** @@ -221,7 +225,7 @@ static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel) */ static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel) { - dev->in[channel].link.stop = 1; + dev->channel[channel].in.link.stop = 1; } /** @@ -229,7 +233,7 @@ static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel) */ static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel) { - dev->in[channel].link.restart = 1; + dev->channel[channel].in.link.restart = 1; } /** @@ -237,7 +241,7 @@ static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel) */ static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t channel, bool enable) { - dev->in[channel].link.auto_ret = enable; + dev->channel[channel].in.link.auto_ret = enable; } /** @@ -245,7 +249,7 @@ static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t chann */ static inline bool gdma_ll_rx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel) { - return dev->in[channel].link.park; + return dev->channel[channel].in.link.park; } /** @@ -253,7 +257,7 @@ static inline bool gdma_ll_rx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel) */ static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uint32_t channel) { - return dev->in[channel].suc_eof_des_addr; + return dev->channel[channel].in.suc_eof_des_addr; } /** @@ -261,7 +265,7 @@ static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uin */ static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint32_t channel) { - return dev->in[channel].err_eof_des_addr; + return dev->channel[channel].in.err_eof_des_addr; } /** @@ -269,7 +273,7 @@ static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint3 */ static inline uint32_t gdma_ll_rx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel) { - return dev->in[channel].dscr; + return dev->channel[channel].in.dscr; } /** @@ -277,7 +281,7 @@ static inline uint32_t gdma_ll_rx_get_current_desc_addr(gdma_dev_t *dev, uint32_ */ static inline void gdma_ll_rx_set_weight(gdma_dev_t *dev, uint32_t channel, uint32_t weight) { - dev->in[channel].wight.rx_weight = weight; + dev->channel[channel].in.wight.rx_weight = weight; } /** @@ -285,7 +289,7 @@ static inline void gdma_ll_rx_set_weight(gdma_dev_t *dev, uint32_t channel, uint */ static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio) { - dev->in[channel].pri.rx_pri = prio; + dev->channel[channel].in.pri.rx_pri = prio; } /** @@ -293,7 +297,7 @@ static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, ui */ static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id) { - dev->in[channel].peri_sel.sel = periph_id; + dev->channel[channel].in.peri_sel.sel = periph_id; } /** @@ -304,7 +308,7 @@ static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channe static inline void gdma_ll_rx_extend_l2_fifo_size_to(gdma_dev_t *dev, uint32_t channel, uint32_t size_in_bytes) { if (size_in_bytes > SOC_GDMA_L2_FIFO_BASE_SIZE) { - dev->in[channel].sram_size.in_size = (size_in_bytes - SOC_GDMA_L2_FIFO_BASE_SIZE) / 8; + dev->sram_size[channel].in.in_size = (size_in_bytes - SOC_GDMA_L2_FIFO_BASE_SIZE) / 8; } } @@ -315,7 +319,7 @@ static inline void gdma_ll_rx_extend_l2_fifo_size_to(gdma_dev_t *dev, uint32_t c */ static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel) { - return dev->out[channel].int_st.val; + return dev->channel[channel].out.int_st.val; } /** @@ -324,9 +328,9 @@ static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t static inline void gdma_ll_tx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable) { if (enable) { - dev->out[channel].int_ena.val |= mask; + dev->channel[channel].out.int_ena.val |= mask; } else { - dev->out[channel].int_ena.val &= ~mask; + dev->channel[channel].out.int_ena.val &= ~mask; } } @@ -335,7 +339,7 @@ static inline void gdma_ll_tx_enable_interrupt(gdma_dev_t *dev, uint32_t channel */ static inline void gdma_ll_tx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask) { - dev->out[channel].int_clr.val = mask; + dev->channel[channel].out.int_clr.val = mask; } /** @@ -343,7 +347,7 @@ static inline void gdma_ll_tx_clear_interrupt_status(gdma_dev_t *dev, uint32_t c */ static inline volatile void *gdma_ll_tx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel) { - return (volatile void *)(&dev->out[channel].int_st); + return (volatile void *)(&dev->channel[channel].out.int_st); } /** @@ -351,7 +355,7 @@ static inline volatile void *gdma_ll_tx_get_interrupt_status_reg(gdma_dev_t *dev */ static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) { - dev->out[channel].conf1.out_check_owner = enable; + dev->channel[channel].out.conf1.out_check_owner = enable; } /** @@ -359,7 +363,7 @@ static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t chann */ static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable) { - dev->out[channel].conf0.out_data_burst_en = enable; + dev->channel[channel].out.conf0.out_data_burst_en = enable; } /** @@ -367,7 +371,7 @@ static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channe */ static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable) { - dev->out[channel].conf0.outdscr_burst_en = enable; + dev->channel[channel].out.conf0.outdscr_burst_en = enable; } /** @@ -375,7 +379,7 @@ static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t */ static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, uint32_t mode) { - dev->out[channel].conf0.out_eof_mode = mode; + dev->channel[channel].out.conf0.out_eof_mode = mode; } /** @@ -383,7 +387,7 @@ static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, ui */ static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t channel, bool enable) { - dev->out[channel].conf0.out_auto_wrback = enable; + dev->channel[channel].out.conf0.out_auto_wrback = enable; } /** @@ -391,8 +395,8 @@ static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t c */ static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel) { - dev->out[channel].conf0.out_rst = 1; - dev->out[channel].conf0.out_rst = 0; + dev->channel[channel].out.conf0.out_rst = 1; + dev->channel[channel].out.conf0.out_rst = 0; } /** @@ -401,7 +405,7 @@ static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel) */ static inline void gdma_ll_tx_set_block_size_psram(gdma_dev_t *dev, uint32_t channel, uint32_t size_index) { - dev->out[channel].conf1.out_ext_mem_bk_size = size_index; + dev->channel[channel].out.conf1.out_ext_mem_bk_size = size_index; } /** @@ -410,7 +414,7 @@ static inline void gdma_ll_tx_set_block_size_psram(gdma_dev_t *dev, uint32_t cha */ static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) { - return dev->out[channel].outfifo_status.val & (1 << 2 * (fifo_level - 1)); + return dev->channel[channel].out.outfifo_status.val & (1 << 2 * (fifo_level - 1)); } /** @@ -419,7 +423,7 @@ static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, ui */ static inline bool gdma_ll_tx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level) { - return dev->out[channel].outfifo_status.val & (1 << (2 * (fifo_level - 1) + 1)); + return dev->channel[channel].out.outfifo_status.val & (1 << (2 * (fifo_level - 1) + 1)); } /** @@ -430,11 +434,11 @@ static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t chann { switch (fifo_level) { case 1: - return dev->out[channel].outfifo_status.outfifo_cnt_l1; + return dev->channel[channel].out.outfifo_status.outfifo_cnt_l1; case 2: - return dev->out[channel].outfifo_status.outfifo_cnt_l2; + return dev->channel[channel].out.outfifo_status.outfifo_cnt_l2; case 3: - return dev->out[channel].outfifo_status.outfifo_cnt_l3; + return dev->channel[channel].out.outfifo_status.outfifo_cnt_l3; } } @@ -443,8 +447,8 @@ static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t chann */ static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint32_t data) { - dev->out[channel].push.outfifo_wdata = data; - dev->out[channel].push.outfifo_push = 1; + dev->channel[channel].out.push.outfifo_wdata = data; + dev->channel[channel].out.push.outfifo_push = 1; } /** @@ -452,7 +456,7 @@ static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint3 */ static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr) { - dev->out[channel].link.addr = addr; + dev->channel[channel].out.link.addr = addr; } /** @@ -460,7 +464,7 @@ static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, u */ static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel) { - dev->out[channel].link.start = 1; + dev->channel[channel].out.link.start = 1; } /** @@ -468,7 +472,7 @@ static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel) */ static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel) { - dev->out[channel].link.stop = 1; + dev->channel[channel].out.link.stop = 1; } /** @@ -476,7 +480,7 @@ static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel) */ static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel) { - dev->out[channel].link.restart = 1; + dev->channel[channel].out.link.restart = 1; } /** @@ -484,7 +488,7 @@ static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel) */ static inline bool gdma_ll_tx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel) { - return dev->out[channel].link.park; + return dev->channel[channel].out.link.park; } /** @@ -492,7 +496,7 @@ static inline bool gdma_ll_tx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel) */ static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t channel) { - return dev->out[channel].eof_des_addr; + return dev->channel[channel].out.eof_des_addr; } /** @@ -500,7 +504,7 @@ static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t ch */ static inline uint32_t gdma_ll_tx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel) { - return dev->out[channel].dscr; + return dev->channel[channel].out.dscr; } /** @@ -508,7 +512,7 @@ static inline uint32_t gdma_ll_tx_get_current_desc_addr(gdma_dev_t *dev, uint32_ */ static inline void gdma_ll_tx_set_weight(gdma_dev_t *dev, uint32_t channel, uint32_t weight) { - dev->out[channel].wight.tx_weight = weight; + dev->channel[channel].out.wight.tx_weight = weight; } /** @@ -516,7 +520,7 @@ static inline void gdma_ll_tx_set_weight(gdma_dev_t *dev, uint32_t channel, uint */ static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio) { - dev->out[channel].pri.tx_pri = prio; + dev->channel[channel].out.pri.tx_pri = prio; } /** @@ -524,7 +528,7 @@ static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, ui */ static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id) { - dev->out[channel].peri_sel.sel = periph_id; + dev->channel[channel].out.peri_sel.sel = periph_id; } /** @@ -535,7 +539,7 @@ static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channe static inline void gdma_ll_tx_extend_fifo_size_to(gdma_dev_t *dev, uint32_t channel, uint32_t size_in_bytes) { if (size_in_bytes > SOC_GDMA_L2_FIFO_BASE_SIZE) { - dev->out[channel].sram_size.out_size = (size_in_bytes - SOC_GDMA_L2_FIFO_BASE_SIZE) / 8; + dev->sram_size[channel].out.out_size = (size_in_bytes - SOC_GDMA_L2_FIFO_BASE_SIZE) / 8; } } diff --git a/components/mbedtls/port/crypto_shared_gdma/esp_crypto_shared_gdma.c b/components/mbedtls/port/crypto_shared_gdma/esp_crypto_shared_gdma.c index 118fee0a4f..fb209d72f5 100644 --- a/components/mbedtls/port/crypto_shared_gdma/esp_crypto_shared_gdma.c +++ b/components/mbedtls/port/crypto_shared_gdma/esp_crypto_shared_gdma.c @@ -67,8 +67,8 @@ static void esp_crypto_shared_dma_init_extmem(void) /* An L2 FIFO bigger than 40 bytes is need when accessing external ram */ gdma_ll_tx_extend_fifo_size_to(&GDMA, tx_ch_id, 40); gdma_ll_rx_extend_l2_fifo_size_to(&GDMA, rx_ch_id, 40); - gdma_ll_tx_set_block_size_psram(&GDMA, tx_ch_id, GDMA_OUT_EXT_MEM_BK_SIZE_16B); - gdma_ll_rx_set_block_size_psram(&GDMA, rx_ch_id, GDMA_OUT_EXT_MEM_BK_SIZE_16B); + gdma_ll_tx_set_block_size_psram(&GDMA, tx_ch_id, GDMA_LL_OUT_EXT_MEM_BK_SIZE_16B); + gdma_ll_rx_set_block_size_psram(&GDMA, rx_ch_id, GDMA_LL_OUT_EXT_MEM_BK_SIZE_16B); } #endif //SOC_GDMA_SUPPORT_EXTMEM diff --git a/components/soc/esp32s3/include/soc/gdma_reg.h b/components/soc/esp32s3/include/soc/gdma_reg.h index 99e74dc6e8..4172a6d1a0 100644 --- a/components/soc/esp32s3/include/soc/gdma_reg.h +++ b/components/soc/esp32s3/include/soc/gdma_reg.h @@ -544,7 +544,7 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_INLINK_DSCR_BF1_CH0_S 0 #define GDMA_IN_WIGHT_CH0_REG (DR_REG_GDMA_BASE + 0x3C) -/* GDMA_RX_WEIGHT_CH0 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/* GDMA_RX_WEIGHT_CH0 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Rx channel 0. .*/ #define GDMA_RX_WEIGHT_CH0 0x0000000F #define GDMA_RX_WEIGHT_CH0_M ((GDMA_RX_WEIGHT_CH0_V)<<(GDMA_RX_WEIGHT_CH0_S)) @@ -563,7 +563,7 @@ y..*/ #define GDMA_IN_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0x48) /* GDMA_PERI_IN_SEL_CH0 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ /*description: This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: - UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM. 7: AES. 8: SHA. 9: ADC_DAC..*/ + UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT..*/ #define GDMA_PERI_IN_SEL_CH0 0x0000003F #define GDMA_PERI_IN_SEL_CH0_M ((GDMA_PERI_IN_SEL_CH0_V)<<(GDMA_PERI_IN_SEL_CH0_S)) #define GDMA_PERI_IN_SEL_CH0_V 0x3F @@ -619,11 +619,6 @@ r has been transmitted..*/ #define GDMA_OUT_EXT_MEM_BK_SIZE_CH0_M ((GDMA_OUT_EXT_MEM_BK_SIZE_CH0_V)<<(GDMA_OUT_EXT_MEM_BK_SIZE_CH0_S)) #define GDMA_OUT_EXT_MEM_BK_SIZE_CH0_V 0x3 #define GDMA_OUT_EXT_MEM_BK_SIZE_CH0_S 13 - -/* Memory block size value supported by TX channel */ -#define GDMA_OUT_EXT_MEM_BK_SIZE_16B (0) -#define GDMA_OUT_EXT_MEM_BK_SIZE_32B (1) - /* GDMA_OUT_CHECK_OWNER_CH0 : R/W ;bitpos:[12] ;default: 1'b0 ; */ /*description: Set this bit to enable checking the owner attribute of the link descriptor..*/ #define GDMA_OUT_CHECK_OWNER_CH0 (BIT(12)) @@ -1032,7 +1027,7 @@ nk descriptor..*/ #define GDMA_OUTLINK_DSCR_BF1_CH0_S 0 #define GDMA_OUT_WIGHT_CH0_REG (DR_REG_GDMA_BASE + 0x9C) -/* GDMA_TX_WEIGHT_CH0 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/* GDMA_TX_WEIGHT_CH0 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Tx channel 0. .*/ #define GDMA_TX_WEIGHT_CH0 0x0000000F #define GDMA_TX_WEIGHT_CH0_M ((GDMA_TX_WEIGHT_CH0_V)<<(GDMA_TX_WEIGHT_CH0_S)) @@ -1051,7 +1046,8 @@ y..*/ #define GDMA_OUT_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0xA8) /* GDMA_PERI_OUT_SEL_CH0 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ /*description: This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: - UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC..*/ + UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT.; 7: AE +S. 8: SHA. 9: ADC_DAC..*/ #define GDMA_PERI_OUT_SEL_CH0 0x0000003F #define GDMA_PERI_OUT_SEL_CH0_M ((GDMA_PERI_OUT_SEL_CH0_V)<<(GDMA_PERI_OUT_SEL_CH0_S)) #define GDMA_PERI_OUT_SEL_CH0_V 0x3F @@ -1100,11 +1096,6 @@ scriptor when accessing internal SRAM. .*/ #define GDMA_IN_EXT_MEM_BK_SIZE_CH1_M ((GDMA_IN_EXT_MEM_BK_SIZE_CH1_V)<<(GDMA_IN_EXT_MEM_BK_SIZE_CH1_S)) #define GDMA_IN_EXT_MEM_BK_SIZE_CH1_V 0x3 #define GDMA_IN_EXT_MEM_BK_SIZE_CH1_S 13 - -/* Memory block size value supported by RX channel */ -#define GDMA_IN_EXT_MEM_BK_SIZE_16B (0) -#define GDMA_IN_EXT_MEM_BK_SIZE_32B (1) - /* GDMA_IN_CHECK_OWNER_CH1 : R/W ;bitpos:[12] ;default: 1'b0 ; */ /*description: Set this bit to enable checking the owner attribute of the link descriptor..*/ #define GDMA_IN_CHECK_OWNER_CH1 (BIT(12)) @@ -1586,7 +1577,7 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_INLINK_DSCR_BF1_CH1_S 0 #define GDMA_IN_WIGHT_CH1_REG (DR_REG_GDMA_BASE + 0xFC) -/* GDMA_RX_WEIGHT_CH1 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/* GDMA_RX_WEIGHT_CH1 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Rx channel 1. .*/ #define GDMA_RX_WEIGHT_CH1 0x0000000F #define GDMA_RX_WEIGHT_CH1_M ((GDMA_RX_WEIGHT_CH1_V)<<(GDMA_RX_WEIGHT_CH1_S)) @@ -1605,7 +1596,7 @@ y..*/ #define GDMA_IN_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x108) /* GDMA_PERI_IN_SEL_CH1 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ /*description: This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: SPI3. 2: - UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM. 7: AES. 8: SHA. 9: ADC_DAC..*/ + UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT..*/ #define GDMA_PERI_IN_SEL_CH1 0x0000003F #define GDMA_PERI_IN_SEL_CH1_M ((GDMA_PERI_IN_SEL_CH1_V)<<(GDMA_PERI_IN_SEL_CH1_S)) #define GDMA_PERI_IN_SEL_CH1_V 0x3F @@ -2069,7 +2060,7 @@ nk descriptor..*/ #define GDMA_OUTLINK_DSCR_BF1_CH1_S 0 #define GDMA_OUT_WIGHT_CH1_REG (DR_REG_GDMA_BASE + 0x15C) -/* GDMA_TX_WEIGHT_CH1 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/* GDMA_TX_WEIGHT_CH1 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Tx channel 1. .*/ #define GDMA_TX_WEIGHT_CH1 0x0000000F #define GDMA_TX_WEIGHT_CH1_M ((GDMA_TX_WEIGHT_CH1_V)<<(GDMA_TX_WEIGHT_CH1_S)) @@ -2088,7 +2079,8 @@ y..*/ #define GDMA_OUT_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x168) /* GDMA_PERI_OUT_SEL_CH1 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ /*description: This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: SPI3. 2: - UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC..*/ + UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT.; 7: AE +S. 8: SHA. 9: ADC_DAC..*/ #define GDMA_PERI_OUT_SEL_CH1 0x0000003F #define GDMA_PERI_OUT_SEL_CH1_M ((GDMA_PERI_OUT_SEL_CH1_V)<<(GDMA_PERI_OUT_SEL_CH1_S)) #define GDMA_PERI_OUT_SEL_CH1_V 0x3F @@ -2618,7 +2610,7 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_INLINK_DSCR_BF1_CH2_S 0 #define GDMA_IN_WIGHT_CH2_REG (DR_REG_GDMA_BASE + 0x1BC) -/* GDMA_RX_WEIGHT_CH2 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/* GDMA_RX_WEIGHT_CH2 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Rx channel 2. .*/ #define GDMA_RX_WEIGHT_CH2 0x0000000F #define GDMA_RX_WEIGHT_CH2_M ((GDMA_RX_WEIGHT_CH2_V)<<(GDMA_RX_WEIGHT_CH2_S)) @@ -2637,7 +2629,7 @@ y..*/ #define GDMA_IN_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x1C8) /* GDMA_PERI_IN_SEL_CH2 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ /*description: This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: SPI3. 2: - UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM. 7: AES. 8: SHA. 9: ADC_DAC..*/ + UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT..*/ #define GDMA_PERI_IN_SEL_CH2 0x0000003F #define GDMA_PERI_IN_SEL_CH2_M ((GDMA_PERI_IN_SEL_CH2_V)<<(GDMA_PERI_IN_SEL_CH2_S)) #define GDMA_PERI_IN_SEL_CH2_V 0x3F @@ -3101,7 +3093,7 @@ nk descriptor..*/ #define GDMA_OUTLINK_DSCR_BF1_CH2_S 0 #define GDMA_OUT_WIGHT_CH2_REG (DR_REG_GDMA_BASE + 0x21C) -/* GDMA_TX_WEIGHT_CH2 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/* GDMA_TX_WEIGHT_CH2 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Tx channel 2. .*/ #define GDMA_TX_WEIGHT_CH2 0x0000000F #define GDMA_TX_WEIGHT_CH2_M ((GDMA_TX_WEIGHT_CH2_V)<<(GDMA_TX_WEIGHT_CH2_S)) @@ -3120,7 +3112,8 @@ y..*/ #define GDMA_OUT_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x228) /* GDMA_PERI_OUT_SEL_CH2 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ /*description: This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: SPI3. 2: - UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC..*/ + UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT.; 7: AE +S. 8: SHA. 9: ADC_DAC..*/ #define GDMA_PERI_OUT_SEL_CH2 0x0000003F #define GDMA_PERI_OUT_SEL_CH2_M ((GDMA_PERI_OUT_SEL_CH2_V)<<(GDMA_PERI_OUT_SEL_CH2_S)) #define GDMA_PERI_OUT_SEL_CH2_V 0x3F @@ -3650,7 +3643,7 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_INLINK_DSCR_BF1_CH3_S 0 #define GDMA_IN_WIGHT_CH3_REG (DR_REG_GDMA_BASE + 0x27C) -/* GDMA_RX_WEIGHT_CH3 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/* GDMA_RX_WEIGHT_CH3 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Rx channel 3. .*/ #define GDMA_RX_WEIGHT_CH3 0x0000000F #define GDMA_RX_WEIGHT_CH3_M ((GDMA_RX_WEIGHT_CH3_V)<<(GDMA_RX_WEIGHT_CH3_S)) @@ -3669,7 +3662,7 @@ y..*/ #define GDMA_IN_PERI_SEL_CH3_REG (DR_REG_GDMA_BASE + 0x288) /* GDMA_PERI_IN_SEL_CH3 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ /*description: This register is used to select peripheral for Rx channel 3. 0:SPI2. 1: SPI3. 2: - UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM. 7: AES. 8: SHA. 9: ADC_DAC..*/ + UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT..*/ #define GDMA_PERI_IN_SEL_CH3 0x0000003F #define GDMA_PERI_IN_SEL_CH3_M ((GDMA_PERI_IN_SEL_CH3_V)<<(GDMA_PERI_IN_SEL_CH3_S)) #define GDMA_PERI_IN_SEL_CH3_V 0x3F @@ -4133,7 +4126,7 @@ nk descriptor..*/ #define GDMA_OUTLINK_DSCR_BF1_CH3_S 0 #define GDMA_OUT_WIGHT_CH3_REG (DR_REG_GDMA_BASE + 0x2DC) -/* GDMA_TX_WEIGHT_CH3 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/* GDMA_TX_WEIGHT_CH3 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Tx channel 3. .*/ #define GDMA_TX_WEIGHT_CH3 0x0000000F #define GDMA_TX_WEIGHT_CH3_M ((GDMA_TX_WEIGHT_CH3_V)<<(GDMA_TX_WEIGHT_CH3_S)) @@ -4152,7 +4145,8 @@ y..*/ #define GDMA_OUT_PERI_SEL_CH3_REG (DR_REG_GDMA_BASE + 0x2E8) /* GDMA_PERI_OUT_SEL_CH3 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ /*description: This register is used to select peripheral for Tx channel 3. 0:SPI2. 1: SPI3. 2: - UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC..*/ + UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT.; 7: AE +S. 8: SHA. 9: ADC_DAC..*/ #define GDMA_PERI_OUT_SEL_CH3 0x0000003F #define GDMA_PERI_OUT_SEL_CH3_M ((GDMA_PERI_OUT_SEL_CH3_V)<<(GDMA_PERI_OUT_SEL_CH3_S)) #define GDMA_PERI_OUT_SEL_CH3_V 0x3F @@ -4682,7 +4676,7 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_INLINK_DSCR_BF1_CH4_S 0 #define GDMA_IN_WIGHT_CH4_REG (DR_REG_GDMA_BASE + 0x33C) -/* GDMA_RX_WEIGHT_CH4 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/* GDMA_RX_WEIGHT_CH4 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Rx channel 4. .*/ #define GDMA_RX_WEIGHT_CH4 0x0000000F #define GDMA_RX_WEIGHT_CH4_M ((GDMA_RX_WEIGHT_CH4_V)<<(GDMA_RX_WEIGHT_CH4_S)) @@ -4701,7 +4695,7 @@ y..*/ #define GDMA_IN_PERI_SEL_CH4_REG (DR_REG_GDMA_BASE + 0x348) /* GDMA_PERI_IN_SEL_CH4 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ /*description: This register is used to select peripheral for Rx channel 5. 0:SPI2. 1: SPI3. 2: - UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM. 7: AES. 8: SHA. 9: ADC_DAC..*/ + UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT..*/ #define GDMA_PERI_IN_SEL_CH4 0x0000003F #define GDMA_PERI_IN_SEL_CH4_M ((GDMA_PERI_IN_SEL_CH4_V)<<(GDMA_PERI_IN_SEL_CH4_S)) #define GDMA_PERI_IN_SEL_CH4_V 0x3F @@ -5165,7 +5159,7 @@ nk descriptor..*/ #define GDMA_OUTLINK_DSCR_BF1_CH4_S 0 #define GDMA_OUT_WIGHT_CH4_REG (DR_REG_GDMA_BASE + 0x39C) -/* GDMA_TX_WEIGHT_CH4 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/* GDMA_TX_WEIGHT_CH4 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Tx channel 4. .*/ #define GDMA_TX_WEIGHT_CH4 0x0000000F #define GDMA_TX_WEIGHT_CH4_M ((GDMA_TX_WEIGHT_CH4_V)<<(GDMA_TX_WEIGHT_CH4_S)) @@ -5184,7 +5178,8 @@ y..*/ #define GDMA_OUT_PERI_SEL_CH4_REG (DR_REG_GDMA_BASE + 0x3A8) /* GDMA_PERI_OUT_SEL_CH4 : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ /*description: This register is used to select peripheral for Tx channel 4. 0:SPI2. 1: SPI3. 2: - UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC..*/ + UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT.; 7: AE +S. 8: SHA. 9: ADC_DAC..*/ #define GDMA_PERI_OUT_SEL_CH4 0x0000003F #define GDMA_PERI_OUT_SEL_CH4_M ((GDMA_PERI_OUT_SEL_CH4_V)<<(GDMA_PERI_OUT_SEL_CH4_S)) #define GDMA_PERI_OUT_SEL_CH4_V 0x3F @@ -5374,7 +5369,8 @@ ing external RAM..*/ #define GDMA_EXTMEM_REJECT_CHANNEL_NUM_V 0xF #define GDMA_EXTMEM_REJECT_CHANNEL_NUM_S 2 /* GDMA_EXTMEM_REJECT_ATTR : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: The reject operation. Bit 0 is 1 indicate write data.*/ +/*description: The reject accessing. Bit 0: if this bit is 1, the rejected accessing is READ. B +it 1: if this bit is 1, the rejected accessing is WRITE..*/ #define GDMA_EXTMEM_REJECT_ATTR 0x00000003 #define GDMA_EXTMEM_REJECT_ATTR_M ((GDMA_EXTMEM_REJECT_ATTR_V)<<(GDMA_EXTMEM_REJECT_ATTR_S)) #define GDMA_EXTMEM_REJECT_ATTR_V 0x3 @@ -5414,7 +5410,7 @@ d by permission control..*/ #define GDMA_EXTMEM_REJECT_INT_CLR_S 0 #define GDMA_DATE_REG (DR_REG_GDMA_BASE + 0x40C) -/* GDMA_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101080 ; */ +/* GDMA_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101180 ; */ /*description: register version..*/ #define GDMA_DATE 0xFFFFFFFF #define GDMA_DATE_M ((GDMA_DATE_V)<<(GDMA_DATE_S)) diff --git a/components/soc/esp32s3/include/soc/gdma_struct.h b/components/soc/esp32s3/include/soc/gdma_struct.h index 9c6582ce0a..6663d16b78 100644 --- a/components/soc/esp32s3/include/soc/gdma_struct.h +++ b/components/soc/esp32s3/include/soc/gdma_struct.h @@ -11,353 +11,347 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#pragma once - -#include +#ifndef _SOC_GDMA_STRUCT_H_ +#define _SOC_GDMA_STRUCT_H_ #ifdef __cplusplus extern "C" { #endif +#include "soc.h" typedef volatile struct { struct { - union { - struct { - uint32_t in_rst : 1; /*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/ - uint32_t in_loop_test : 1; /*reserved*/ - uint32_t indscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. */ - uint32_t in_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. */ - uint32_t mem_trans_en : 1; /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/ - uint32_t reserved5 : 27; /*reserved*/ - }; - uint32_t val; - } conf0; - union { - struct { - uint32_t dma_infifo_full_thrs : 12; /*This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register.*/ - uint32_t in_check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/ - uint32_t in_ext_mem_bk_size : 2; /*Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/ - uint32_t reserved15 : 17; /*reserved*/ - }; - uint32_t val; - } conf1; - union { - struct { - uint32_t in_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/ - uint32_t in_suc_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/ - uint32_t in_err_eof : 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.*/ - uint32_t in_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.*/ - uint32_t in_dscr_empty : 1; /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.*/ - uint32_t infifo_full_wm : 1; /*The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0.*/ - uint32_t infifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. */ - uint32_t infifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. */ - uint32_t infifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow. */ - uint32_t infifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow. */ - uint32_t reserved10 : 22; /*reserved*/ - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t in_done : 1; /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ - uint32_t in_suc_eof : 1; /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ - uint32_t in_err_eof : 1; /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ - uint32_t in_dscr_err : 1; /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ - uint32_t in_dscr_empty : 1; /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ - uint32_t infifo_full_wm : 1; /*The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ - uint32_t infifo_ovf_l1 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ - uint32_t infifo_udf_l1 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ - uint32_t infifo_ovf_l3 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ - uint32_t infifo_udf_l3 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ - uint32_t reserved10 : 22; /*reserved*/ - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t in_done : 1; /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ - uint32_t in_suc_eof : 1; /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ - uint32_t in_err_eof : 1; /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ - uint32_t in_dscr_err : 1; /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ - uint32_t in_dscr_empty : 1; /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ - uint32_t infifo_full_wm : 1; /*The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ - uint32_t infifo_ovf_l1 : 1; /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ - uint32_t infifo_udf_l1 : 1; /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ - uint32_t infifo_ovf_l3 : 1; /*The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ - uint32_t infifo_udf_l3 : 1; /*The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ - uint32_t reserved10 : 22; /*reserved*/ - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t in_done : 1; /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/ - uint32_t in_suc_eof : 1; /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ - uint32_t in_err_eof : 1; /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ - uint32_t in_dscr_err : 1; /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ - uint32_t in_dscr_empty : 1; /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ - uint32_t dma_infifo_full_wm : 1; /*Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/ - uint32_t infifo_ovf_l1 : 1; /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ - uint32_t infifo_udf_l1 : 1; /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ - uint32_t infifo_ovf_l3 : 1; /*Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/ - uint32_t infifo_udf_l3 : 1; /*Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/ - uint32_t reserved10 : 22; /*reserved*/ - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t infifo_full_l1 : 1; /*L1 Rx FIFO full signal for Rx channel 0.*/ - uint32_t infifo_empty_l1 : 1; /*L1 Rx FIFO empty signal for Rx channel 0.*/ - uint32_t infifo_full_l2 : 1; /*L2 Rx FIFO full signal for Rx channel 0.*/ - uint32_t infifo_empty_l2 : 1; /*L2 Rx FIFO empty signal for Rx channel 0.*/ - uint32_t infifo_full_l3 : 1; /*L3 Rx FIFO full signal for Rx channel 0.*/ - uint32_t infifo_empty_l3 : 1; /*L3 Rx FIFO empty signal for Rx channel 0.*/ - uint32_t infifo_cnt_l1 : 5; /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/ - uint32_t infifo_cnt_l2 : 7; /*The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.*/ - uint32_t infifo_cnt_l3 : 5; /*The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.*/ - uint32_t in_remain_under_1b_l3 : 1; /*reserved*/ - uint32_t in_remain_under_2b_l3 : 1; /*reserved*/ - uint32_t in_remain_under_3b_l3 : 1; /*reserved*/ - uint32_t in_remain_under_4b_l3 : 1; /*reserved*/ - uint32_t in_buf_hungry : 1; /*reserved*/ - uint32_t reserved28 : 4; /*reserved*/ - }; - uint32_t val; - } infifo_status; - union { - struct { - uint32_t infifo_rdata : 12; /*This register stores the data popping from DMA FIFO.*/ - uint32_t infifo_pop : 1; /*Set this bit to pop data from DMA FIFO.*/ - uint32_t reserved13 : 19; /*reserved*/ - }; - uint32_t val; - } pop; - union { - struct { - uint32_t addr : 20; /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/ - uint32_t auto_ret : 1; /*Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.*/ - uint32_t stop : 1; /*Set this bit to stop dealing with the inlink descriptors.*/ - uint32_t start : 1; /*Set this bit to start dealing with the inlink descriptors.*/ - uint32_t restart : 1; /*Set this bit to mount a new inlink descriptor.*/ - uint32_t park : 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/ - uint32_t reserved25 : 7; - }; - uint32_t val; - } link; - union { - struct { - uint32_t dscr_addr : 18; /*This register stores the current inlink descriptor's address.*/ - uint32_t in_dscr_state : 2; /*reserved*/ - uint32_t in_state : 3; /*reserved*/ - uint32_t reserved23 : 9; /*reserved*/ - }; - uint32_t val; - } state; - uint32_t suc_eof_des_addr; - uint32_t err_eof_des_addr; - uint32_t dscr; - uint32_t dscr_bf0; - uint32_t dscr_bf1; - union { - struct { - uint32_t rx_weight : 4; /*The weight of Rx channel 0. */ - uint32_t reserved4 : 28; - }; - uint32_t val; - } wight; - union { - struct { - uint32_t in_size : 5; /*This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes.*/ - uint32_t reserved5 : 27; - }; - uint32_t val; - } sram_size; - union { - struct { - uint32_t rx_pri : 4; /*The priority of Rx channel 0. The larger of the value, the higher of the priority.*/ - uint32_t reserved4 : 28; - }; - uint32_t val; - } pri; - union { - struct { - uint32_t sel : 6; /*This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC.*/ - uint32_t reserved6 : 26; - }; - uint32_t val; - } peri_sel; - uint32_t reserved_4c; - uint32_t reserved_50; - uint32_t reserved_54; - uint32_t reserved_58; - uint32_t reserved_5c; - } in[5]; - struct { - union { - struct { - uint32_t out_rst : 1; /*This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/ - uint32_t out_loop_test : 1; /*reserved*/ - uint32_t out_auto_wrback : 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/ - uint32_t out_eof_mode : 1; /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/ - uint32_t outdscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. */ - uint32_t out_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. */ - uint32_t reserved6 : 26; - }; - uint32_t val; - } conf0; - union { - struct { - uint32_t reserved0 : 12; - uint32_t out_check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/ - uint32_t out_ext_mem_bk_size : 2; /*Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/ - uint32_t reserved15 : 17; /*reserved*/ - }; - uint32_t val; - } conf1; - union { - struct { - uint32_t out_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/ - uint32_t out_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. */ - uint32_t out_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.*/ - uint32_t out_total_eof : 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/ - uint32_t outfifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. */ - uint32_t outfifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. */ - uint32_t outfifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow. */ - uint32_t outfifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow. */ - uint32_t reserved8 : 24; /*reserved*/ - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t out_done : 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ - uint32_t out_eof : 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ - uint32_t out_dscr_err : 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ - uint32_t out_total_eof : 1; /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ - uint32_t outfifo_ovf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ - uint32_t outfifo_udf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ - uint32_t outfifo_ovf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ - uint32_t outfifo_udf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ - uint32_t reserved8 : 24; /*reserved*/ - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t out_done : 1; /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ - uint32_t out_eof : 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ - uint32_t out_dscr_err : 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ - uint32_t out_total_eof : 1; /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ - uint32_t outfifo_ovf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ - uint32_t outfifo_udf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ - uint32_t outfifo_ovf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ - uint32_t outfifo_udf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ - uint32_t reserved8 : 24; /*reserved*/ - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t out_done : 1; /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ - uint32_t out_eof : 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ - uint32_t out_dscr_err : 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ - uint32_t out_total_eof : 1; /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ - uint32_t outfifo_ovf_l1 : 1; /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ - uint32_t outfifo_udf_l1 : 1; /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ - uint32_t outfifo_ovf_l3 : 1; /*Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/ - uint32_t outfifo_udf_l3 : 1; /*Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/ - uint32_t reserved8 : 24; /*reserved*/ - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t outfifo_full_l1 : 1; /*L1 Tx FIFO full signal for Tx channel 0.*/ - uint32_t outfifo_empty_l1 : 1; /*L1 Tx FIFO empty signal for Tx channel 0.*/ - uint32_t outfifo_full_l2 : 1; /*L2 Tx FIFO full signal for Tx channel 0.*/ - uint32_t outfifo_empty_l2 : 1; /*L2 Tx FIFO empty signal for Tx channel 0.*/ - uint32_t outfifo_full_l3 : 1; /*L3 Tx FIFO full signal for Tx channel 0.*/ - uint32_t outfifo_empty_l3 : 1; /*L3 Tx FIFO empty signal for Tx channel 0.*/ - uint32_t outfifo_cnt_l1 : 5; /*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/ - uint32_t outfifo_cnt_l2 : 7; /*The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.*/ - uint32_t outfifo_cnt_l3 : 5; /*The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0.*/ - uint32_t out_remain_under_1b_l3 : 1; /*reserved*/ - uint32_t out_remain_under_2b_l3 : 1; /*reserved*/ - uint32_t out_remain_under_3b_l3 : 1; /*reserved*/ - uint32_t out_remain_under_4b_l3 : 1; /*reserved*/ - uint32_t reserved27 : 5; /*reserved*/ - }; - uint32_t val; - } outfifo_status; - union { - struct { - uint32_t outfifo_wdata : 9; /*This register stores the data that need to be pushed into DMA FIFO.*/ - uint32_t outfifo_push : 1; /*Set this bit to push data into DMA FIFO.*/ - uint32_t reserved10 : 22; /*reserved*/ - }; - uint32_t val; - } push; - union { - struct { - uint32_t addr : 20; /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/ - uint32_t stop : 1; /*Set this bit to stop dealing with the outlink descriptors.*/ - uint32_t start : 1; /*Set this bit to start dealing with the outlink descriptors.*/ - uint32_t restart : 1; /*Set this bit to restart a new outlink from the last address. */ - uint32_t park : 1; /*1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.*/ - uint32_t reserved24 : 8; - }; - uint32_t val; - } link; - union { - struct { - uint32_t dscr_addr : 18; /*This register stores the current outlink descriptor's address.*/ - uint32_t out_dscr_state : 2; /*reserved*/ - uint32_t out_state : 3; /*reserved*/ - uint32_t reserved23 : 9; /*reserved*/ - }; - uint32_t val; - } state; - uint32_t eof_des_addr; - uint32_t eof_bfr_des_addr; - uint32_t dscr; - uint32_t dscr_bf0; - uint32_t dscr_bf1; - union { - struct { - uint32_t tx_weight : 4; /*The weight of Tx channel 0. */ - uint32_t reserved4 : 28; - }; - uint32_t val; - } wight; - union { - struct { - uint32_t out_size : 5; /*This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes.*/ - uint32_t reserved5 : 27; - }; - uint32_t val; - } sram_size; - union { - struct { - uint32_t tx_pri : 4; /*The priority of Tx channel 0. The larger of the value, the higher of the priority.*/ - uint32_t reserved4 : 28; - }; - uint32_t val; - } pri; - union { - struct { - uint32_t sel : 6; /*This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC.*/ - uint32_t reserved6 : 26; - }; - uint32_t val; - } peri_sel; - uint32_t reserved_22c; - uint32_t reserved_230; - uint32_t reserved_234; - uint32_t reserved_238; - uint32_t reserved_23c; - } out[5]; + struct { + union { + struct { + uint32_t in_rst : 1; /*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/ + uint32_t in_loop_test : 1; /*reserved*/ + uint32_t indscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. */ + uint32_t in_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. */ + uint32_t mem_trans_en : 1; /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/ + uint32_t reserved5 : 1; /*reserved*/ + uint32_t reserved6 : 26; /*reserved*/ + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t dma_infifo_full_thrs : 12; /*This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register.*/ + uint32_t in_check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/ + uint32_t in_ext_mem_bk_size : 2; /*Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/ + uint32_t reserved15 : 17; /*reserved*/ + }; + uint32_t val; + } conf1; + union { + struct { + uint32_t in_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/ + uint32_t in_suc_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/ + uint32_t in_err_eof : 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.*/ + uint32_t in_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.*/ + uint32_t in_dscr_empty : 1; /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.*/ + uint32_t infifo_full_wm : 1; /*The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0.*/ + uint32_t infifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. */ + uint32_t infifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. */ + uint32_t infifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow. */ + uint32_t infifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow. */ + uint32_t reserved10 : 22; /*reserved*/ + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t in_done : 1; /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof : 1; /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof : 1; /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err : 1; /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty : 1; /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t infifo_full_wm : 1; /*The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ + uint32_t infifo_ovf_l1 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf_l1 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t infifo_ovf_l3 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t infifo_udf_l3 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved10 : 22; /*reserved*/ + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t in_done : 1; /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof : 1; /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof : 1; /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err : 1; /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty : 1; /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t infifo_full_wm : 1; /*The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ + uint32_t infifo_ovf_l1 : 1; /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf_l1 : 1; /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t infifo_ovf_l3 : 1; /*The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t infifo_udf_l3 : 1; /*The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved10 : 22; /*reserved*/ + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t in_done : 1; /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof : 1; /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof : 1; /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err : 1; /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty : 1; /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t dma_infifo_full_wm : 1; /*Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/ + uint32_t infifo_ovf_l1 : 1; /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf_l1 : 1; /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t infifo_ovf_l3 : 1; /*Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t infifo_udf_l3 : 1; /*Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved10 : 22; /*reserved*/ + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t infifo_full_l1 : 1; /*L1 Rx FIFO full signal for Rx channel 0.*/ + uint32_t infifo_empty_l1 : 1; /*L1 Rx FIFO empty signal for Rx channel 0.*/ + uint32_t infifo_full_l2 : 1; /*L2 Rx FIFO full signal for Rx channel 0.*/ + uint32_t infifo_empty_l2 : 1; /*L2 Rx FIFO empty signal for Rx channel 0.*/ + uint32_t infifo_full_l3 : 1; /*L3 Rx FIFO full signal for Rx channel 0.*/ + uint32_t infifo_empty_l3 : 1; /*L3 Rx FIFO empty signal for Rx channel 0.*/ + uint32_t infifo_cnt_l1 : 6; /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/ + uint32_t infifo_cnt_l2 : 7; /*The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.*/ + uint32_t infifo_cnt_l3 : 5; /*The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.*/ + uint32_t in_remain_under_1b_l3 : 1; /*reserved*/ + uint32_t in_remain_under_2b_l3 : 1; /*reserved*/ + uint32_t in_remain_under_3b_l3 : 1; /*reserved*/ + uint32_t in_remain_under_4b_l3 : 1; /*reserved*/ + uint32_t in_buf_hungry : 1; /*reserved*/ + uint32_t reserved29 : 3; /*reserved*/ + }; + uint32_t val; + } infifo_status; + union { + struct { + uint32_t infifo_rdata : 12; /*This register stores the data popping from DMA FIFO.*/ + uint32_t infifo_pop : 1; /*Set this bit to pop data from DMA FIFO.*/ + uint32_t reserved13 : 19; /*reserved*/ + }; + uint32_t val; + } pop; + union { + struct { + uint32_t addr : 20; /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/ + uint32_t auto_ret : 1; /*Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.*/ + uint32_t stop : 1; /*Set this bit to stop dealing with the inlink descriptors.*/ + uint32_t start : 1; /*Set this bit to start dealing with the inlink descriptors.*/ + uint32_t restart : 1; /*Set this bit to mount a new inlink descriptor.*/ + uint32_t park : 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/ + uint32_t reserved25 : 7; + }; + uint32_t val; + } link; + union { + struct { + uint32_t dscr_addr : 18; /*This register stores the current inlink descriptor's address.*/ + uint32_t in_dscr_state : 2; /*reserved*/ + uint32_t in_state : 3; /*reserved*/ + uint32_t reserved23 : 9; /*reserved*/ + }; + uint32_t val; + } state; + uint32_t suc_eof_des_addr; + uint32_t err_eof_des_addr; + uint32_t dscr; + uint32_t dscr_bf0; + uint32_t dscr_bf1; + union { + struct { + uint32_t reserved0 : 8; + uint32_t rx_weight : 4; /*The weight of Rx channel 0. */ + uint32_t reserved12 : 20; + }; + uint32_t val; + } wight; + uint32_t reserved_40; + union { + struct { + uint32_t rx_pri : 4; /*The priority of Rx channel 0. The larger of the value, the higher of the priority.*/ + uint32_t reserved4 : 28; + }; + uint32_t val; + } pri; + union { + struct { + uint32_t sel : 6; /*This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT.*/ + uint32_t reserved6 : 26; + }; + uint32_t val; + } peri_sel; + uint32_t reserved_4c; + uint32_t reserved_50; + uint32_t reserved_54; + uint32_t reserved_58; + uint32_t reserved_5c; + } in; + struct { + union { + struct { + uint32_t out_rst : 1; /*This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/ + uint32_t out_loop_test : 1; /*reserved*/ + uint32_t out_auto_wrback : 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/ + uint32_t out_eof_mode : 1; /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/ + uint32_t outdscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. */ + uint32_t out_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. */ + uint32_t reserved6 : 1; + uint32_t reserved7 : 25; + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t reserved0 : 12; + uint32_t out_check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/ + uint32_t out_ext_mem_bk_size : 2; /*Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/ + uint32_t reserved15 : 17; /*reserved*/ + }; + uint32_t val; + } conf1; + union { + struct { + uint32_t out_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/ + uint32_t out_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. */ + uint32_t out_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.*/ + uint32_t out_total_eof : 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/ + uint32_t outfifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. */ + uint32_t outfifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. */ + uint32_t outfifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow. */ + uint32_t outfifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow. */ + uint32_t reserved8 : 24; /*reserved*/ + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t out_done : 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof : 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ + uint32_t out_dscr_err : 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_total_eof : 1; /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t outfifo_udf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved8 : 24; /*reserved*/ + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t out_done : 1; /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof : 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ + uint32_t out_dscr_err : 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_total_eof : 1; /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t outfifo_udf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved8 : 24; /*reserved*/ + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t out_done : 1; /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof : 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ + uint32_t out_dscr_err : 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_total_eof : 1; /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l1 : 1; /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf_l1 : 1; /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l3 : 1; /*Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t outfifo_udf_l3 : 1; /*Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved8 : 24; /*reserved*/ + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t outfifo_full_l1 : 1; /*L1 Tx FIFO full signal for Tx channel 0.*/ + uint32_t outfifo_empty_l1 : 1; /*L1 Tx FIFO empty signal for Tx channel 0.*/ + uint32_t outfifo_full_l2 : 1; /*L2 Tx FIFO full signal for Tx channel 0.*/ + uint32_t outfifo_empty_l2 : 1; /*L2 Tx FIFO empty signal for Tx channel 0.*/ + uint32_t outfifo_full_l3 : 1; /*L3 Tx FIFO full signal for Tx channel 0.*/ + uint32_t outfifo_empty_l3 : 1; /*L3 Tx FIFO empty signal for Tx channel 0.*/ + uint32_t outfifo_cnt_l1 : 5; /*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/ + uint32_t outfifo_cnt_l2 : 7; /*The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.*/ + uint32_t outfifo_cnt_l3 : 5; /*The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0.*/ + uint32_t out_remain_under_1b_l3 : 1; /*reserved*/ + uint32_t out_remain_under_2b_l3 : 1; /*reserved*/ + uint32_t out_remain_under_3b_l3 : 1; /*reserved*/ + uint32_t out_remain_under_4b_l3 : 1; /*reserved*/ + uint32_t reserved27 : 5; /*reserved*/ + }; + uint32_t val; + } outfifo_status; + union { + struct { + uint32_t outfifo_wdata : 9; /*This register stores the data that need to be pushed into DMA FIFO.*/ + uint32_t outfifo_push : 1; /*Set this bit to push data into DMA FIFO.*/ + uint32_t reserved10 : 22; /*reserved*/ + }; + uint32_t val; + } push; + union { + struct { + uint32_t addr : 20; /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/ + uint32_t stop : 1; /*Set this bit to stop dealing with the outlink descriptors.*/ + uint32_t start : 1; /*Set this bit to start dealing with the outlink descriptors.*/ + uint32_t restart : 1; /*Set this bit to restart a new outlink from the last address. */ + uint32_t park : 1; /*1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.*/ + uint32_t reserved24 : 8; + }; + uint32_t val; + } link; + union { + struct { + uint32_t dscr_addr : 18; /*This register stores the current outlink descriptor's address.*/ + uint32_t out_dscr_state : 2; /*reserved*/ + uint32_t out_state : 3; /*reserved*/ + uint32_t reserved23 : 9; /*reserved*/ + }; + uint32_t val; + } state; + uint32_t eof_des_addr; + uint32_t eof_bfr_des_addr; + uint32_t dscr; + uint32_t dscr_bf0; + uint32_t dscr_bf1; + union { + struct { + uint32_t reserved0 : 8; + uint32_t tx_weight : 4; /*The weight of Tx channel 0. */ + uint32_t reserved12 : 20; + }; + uint32_t val; + } wight; + uint32_t reserved_a0; + union { + struct { + uint32_t tx_pri : 4; /*The priority of Tx channel 0. The larger of the value, the higher of the priority.*/ + uint32_t reserved4 : 28; + }; + uint32_t val; + } pri; + union { + struct { + uint32_t sel : 6; /*This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT.; 7: AES. 8: SHA. 9: ADC_DAC.*/ + uint32_t reserved6 : 26; + }; + uint32_t val; + } peri_sel; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + } out; + } channel[5]; union { struct { uint32_t ahb_testmode : 3; /*reserved*/ @@ -382,14 +376,73 @@ typedef volatile struct { uint32_t ahbm_rst_inter : 1; /*Set this bit, then clear this bit to reset the internal ahb FSM.*/ uint32_t ahbm_rst_exter : 1; /*Set this bit, then clear this bit to reset the external ahb FSM.*/ uint32_t arb_pri_dis : 1; /*Set this bit to disable priority arbitration function.*/ + uint32_t reserved3 : 1; uint32_t clk_en : 1; - uint32_t reserved4 : 28; + uint32_t reserved5 : 27; }; uint32_t val; } misc_conf; + struct { + union { + struct { + uint32_t in_size : 7; /*This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes.*/ + uint32_t reserved7 : 25; + }; + uint32_t val; + } in; + union { + struct { + uint32_t out_size : 7; /*This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes.*/ + uint32_t reserved7 : 25; + }; + uint32_t val; + } out; + } sram_size[5]; + uint32_t extmem_reject_addr; + union { + struct { + uint32_t extmem_reject_attr : 2; /*The reject accessing. Bit 0: if this bit is 1, the rejected accessing is READ. Bit 1: if this bit is 1, the rejected accessing is WRITE.*/ + uint32_t extmem_reject_channel_num : 4; /*The register indicate the reject accessing from which channel.*/ + uint32_t extmem_reject_peri_num : 6; /*This register indicate reject accessing from which peripheral.*/ + uint32_t reserved12 : 20; + }; + uint32_t val; + } extmem_reject_st; + union { + struct { + uint32_t extmem_reject : 1; /*The raw interrupt bit turns to high level when accessing external RAM is rejected by permission control.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } extmem_reject_int_raw; + union { + struct { + uint32_t extmem_reject : 1; /*The raw interrupt status bit for the EXTMEM_REJECT_INT interrupt.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } extmem_reject_int_st; + union { + struct { + uint32_t extmem_reject : 1; /*The interrupt enable bit for the EXTMEM_REJECT_INT interrupt.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } extmem_reject_int_ena; + union { + struct { + uint32_t extmem_reject : 1; /*Set this bit to clear the EXTMEM_REJECT_INT interrupt.*/ + uint32_t reserved1 : 31; /*reserved*/ + }; + uint32_t val; + } extmem_reject_int_clr; uint32_t date; } gdma_dev_t; extern gdma_dev_t GDMA; #ifdef __cplusplus } #endif + + + +#endif /*_SOC_GDMA_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h b/components/soc/esp32s3/include/soc/rtc_cntl_reg.h index f6f46572bd..583aeafa8f 100644 --- a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32s3/include/soc/rtc_cntl_reg.h @@ -14,6 +14,7 @@ #ifndef _SOC_RTC_CNTL_REG_H_ #define _SOC_RTC_CNTL_REG_H_ + #ifdef __cplusplus extern "C" { #endif @@ -36,1581 +37,1605 @@ extern "C" { #define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG #define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG -#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0000) +#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) /* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ -/*description: SW system reset*/ -#define RTC_CNTL_SW_SYS_RST (BIT(31)) +/*description: SW system reset.*/ +#define RTC_CNTL_SW_SYS_RST (BIT(31)) #define RTC_CNTL_SW_SYS_RST_M (BIT(31)) #define RTC_CNTL_SW_SYS_RST_V 0x1 #define RTC_CNTL_SW_SYS_RST_S 31 /* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: digital core force no reset in deep sleep*/ -#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) +/*description: digital core force no reset in deep sleep.*/ +#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) #define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) #define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 #define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 /* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: digital wrap force reset in deep sleep*/ -#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) +/*description: digital wrap force reset in deep sleep.*/ +#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) #define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) #define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 #define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 /* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ -/*description: */ -#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) +/*description: .*/ +#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) #define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) #define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 #define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 /* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ -/*description: */ -#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) +/*description: .*/ +#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) #define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) #define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 #define RTC_CNTL_PLL_FORCE_NOISO_S 27 /* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ -/*description: */ -#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) +/*description: .*/ +#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) #define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) #define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 #define RTC_CNTL_XTL_FORCE_NOISO_S 26 /* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) +/*description: .*/ +#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) #define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) #define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 #define RTC_CNTL_ANALOG_FORCE_ISO_S 25 /* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) +/*description: .*/ +#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) #define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) #define RTC_CNTL_PLL_FORCE_ISO_V 0x1 #define RTC_CNTL_PLL_FORCE_ISO_S 24 /* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) +/*description: .*/ +#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) #define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) #define RTC_CNTL_XTL_FORCE_ISO_V 0x1 #define RTC_CNTL_XTL_FORCE_ISO_S 23 /* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */ -/*description: wait bias_sleep and current source wakeup*/ -#define RTC_CNTL_XTL_EN_WAIT 0x0000000F +/*description: wait bias_sleep and current source wakeup.*/ +#define RTC_CNTL_XTL_EN_WAIT 0x0000000F #define RTC_CNTL_XTL_EN_WAIT_M ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S)) #define RTC_CNTL_XTL_EN_WAIT_V 0xF #define RTC_CNTL_XTL_EN_WAIT_S 14 /* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ -/*description: crystall force power up*/ -#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) +/*description: crystall force power up.*/ +#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) #define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) #define RTC_CNTL_XTL_FORCE_PU_V 0x1 #define RTC_CNTL_XTL_FORCE_PU_S 13 /* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: crystall force power down*/ -#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) +/*description: crystall force power down.*/ +#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) #define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) #define RTC_CNTL_XTL_FORCE_PD_V 0x1 #define RTC_CNTL_XTL_FORCE_PD_S 12 /* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: BB_PLL force power up*/ -#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) +/*description: BB_PLL force power up.*/ +#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) #define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) #define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 #define RTC_CNTL_BBPLL_FORCE_PU_S 11 /* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: BB_PLL force power down*/ -#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) +/*description: BB_PLL force power down.*/ +#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) #define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) #define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 #define RTC_CNTL_BBPLL_FORCE_PD_S 10 /* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: BB_PLL_I2C force power up*/ -#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) +/*description: BB_PLL_I2C force power up.*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) #define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) #define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 /* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: BB_PLL _I2C force power down*/ -#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) +/*description: BB_PLL _I2C force power down.*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) #define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) #define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 /* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: BB_I2C force power up*/ -#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) +/*description: BB_I2C force power up.*/ +#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) #define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) #define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 #define RTC_CNTL_BB_I2C_FORCE_PU_S 7 /* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: BB_I2C force power down*/ -#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) +/*description: BB_I2C force power down.*/ +#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) #define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) #define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 #define RTC_CNTL_BB_I2C_FORCE_PD_S 6 /* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: PRO CPU SW reset*/ -#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) +/*description: PRO CPU SW reset.*/ +#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) #define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) #define RTC_CNTL_SW_PROCPU_RST_V 0x1 #define RTC_CNTL_SW_PROCPU_RST_S 5 /* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: APP CPU SW reset*/ -#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) +/*description: APP CPU SW reset.*/ +#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) #define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) #define RTC_CNTL_SW_APPCPU_RST_V 0x1 #define RTC_CNTL_SW_APPCPU_RST_S 4 /* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == - 0x86 will stall PRO CPU*/ -#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 +/*description: {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall P +RO CPU.*/ +#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 #define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) #define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 #define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 /* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == - 0x86 will stall APP CPU*/ -#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 +/*description: {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall A +PP CPU.*/ +#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 #define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) #define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 #define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 -#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x0004) +#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) /* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF +/*description: .*/ +#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF #define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) #define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF #define RTC_CNTL_SLP_VAL_LO_S 0 -#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x0008) +#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) /* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO ;bitpos:[16] ;default: 1'h0 ; */ -/*description: timer alarm enable bit*/ -#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) +/*description: timer alarm enable bit.*/ +#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) #define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) #define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 /* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: RTC sleep timer high 16 bits*/ -#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF +/*description: RTC sleep timer high 16 bits.*/ +#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF #define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) #define RTC_CNTL_SLP_VAL_HI_V 0xFFFF #define RTC_CNTL_SLP_VAL_HI_S 0 -#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0x000C) +#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xC) /* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: Set 1: to update register with RTC timer*/ -#define RTC_CNTL_TIME_UPDATE (BIT(31)) +/*description: Set 1: to update register with RTC timer.*/ +#define RTC_CNTL_TIME_UPDATE (BIT(31)) #define RTC_CNTL_TIME_UPDATE_M (BIT(31)) #define RTC_CNTL_TIME_UPDATE_V 0x1 #define RTC_CNTL_TIME_UPDATE_S 31 /* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: enable to record system reset time*/ -#define RTC_CNTL_TIMER_SYS_RST (BIT(29)) +/*description: enable to record system reset time.*/ +#define RTC_CNTL_TIMER_SYS_RST (BIT(29)) #define RTC_CNTL_TIMER_SYS_RST_M (BIT(29)) #define RTC_CNTL_TIMER_SYS_RST_V 0x1 #define RTC_CNTL_TIMER_SYS_RST_S 29 /* RTC_CNTL_TIMER_XTL_OFF : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Enable to record 40M XTAL OFF time*/ -#define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) +/*description: Enable to record 40M XTAL OFF time.*/ +#define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) #define RTC_CNTL_TIMER_XTL_OFF_M (BIT(28)) #define RTC_CNTL_TIMER_XTL_OFF_V 0x1 #define RTC_CNTL_TIMER_XTL_OFF_S 28 /* RTC_CNTL_TIMER_SYS_STALL : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Enable to record system stall time*/ -#define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) +/*description: Enable to record system stall time.*/ +#define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) #define RTC_CNTL_TIMER_SYS_STALL_M (BIT(27)) #define RTC_CNTL_TIMER_SYS_STALL_V 0x1 #define RTC_CNTL_TIMER_SYS_STALL_S 27 -#define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x0010) +#define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x10) /* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: RTC timer low 32 bits*/ -#define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFF +/*description: RTC timer low 32 bits.*/ +#define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFF #define RTC_CNTL_TIMER_VALUE0_LOW_M ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S)) #define RTC_CNTL_TIMER_VALUE0_LOW_V 0xFFFFFFFF #define RTC_CNTL_TIMER_VALUE0_LOW_S 0 -#define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x0014) +#define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x14) /* RTC_CNTL_TIMER_VALUE0_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: RTC timer high 16 bits*/ -#define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF +/*description: RTC timer high 16 bits.*/ +#define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF #define RTC_CNTL_TIMER_VALUE0_HIGH_M ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S)) #define RTC_CNTL_TIMER_VALUE0_HIGH_V 0xFFFF #define RTC_CNTL_TIMER_VALUE0_HIGH_S 0 -#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x0018) +#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) /* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: sleep enable bit*/ -#define RTC_CNTL_SLEEP_EN (BIT(31)) +/*description: sleep enable bit.*/ +#define RTC_CNTL_SLEEP_EN (BIT(31)) #define RTC_CNTL_SLEEP_EN_M (BIT(31)) #define RTC_CNTL_SLEEP_EN_V 0x1 #define RTC_CNTL_SLEEP_EN_S 31 /* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: leep reject bit*/ -#define RTC_CNTL_SLP_REJECT (BIT(30)) +/*description: leep reject bit.*/ +#define RTC_CNTL_SLP_REJECT (BIT(30)) #define RTC_CNTL_SLP_REJECT_M (BIT(30)) #define RTC_CNTL_SLP_REJECT_V 0x1 #define RTC_CNTL_SLP_REJECT_S 30 /* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: leep wakeup bit*/ -#define RTC_CNTL_SLP_WAKEUP (BIT(29)) +/*description: leep wakeup bit.*/ +#define RTC_CNTL_SLP_WAKEUP (BIT(29)) #define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) #define RTC_CNTL_SLP_WAKEUP_V 0x1 #define RTC_CNTL_SLP_WAKEUP_S 29 /* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ -/*description: SDIO active indication*/ -#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) +/*description: SDIO active indication.*/ +#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) #define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) #define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 #define RTC_CNTL_SDIO_ACTIVE_IND_S 28 /* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: 1: APB to RTC using bridge*/ -#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) +/*description: 1: APB to RTC using bridge.*/ +#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) #define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) #define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 /* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: clear rtc sleep reject cause*/ -#define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) +/*description: clear rtc sleep reject cause.*/ +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) #define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M (BIT(1)) #define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V 0x1 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S 1 /* RTC_CNTL_SW_CPU_INT : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: rtc software interrupt to main cpu*/ -#define RTC_CNTL_SW_CPU_INT (BIT(0)) +/*description: rtc software interrupt to main cpu.*/ +#define RTC_CNTL_SW_CPU_INT (BIT(0)) #define RTC_CNTL_SW_CPU_INT_M (BIT(0)) #define RTC_CNTL_SW_CPU_INT_V 0x1 #define RTC_CNTL_SW_CPU_INT_S 0 -#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x001C) +#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1C) /* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ -/*description: PLL wait cycles in slow_clk_rtc*/ -#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF +/*description: PLL wait cycles in slow_clk_rtc.*/ +#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF #define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) #define RTC_CNTL_PLL_BUF_WAIT_V 0xFF #define RTC_CNTL_PLL_BUF_WAIT_S 24 /* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ -/*description: XTAL wait cycles in slow_clk_rtc*/ -#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF +/*description: XTAL wait cycles in slow_clk_rtc.*/ +#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF #define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) #define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF #define RTC_CNTL_XTL_BUF_WAIT_S 14 /* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ -/*description: CK8M wait cycles in slow_clk_rtc*/ -#define RTC_CNTL_CK8M_WAIT 0x000000FF +/*description: CK8M wait cycles in slow_clk_rtc.*/ +#define RTC_CNTL_CK8M_WAIT 0x000000FF #define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) #define RTC_CNTL_CK8M_WAIT_V 0xFF #define RTC_CNTL_CK8M_WAIT_S 6 /* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ -/*description: CPU stall wait cycles in fast_clk_rtc*/ -#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F +/*description: CPU stall wait cycles in fast_clk_rtc.*/ +#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F #define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) #define RTC_CNTL_CPU_STALL_WAIT_V 0x1F #define RTC_CNTL_CPU_STALL_WAIT_S 1 /* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ -/*description: CPU stall enable bit*/ -#define RTC_CNTL_CPU_STALL_EN (BIT(0)) +/*description: CPU stall enable bit.*/ +#define RTC_CNTL_CPU_STALL_EN (BIT(0)) #define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) #define RTC_CNTL_CPU_STALL_EN_V 0x1 #define RTC_CNTL_CPU_STALL_EN_S 0 -#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x0020) +#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) /* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ -/*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/ -#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF +/*description: minimal cycles in slow_clk_rtc for CK8M in power down state.*/ +#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF #define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) #define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF #define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 /* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */ -/*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller - start to work*/ -#define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF +/*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to w +ork.*/ +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF #define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V)<<(RTC_CNTL_ULPCP_TOUCH_START_WAIT_S)) #define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x1FF #define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15 -#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x0024) +#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) /* RTC_CNTL_BT_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */ -/*description: */ -#define RTC_CNTL_BT_POWERUP_TIMER 0x0000007F +/*description: .*/ +#define RTC_CNTL_BT_POWERUP_TIMER 0x0000007F #define RTC_CNTL_BT_POWERUP_TIMER_M ((RTC_CNTL_BT_POWERUP_TIMER_V)<<(RTC_CNTL_BT_POWERUP_TIMER_S)) #define RTC_CNTL_BT_POWERUP_TIMER_V 0x7F #define RTC_CNTL_BT_POWERUP_TIMER_S 25 /* RTC_CNTL_BT_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */ -/*description: */ -#define RTC_CNTL_BT_WAIT_TIMER 0x000001FF +/*description: .*/ +#define RTC_CNTL_BT_WAIT_TIMER 0x000001FF #define RTC_CNTL_BT_WAIT_TIMER_M ((RTC_CNTL_BT_WAIT_TIMER_V)<<(RTC_CNTL_BT_WAIT_TIMER_S)) #define RTC_CNTL_BT_WAIT_TIMER_V 0x1FF #define RTC_CNTL_BT_WAIT_TIMER_S 16 /* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ -/*description: */ -#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F +/*description: .*/ +#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F #define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) #define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F #define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 /* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ -/*description: */ -#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF +/*description: .*/ +#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF #define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) #define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF #define RTC_CNTL_WIFI_WAIT_TIMER_S 0 -#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x0028) +#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) /* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ -/*description: */ -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F +/*description: .*/ +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 /* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ -/*description: */ -#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF +/*description: .*/ +#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF #define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) #define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF #define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 /* RTC_CNTL_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ -/*description: */ -#define RTC_CNTL_POWERUP_TIMER 0x0000007F +/*description: .*/ +#define RTC_CNTL_POWERUP_TIMER 0x0000007F #define RTC_CNTL_POWERUP_TIMER_M ((RTC_CNTL_POWERUP_TIMER_V)<<(RTC_CNTL_POWERUP_TIMER_S)) #define RTC_CNTL_POWERUP_TIMER_V 0x7F #define RTC_CNTL_POWERUP_TIMER_S 9 /* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ -/*description: */ -#define RTC_CNTL_WAIT_TIMER 0x000001FF +/*description: .*/ +#define RTC_CNTL_WAIT_TIMER 0x000001FF #define RTC_CNTL_WAIT_TIMER_M ((RTC_CNTL_WAIT_TIMER_V)<<(RTC_CNTL_WAIT_TIMER_S)) #define RTC_CNTL_WAIT_TIMER_V 0x1FF #define RTC_CNTL_WAIT_TIMER_S 0 -#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x002C) +#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2C) /* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ -/*description: minimal sleep cycles in slow_clk_rtc*/ -#define RTC_CNTL_MIN_SLP_VAL 0x000000FF +/*description: minimal sleep cycles in slow_clk_rtc.*/ +#define RTC_CNTL_MIN_SLP_VAL 0x000000FF #define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) #define RTC_CNTL_MIN_SLP_VAL_V 0xFF #define RTC_CNTL_MIN_SLP_VAL_S 8 #define RTC_CNTL_MIN_SLP_VAL_MIN 2 -#define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x0030) +#define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x30) /* RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ -/*description: */ -#define RTC_CNTL_DG_PERI_POWERUP_TIMER 0x0000007F +/*description: .*/ +#define RTC_CNTL_DG_PERI_POWERUP_TIMER 0x0000007F #define RTC_CNTL_DG_PERI_POWERUP_TIMER_M ((RTC_CNTL_DG_PERI_POWERUP_TIMER_V)<<(RTC_CNTL_DG_PERI_POWERUP_TIMER_S)) #define RTC_CNTL_DG_PERI_POWERUP_TIMER_V 0x7F #define RTC_CNTL_DG_PERI_POWERUP_TIMER_S 25 /* RTC_CNTL_DG_PERI_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ -/*description: */ -#define RTC_CNTL_DG_PERI_WAIT_TIMER 0x000001FF +/*description: .*/ +#define RTC_CNTL_DG_PERI_WAIT_TIMER 0x000001FF #define RTC_CNTL_DG_PERI_WAIT_TIMER_M ((RTC_CNTL_DG_PERI_WAIT_TIMER_V)<<(RTC_CNTL_DG_PERI_WAIT_TIMER_S)) #define RTC_CNTL_DG_PERI_WAIT_TIMER_V 0x1FF #define RTC_CNTL_DG_PERI_WAIT_TIMER_S 16 /* RTC_CNTL_CPU_TOP_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ -/*description: */ -#define RTC_CNTL_CPU_TOP_POWERUP_TIMER 0x0000007F +/*description: .*/ +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER 0x0000007F #define RTC_CNTL_CPU_TOP_POWERUP_TIMER_M ((RTC_CNTL_CPU_TOP_POWERUP_TIMER_V)<<(RTC_CNTL_CPU_TOP_POWERUP_TIMER_S)) #define RTC_CNTL_CPU_TOP_POWERUP_TIMER_V 0x7F #define RTC_CNTL_CPU_TOP_POWERUP_TIMER_S 9 /* RTC_CNTL_CPU_TOP_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ -/*description: */ -#define RTC_CNTL_CPU_TOP_WAIT_TIMER 0x000001FF +/*description: .*/ +#define RTC_CNTL_CPU_TOP_WAIT_TIMER 0x000001FF #define RTC_CNTL_CPU_TOP_WAIT_TIMER_M ((RTC_CNTL_CPU_TOP_WAIT_TIMER_V)<<(RTC_CNTL_CPU_TOP_WAIT_TIMER_S)) #define RTC_CNTL_CPU_TOP_WAIT_TIMER_V 0x1FF #define RTC_CNTL_CPU_TOP_WAIT_TIMER_S 0 -#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0034) +#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x34) /* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_PLL_I2C_PU (BIT(31)) +/*description: .*/ +#define RTC_CNTL_PLL_I2C_PU (BIT(31)) #define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) #define RTC_CNTL_PLL_I2C_PU_V 0x1 #define RTC_CNTL_PLL_I2C_PU_S 31 /* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: 1: CKGEN_I2C power up*/ -#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) +/*description: 1: CKGEN_I2C power up.*/ +#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) #define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) #define RTC_CNTL_CKGEN_I2C_PU_V 0x1 #define RTC_CNTL_CKGEN_I2C_PU_S 30 /* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: 1: RFRX_PBUS power up*/ -#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) +/*description: 1: RFRX_PBUS power up.*/ +#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) #define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) #define RTC_CNTL_RFRX_PBUS_PU_V 0x1 #define RTC_CNTL_RFRX_PBUS_PU_S 28 /* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: 1: TXRF_I2C power up*/ -#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) +/*description: 1: TXRF_I2C power up.*/ +#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) #define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) #define RTC_CNTL_TXRF_I2C_PU_V 0x1 #define RTC_CNTL_TXRF_I2C_PU_S 27 /* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: 1: PVTMON power up*/ -#define RTC_CNTL_PVTMON_PU (BIT(26)) +/*description: 1: PVTMON power up.*/ +#define RTC_CNTL_PVTMON_PU (BIT(26)) #define RTC_CNTL_PVTMON_PU_M (BIT(26)) #define RTC_CNTL_PVTMON_PU_V 0x1 #define RTC_CNTL_PVTMON_PU_S 26 /* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: start BBPLL calibration during sleep*/ -#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) +/*description: start BBPLL calibration during sleep.*/ +#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) #define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) #define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 #define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 -/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: PLLA force power up*/ -#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) -#define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) -#define RTC_CNTL_PLLA_FORCE_PU_V 0x1 -#define RTC_CNTL_PLLA_FORCE_PU_S 24 -/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */ -/*description: PLLA force power down*/ -#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) -#define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) -#define RTC_CNTL_PLLA_FORCE_PD_V 0x1 -#define RTC_CNTL_PLLA_FORCE_PD_S 23 +/* RTC_CNTL_ANALOG_TOP_ISO_MONITOR : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: PLLA force power up.*/ +#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR (BIT(24)) +#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_M (BIT(24)) +#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_V 0x1 +#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_S 24 +/* RTC_CNTL_ANALOG_TOP_ISO_SLEEP : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: PLLA force power down.*/ +#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP (BIT(23)) +#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP_M (BIT(23)) +#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP_V 0x1 +#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP_S 23 /* RTC_CNTL_SAR_I2C_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: PLLA force power up*/ -#define RTC_CNTL_SAR_I2C_PU (BIT(22)) +/*description: PLLA force power up.*/ +#define RTC_CNTL_SAR_I2C_PU (BIT(22)) #define RTC_CNTL_SAR_I2C_PU_M (BIT(22)) #define RTC_CNTL_SAR_I2C_PU_V 0x1 #define RTC_CNTL_SAR_I2C_PU_S 22 /* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_GLITCH_RST_EN (BIT(20)) +/*description: .*/ +#define RTC_CNTL_GLITCH_RST_EN (BIT(20)) #define RTC_CNTL_GLITCH_RST_EN_M (BIT(20)) #define RTC_CNTL_GLITCH_RST_EN_V 0x1 #define RTC_CNTL_GLITCH_RST_EN_S 20 /* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) +/*description: .*/ +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) #define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (BIT(19)) #define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x1 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 /* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) +/*description: .*/ +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (BIT(18)) #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x1 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 -#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x0038) +#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) /* RTC_CNTL_PRO_DRESET_MASK : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_PRO_DRESET_MASK (BIT(25)) +/*description: .*/ +#define RTC_CNTL_PRO_DRESET_MASK (BIT(25)) #define RTC_CNTL_PRO_DRESET_MASK_M (BIT(25)) #define RTC_CNTL_PRO_DRESET_MASK_V 0x1 #define RTC_CNTL_PRO_DRESET_MASK_S 25 /* RTC_CNTL_APP_DRESET_MASK : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_APP_DRESET_MASK (BIT(24)) +/*description: .*/ +#define RTC_CNTL_APP_DRESET_MASK (BIT(24)) #define RTC_CNTL_APP_DRESET_MASK_M (BIT(24)) #define RTC_CNTL_APP_DRESET_MASK_V 0x1 #define RTC_CNTL_APP_DRESET_MASK_S 24 /* RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR (BIT(23)) +/*description: .*/ +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR (BIT(23)) #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_M (BIT(23)) #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_V 0x1 #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_S 23 /* RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR (BIT(22)) +/*description: .*/ +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR (BIT(22)) #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_M (BIT(22)) #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_V 0x1 #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_S 22 /* RTC_CNTL_RESET_FLAG_JTAG_APPCPU : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU (BIT(21)) +/*description: .*/ +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU (BIT(21)) #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_M (BIT(21)) #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_V 0x1 #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_S 21 /* RTC_CNTL_RESET_FLAG_JTAG_PROCPU : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU (BIT(20)) +/*description: .*/ +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU (BIT(20)) #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_M (BIT(20)) #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_V 0x1 #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_S 20 /* RTC_CNTL_PROCPU_OCD_HALT_ON_RESET : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: PROCPU OcdHaltOnReset*/ -#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET (BIT(19)) +/*description: PROCPU OcdHaltOnReset.*/ +#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET (BIT(19)) #define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_M (BIT(19)) #define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_V 0x1 #define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_S 19 /* RTC_CNTL_APPCPU_OCD_HALT_ON_RESET : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: APPCPU OcdHaltOnReset*/ -#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET (BIT(18)) +/*description: APPCPU OcdHaltOnReset.*/ +#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET (BIT(18)) #define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_M (BIT(18)) #define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_V 0x1 #define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_S 18 /* RTC_CNTL_RESET_FLAG_APPCPU_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: clear APP CPU reset flag*/ -#define RTC_CNTL_RESET_FLAG_APPCPU_CLR (BIT(17)) +/*description: clear APP CPU reset flag.*/ +#define RTC_CNTL_RESET_FLAG_APPCPU_CLR (BIT(17)) #define RTC_CNTL_RESET_FLAG_APPCPU_CLR_M (BIT(17)) #define RTC_CNTL_RESET_FLAG_APPCPU_CLR_V 0x1 #define RTC_CNTL_RESET_FLAG_APPCPU_CLR_S 17 /* RTC_CNTL_RESET_FLAG_PROCPU_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: clear PRO CPU reset_flag*/ -#define RTC_CNTL_RESET_FLAG_PROCPU_CLR (BIT(16)) +/*description: clear PRO CPU reset_flag.*/ +#define RTC_CNTL_RESET_FLAG_PROCPU_CLR (BIT(16)) #define RTC_CNTL_RESET_FLAG_PROCPU_CLR_M (BIT(16)) #define RTC_CNTL_RESET_FLAG_PROCPU_CLR_V 0x1 #define RTC_CNTL_RESET_FLAG_PROCPU_CLR_S 16 /* RTC_CNTL_RESET_FLAG_APPCPU : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: APP CPU reset flag*/ -#define RTC_CNTL_RESET_FLAG_APPCPU (BIT(15)) +/*description: APP CPU reset flag.*/ +#define RTC_CNTL_RESET_FLAG_APPCPU (BIT(15)) #define RTC_CNTL_RESET_FLAG_APPCPU_M (BIT(15)) #define RTC_CNTL_RESET_FLAG_APPCPU_V 0x1 #define RTC_CNTL_RESET_FLAG_APPCPU_S 15 /* RTC_CNTL_RESET_FLAG_PROCPU : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: PRO CPU reset_flag*/ -#define RTC_CNTL_RESET_FLAG_PROCPU (BIT(14)) +/*description: PRO CPU reset_flag.*/ +#define RTC_CNTL_RESET_FLAG_PROCPU (BIT(14)) #define RTC_CNTL_RESET_FLAG_PROCPU_M (BIT(14)) #define RTC_CNTL_RESET_FLAG_PROCPU_V 0x1 #define RTC_CNTL_RESET_FLAG_PROCPU_S 14 /* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: PRO CPU state vector sel*/ -#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) +/*description: PRO CPU state vector sel.*/ +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (BIT(13)) #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x1 #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13 /* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: APP CPU state vector sel*/ -#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) +/*description: APP CPU state vector sel.*/ +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (BIT(12)) #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x1 #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12 /* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ -/*description: reset cause of APP CPU*/ -#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F +/*description: reset cause of APP CPU.*/ +#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F #define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) #define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F #define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 /* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ -/*description: reset cause of PRO CPU*/ -#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F +/*description: reset cause of PRO CPU.*/ +#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F #define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) #define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F #define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 -#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x003C) +#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x3C) /* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:15] ;default: 17'b1100 ; */ -/*description: wakeup enable bitmap*/ -#define RTC_CNTL_WAKEUP_ENA 0x0001FFFF +/*description: wakeup enable bitmap.*/ +#define RTC_CNTL_WAKEUP_ENA 0x0001FFFF #define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) #define RTC_CNTL_WAKEUP_ENA_V 0x1FFFF #define RTC_CNTL_WAKEUP_ENA_S 15 -#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x0040) +#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x40) /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA (BIT(20)) +/*description: .*/ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x1 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 20 /* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: enbale gitch det interrupt*/ -#define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) +/*description: enbale gitch det interrupt.*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_M (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x1 #define RTC_CNTL_GLITCH_DET_INT_ENA_S 19 /* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: enable touch timeout interrupt*/ -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA (BIT(18)) +/*description: enable touch timeout interrupt.*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_M (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_V 0x1 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_S 18 /* RTC_CNTL_COCPU_TRAP_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: enable cocpu trap interrupt*/ -#define RTC_CNTL_COCPU_TRAP_INT_ENA (BIT(17)) +/*description: enable cocpu trap interrupt.*/ +#define RTC_CNTL_COCPU_TRAP_INT_ENA (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_ENA_M (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_ENA_V 0x1 #define RTC_CNTL_COCPU_TRAP_INT_ENA_S 17 /* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: enable xtal32k_dead interrupt*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) +/*description: enable xtal32k_dead interrupt.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x1 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S 16 /* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: enable super watch dog interrupt*/ -#define RTC_CNTL_SWD_INT_ENA (BIT(15)) +/*description: enable super watch dog interrupt.*/ +#define RTC_CNTL_SWD_INT_ENA (BIT(15)) #define RTC_CNTL_SWD_INT_ENA_M (BIT(15)) #define RTC_CNTL_SWD_INT_ENA_V 0x1 #define RTC_CNTL_SWD_INT_ENA_S 15 /* RTC_CNTL_SARADC2_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: enable saradc2 interrupt*/ -#define RTC_CNTL_SARADC2_INT_ENA (BIT(14)) +/*description: enable saradc2 interrupt.*/ +#define RTC_CNTL_SARADC2_INT_ENA (BIT(14)) #define RTC_CNTL_SARADC2_INT_ENA_M (BIT(14)) #define RTC_CNTL_SARADC2_INT_ENA_V 0x1 #define RTC_CNTL_SARADC2_INT_ENA_S 14 /* RTC_CNTL_COCPU_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: enable riscV cocpu interrupt*/ -#define RTC_CNTL_COCPU_INT_ENA (BIT(13)) +/*description: enable riscV cocpu interrupt.*/ +#define RTC_CNTL_COCPU_INT_ENA (BIT(13)) #define RTC_CNTL_COCPU_INT_ENA_M (BIT(13)) #define RTC_CNTL_COCPU_INT_ENA_V 0x1 #define RTC_CNTL_COCPU_INT_ENA_S 13 /* RTC_CNTL_TSENS_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: enable tsens interrupt*/ -#define RTC_CNTL_TSENS_INT_ENA (BIT(12)) +/*description: enable tsens interrupt.*/ +#define RTC_CNTL_TSENS_INT_ENA (BIT(12)) #define RTC_CNTL_TSENS_INT_ENA_M (BIT(12)) #define RTC_CNTL_TSENS_INT_ENA_V 0x1 #define RTC_CNTL_TSENS_INT_ENA_S 12 /* RTC_CNTL_SARADC1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: enable saradc1 interrupt*/ -#define RTC_CNTL_SARADC1_INT_ENA (BIT(11)) +/*description: enable saradc1 interrupt.*/ +#define RTC_CNTL_SARADC1_INT_ENA (BIT(11)) #define RTC_CNTL_SARADC1_INT_ENA_M (BIT(11)) #define RTC_CNTL_SARADC1_INT_ENA_V 0x1 #define RTC_CNTL_SARADC1_INT_ENA_S 11 /* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: enable RTC main timer interrupt*/ -#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) +/*description: enable RTC main timer interrupt.*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 #define RTC_CNTL_MAIN_TIMER_INT_ENA_S 10 /* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: enable brown out interrupt*/ -#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) +/*description: enable brown out interrupt.*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 #define RTC_CNTL_BROWN_OUT_INT_ENA_S 9 /* RTC_CNTL_TOUCH_INACTIVE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: enable touch inactive interrupt*/ -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA (BIT(8)) +/*description: enable touch inactive interrupt.*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_M (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_V 0x1 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_S 8 /* RTC_CNTL_TOUCH_ACTIVE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: enable touch active interrupt*/ -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA (BIT(7)) +/*description: enable touch active interrupt.*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_M (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_V 0x1 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_S 7 /* RTC_CNTL_TOUCH_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: enable touch done interrupt*/ -#define RTC_CNTL_TOUCH_DONE_INT_ENA (BIT(6)) +/*description: enable touch done interrupt.*/ +#define RTC_CNTL_TOUCH_DONE_INT_ENA (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_ENA_M (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_ENA_V 0x1 #define RTC_CNTL_TOUCH_DONE_INT_ENA_S 6 /* RTC_CNTL_ULP_CP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: enable ULP-coprocessor interrupt*/ -#define RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) +/*description: enable ULP-coprocessor interrupt.*/ +#define RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) #define RTC_CNTL_ULP_CP_INT_ENA_M (BIT(5)) #define RTC_CNTL_ULP_CP_INT_ENA_V 0x1 #define RTC_CNTL_ULP_CP_INT_ENA_S 5 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: enable touch scan done interrupt*/ -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA (BIT(4)) +/*description: enable touch scan done interrupt.*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_M (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_V 0x1 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_S 4 /* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: enable RTC WDT interrupt*/ -#define RTC_CNTL_WDT_INT_ENA (BIT(3)) +/*description: enable RTC WDT interrupt.*/ +#define RTC_CNTL_WDT_INT_ENA (BIT(3)) #define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) #define RTC_CNTL_WDT_INT_ENA_V 0x1 #define RTC_CNTL_WDT_INT_ENA_S 3 /* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: enable SDIO idle interrupt*/ -#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) +/*description: enable SDIO idle interrupt.*/ +#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_ENA_M (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x1 #define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2 /* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: enable sleep reject interrupt*/ -#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) +/*description: enable sleep reject interrupt.*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 #define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 /* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: enable sleep wakeup interrupt*/ -#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) +/*description: enable sleep wakeup interrupt.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 -#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x0044) +#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x44) /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW (BIT(20)) +/*description: .*/ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V 0x1 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S 20 /* RTC_CNTL_GLITCH_DET_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: glitch_det_interrupt_raw*/ -#define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) +/*description: glitch_det_interrupt_raw.*/ +#define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_RAW_M (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_RAW_V 0x1 #define RTC_CNTL_GLITCH_DET_INT_RAW_S 19 /* RTC_CNTL_TOUCH_TIMEOUT_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: touch timeout interrupt raw*/ -#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW (BIT(18)) +/*description: touch timeout interrupt raw.*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_M (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_V 0x1 #define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_S 18 /* RTC_CNTL_COCPU_TRAP_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: cocpu trap interrupt raw*/ -#define RTC_CNTL_COCPU_TRAP_INT_RAW (BIT(17)) +/*description: cocpu trap interrupt raw.*/ +#define RTC_CNTL_COCPU_TRAP_INT_RAW (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_RAW_M (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_RAW_V 0x1 #define RTC_CNTL_COCPU_TRAP_INT_RAW_S 17 /* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: xtal32k dead detection interrupt raw*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) +/*description: xtal32k dead detection interrupt raw.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V 0x1 #define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S 16 /* RTC_CNTL_SWD_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: super watch dog interrupt raw*/ -#define RTC_CNTL_SWD_INT_RAW (BIT(15)) +/*description: super watch dog interrupt raw.*/ +#define RTC_CNTL_SWD_INT_RAW (BIT(15)) #define RTC_CNTL_SWD_INT_RAW_M (BIT(15)) #define RTC_CNTL_SWD_INT_RAW_V 0x1 #define RTC_CNTL_SWD_INT_RAW_S 15 /* RTC_CNTL_SARADC2_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: saradc2 interrupt raw*/ -#define RTC_CNTL_SARADC2_INT_RAW (BIT(14)) +/*description: saradc2 interrupt raw.*/ +#define RTC_CNTL_SARADC2_INT_RAW (BIT(14)) #define RTC_CNTL_SARADC2_INT_RAW_M (BIT(14)) #define RTC_CNTL_SARADC2_INT_RAW_V 0x1 #define RTC_CNTL_SARADC2_INT_RAW_S 14 /* RTC_CNTL_COCPU_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: riscV cocpu interrupt raw*/ -#define RTC_CNTL_COCPU_INT_RAW (BIT(13)) +/*description: riscV cocpu interrupt raw.*/ +#define RTC_CNTL_COCPU_INT_RAW (BIT(13)) #define RTC_CNTL_COCPU_INT_RAW_M (BIT(13)) #define RTC_CNTL_COCPU_INT_RAW_V 0x1 #define RTC_CNTL_COCPU_INT_RAW_S 13 /* RTC_CNTL_TSENS_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: tsens interrupt raw*/ -#define RTC_CNTL_TSENS_INT_RAW (BIT(12)) +/*description: tsens interrupt raw.*/ +#define RTC_CNTL_TSENS_INT_RAW (BIT(12)) #define RTC_CNTL_TSENS_INT_RAW_M (BIT(12)) #define RTC_CNTL_TSENS_INT_RAW_V 0x1 #define RTC_CNTL_TSENS_INT_RAW_S 12 /* RTC_CNTL_SARADC1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: saradc1 interrupt raw*/ -#define RTC_CNTL_SARADC1_INT_RAW (BIT(11)) +/*description: saradc1 interrupt raw.*/ +#define RTC_CNTL_SARADC1_INT_RAW (BIT(11)) #define RTC_CNTL_SARADC1_INT_RAW_M (BIT(11)) #define RTC_CNTL_SARADC1_INT_RAW_V 0x1 #define RTC_CNTL_SARADC1_INT_RAW_S 11 /* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: RTC main timer interrupt raw*/ -#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) +/*description: RTC main timer interrupt raw.*/ +#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 #define RTC_CNTL_MAIN_TIMER_INT_RAW_S 10 /* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: brown out interrupt raw*/ -#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) +/*description: brown out interrupt raw.*/ +#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 #define RTC_CNTL_BROWN_OUT_INT_RAW_S 9 /* RTC_CNTL_TOUCH_INACTIVE_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: touch inactive interrupt raw*/ -#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW (BIT(8)) +/*description: touch inactive interrupt raw.*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_M (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_V 0x1 #define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_S 8 /* RTC_CNTL_TOUCH_ACTIVE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: touch active interrupt raw*/ -#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW (BIT(7)) +/*description: touch active interrupt raw.*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_M (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_V 0x1 #define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_S 7 /* RTC_CNTL_TOUCH_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: touch interrupt raw*/ -#define RTC_CNTL_TOUCH_DONE_INT_RAW (BIT(6)) +/*description: touch interrupt raw.*/ +#define RTC_CNTL_TOUCH_DONE_INT_RAW (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_RAW_M (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_RAW_V 0x1 #define RTC_CNTL_TOUCH_DONE_INT_RAW_S 6 /* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: ULP-coprocessor interrupt raw*/ -#define RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) +/*description: ULP-coprocessor interrupt raw.*/ +#define RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) #define RTC_CNTL_ULP_CP_INT_RAW_M (BIT(5)) #define RTC_CNTL_ULP_CP_INT_RAW_V 0x1 #define RTC_CNTL_ULP_CP_INT_RAW_S 5 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW (BIT(4)) +/*description: .*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_M (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_V 0x1 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_S 4 /* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: RTC WDT interrupt raw*/ -#define RTC_CNTL_WDT_INT_RAW (BIT(3)) +/*description: RTC WDT interrupt raw.*/ +#define RTC_CNTL_WDT_INT_RAW (BIT(3)) #define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) #define RTC_CNTL_WDT_INT_RAW_V 0x1 #define RTC_CNTL_WDT_INT_RAW_S 3 /* RTC_CNTL_SDIO_IDLE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: SDIO idle interrupt raw*/ -#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) +/*description: SDIO idle interrupt raw.*/ +#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_RAW_M (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x1 #define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2 /* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: sleep reject interrupt raw*/ -#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) +/*description: sleep reject interrupt raw.*/ +#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 #define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 /* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: sleep wakeup interrupt raw*/ -#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) +/*description: sleep wakeup interrupt raw.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 -#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x0048) +#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x48) /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST (BIT(20)) +/*description: .*/ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_M (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_V 0x1 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_S 20 /* RTC_CNTL_GLITCH_DET_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: glitch_det_interrupt state*/ -#define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) +/*description: glitch_det_interrupt state.*/ +#define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ST_M (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ST_V 0x1 #define RTC_CNTL_GLITCH_DET_INT_ST_S 19 /* RTC_CNTL_TOUCH_TIMEOUT_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: Touch timeout interrupt state*/ -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST (BIT(18)) +/*description: Touch timeout interrupt state.*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_M (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_V 0x1 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_S 18 /* RTC_CNTL_COCPU_TRAP_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: cocpu trap interrupt state*/ -#define RTC_CNTL_COCPU_TRAP_INT_ST (BIT(17)) +/*description: cocpu trap interrupt state.*/ +#define RTC_CNTL_COCPU_TRAP_INT_ST (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_ST_M (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_ST_V 0x1 #define RTC_CNTL_COCPU_TRAP_INT_ST_S 17 /* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: xtal32k dead detection interrupt state*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) +/*description: xtal32k dead detection interrupt state.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_ST_M (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_ST_V 0x1 #define RTC_CNTL_XTAL32K_DEAD_INT_ST_S 16 /* RTC_CNTL_SWD_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: super watch dog interrupt state*/ -#define RTC_CNTL_SWD_INT_ST (BIT(15)) +/*description: super watch dog interrupt state.*/ +#define RTC_CNTL_SWD_INT_ST (BIT(15)) #define RTC_CNTL_SWD_INT_ST_M (BIT(15)) #define RTC_CNTL_SWD_INT_ST_V 0x1 #define RTC_CNTL_SWD_INT_ST_S 15 /* RTC_CNTL_SARADC2_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: saradc2 interrupt state*/ -#define RTC_CNTL_SARADC2_INT_ST (BIT(14)) +/*description: saradc2 interrupt state.*/ +#define RTC_CNTL_SARADC2_INT_ST (BIT(14)) #define RTC_CNTL_SARADC2_INT_ST_M (BIT(14)) #define RTC_CNTL_SARADC2_INT_ST_V 0x1 #define RTC_CNTL_SARADC2_INT_ST_S 14 /* RTC_CNTL_COCPU_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: riscV cocpu interrupt state*/ -#define RTC_CNTL_COCPU_INT_ST (BIT(13)) +/*description: riscV cocpu interrupt state.*/ +#define RTC_CNTL_COCPU_INT_ST (BIT(13)) #define RTC_CNTL_COCPU_INT_ST_M (BIT(13)) #define RTC_CNTL_COCPU_INT_ST_V 0x1 #define RTC_CNTL_COCPU_INT_ST_S 13 /* RTC_CNTL_TSENS_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: tsens interrupt state*/ -#define RTC_CNTL_TSENS_INT_ST (BIT(12)) +/*description: tsens interrupt state.*/ +#define RTC_CNTL_TSENS_INT_ST (BIT(12)) #define RTC_CNTL_TSENS_INT_ST_M (BIT(12)) #define RTC_CNTL_TSENS_INT_ST_V 0x1 #define RTC_CNTL_TSENS_INT_ST_S 12 /* RTC_CNTL_SARADC1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: saradc1 interrupt state*/ -#define RTC_CNTL_SARADC1_INT_ST (BIT(11)) +/*description: saradc1 interrupt state.*/ +#define RTC_CNTL_SARADC1_INT_ST (BIT(11)) #define RTC_CNTL_SARADC1_INT_ST_M (BIT(11)) #define RTC_CNTL_SARADC1_INT_ST_V 0x1 #define RTC_CNTL_SARADC1_INT_ST_S 11 /* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: RTC main timer interrupt state*/ -#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) +/*description: RTC main timer interrupt state.*/ +#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 #define RTC_CNTL_MAIN_TIMER_INT_ST_S 10 /* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: brown out interrupt state*/ -#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) +/*description: brown out interrupt state.*/ +#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 #define RTC_CNTL_BROWN_OUT_INT_ST_S 9 /* RTC_CNTL_TOUCH_INACTIVE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: touch inactive interrupt state*/ -#define RTC_CNTL_TOUCH_INACTIVE_INT_ST (BIT(8)) +/*description: touch inactive interrupt state.*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_ST_M (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_ST_V 0x1 #define RTC_CNTL_TOUCH_INACTIVE_INT_ST_S 8 /* RTC_CNTL_TOUCH_ACTIVE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: touch active interrupt state*/ -#define RTC_CNTL_TOUCH_ACTIVE_INT_ST (BIT(7)) +/*description: touch active interrupt state.*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_ST_M (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_ST_V 0x1 #define RTC_CNTL_TOUCH_ACTIVE_INT_ST_S 7 /* RTC_CNTL_TOUCH_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: touch done interrupt state*/ -#define RTC_CNTL_TOUCH_DONE_INT_ST (BIT(6)) +/*description: touch done interrupt state.*/ +#define RTC_CNTL_TOUCH_DONE_INT_ST (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_ST_M (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_ST_V 0x1 #define RTC_CNTL_TOUCH_DONE_INT_ST_S 6 /* RTC_CNTL_ULP_CP_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: ULP-coprocessor interrupt state*/ -#define RTC_CNTL_ULP_CP_INT_ST (BIT(5)) +/*description: ULP-coprocessor interrupt state.*/ +#define RTC_CNTL_ULP_CP_INT_ST (BIT(5)) #define RTC_CNTL_ULP_CP_INT_ST_M (BIT(5)) #define RTC_CNTL_ULP_CP_INT_ST_V 0x1 #define RTC_CNTL_ULP_CP_INT_ST_S 5 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST (BIT(4)) +/*description: .*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_M (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_V 0x1 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_S 4 /* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: RTC WDT interrupt state*/ -#define RTC_CNTL_WDT_INT_ST (BIT(3)) +/*description: RTC WDT interrupt state.*/ +#define RTC_CNTL_WDT_INT_ST (BIT(3)) #define RTC_CNTL_WDT_INT_ST_M (BIT(3)) #define RTC_CNTL_WDT_INT_ST_V 0x1 #define RTC_CNTL_WDT_INT_ST_S 3 /* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: SDIO idle interrupt state*/ -#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) +/*description: SDIO idle interrupt state.*/ +#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_ST_M (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x1 #define RTC_CNTL_SDIO_IDLE_INT_ST_S 2 /* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: sleep reject interrupt state*/ -#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) +/*description: sleep reject interrupt state.*/ +#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 #define RTC_CNTL_SLP_REJECT_INT_ST_S 1 /* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: sleep wakeup interrupt state*/ -#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) +/*description: sleep wakeup interrupt state.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 #define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 -#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x004C) +#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x4C) /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR (BIT(20)) +/*description: .*/ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x1 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 20 /* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Clear glitch det interrupt state*/ -#define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) +/*description: Clear glitch det interrupt state.*/ +#define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_CLR_M (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_CLR_V 0x1 #define RTC_CNTL_GLITCH_DET_INT_CLR_S 19 /* RTC_CNTL_TOUCH_TIMEOUT_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: Clear touch timeout interrupt state*/ -#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR (BIT(18)) +/*description: Clear touch timeout interrupt state.*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_M (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_V 0x1 #define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_S 18 /* RTC_CNTL_COCPU_TRAP_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Clear cocpu trap interrupt state*/ -#define RTC_CNTL_COCPU_TRAP_INT_CLR (BIT(17)) +/*description: Clear cocpu trap interrupt state.*/ +#define RTC_CNTL_COCPU_TRAP_INT_CLR (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_CLR_M (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_CLR_V 0x1 #define RTC_CNTL_COCPU_TRAP_INT_CLR_S 17 /* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Clear RTC WDT interrupt state*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) +/*description: Clear RTC WDT interrupt state.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V 0x1 #define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S 16 /* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Clear super watch dog interrupt state*/ -#define RTC_CNTL_SWD_INT_CLR (BIT(15)) +/*description: Clear super watch dog interrupt state.*/ +#define RTC_CNTL_SWD_INT_CLR (BIT(15)) #define RTC_CNTL_SWD_INT_CLR_M (BIT(15)) #define RTC_CNTL_SWD_INT_CLR_V 0x1 #define RTC_CNTL_SWD_INT_CLR_S 15 /* RTC_CNTL_SARADC2_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Clear saradc2 interrupt state*/ -#define RTC_CNTL_SARADC2_INT_CLR (BIT(14)) +/*description: Clear saradc2 interrupt state.*/ +#define RTC_CNTL_SARADC2_INT_CLR (BIT(14)) #define RTC_CNTL_SARADC2_INT_CLR_M (BIT(14)) #define RTC_CNTL_SARADC2_INT_CLR_V 0x1 #define RTC_CNTL_SARADC2_INT_CLR_S 14 /* RTC_CNTL_COCPU_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Clear riscV cocpu interrupt state*/ -#define RTC_CNTL_COCPU_INT_CLR (BIT(13)) +/*description: Clear riscV cocpu interrupt state.*/ +#define RTC_CNTL_COCPU_INT_CLR (BIT(13)) #define RTC_CNTL_COCPU_INT_CLR_M (BIT(13)) #define RTC_CNTL_COCPU_INT_CLR_V 0x1 #define RTC_CNTL_COCPU_INT_CLR_S 13 /* RTC_CNTL_TSENS_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Clear tsens interrupt state*/ -#define RTC_CNTL_TSENS_INT_CLR (BIT(12)) +/*description: Clear tsens interrupt state.*/ +#define RTC_CNTL_TSENS_INT_CLR (BIT(12)) #define RTC_CNTL_TSENS_INT_CLR_M (BIT(12)) #define RTC_CNTL_TSENS_INT_CLR_V 0x1 #define RTC_CNTL_TSENS_INT_CLR_S 12 /* RTC_CNTL_SARADC1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Clear saradc1 interrupt state*/ -#define RTC_CNTL_SARADC1_INT_CLR (BIT(11)) +/*description: Clear saradc1 interrupt state.*/ +#define RTC_CNTL_SARADC1_INT_CLR (BIT(11)) #define RTC_CNTL_SARADC1_INT_CLR_M (BIT(11)) #define RTC_CNTL_SARADC1_INT_CLR_V 0x1 #define RTC_CNTL_SARADC1_INT_CLR_S 11 /* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Clear RTC main timer interrupt state*/ -#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) +/*description: Clear RTC main timer interrupt state.*/ +#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 #define RTC_CNTL_MAIN_TIMER_INT_CLR_S 10 /* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Clear brown out interrupt state*/ -#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) +/*description: Clear brown out interrupt state.*/ +#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 #define RTC_CNTL_BROWN_OUT_INT_CLR_S 9 /* RTC_CNTL_TOUCH_INACTIVE_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Clear touch inactive interrupt state*/ -#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR (BIT(8)) +/*description: Clear touch inactive interrupt state.*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_M (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_V 0x1 #define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_S 8 /* RTC_CNTL_TOUCH_ACTIVE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Clear touch active interrupt state*/ -#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR (BIT(7)) +/*description: Clear touch active interrupt state.*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_M (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_V 0x1 #define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_S 7 /* RTC_CNTL_TOUCH_DONE_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Clear touch done interrupt state*/ -#define RTC_CNTL_TOUCH_DONE_INT_CLR (BIT(6)) +/*description: Clear touch done interrupt state.*/ +#define RTC_CNTL_TOUCH_DONE_INT_CLR (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_CLR_M (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_CLR_V 0x1 #define RTC_CNTL_TOUCH_DONE_INT_CLR_S 6 /* RTC_CNTL_ULP_CP_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Clear ULP-coprocessor interrupt state*/ -#define RTC_CNTL_ULP_CP_INT_CLR (BIT(5)) +/*description: Clear ULP-coprocessor interrupt state.*/ +#define RTC_CNTL_ULP_CP_INT_CLR (BIT(5)) #define RTC_CNTL_ULP_CP_INT_CLR_M (BIT(5)) #define RTC_CNTL_ULP_CP_INT_CLR_V 0x1 #define RTC_CNTL_ULP_CP_INT_CLR_S 5 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR (BIT(4)) +/*description: .*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_M (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_V 0x1 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_S 4 /* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Clear RTC WDT interrupt state*/ -#define RTC_CNTL_WDT_INT_CLR (BIT(3)) +/*description: Clear RTC WDT interrupt state.*/ +#define RTC_CNTL_WDT_INT_CLR (BIT(3)) #define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) #define RTC_CNTL_WDT_INT_CLR_V 0x1 #define RTC_CNTL_WDT_INT_CLR_S 3 /* RTC_CNTL_SDIO_IDLE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Clear SDIO idle interrupt state*/ -#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) +/*description: Clear SDIO idle interrupt state.*/ +#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_CLR_M (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x1 #define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2 /* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Clear sleep reject interrupt state*/ -#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) +/*description: Clear sleep reject interrupt state.*/ +#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 #define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 /* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Clear sleep wakeup interrupt state*/ -#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) +/*description: Clear sleep wakeup interrupt state.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 -#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x0050) +#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x50) /* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH0 0xFFFFFFFF +/*description: .*/ +#define RTC_CNTL_SCRATCH0 0xFFFFFFFF #define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) #define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH0_S 0 -#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x0054) +#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x54) /* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH1 0xFFFFFFFF +/*description: .*/ +#define RTC_CNTL_SCRATCH1 0xFFFFFFFF #define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) #define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH1_S 0 -#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x0058) +#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x58) /* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH2 0xFFFFFFFF +/*description: .*/ +#define RTC_CNTL_SCRATCH2 0xFFFFFFFF #define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) #define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH2_S 0 -#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x005C) +#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x5C) /* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH3 0xFFFFFFFF +/*description: .*/ +#define RTC_CNTL_SCRATCH3 0xFFFFFFFF #define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) #define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH3_S 0 -#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0060) +#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) /* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) +/*description: .*/ +#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) #define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) #define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 #define RTC_CNTL_XTL_EXT_CTR_EN_S 31 /* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: 0: power down XTAL at high level*/ -#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) +/*description: 0: power down XTAL at high level.*/ +#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) #define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) #define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 #define RTC_CNTL_XTL_EXT_CTR_LV_S 30 /* RTC_CNTL_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: XTAL_32K sel. 0: external XTAL_32K*/ -#define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) +/*description: XTAL_32K sel. 0: external XTAL_32K.*/ +#define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) #define RTC_CNTL_XTAL32K_GPIO_SEL_M (BIT(23)) #define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x1 #define RTC_CNTL_XTAL32K_GPIO_SEL_S 23 /* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */ -/*description: state of 32k_wdt*/ -#define RTC_CNTL_WDT_STATE 0x00000007 +/*description: state of 32k_wdt.*/ +#define RTC_CNTL_WDT_STATE 0x00000007 #define RTC_CNTL_WDT_STATE_M ((RTC_CNTL_WDT_STATE_V)<<(RTC_CNTL_WDT_STATE_S)) #define RTC_CNTL_WDT_STATE_V 0x7 #define RTC_CNTL_WDT_STATE_S 20 /* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */ -/*description: DAC_XTAL_32K*/ -#define RTC_CNTL_DAC_XTAL_32K 0x00000007 +/*description: DAC_XTAL_32K.*/ +#define RTC_CNTL_DAC_XTAL_32K 0x00000007 #define RTC_CNTL_DAC_XTAL_32K_M ((RTC_CNTL_DAC_XTAL_32K_V)<<(RTC_CNTL_DAC_XTAL_32K_S)) #define RTC_CNTL_DAC_XTAL_32K_V 0x7 #define RTC_CNTL_DAC_XTAL_32K_S 17 /* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: XPD_XTAL_32K*/ -#define RTC_CNTL_XPD_XTAL_32K (BIT(16)) +/*description: XPD_XTAL_32K.*/ +#define RTC_CNTL_XPD_XTAL_32K (BIT(16)) #define RTC_CNTL_XPD_XTAL_32K_M (BIT(16)) #define RTC_CNTL_XPD_XTAL_32K_V 0x1 #define RTC_CNTL_XPD_XTAL_32K_S 16 /* RTC_CNTL_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */ -/*description: DRES_XTAL_32K*/ -#define RTC_CNTL_DRES_XTAL_32K 0x00000007 +/*description: DRES_XTAL_32K.*/ +#define RTC_CNTL_DRES_XTAL_32K 0x00000007 #define RTC_CNTL_DRES_XTAL_32K_M ((RTC_CNTL_DRES_XTAL_32K_V)<<(RTC_CNTL_DRES_XTAL_32K_S)) #define RTC_CNTL_DRES_XTAL_32K_V 0x7 #define RTC_CNTL_DRES_XTAL_32K_S 13 /* RTC_CNTL_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ -/*description: xtal_32k gm control*/ -#define RTC_CNTL_DGM_XTAL_32K 0x00000007 +/*description: xtal_32k gm control.*/ +#define RTC_CNTL_DGM_XTAL_32K 0x00000007 #define RTC_CNTL_DGM_XTAL_32K_M ((RTC_CNTL_DGM_XTAL_32K_V)<<(RTC_CNTL_DGM_XTAL_32K_S)) #define RTC_CNTL_DGM_XTAL_32K_V 0x7 #define RTC_CNTL_DGM_XTAL_32K_S 10 /* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: 0: single-end buffer 1: differential buffer*/ -#define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) +/*description: 0: single-end buffer 1: differential buffer.*/ +#define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) #define RTC_CNTL_DBUF_XTAL_32K_M (BIT(9)) #define RTC_CNTL_DBUF_XTAL_32K_V 0x1 #define RTC_CNTL_DBUF_XTAL_32K_S 9 /* RTC_CNTL_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: apply an internal clock to help xtal 32k to start*/ -#define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) +/*description: apply an internal clock to help xtal 32k to start.*/ +#define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) #define RTC_CNTL_ENCKINIT_XTAL_32K_M (BIT(8)) #define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x1 #define RTC_CNTL_ENCKINIT_XTAL_32K_S 8 /* RTC_CNTL_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: Xtal 32k xpd control by sw or fsm*/ -#define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) +/*description: Xtal 32k xpd control by sw or fsm.*/ +#define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) #define RTC_CNTL_XTAL32K_XPD_FORCE_M (BIT(7)) #define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x1 #define RTC_CNTL_XTAL32K_XPD_FORCE_S 7 /* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: xtal 32k switch back xtal when xtal is restarted*/ -#define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) +/*description: xtal 32k switch back xtal when xtal is restarted.*/ +#define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) #define RTC_CNTL_XTAL32K_AUTO_RETURN_M (BIT(6)) #define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x1 #define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6 /* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: xtal 32k restart xtal when xtal is dead*/ -#define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) +/*description: xtal 32k restart xtal when xtal is dead.*/ +#define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) #define RTC_CNTL_XTAL32K_AUTO_RESTART_M (BIT(5)) #define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x1 #define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5 /* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: xtal 32k switch to back up clock when xtal is dead*/ -#define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) +/*description: xtal 32k switch to back up clock when xtal is dead.*/ +#define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) #define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (BIT(4)) #define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x1 #define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4 /* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: xtal 32k external xtal clock force on*/ -#define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) +/*description: xtal 32k external xtal clock force on.*/ +#define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) #define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (BIT(3)) #define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x1 #define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3 /* RTC_CNTL_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: xtal 32k watch dog sw reset*/ -#define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) +/*description: xtal 32k watch dog sw reset.*/ +#define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) #define RTC_CNTL_XTAL32K_WDT_RESET_M (BIT(2)) #define RTC_CNTL_XTAL32K_WDT_RESET_V 0x1 #define RTC_CNTL_XTAL32K_WDT_RESET_S 2 /* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: xtal 32k watch dog clock force on*/ -#define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) +/*description: xtal 32k watch dog clock force on.*/ +#define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) #define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (BIT(1)) #define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x1 #define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1 /* RTC_CNTL_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: xtal 32k watch dog enable*/ -#define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) +/*description: xtal 32k watch dog enable.*/ +#define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) #define RTC_CNTL_XTAL32K_WDT_EN_M (BIT(0)) #define RTC_CNTL_XTAL32K_WDT_EN_V 0x1 #define RTC_CNTL_XTAL32K_WDT_EN_S 0 -#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0064) +#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) /* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) +/*description: .*/ +#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) #define RTC_CNTL_EXT_WAKEUP1_LV_M (BIT(31)) #define RTC_CNTL_EXT_WAKEUP1_LV_V 0x1 #define RTC_CNTL_EXT_WAKEUP1_LV_S 31 /* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: 0: external wakeup at low level*/ -#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) +/*description: 0: external wakeup at low level.*/ +#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) #define RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30)) #define RTC_CNTL_EXT_WAKEUP0_LV_V 0x1 #define RTC_CNTL_EXT_WAKEUP0_LV_S 30 /* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: enable filter for gpio wakeup event*/ -#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(29)) +/*description: enable filter for gpio wakeup event.*/ +#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(29)) #define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(29)) #define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 #define RTC_CNTL_GPIO_WAKEUP_FILTER_S 29 -#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0068) +#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) /* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: enable reject for deep sleep*/ -#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) +/*description: enable reject for deep sleep.*/ +#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) #define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(31)) #define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 #define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31 /* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: enable reject for light sleep*/ -#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) +/*description: enable reject for light sleep.*/ +#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) #define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(30)) #define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 /* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:12] ;default: 17'd0 ; */ -/*description: sleep reject enable*/ -#define RTC_CNTL_SLEEP_REJECT_ENA 0x0003FFFF +/*description: sleep reject enable.*/ +#define RTC_CNTL_SLEEP_REJECT_ENA 0x0003FFFF #define RTC_CNTL_SLEEP_REJECT_ENA_M ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S)) #define RTC_CNTL_SLEEP_REJECT_ENA_V 0x3FFFF #define RTC_CNTL_SLEEP_REJECT_ENA_S 12 -#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x006C) +#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6C) /* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ -/*description: */ -#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 +/*description: .*/ +#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 #define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) #define RTC_CNTL_CPUPERIOD_SEL_V 0x3 #define RTC_CNTL_CPUPERIOD_SEL_S 30 /* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: CPU sel option*/ -#define RTC_CNTL_CPUSEL_CONF (BIT(29)) +/*description: CPU sel option.*/ +#define RTC_CNTL_CPUSEL_CONF (BIT(29)) #define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) #define RTC_CNTL_CPUSEL_CONF_V 0x1 #define RTC_CNTL_CPUSEL_CONF_S 29 -#define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0070) +#define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) /* RTC_CNTL_SDIO_ACT_DNUM : R/W ;bitpos:[31:22] ;default: 10'b0 ; */ -/*description: */ -#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF +/*description: .*/ +#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF #define RTC_CNTL_SDIO_ACT_DNUM_M ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S)) #define RTC_CNTL_SDIO_ACT_DNUM_V 0x3FF #define RTC_CNTL_SDIO_ACT_DNUM_S 22 -#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0074) +#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) /* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: */ -#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 +/*description: .*/ +#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 #define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) #define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 #define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 /* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: fast_clk_rtc sel. 0: XTAL div 4*/ -#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) +/*description: fast_clk_rtc sel. 0: XTAL div 4.*/ +#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) #define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) #define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 #define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 +/* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: .*/ +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING (BIT(28)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M (BIT(28)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S 28 +/* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING (BIT(27)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M (BIT(27)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V 0x1 +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S 27 /* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ -/*description: CK8M force power up*/ -#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) +/*description: CK8M force power up.*/ +#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) #define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) #define RTC_CNTL_CK8M_FORCE_PU_V 0x1 #define RTC_CNTL_CK8M_FORCE_PU_S 26 /* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ -/*description: CK8M force power down*/ -#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) +/*description: CK8M force power down.*/ +#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) #define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) #define RTC_CNTL_CK8M_FORCE_PD_V 0x1 #define RTC_CNTL_CK8M_FORCE_PD_S 25 /* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd172 ; */ -/*description: CK8M_DFREQ*/ -#define RTC_CNTL_CK8M_DFREQ 0x000000FF +/*description: CK8M_DFREQ.*/ +#define RTC_CNTL_CK8M_DFREQ 0x000000FF #define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) #define RTC_CNTL_CK8M_DFREQ_V 0xFF #define RTC_CNTL_CK8M_DFREQ_S 17 /* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: CK8M force no gating during sleep*/ -#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) +/*description: CK8M force no gating during sleep.*/ +#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) #define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) #define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 #define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 /* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: XTAL force no gating during sleep*/ -#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) +/*description: XTAL force no gating during sleep.*/ +#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) #define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) #define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 #define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 /* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd3 ; */ -/*description: divider = reg_ck8m_div_sel + 1*/ -#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 +/*description: divider = reg_ck8m_div_sel + 1.*/ +#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 #define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) #define RTC_CNTL_CK8M_DIV_SEL_V 0x7 #define RTC_CNTL_CK8M_DIV_SEL_S 12 /* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: enable CK8M for digital core (no relationship with RTC core)*/ -#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) +/*description: enable CK8M for digital core (no relationship with RTC core).*/ +#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) #define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) #define RTC_CNTL_DIG_CLK8M_EN_V 0x1 #define RTC_CNTL_DIG_CLK8M_EN_S 10 /* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ -/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ -#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) +/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core).*/ +#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) #define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) #define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 #define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 /* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ -#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) +/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core).*/ +#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) #define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) #define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 #define RTC_CNTL_DIG_XTAL32K_EN_S 8 /* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: 1: CK8M_D256_OUT is actually CK8M*/ -#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) +/*description: 1: CK8M_D256_OUT is actually CK8M.*/ +#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) #define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) #define RTC_CNTL_ENB_CK8M_DIV_V 0x1 #define RTC_CNTL_ENB_CK8M_DIV_S 7 /* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: disable CK8M and CK8M_D256_OUT*/ -#define RTC_CNTL_ENB_CK8M (BIT(6)) +/*description: disable CK8M and CK8M_D256_OUT.*/ +#define RTC_CNTL_ENB_CK8M (BIT(6)) #define RTC_CNTL_ENB_CK8M_M (BIT(6)) #define RTC_CNTL_ENB_CK8M_V 0x1 #define RTC_CNTL_ENB_CK8M_S 6 /* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ -/*description: CK8M_D256_OUT divider. 00: div128*/ -#define RTC_CNTL_CK8M_DIV 0x00000003 +/*description: CK8M_D256_OUT divider. 00: div128.*/ +#define RTC_CNTL_CK8M_DIV 0x00000003 #define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) #define RTC_CNTL_CK8M_DIV_V 0x3 #define RTC_CNTL_CK8M_DIV_S 4 /* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/ -#define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) +/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel.*/ +#define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) #define RTC_CNTL_CK8M_DIV_SEL_VLD_M (BIT(3)) #define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x1 #define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3 +/* RTC_CNTL_EFUSE_CLK_FORCE_NOGATING : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: .*/ +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING (BIT(2)) +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M (BIT(2)) +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S 2 +/* RTC_CNTL_EFUSE_CLK_FORCE_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING (BIT(1)) +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M (BIT(1)) +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V 0x1 +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S 1 -#define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0078) +#define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) /* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) +/*description: .*/ +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) #define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M (BIT(31)) #define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V 0x1 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S 31 /* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */ -/*description: */ -#define RTC_CNTL_ANA_CLK_DIV 0x000000FF +/*description: .*/ +#define RTC_CNTL_ANA_CLK_DIV 0x000000FF #define RTC_CNTL_ANA_CLK_DIV_M ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S)) #define RTC_CNTL_ANA_CLK_DIV_V 0xFF #define RTC_CNTL_ANA_CLK_DIV_S 23 /* RTC_CNTL_ANA_CLK_DIV_VLD : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/ -#define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) +/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div.*/ +#define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) #define RTC_CNTL_ANA_CLK_DIV_VLD_M (BIT(22)) #define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x1 #define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 -#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x007C) +#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x7C) /* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) +/*description: .*/ +#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) #define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) #define RTC_CNTL_XPD_SDIO_REG_V 0x1 #define RTC_CNTL_XPD_SDIO_REG_S 31 /* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ -/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ -#define RTC_CNTL_DREFH_SDIO 0x00000003 +/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1.*/ +#define RTC_CNTL_DREFH_SDIO 0x00000003 #define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) #define RTC_CNTL_DREFH_SDIO_V 0x3 #define RTC_CNTL_DREFH_SDIO_S 29 /* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b01 ; */ -/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ -#define RTC_CNTL_DREFM_SDIO 0x00000003 +/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1.*/ +#define RTC_CNTL_DREFM_SDIO 0x00000003 #define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) #define RTC_CNTL_DREFM_SDIO_V 0x3 #define RTC_CNTL_DREFM_SDIO_S 27 /* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ -/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ -#define RTC_CNTL_DREFL_SDIO 0x00000003 +/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1.*/ +#define RTC_CNTL_DREFL_SDIO 0x00000003 #define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) #define RTC_CNTL_DREFL_SDIO_V 0x3 #define RTC_CNTL_DREFL_SDIO_S 25 /* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ -/*description: read only register for REG1P8_READY*/ -#define RTC_CNTL_REG1P8_READY (BIT(24)) +/*description: read only register for REG1P8_READY.*/ +#define RTC_CNTL_REG1P8_READY (BIT(24)) #define RTC_CNTL_REG1P8_READY_M (BIT(24)) #define RTC_CNTL_REG1P8_READY_V 0x1 #define RTC_CNTL_REG1P8_READY_S 24 /* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ -/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ -#define RTC_CNTL_SDIO_TIEH (BIT(23)) +/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1.*/ +#define RTC_CNTL_SDIO_TIEH (BIT(23)) #define RTC_CNTL_SDIO_TIEH_M (BIT(23)) #define RTC_CNTL_SDIO_TIEH_V 0x1 #define RTC_CNTL_SDIO_TIEH_S 23 /* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: 1: use SW option to control SDIO_REG*/ -#define RTC_CNTL_SDIO_FORCE (BIT(22)) +/*description: 1: use SW option to control SDIO_REG.*/ +#define RTC_CNTL_SDIO_FORCE (BIT(22)) #define RTC_CNTL_SDIO_FORCE_M (BIT(22)) #define RTC_CNTL_SDIO_FORCE_V 0x1 #define RTC_CNTL_SDIO_FORCE_S 22 /* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ -/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ -#define RTC_CNTL_SDIO_PD_EN (BIT(21)) +/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0.*/ +#define RTC_CNTL_SDIO_PD_EN (BIT(21)) #define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) #define RTC_CNTL_SDIO_PD_EN_V 0x1 #define RTC_CNTL_SDIO_PD_EN_S 21 /* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */ -/*description: enable current limit*/ -#define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) +/*description: enable current limit.*/ +#define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) #define RTC_CNTL_SDIO_ENCURLIM_M (BIT(20)) #define RTC_CNTL_SDIO_ENCURLIM_V 0x1 #define RTC_CNTL_SDIO_ENCURLIM_S 20 /* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: select current limit mode*/ -#define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) +/*description: select current limit mode.*/ +#define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) #define RTC_CNTL_SDIO_MODECURLIM_M (BIT(19)) #define RTC_CNTL_SDIO_MODECURLIM_V 0x1 #define RTC_CNTL_SDIO_MODECURLIM_S 19 /* RTC_CNTL_SDIO_DCURLIM : R/W ;bitpos:[18:16] ;default: 3'd0 ; */ -/*description: tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ -#define RTC_CNTL_SDIO_DCURLIM 0x00000007 +/*description: tune current limit threshold when tieh = 0. About 800mA/(8+d).*/ +#define RTC_CNTL_SDIO_DCURLIM 0x00000007 #define RTC_CNTL_SDIO_DCURLIM_M ((RTC_CNTL_SDIO_DCURLIM_V)<<(RTC_CNTL_SDIO_DCURLIM_S)) #define RTC_CNTL_SDIO_DCURLIM_V 0x7 #define RTC_CNTL_SDIO_DCURLIM_S 16 /* RTC_CNTL_SDIO_EN_INITI : R/W ;bitpos:[15] ;default: 1'd1 ; */ -/*description: 0 to set init[1:0]=0*/ -#define RTC_CNTL_SDIO_EN_INITI (BIT(15)) +/*description: 0 to set init[1:0]=0.*/ +#define RTC_CNTL_SDIO_EN_INITI (BIT(15)) #define RTC_CNTL_SDIO_EN_INITI_M (BIT(15)) #define RTC_CNTL_SDIO_EN_INITI_V 0x1 #define RTC_CNTL_SDIO_EN_INITI_S 15 /* RTC_CNTL_SDIO_INITI : R/W ;bitpos:[14:13] ;default: 2'd1 ; */ -/*description: add resistor from ldo output to ground. 0: no res*/ -#define RTC_CNTL_SDIO_INITI 0x00000003 +/*description: add resistor from ldo output to ground. 0: no res.*/ +#define RTC_CNTL_SDIO_INITI 0x00000003 #define RTC_CNTL_SDIO_INITI_M ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S)) #define RTC_CNTL_SDIO_INITI_V 0x3 #define RTC_CNTL_SDIO_INITI_S 13 /* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */ -/*description: ability to prevent LDO from overshoot*/ -#define RTC_CNTL_SDIO_DCAP 0x00000003 +/*description: ability to prevent LDO from overshoot.*/ +#define RTC_CNTL_SDIO_DCAP 0x00000003 #define RTC_CNTL_SDIO_DCAP_M ((RTC_CNTL_SDIO_DCAP_V)<<(RTC_CNTL_SDIO_DCAP_S)) #define RTC_CNTL_SDIO_DCAP_V 0x3 #define RTC_CNTL_SDIO_DCAP_S 11 /* RTC_CNTL_SDIO_DTHDRV : R/W ;bitpos:[10:9] ;default: 2'b11 ; */ -/*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/ -#define RTC_CNTL_SDIO_DTHDRV 0x00000003 +/*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current.*/ +#define RTC_CNTL_SDIO_DTHDRV 0x00000003 #define RTC_CNTL_SDIO_DTHDRV_M ((RTC_CNTL_SDIO_DTHDRV_V)<<(RTC_CNTL_SDIO_DTHDRV_S)) #define RTC_CNTL_SDIO_DTHDRV_V 0x3 #define RTC_CNTL_SDIO_DTHDRV_S 9 /* RTC_CNTL_SDIO_TIMER_TARGET : R/W ;bitpos:[7:0] ;default: 8'd10 ; */ -/*description: timer count to apply reg_sdio_dcap after sdio power on*/ -#define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF +/*description: timer count to apply reg_sdio_dcap after sdio power on.*/ +#define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF #define RTC_CNTL_SDIO_TIMER_TARGET_M ((RTC_CNTL_SDIO_TIMER_TARGET_V)<<(RTC_CNTL_SDIO_TIMER_TARGET_S)) #define RTC_CNTL_SDIO_TIMER_TARGET_V 0xFF #define RTC_CNTL_SDIO_TIMER_TARGET_S 0 -#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0080) +#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x80) /* RTC_CNTL_DBG_ATTEN_WAKEUP : R/W ;bitpos:[29:26] ;default: 4'd0 ; */ -/*description: */ -#define RTC_CNTL_DBG_ATTEN_WAKEUP 0x0000000F +/*description: .*/ +#define RTC_CNTL_DBG_ATTEN_WAKEUP 0x0000000F #define RTC_CNTL_DBG_ATTEN_WAKEUP_M ((RTC_CNTL_DBG_ATTEN_WAKEUP_V)<<(RTC_CNTL_DBG_ATTEN_WAKEUP_S)) #define RTC_CNTL_DBG_ATTEN_WAKEUP_V 0xF #define RTC_CNTL_DBG_ATTEN_WAKEUP_S 26 /* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */ -/*description: DBG_ATTEN when rtc in monitor state*/ -#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F +/*description: DBG_ATTEN when rtc in monitor state.*/ +#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F #define RTC_CNTL_DBG_ATTEN_MONITOR_M ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S)) #define RTC_CNTL_DBG_ATTEN_MONITOR_V 0xF #define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 /* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W ;bitpos:[21:18] ;default: 4'd0 ; */ -/*description: DBG_ATTEN when rtc in sleep state*/ -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F +/*description: DBG_ATTEN when rtc in sleep state.*/ +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F #define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S)) #define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0xF #define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 /* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: bias_sleep when rtc in monitor state*/ -#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) +/*description: bias_sleep when rtc in monitor state.*/ +#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) #define RTC_CNTL_BIAS_SLEEP_MONITOR_M (BIT(17)) #define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x1 #define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 /* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W ;bitpos:[16] ;default: 1'b1 ; */ -/*description: bias_sleep when rtc in sleep_state*/ -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) +/*description: bias_sleep when rtc in sleep_state.*/ +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (BIT(16)) #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x1 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 /* RTC_CNTL_PD_CUR_MONITOR : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: xpd cur when rtc in monitor state*/ -#define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) +/*description: xpd cur when rtc in monitor state.*/ +#define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) #define RTC_CNTL_PD_CUR_MONITOR_M (BIT(15)) #define RTC_CNTL_PD_CUR_MONITOR_V 0x1 #define RTC_CNTL_PD_CUR_MONITOR_S 15 /* RTC_CNTL_PD_CUR_DEEP_SLP : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: xpd cur when rtc in sleep_state*/ -#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) +/*description: xpd cur when rtc in sleep_state.*/ +#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) #define RTC_CNTL_PD_CUR_DEEP_SLP_M (BIT(14)) #define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x1 #define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 /* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) +/*description: .*/ +#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) #define RTC_CNTL_BIAS_BUF_MONITOR_M (BIT(13)) #define RTC_CNTL_BIAS_BUF_MONITOR_V 0x1 #define RTC_CNTL_BIAS_BUF_MONITOR_S 13 /* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) +/*description: .*/ +#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) #define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (BIT(12)) #define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x1 #define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 /* RTC_CNTL_BIAS_BUF_WAKE : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) +/*description: .*/ +#define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) #define RTC_CNTL_BIAS_BUF_WAKE_M (BIT(11)) #define RTC_CNTL_BIAS_BUF_WAKE_V 0x1 #define RTC_CNTL_BIAS_BUF_WAKE_S 11 /* RTC_CNTL_BIAS_BUF_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) +/*description: .*/ +#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) #define RTC_CNTL_BIAS_BUF_IDLE_M (BIT(10)) #define RTC_CNTL_BIAS_BUF_IDLE_V 0x1 #define RTC_CNTL_BIAS_BUF_IDLE_S 10 -#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x0084) +#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x84) /* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ -/*description: */ -#define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) +/*description: .*/ +#define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) #define RTC_CNTL_REGULATOR_FORCE_PU_M (BIT(31)) #define RTC_CNTL_REGULATOR_FORCE_PU_V 0x1 #define RTC_CNTL_REGULATOR_FORCE_PU_S 31 /* RTC_CNTL_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: RTC_REG force power down (for RTC_REG power down means decrease - the voltage to 0.8v or lower )*/ -#define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) +/*description: RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0 +.8v or lower ).*/ +#define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) #define RTC_CNTL_REGULATOR_FORCE_PD_M (BIT(30)) #define RTC_CNTL_REGULATOR_FORCE_PD_V 0x1 #define RTC_CNTL_REGULATOR_FORCE_PD_S 30 /* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ -/*description: RTC_DBOOST force power up*/ -#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) +/*description: RTC_DBOOST force power up.*/ +#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) #define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) #define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 #define RTC_CNTL_DBOOST_FORCE_PU_S 29 /* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: RTC_DBOOST force power down*/ -#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) +/*description: RTC_DBOOST force power down.*/ +#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) #define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) #define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 #define RTC_CNTL_DBOOST_FORCE_PD_S 28 @@ -1629,364 +1654,390 @@ extern "C" { /* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ -/*description: SCK_DCAP*/ -#define RTC_CNTL_SCK_DCAP 0x000000FF +/*description: SCK_DCAP.*/ +#define RTC_CNTL_SCK_DCAP 0x000000FF #define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) #define RTC_CNTL_SCK_DCAP_V 0xFF #define RTC_CNTL_SCK_DCAP_S 14 /* RTC_CNTL_DIG_CAL_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_DIG_CAL_EN (BIT(7)) +/*description: .*/ +#define RTC_CNTL_DIG_CAL_EN (BIT(7)) #define RTC_CNTL_DIG_CAL_EN_M (BIT(7)) #define RTC_CNTL_DIG_CAL_EN_V 0x1 #define RTC_CNTL_DIG_CAL_EN_S 7 -#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x0088) +#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x88) /* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: rtc pad force hold*/ -#define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) +/*description: rtc pad force hold.*/ +#define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) #define RTC_CNTL_PAD_FORCE_HOLD_M (BIT(21)) #define RTC_CNTL_PAD_FORCE_HOLD_V 0x1 #define RTC_CNTL_PAD_FORCE_HOLD_S 21 /* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: enable power down rtc_peri in sleep*/ -#define RTC_CNTL_PD_EN (BIT(20)) +/*description: enable power down rtc_peri in sleep .*/ +#define RTC_CNTL_PD_EN (BIT(20)) #define RTC_CNTL_PD_EN_M (BIT(20)) #define RTC_CNTL_PD_EN_V 0x1 #define RTC_CNTL_PD_EN_S 20 /* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: rtc_peri force power up*/ -#define RTC_CNTL_FORCE_PU (BIT(19)) +/*description: rtc_peri force power up.*/ +#define RTC_CNTL_FORCE_PU (BIT(19)) #define RTC_CNTL_FORCE_PU_M (BIT(19)) #define RTC_CNTL_FORCE_PU_V 0x1 #define RTC_CNTL_FORCE_PU_S 19 /* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: rtc_peri force power down*/ -#define RTC_CNTL_FORCE_PD (BIT(18)) +/*description: rtc_peri force power down.*/ +#define RTC_CNTL_FORCE_PD (BIT(18)) #define RTC_CNTL_FORCE_PD_M (BIT(18)) #define RTC_CNTL_FORCE_PD_V 0x1 #define RTC_CNTL_FORCE_PD_S 18 /* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: RTC memory force no PD*/ -#define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) +/*description: RTC memory force no PD.*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) #define RTC_CNTL_SLOWMEM_FORCE_LPU_M (BIT(11)) #define RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x1 #define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 /* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: RTC memory force PD*/ -#define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) +/*description: RTC memory force PD.*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) #define RTC_CNTL_SLOWMEM_FORCE_LPD_M (BIT(10)) #define RTC_CNTL_SLOWMEM_FORCE_LPD_V 0x1 #define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 /* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: 1: RTC memory PD following CPU*/ -#define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) +/*description: 1: RTC memory PD following CPU.*/ +#define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) #define RTC_CNTL_SLOWMEM_FOLW_CPU_M (BIT(9)) #define RTC_CNTL_SLOWMEM_FOLW_CPU_V 0x1 #define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 /* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: Fast RTC memory force no PD*/ -#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) +/*description: Fast RTC memory force no PD.*/ +#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) #define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(8)) #define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 #define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 /* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Fast RTC memory force PD*/ -#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) +/*description: Fast RTC memory force PD.*/ +#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) #define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(7)) #define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 #define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 /* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: 1: Fast RTC memory PD following CPU*/ -#define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) +/*description: 1: Fast RTC memory PD following CPU.*/ +#define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) #define RTC_CNTL_FASTMEM_FOLW_CPU_M (BIT(6)) #define RTC_CNTL_FASTMEM_FOLW_CPU_V 0x1 #define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 /* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */ -/*description: rtc_peri force no ISO*/ -#define RTC_CNTL_FORCE_NOISO (BIT(5)) +/*description: rtc_peri force no ISO.*/ +#define RTC_CNTL_FORCE_NOISO (BIT(5)) #define RTC_CNTL_FORCE_NOISO_M (BIT(5)) #define RTC_CNTL_FORCE_NOISO_V 0x1 #define RTC_CNTL_FORCE_NOISO_S 5 /* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: rtc_peri force ISO*/ -#define RTC_CNTL_FORCE_ISO (BIT(4)) +/*description: rtc_peri force ISO.*/ +#define RTC_CNTL_FORCE_ISO (BIT(4)) #define RTC_CNTL_FORCE_ISO_M (BIT(4)) #define RTC_CNTL_FORCE_ISO_V 0x1 #define RTC_CNTL_FORCE_ISO_S 4 /* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: RTC memory force ISO*/ -#define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) +/*description: RTC memory force ISO.*/ +#define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) #define RTC_CNTL_SLOWMEM_FORCE_ISO_M (BIT(3)) #define RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x1 #define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 /* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: RTC memory force no ISO*/ -#define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) +/*description: RTC memory force no ISO.*/ +#define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) #define RTC_CNTL_SLOWMEM_FORCE_NOISO_M (BIT(2)) #define RTC_CNTL_SLOWMEM_FORCE_NOISO_V 0x1 #define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 /* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Fast RTC memory force ISO*/ -#define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) +/*description: Fast RTC memory force ISO.*/ +#define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) #define RTC_CNTL_FASTMEM_FORCE_ISO_M (BIT(1)) #define RTC_CNTL_FASTMEM_FORCE_ISO_V 0x1 #define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 /* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: Fast RTC memory force no ISO*/ -#define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) +/*description: Fast RTC memory force no ISO.*/ +#define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) #define RTC_CNTL_FASTMEM_FORCE_NOISO_M (BIT(0)) #define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x1 #define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 -#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x008C) +#define RTC_CNTL_REGULATOR_DRV_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x8C) +/* RTC_CNTL_DG_VDD_DRV_B_MONITOR : R/W ;bitpos:[27:20] ;default: 8'h0 ; */ +/*description: .*/ +#define RTC_CNTL_DG_VDD_DRV_B_MONITOR 0x000000FF +#define RTC_CNTL_DG_VDD_DRV_B_MONITOR_M ((RTC_CNTL_DG_VDD_DRV_B_MONITOR_V)<<(RTC_CNTL_DG_VDD_DRV_B_MONITOR_S)) +#define RTC_CNTL_DG_VDD_DRV_B_MONITOR_V 0xFF +#define RTC_CNTL_DG_VDD_DRV_B_MONITOR_S 20 +/* RTC_CNTL_DG_VDD_DRV_B_SLP : R/W ;bitpos:[19:12] ;default: 8'h0 ; */ +/*description: .*/ +#define RTC_CNTL_DG_VDD_DRV_B_SLP 0x000000FF +#define RTC_CNTL_DG_VDD_DRV_B_SLP_M ((RTC_CNTL_DG_VDD_DRV_B_SLP_V)<<(RTC_CNTL_DG_VDD_DRV_B_SLP_S)) +#define RTC_CNTL_DG_VDD_DRV_B_SLP_V 0xFF +#define RTC_CNTL_DG_VDD_DRV_B_SLP_S 12 +/* RTC_CNTL_REGULATOR_DRV_B_SLP : R/W ;bitpos:[11:6] ;default: 6'b0 ; */ +/*description: .*/ +#define RTC_CNTL_REGULATOR_DRV_B_SLP 0x0000003F +#define RTC_CNTL_REGULATOR_DRV_B_SLP_M ((RTC_CNTL_REGULATOR_DRV_B_SLP_V)<<(RTC_CNTL_REGULATOR_DRV_B_SLP_S)) +#define RTC_CNTL_REGULATOR_DRV_B_SLP_V 0x3F +#define RTC_CNTL_REGULATOR_DRV_B_SLP_S 6 +/* RTC_CNTL_REGULATOR_DRV_B_MONITOR : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/*description: .*/ +#define RTC_CNTL_REGULATOR_DRV_B_MONITOR 0x0000003F +#define RTC_CNTL_REGULATOR_DRV_B_MONITOR_M ((RTC_CNTL_REGULATOR_DRV_B_MONITOR_V)<<(RTC_CNTL_REGULATOR_DRV_B_MONITOR_S)) +#define RTC_CNTL_REGULATOR_DRV_B_MONITOR_V 0x3F +#define RTC_CNTL_REGULATOR_DRV_B_MONITOR_S 0 + +#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x90) /* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) +/*description: .*/ +#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) #define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) #define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 #define RTC_CNTL_DG_WRAP_PD_EN_S 31 /* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0 ; */ -/*description: enable power down wifi in sleep*/ -#define RTC_CNTL_WIFI_PD_EN (BIT(30)) +/*description: enable power down wifi in sleep.*/ +#define RTC_CNTL_WIFI_PD_EN (BIT(30)) #define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) #define RTC_CNTL_WIFI_PD_EN_V 0x1 #define RTC_CNTL_WIFI_PD_EN_S 30 /* RTC_CNTL_CPU_TOP_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */ -/*description: enable power down internal SRAM 4 in sleep*/ -#define RTC_CNTL_CPU_TOP_PD_EN (BIT(29)) +/*description: enable power down internal SRAM 4 in sleep.*/ +#define RTC_CNTL_CPU_TOP_PD_EN (BIT(29)) #define RTC_CNTL_CPU_TOP_PD_EN_M (BIT(29)) #define RTC_CNTL_CPU_TOP_PD_EN_V 0x1 #define RTC_CNTL_CPU_TOP_PD_EN_S 29 /* RTC_CNTL_DG_PERI_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */ -/*description: enable power down internal SRAM 3 in sleep*/ -#define RTC_CNTL_DG_PERI_PD_EN (BIT(28)) +/*description: enable power down internal SRAM 3 in sleep.*/ +#define RTC_CNTL_DG_PERI_PD_EN (BIT(28)) #define RTC_CNTL_DG_PERI_PD_EN_M (BIT(28)) #define RTC_CNTL_DG_PERI_PD_EN_V 0x1 #define RTC_CNTL_DG_PERI_PD_EN_S 28 /* RTC_CNTL_BT_PD_EN : R/W ;bitpos:[27] ;default: 0 ; */ -/*description: enable power down internal SRAM 2 in sleep*/ -#define RTC_CNTL_BT_PD_EN (BIT(27)) +/*description: enable power down internal SRAM 2 in sleep.*/ +#define RTC_CNTL_BT_PD_EN (BIT(27)) #define RTC_CNTL_BT_PD_EN_M (BIT(27)) #define RTC_CNTL_BT_PD_EN_V 0x1 #define RTC_CNTL_BT_PD_EN_S 27 /* RTC_CNTL_CPU_TOP_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */ -/*description: digital dcdc force power up*/ -#define RTC_CNTL_CPU_TOP_FORCE_PU (BIT(22)) +/*description: digital dcdc force power up.*/ +#define RTC_CNTL_CPU_TOP_FORCE_PU (BIT(22)) #define RTC_CNTL_CPU_TOP_FORCE_PU_M (BIT(22)) #define RTC_CNTL_CPU_TOP_FORCE_PU_V 0x1 #define RTC_CNTL_CPU_TOP_FORCE_PU_S 22 /* RTC_CNTL_CPU_TOP_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: digital dcdc force power down*/ -#define RTC_CNTL_CPU_TOP_FORCE_PD (BIT(21)) +/*description: digital dcdc force power down.*/ +#define RTC_CNTL_CPU_TOP_FORCE_PD (BIT(21)) #define RTC_CNTL_CPU_TOP_FORCE_PD_M (BIT(21)) #define RTC_CNTL_CPU_TOP_FORCE_PD_V 0x1 #define RTC_CNTL_CPU_TOP_FORCE_PD_S 21 /* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */ -/*description: digital core force power up*/ -#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) +/*description: digital core force power up.*/ +#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) #define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) #define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 #define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 /* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: digital core force power down*/ -#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) +/*description: digital core force power down.*/ +#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) #define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) #define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 #define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 /* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ -/*description: wifi force power up*/ -#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) +/*description: wifi force power up.*/ +#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) #define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) #define RTC_CNTL_WIFI_FORCE_PU_V 0x1 #define RTC_CNTL_WIFI_FORCE_PU_S 18 /* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: wifi force power down*/ -#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) +/*description: wifi force power down.*/ +#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) #define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) #define RTC_CNTL_WIFI_FORCE_PD_V 0x1 #define RTC_CNTL_WIFI_FORCE_PD_S 17 /* RTC_CNTL_DG_PERI_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */ -/*description: internal SRAM 3 force power up*/ -#define RTC_CNTL_DG_PERI_FORCE_PU (BIT(14)) +/*description: internal SRAM 3 force power up.*/ +#define RTC_CNTL_DG_PERI_FORCE_PU (BIT(14)) #define RTC_CNTL_DG_PERI_FORCE_PU_M (BIT(14)) #define RTC_CNTL_DG_PERI_FORCE_PU_V 0x1 #define RTC_CNTL_DG_PERI_FORCE_PU_S 14 /* RTC_CNTL_DG_PERI_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: internal SRAM 3 force power down*/ -#define RTC_CNTL_DG_PERI_FORCE_PD (BIT(13)) +/*description: internal SRAM 3 force power down.*/ +#define RTC_CNTL_DG_PERI_FORCE_PD (BIT(13)) #define RTC_CNTL_DG_PERI_FORCE_PD_M (BIT(13)) #define RTC_CNTL_DG_PERI_FORCE_PD_V 0x1 #define RTC_CNTL_DG_PERI_FORCE_PD_S 13 /* RTC_CNTL_BT_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ -/*description: internal SRAM 2 force power up*/ -#define RTC_CNTL_BT_FORCE_PU (BIT(12)) +/*description: internal SRAM 2 force power up.*/ +#define RTC_CNTL_BT_FORCE_PU (BIT(12)) #define RTC_CNTL_BT_FORCE_PU_M (BIT(12)) #define RTC_CNTL_BT_FORCE_PU_V 0x1 #define RTC_CNTL_BT_FORCE_PU_S 12 /* RTC_CNTL_BT_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: internal SRAM 2 force power down*/ -#define RTC_CNTL_BT_FORCE_PD (BIT(11)) +/*description: internal SRAM 2 force power down.*/ +#define RTC_CNTL_BT_FORCE_PD (BIT(11)) #define RTC_CNTL_BT_FORCE_PD_M (BIT(11)) #define RTC_CNTL_BT_FORCE_PD_V 0x1 #define RTC_CNTL_BT_FORCE_PD_S 11 /* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: memories in digital core force no PD in sleep*/ -#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) +/*description: memories in digital core force no PD in sleep.*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) #define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) #define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 #define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 /* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: memories in digital core force PD in sleep*/ -#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) +/*description: memories in digital core force PD in sleep.*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) #define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) #define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 #define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 -#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x0090) +#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x94) /* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ -/*description: */ -#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) +/*description: .*/ +#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) #define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) #define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 /* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: digital core force ISO*/ -#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) +/*description: digital core force ISO.*/ +#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) #define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) #define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 #define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 /* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ -/*description: wifi force no ISO*/ -#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) +/*description: wifi force no ISO.*/ +#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) #define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) #define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 #define RTC_CNTL_WIFI_FORCE_NOISO_S 29 /* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: wifi force ISO*/ -#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) +/*description: wifi force ISO.*/ +#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) #define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) #define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 #define RTC_CNTL_WIFI_FORCE_ISO_S 28 /* RTC_CNTL_CPU_TOP_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ -/*description: internal SRAM 4 force no ISO*/ -#define RTC_CNTL_CPU_TOP_FORCE_NOISO (BIT(27)) +/*description: internal SRAM 4 force no ISO.*/ +#define RTC_CNTL_CPU_TOP_FORCE_NOISO (BIT(27)) #define RTC_CNTL_CPU_TOP_FORCE_NOISO_M (BIT(27)) #define RTC_CNTL_CPU_TOP_FORCE_NOISO_V 0x1 #define RTC_CNTL_CPU_TOP_FORCE_NOISO_S 27 /* RTC_CNTL_CPU_TOP_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ -/*description: internal SRAM 4 force ISO*/ -#define RTC_CNTL_CPU_TOP_FORCE_ISO (BIT(26)) +/*description: internal SRAM 4 force ISO.*/ +#define RTC_CNTL_CPU_TOP_FORCE_ISO (BIT(26)) #define RTC_CNTL_CPU_TOP_FORCE_ISO_M (BIT(26)) #define RTC_CNTL_CPU_TOP_FORCE_ISO_V 0x1 #define RTC_CNTL_CPU_TOP_FORCE_ISO_S 26 /* RTC_CNTL_DG_PERI_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ -/*description: internal SRAM 3 force no ISO*/ -#define RTC_CNTL_DG_PERI_FORCE_NOISO (BIT(25)) +/*description: internal SRAM 3 force no ISO.*/ +#define RTC_CNTL_DG_PERI_FORCE_NOISO (BIT(25)) #define RTC_CNTL_DG_PERI_FORCE_NOISO_M (BIT(25)) #define RTC_CNTL_DG_PERI_FORCE_NOISO_V 0x1 #define RTC_CNTL_DG_PERI_FORCE_NOISO_S 25 /* RTC_CNTL_DG_PERI_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: internal SRAM 3 force ISO*/ -#define RTC_CNTL_DG_PERI_FORCE_ISO (BIT(24)) +/*description: internal SRAM 3 force ISO.*/ +#define RTC_CNTL_DG_PERI_FORCE_ISO (BIT(24)) #define RTC_CNTL_DG_PERI_FORCE_ISO_M (BIT(24)) #define RTC_CNTL_DG_PERI_FORCE_ISO_V 0x1 #define RTC_CNTL_DG_PERI_FORCE_ISO_S 24 /* RTC_CNTL_BT_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ -/*description: internal SRAM 2 force no ISO*/ -#define RTC_CNTL_BT_FORCE_NOISO (BIT(23)) +/*description: internal SRAM 2 force no ISO.*/ +#define RTC_CNTL_BT_FORCE_NOISO (BIT(23)) #define RTC_CNTL_BT_FORCE_NOISO_M (BIT(23)) #define RTC_CNTL_BT_FORCE_NOISO_V 0x1 #define RTC_CNTL_BT_FORCE_NOISO_S 23 /* RTC_CNTL_BT_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: internal SRAM 2 force ISO*/ -#define RTC_CNTL_BT_FORCE_ISO (BIT(22)) +/*description: internal SRAM 2 force ISO.*/ +#define RTC_CNTL_BT_FORCE_ISO (BIT(22)) #define RTC_CNTL_BT_FORCE_ISO_M (BIT(22)) #define RTC_CNTL_BT_FORCE_ISO_V 0x1 #define RTC_CNTL_BT_FORCE_ISO_S 22 /* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: digital pad force hold*/ -#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) +/*description: digital pad force hold.*/ +#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) #define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) #define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 #define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 /* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ -/*description: digital pad force un-hold*/ -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) +/*description: digital pad force un-hold.*/ +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 /* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: digital pad force ISO*/ -#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) +/*description: digital pad force ISO.*/ +#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) #define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) #define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 #define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 /* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ -/*description: digital pad force no ISO*/ -#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) +/*description: digital pad force no ISO.*/ +#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) #define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) #define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 #define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 /* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: digital pad enable auto-hold*/ -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) +/*description: digital pad enable auto-hold.*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 /* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ -/*description: wtite only register to clear digital pad auto-hold*/ -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) +/*description: wtite only register to clear digital pad auto-hold.*/ +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 /* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: read only register to indicate digital pad auto-hold status*/ -#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) +/*description: read only register to indicate digital pad auto-hold status.*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) #define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) #define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 #define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 /* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) +/*description: .*/ +#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) #define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) #define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 #define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 /* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd1 ; */ -/*description: */ -#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) +/*description: .*/ +#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) #define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) #define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 #define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 -#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x0094) +#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x98) /* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define RTC_CNTL_WDT_EN (BIT(31)) +/*description: .*/ +#define RTC_CNTL_WDT_EN (BIT(31)) #define RTC_CNTL_WDT_EN_M (BIT(31)) #define RTC_CNTL_WDT_EN_V 0x1 #define RTC_CNTL_WDT_EN_S 31 /* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ -/*description: 1: interrupt stage en*/ -#define RTC_CNTL_WDT_STG0 0x00000007 +/*description: 1: interrupt stage en.*/ +#define RTC_CNTL_WDT_STG0 0x00000007 #define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) #define RTC_CNTL_WDT_STG0_V 0x7 #define RTC_CNTL_WDT_STG0_S 28 /* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ -/*description: 1: interrupt stage en*/ -#define RTC_CNTL_WDT_STG1 0x00000007 +/*description: 1: interrupt stage en.*/ +#define RTC_CNTL_WDT_STG1 0x00000007 #define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) #define RTC_CNTL_WDT_STG1_V 0x7 #define RTC_CNTL_WDT_STG1_S 25 /* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ -/*description: 1: interrupt stage en*/ -#define RTC_CNTL_WDT_STG2 0x00000007 +/*description: 1: interrupt stage en.*/ +#define RTC_CNTL_WDT_STG2 0x00000007 #define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) #define RTC_CNTL_WDT_STG2_V 0x7 #define RTC_CNTL_WDT_STG2_S 22 /* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ -/*description: 1: interrupt stage en*/ -#define RTC_CNTL_WDT_STG3 0x00000007 +/*description: 1: interrupt stage en.*/ +#define RTC_CNTL_WDT_STG3 0x00000007 #define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) #define RTC_CNTL_WDT_STG3_V 0x7 #define RTC_CNTL_WDT_STG3_S 19 @@ -2011,1497 +2062,1656 @@ extern "C" { #define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13 /* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ -/*description: enable WDT in flash boot*/ -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) +/*description: enable WDT in flash boot.*/ +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(12)) #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12 /* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: enable WDT reset PRO CPU*/ -#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) +/*description: enable WDT reset PRO CPU.*/ +#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) #define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(11)) #define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 #define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11 /* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: enable WDT reset APP CPU*/ -#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) +/*description: enable WDT reset APP CPU.*/ +#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) #define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(10)) #define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 #define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10 /* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[9] ;default: 1'd1 ; */ -/*description: pause WDT in sleep*/ -#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) +/*description: pause WDT in sleep.*/ +#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) #define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(9)) #define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 #define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9 /* RTC_CNTL_WDT_CHIP_RESET_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: wdt reset whole chip enable*/ -#define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) +/*description: wdt reset whole chip enable.*/ +#define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) #define RTC_CNTL_WDT_CHIP_RESET_EN_M (BIT(8)) #define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x1 #define RTC_CNTL_WDT_CHIP_RESET_EN_S 8 /* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */ -/*description: chip reset siginal pulse width*/ -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FF +/*description: chip reset siginal pulse width.*/ +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FF #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S)) #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0xFF #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 -#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x0098) +#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x9C) /* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */ -/*description: */ -#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF +/*description: .*/ +#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF #define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) #define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF #define RTC_CNTL_WDT_STG0_HOLD_S 0 -#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x009C) +#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0xA0) /* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ -/*description: */ -#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF +/*description: .*/ +#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF #define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) #define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF #define RTC_CNTL_WDT_STG1_HOLD_S 0 -#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x00A0) +#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0xA4) /* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ -/*description: */ -#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF +/*description: .*/ +#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF #define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) #define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF #define RTC_CNTL_WDT_STG2_HOLD_S 0 -#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x00A4) +#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0xA8) /* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ -/*description: */ -#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF +/*description: .*/ +#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF #define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) #define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF #define RTC_CNTL_WDT_STG3_HOLD_S 0 -#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0x00A8) +#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xAC) /* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_WDT_FEED (BIT(31)) +/*description: .*/ +#define RTC_CNTL_WDT_FEED (BIT(31)) #define RTC_CNTL_WDT_FEED_M (BIT(31)) #define RTC_CNTL_WDT_FEED_V 0x1 #define RTC_CNTL_WDT_FEED_S 31 -#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00AC) +#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xB0) /* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ -/*description: */ -#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF +/*description: .*/ +#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF #define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) #define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF #define RTC_CNTL_WDT_WKEY_S 0 -#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00B0) +#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0xB4) /* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: automatically feed swd when int comes*/ -#define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) +/*description: automatically feed swd when int comes.*/ +#define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) #define RTC_CNTL_SWD_AUTO_FEED_EN_M (BIT(31)) #define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x1 #define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 /* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: disabel SWD*/ -#define RTC_CNTL_SWD_DISABLE (BIT(30)) +/*description: disabel SWD.*/ +#define RTC_CNTL_SWD_DISABLE (BIT(30)) #define RTC_CNTL_SWD_DISABLE_M (BIT(30)) #define RTC_CNTL_SWD_DISABLE_V 0x1 #define RTC_CNTL_SWD_DISABLE_S 30 /* RTC_CNTL_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Sw feed swd*/ -#define RTC_CNTL_SWD_FEED (BIT(29)) +/*description: Sw feed swd.*/ +#define RTC_CNTL_SWD_FEED (BIT(29)) #define RTC_CNTL_SWD_FEED_M (BIT(29)) #define RTC_CNTL_SWD_FEED_V 0x1 #define RTC_CNTL_SWD_FEED_S 29 /* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: reset swd reset flag*/ -#define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) +/*description: reset swd reset flag.*/ +#define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) #define RTC_CNTL_SWD_RST_FLAG_CLR_M (BIT(28)) #define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x1 #define RTC_CNTL_SWD_RST_FLAG_CLR_S 28 /* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */ -/*description: adjust signal width send to swd*/ -#define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF +/*description: adjust signal width send to swd.*/ +#define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF #define RTC_CNTL_SWD_SIGNAL_WIDTH_M ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S)) #define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x3FF #define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18 /* RTC_CNTL_SWD_BYPASS_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_SWD_BYPASS_RST (BIT(17)) +/*description: .*/ +#define RTC_CNTL_SWD_BYPASS_RST (BIT(17)) #define RTC_CNTL_SWD_BYPASS_RST_M (BIT(17)) #define RTC_CNTL_SWD_BYPASS_RST_V 0x1 #define RTC_CNTL_SWD_BYPASS_RST_S 17 /* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: swd interrupt for feeding*/ -#define RTC_CNTL_SWD_FEED_INT (BIT(1)) +/*description: swd interrupt for feeding.*/ +#define RTC_CNTL_SWD_FEED_INT (BIT(1)) #define RTC_CNTL_SWD_FEED_INT_M (BIT(1)) #define RTC_CNTL_SWD_FEED_INT_V 0x1 #define RTC_CNTL_SWD_FEED_INT_S 1 /* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: swd reset flag*/ -#define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) +/*description: swd reset flag.*/ +#define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) #define RTC_CNTL_SWD_RESET_FLAG_M (BIT(0)) #define RTC_CNTL_SWD_RESET_FLAG_V 0x1 #define RTC_CNTL_SWD_RESET_FLAG_S 0 -#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00B4) +#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xB8) /* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */ -/*description: */ -#define RTC_CNTL_SWD_WKEY 0xFFFFFFFF +/*description: .*/ +#define RTC_CNTL_SWD_WKEY 0xFFFFFFFF #define RTC_CNTL_SWD_WKEY_M ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S)) #define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF #define RTC_CNTL_SWD_WKEY_S 0 -#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0x00B8) +#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xBC) /* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ -/*description: */ -#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F +/*description: .*/ +#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F #define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) #define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F #define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 /* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ -/*description: {reg_sw_stall_appcpu_c1[5:0]*/ -#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F +/*description: {reg_sw_stall_appcpu_c1[5:0].*/ +#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F #define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) #define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F #define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 -#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0x00BC) +#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xC0) /* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH4 0xFFFFFFFF +/*description: .*/ +#define RTC_CNTL_SCRATCH4 0xFFFFFFFF #define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) #define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH4_S 0 -#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0x00C0) +#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xC4) /* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH5 0xFFFFFFFF +/*description: .*/ +#define RTC_CNTL_SCRATCH5 0xFFFFFFFF #define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) #define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH5_S 0 -#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0x00C4) +#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xC8) /* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH6 0xFFFFFFFF +/*description: .*/ +#define RTC_CNTL_SCRATCH6 0xFFFFFFFF #define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) #define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH6_S 0 -#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0x00C8) +#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xCC) /* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_SCRATCH7 0xFFFFFFFF +/*description: .*/ +#define RTC_CNTL_SCRATCH7 0xFFFFFFFF #define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) #define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH7_S 0 -#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0x00CC) +#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0xD0) /* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */ -/*description: rtc main state machine status*/ -#define RTC_CNTL_MAIN_STATE 0x0000000F +/*description: rtc main state machine status.*/ +#define RTC_CNTL_MAIN_STATE 0x0000000F #define RTC_CNTL_MAIN_STATE_M ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S)) #define RTC_CNTL_MAIN_STATE_V 0xF #define RTC_CNTL_MAIN_STATE_S 28 /* RTC_CNTL_MAIN_STATE_IN_IDLE : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: rtc main state machine is in idle state*/ -#define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) +/*description: rtc main state machine is in idle state.*/ +#define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) #define RTC_CNTL_MAIN_STATE_IN_IDLE_M (BIT(27)) #define RTC_CNTL_MAIN_STATE_IN_IDLE_V 0x1 #define RTC_CNTL_MAIN_STATE_IN_IDLE_S 27 /* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: rtc main state machine is in sleep state*/ -#define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) +/*description: rtc main state machine is in sleep state.*/ +#define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) #define RTC_CNTL_MAIN_STATE_IN_SLP_M (BIT(26)) #define RTC_CNTL_MAIN_STATE_IN_SLP_V 0x1 #define RTC_CNTL_MAIN_STATE_IN_SLP_S 26 /* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: rtc main state machine is in wait xtal state*/ -#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) +/*description: rtc main state machine is in wait xtal state.*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M (BIT(25)) #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V 0x1 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S 25 /* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: rtc main state machine is in wait pll state*/ -#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) +/*description: rtc main state machine is in wait pll state.*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M (BIT(24)) #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V 0x1 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S 24 /* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: rtc main state machine is in wait 8m state*/ -#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) +/*description: rtc main state machine is in wait 8m state.*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M (BIT(23)) #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V 0x1 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S 23 /* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: rtc main state machine is in the states of low power*/ -#define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) +/*description: rtc main state machine is in the states of low power.*/ +#define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) #define RTC_CNTL_IN_LOW_POWER_STATE_M (BIT(22)) #define RTC_CNTL_IN_LOW_POWER_STATE_V 0x1 #define RTC_CNTL_IN_LOW_POWER_STATE_S 22 /* RTC_CNTL_IN_WAKEUP_STATE : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: rtc main state machine is in the states of wakeup process*/ -#define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) +/*description: rtc main state machine is in the states of wakeup process.*/ +#define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) #define RTC_CNTL_IN_WAKEUP_STATE_M (BIT(21)) #define RTC_CNTL_IN_WAKEUP_STATE_V 0x1 #define RTC_CNTL_IN_WAKEUP_STATE_S 21 /* RTC_CNTL_MAIN_STATE_WAIT_END : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: rtc main state machine has been waited for some cycles*/ -#define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) +/*description: rtc main state machine has been waited for some cycles.*/ +#define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) #define RTC_CNTL_MAIN_STATE_WAIT_END_M (BIT(20)) #define RTC_CNTL_MAIN_STATE_WAIT_END_V 0x1 #define RTC_CNTL_MAIN_STATE_WAIT_END_S 20 /* RTC_CNTL_RDY_FOR_WAKEUP : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: rtc is ready to receive wake up trigger from wake up source*/ -#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) +/*description: rtc is ready to receive wake up trigger from wake up source.*/ +#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) #define RTC_CNTL_RDY_FOR_WAKEUP_M (BIT(19)) #define RTC_CNTL_RDY_FOR_WAKEUP_V 0x1 #define RTC_CNTL_RDY_FOR_WAKEUP_S 19 /* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: rtc main state machine is in states that pll should be running*/ -#define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) +/*description: rtc main state machine is in states that pll should be running.*/ +#define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) #define RTC_CNTL_MAIN_STATE_PLL_ON_M (BIT(18)) #define RTC_CNTL_MAIN_STATE_PLL_ON_V 0x1 #define RTC_CNTL_MAIN_STATE_PLL_ON_S 18 /* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: no use any more*/ -#define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) +/*description: no use any more.*/ +#define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) #define RTC_CNTL_MAIN_STATE_XTAL_ISO_M (BIT(17)) #define RTC_CNTL_MAIN_STATE_XTAL_ISO_V 0x1 #define RTC_CNTL_MAIN_STATE_XTAL_ISO_S 17 /* RTC_CNTL_COCPU_STATE_DONE : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: ulp/cocpu is done*/ -#define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) +/*description: ulp/cocpu is done.*/ +#define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) #define RTC_CNTL_COCPU_STATE_DONE_M (BIT(16)) #define RTC_CNTL_COCPU_STATE_DONE_V 0x1 #define RTC_CNTL_COCPU_STATE_DONE_S 16 /* RTC_CNTL_COCPU_STATE_SLP : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: ulp/cocpu is in sleep state*/ -#define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) +/*description: ulp/cocpu is in sleep state.*/ +#define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) #define RTC_CNTL_COCPU_STATE_SLP_M (BIT(15)) #define RTC_CNTL_COCPU_STATE_SLP_V 0x1 #define RTC_CNTL_COCPU_STATE_SLP_S 15 /* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: ulp/cocpu is about to working. Switch rtc main state*/ -#define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) +/*description: ulp/cocpu is about to working. Switch rtc main state.*/ +#define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) #define RTC_CNTL_COCPU_STATE_SWITCH_M (BIT(14)) #define RTC_CNTL_COCPU_STATE_SWITCH_V 0x1 #define RTC_CNTL_COCPU_STATE_SWITCH_S 14 /* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: ulp/cocpu should start to work*/ -#define RTC_CNTL_COCPU_STATE_START (BIT(13)) +/*description: ulp/cocpu should start to work.*/ +#define RTC_CNTL_COCPU_STATE_START (BIT(13)) #define RTC_CNTL_COCPU_STATE_START_M (BIT(13)) #define RTC_CNTL_COCPU_STATE_START_V 0x1 #define RTC_CNTL_COCPU_STATE_START_S 13 /* RTC_CNTL_TOUCH_STATE_DONE : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: touch is done*/ -#define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) +/*description: touch is done.*/ +#define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) #define RTC_CNTL_TOUCH_STATE_DONE_M (BIT(12)) #define RTC_CNTL_TOUCH_STATE_DONE_V 0x1 #define RTC_CNTL_TOUCH_STATE_DONE_S 12 /* RTC_CNTL_TOUCH_STATE_SLP : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: touch is in sleep state*/ -#define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) +/*description: touch is in sleep state.*/ +#define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) #define RTC_CNTL_TOUCH_STATE_SLP_M (BIT(11)) #define RTC_CNTL_TOUCH_STATE_SLP_V 0x1 #define RTC_CNTL_TOUCH_STATE_SLP_S 11 /* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: touch is about to working. Switch rtc main state*/ -#define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) +/*description: touch is about to working. Switch rtc main state.*/ +#define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) #define RTC_CNTL_TOUCH_STATE_SWITCH_M (BIT(10)) #define RTC_CNTL_TOUCH_STATE_SWITCH_V 0x1 #define RTC_CNTL_TOUCH_STATE_SWITCH_S 10 /* RTC_CNTL_TOUCH_STATE_START : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: touch should start to work*/ -#define RTC_CNTL_TOUCH_STATE_START (BIT(9)) +/*description: touch should start to work.*/ +#define RTC_CNTL_TOUCH_STATE_START (BIT(9)) #define RTC_CNTL_TOUCH_STATE_START_M (BIT(9)) #define RTC_CNTL_TOUCH_STATE_START_V 0x1 #define RTC_CNTL_TOUCH_STATE_START_S 9 /* RTC_CNTL_XPD_DIG : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: digital wrap power down*/ -#define RTC_CNTL_XPD_DIG (BIT(8)) +/*description: digital wrap power down.*/ +#define RTC_CNTL_XPD_DIG (BIT(8)) #define RTC_CNTL_XPD_DIG_M (BIT(8)) #define RTC_CNTL_XPD_DIG_V 0x1 #define RTC_CNTL_XPD_DIG_S 8 /* RTC_CNTL_DIG_ISO : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: digital wrap iso*/ -#define RTC_CNTL_DIG_ISO (BIT(7)) +/*description: digital wrap iso.*/ +#define RTC_CNTL_DIG_ISO (BIT(7)) #define RTC_CNTL_DIG_ISO_M (BIT(7)) #define RTC_CNTL_DIG_ISO_V 0x1 #define RTC_CNTL_DIG_ISO_S 7 /* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: wifi wrap power down*/ -#define RTC_CNTL_XPD_WIFI (BIT(6)) +/*description: wifi wrap power down.*/ +#define RTC_CNTL_XPD_WIFI (BIT(6)) #define RTC_CNTL_XPD_WIFI_M (BIT(6)) #define RTC_CNTL_XPD_WIFI_V 0x1 #define RTC_CNTL_XPD_WIFI_S 6 /* RTC_CNTL_WIFI_ISO : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: wifi iso*/ -#define RTC_CNTL_WIFI_ISO (BIT(5)) +/*description: wifi iso.*/ +#define RTC_CNTL_WIFI_ISO (BIT(5)) #define RTC_CNTL_WIFI_ISO_M (BIT(5)) #define RTC_CNTL_WIFI_ISO_V 0x1 #define RTC_CNTL_WIFI_ISO_S 5 /* RTC_CNTL_XPD_RTC_PERI : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: rtc peripheral power down*/ -#define RTC_CNTL_XPD_RTC_PERI (BIT(4)) +/*description: rtc peripheral power down .*/ +#define RTC_CNTL_XPD_RTC_PERI (BIT(4)) #define RTC_CNTL_XPD_RTC_PERI_M (BIT(4)) #define RTC_CNTL_XPD_RTC_PERI_V 0x1 #define RTC_CNTL_XPD_RTC_PERI_S 4 /* RTC_CNTL_PERI_ISO : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: rtc peripheral iso*/ -#define RTC_CNTL_PERI_ISO (BIT(3)) +/*description: rtc peripheral iso.*/ +#define RTC_CNTL_PERI_ISO (BIT(3)) #define RTC_CNTL_PERI_ISO_M (BIT(3)) #define RTC_CNTL_PERI_ISO_V 0x1 #define RTC_CNTL_PERI_ISO_S 3 /* RTC_CNTL_XPD_DIG_DCDC : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: External DCDC power down*/ -#define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) +/*description: External DCDC power down.*/ +#define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) #define RTC_CNTL_XPD_DIG_DCDC_M (BIT(2)) #define RTC_CNTL_XPD_DIG_DCDC_V 0x1 #define RTC_CNTL_XPD_DIG_DCDC_S 2 /* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: rom0 power down*/ -#define RTC_CNTL_XPD_ROM0 (BIT(0)) +/*description: rom0 power down.*/ +#define RTC_CNTL_XPD_ROM0 (BIT(0)) #define RTC_CNTL_XPD_ROM0_M (BIT(0)) #define RTC_CNTL_XPD_ROM0_V 0x1 #define RTC_CNTL_XPD_ROM0_S 0 -#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0x00D0) +#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xD4) /* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ -/*description: */ -#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF +/*description: .*/ +#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF #define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) #define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF #define RTC_CNTL_LOW_POWER_DIAG1_S 0 -#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D4) +#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xD8) /* RTC_CNTL_PAD21_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_PAD21_HOLD (BIT(21)) +/*description: .*/ +#define RTC_CNTL_PAD21_HOLD (BIT(21)) #define RTC_CNTL_PAD21_HOLD_M (BIT(21)) #define RTC_CNTL_PAD21_HOLD_V 0x1 #define RTC_CNTL_PAD21_HOLD_S 21 /* RTC_CNTL_PAD20_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_PAD20_HOLD (BIT(20)) +/*description: .*/ +#define RTC_CNTL_PAD20_HOLD (BIT(20)) #define RTC_CNTL_PAD20_HOLD_M (BIT(20)) #define RTC_CNTL_PAD20_HOLD_V 0x1 #define RTC_CNTL_PAD20_HOLD_S 20 /* RTC_CNTL_PAD19_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_PAD19_HOLD (BIT(19)) +/*description: .*/ +#define RTC_CNTL_PAD19_HOLD (BIT(19)) #define RTC_CNTL_PAD19_HOLD_M (BIT(19)) #define RTC_CNTL_PAD19_HOLD_V 0x1 #define RTC_CNTL_PAD19_HOLD_S 19 /* RTC_CNTL_PDAC2_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_PDAC2_HOLD (BIT(18)) +/*description: .*/ +#define RTC_CNTL_PDAC2_HOLD (BIT(18)) #define RTC_CNTL_PDAC2_HOLD_M (BIT(18)) #define RTC_CNTL_PDAC2_HOLD_V 0x1 #define RTC_CNTL_PDAC2_HOLD_S 18 /* RTC_CNTL_PDAC1_HOLD : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_PDAC1_HOLD (BIT(17)) +/*description: .*/ +#define RTC_CNTL_PDAC1_HOLD (BIT(17)) #define RTC_CNTL_PDAC1_HOLD_M (BIT(17)) #define RTC_CNTL_PDAC1_HOLD_V 0x1 #define RTC_CNTL_PDAC1_HOLD_S 17 /* RTC_CNTL_X32N_HOLD : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_X32N_HOLD (BIT(16)) +/*description: .*/ +#define RTC_CNTL_X32N_HOLD (BIT(16)) #define RTC_CNTL_X32N_HOLD_M (BIT(16)) #define RTC_CNTL_X32N_HOLD_V 0x1 #define RTC_CNTL_X32N_HOLD_S 16 /* RTC_CNTL_X32P_HOLD : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_X32P_HOLD (BIT(15)) +/*description: .*/ +#define RTC_CNTL_X32P_HOLD (BIT(15)) #define RTC_CNTL_X32P_HOLD_M (BIT(15)) #define RTC_CNTL_X32P_HOLD_V 0x1 #define RTC_CNTL_X32P_HOLD_S 15 /* RTC_CNTL_TOUCH_PAD14_HOLD : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD14_HOLD (BIT(14)) +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD14_HOLD (BIT(14)) #define RTC_CNTL_TOUCH_PAD14_HOLD_M (BIT(14)) #define RTC_CNTL_TOUCH_PAD14_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD14_HOLD_S 14 /* RTC_CNTL_TOUCH_PAD13_HOLD : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD13_HOLD (BIT(13)) +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD13_HOLD (BIT(13)) #define RTC_CNTL_TOUCH_PAD13_HOLD_M (BIT(13)) #define RTC_CNTL_TOUCH_PAD13_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD13_HOLD_S 13 /* RTC_CNTL_TOUCH_PAD12_HOLD : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD12_HOLD (BIT(12)) +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD12_HOLD (BIT(12)) #define RTC_CNTL_TOUCH_PAD12_HOLD_M (BIT(12)) #define RTC_CNTL_TOUCH_PAD12_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD12_HOLD_S 12 /* RTC_CNTL_TOUCH_PAD11_HOLD : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD11_HOLD (BIT(11)) +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD11_HOLD (BIT(11)) #define RTC_CNTL_TOUCH_PAD11_HOLD_M (BIT(11)) #define RTC_CNTL_TOUCH_PAD11_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD11_HOLD_S 11 /* RTC_CNTL_TOUCH_PAD10_HOLD : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD10_HOLD (BIT(10)) +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD10_HOLD (BIT(10)) #define RTC_CNTL_TOUCH_PAD10_HOLD_M (BIT(10)) #define RTC_CNTL_TOUCH_PAD10_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD10_HOLD_S 10 /* RTC_CNTL_TOUCH_PAD9_HOLD : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD9_HOLD (BIT(9)) +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD9_HOLD (BIT(9)) #define RTC_CNTL_TOUCH_PAD9_HOLD_M (BIT(9)) #define RTC_CNTL_TOUCH_PAD9_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD9_HOLD_S 9 /* RTC_CNTL_TOUCH_PAD8_HOLD : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD8_HOLD (BIT(8)) +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD8_HOLD (BIT(8)) #define RTC_CNTL_TOUCH_PAD8_HOLD_M (BIT(8)) #define RTC_CNTL_TOUCH_PAD8_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD8_HOLD_S 8 /* RTC_CNTL_TOUCH_PAD7_HOLD : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD7_HOLD (BIT(7)) +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD7_HOLD (BIT(7)) #define RTC_CNTL_TOUCH_PAD7_HOLD_M (BIT(7)) #define RTC_CNTL_TOUCH_PAD7_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD7_HOLD_S 7 /* RTC_CNTL_TOUCH_PAD6_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD6_HOLD (BIT(6)) +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD6_HOLD (BIT(6)) #define RTC_CNTL_TOUCH_PAD6_HOLD_M (BIT(6)) #define RTC_CNTL_TOUCH_PAD6_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD6_HOLD_S 6 /* RTC_CNTL_TOUCH_PAD5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD5_HOLD (BIT(5)) +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD5_HOLD (BIT(5)) #define RTC_CNTL_TOUCH_PAD5_HOLD_M (BIT(5)) #define RTC_CNTL_TOUCH_PAD5_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD5_HOLD_S 5 /* RTC_CNTL_TOUCH_PAD4_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD4_HOLD (BIT(4)) +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD4_HOLD (BIT(4)) #define RTC_CNTL_TOUCH_PAD4_HOLD_M (BIT(4)) #define RTC_CNTL_TOUCH_PAD4_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD4_HOLD_S 4 /* RTC_CNTL_TOUCH_PAD3_HOLD : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD3_HOLD (BIT(3)) +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD3_HOLD (BIT(3)) #define RTC_CNTL_TOUCH_PAD3_HOLD_M (BIT(3)) #define RTC_CNTL_TOUCH_PAD3_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD3_HOLD_S 3 /* RTC_CNTL_TOUCH_PAD2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD2_HOLD (BIT(2)) +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD2_HOLD (BIT(2)) #define RTC_CNTL_TOUCH_PAD2_HOLD_M (BIT(2)) #define RTC_CNTL_TOUCH_PAD2_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD2_HOLD_S 2 /* RTC_CNTL_TOUCH_PAD1_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD1_HOLD (BIT(1)) +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD1_HOLD (BIT(1)) #define RTC_CNTL_TOUCH_PAD1_HOLD_M (BIT(1)) #define RTC_CNTL_TOUCH_PAD1_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD1_HOLD_S 1 /* RTC_CNTL_TOUCH_PAD0_HOLD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_PAD0_HOLD (BIT(0)) +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD0_HOLD (BIT(0)) #define RTC_CNTL_TOUCH_PAD0_HOLD_M (BIT(0)) #define RTC_CNTL_TOUCH_PAD0_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD0_HOLD_S 0 -#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D8) +#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xDC) /* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF +/*description: .*/ +#define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF #define RTC_CNTL_DIG_PAD_HOLD_M ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S)) #define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF #define RTC_CNTL_DIG_PAD_HOLD_S 0 -#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0x00DC) +#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xE0) /* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ -/*description: clear ext wakeup1 status*/ -#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(22)) +/*description: clear ext wakeup1 status.*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(22)) #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (BIT(22)) #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x1 #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 22 /* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[21:0] ;default: 22'd0 ; */ -/*description: Bitmap to select RTC pads for ext wakeup1*/ -#define RTC_CNTL_EXT_WAKEUP1_SEL 0x003FFFFF +/*description: Bitmap to select RTC pads for ext wakeup1.*/ +#define RTC_CNTL_EXT_WAKEUP1_SEL 0x003FFFFF #define RTC_CNTL_EXT_WAKEUP1_SEL_M ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S)) #define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x3FFFFF #define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 -#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0x00E0) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xE4) /* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[21:0] ;default: 22'd0 ; */ -/*description: ext wakeup1 status*/ -#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x003FFFFF +/*description: ext wakeup1 status.*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x003FFFFF #define RTC_CNTL_EXT_WAKEUP1_STATUS_M ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S)) #define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFFF #define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 -#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0x00E4) +#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xE8) /* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) +/*description: .*/ +#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) #define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) #define RTC_CNTL_BROWN_OUT_DET_V 0x1 #define RTC_CNTL_BROWN_OUT_DET_S 31 /* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: enable brown out*/ -#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) +/*description: enable brown out.*/ +#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) #define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) #define RTC_CNTL_BROWN_OUT_ENA_V 0x1 #define RTC_CNTL_BROWN_OUT_ENA_S 30 /* RTC_CNTL_BROWN_OUT_CNT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: clear brown out counter*/ -#define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) +/*description: clear brown out counter.*/ +#define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) #define RTC_CNTL_BROWN_OUT_CNT_CLR_M (BIT(29)) #define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x1 #define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 /* RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28)) +/*description: .*/ +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28)) #define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M (BIT(28)) #define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V 0x1 #define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S 28 /* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: 1: 4-pos reset*/ -#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) +/*description: 1: 4-pos reset.*/ +#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) #define RTC_CNTL_BROWN_OUT_RST_SEL_M (BIT(27)) #define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x1 #define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 /* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: enable brown out reset*/ -#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) +/*description: enable brown out reset.*/ +#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) #define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) #define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 #define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 /* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ -/*description: brown out reset wait cycles*/ -#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF +/*description: brown out reset wait cycles.*/ +#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF #define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) #define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF #define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 /* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: enable power down RF when brown out happens*/ -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) +/*description: enable power down RF when brown out happens.*/ +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 /* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: enable close flash when brown out happens*/ -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) +/*description: enable close flash when brown out happens.*/ +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 /* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W ;bitpos:[13:4] ;default: 10'h1 ; */ -/*description: brown out interrupt wait cycles*/ -#define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FF +/*description: brown out interrupt wait cycles.*/ +#define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FF #define RTC_CNTL_BROWN_OUT_INT_WAIT_M ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S)) #define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x3FF #define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 -#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0x00E8) +#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0xEC) /* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: RTC timer low 32 bits*/ -#define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF +/*description: RTC timer low 32 bits.*/ +#define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF #define RTC_CNTL_TIMER_VALUE1_LOW_M ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S)) #define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF #define RTC_CNTL_TIMER_VALUE1_LOW_S 0 -#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0x00EC) +#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0xF0) /* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: RTC timer high 16 bits*/ -#define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF +/*description: RTC timer high 16 bits.*/ +#define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF #define RTC_CNTL_TIMER_VALUE1_HIGH_M ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S)) #define RTC_CNTL_TIMER_VALUE1_HIGH_V 0xFFFF #define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 -#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0x00F0) +#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0xF4) /* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: xtal 32k watch dog backup clock factor*/ -#define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF +/*description: xtal 32k watch dog backup clock factor.*/ +#define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF #define RTC_CNTL_XTAL32K_CLK_FACTOR_M ((RTC_CNTL_XTAL32K_CLK_FACTOR_V)<<(RTC_CNTL_XTAL32K_CLK_FACTOR_S)) #define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF #define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 -#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00F4) +#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0xF8) /* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: if restarted xtal32k period is smaller than this*/ -#define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F +/*description: if restarted xtal32k period is smaller than this.*/ +#define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F #define RTC_CNTL_XTAL32K_STABLE_THRES_M ((RTC_CNTL_XTAL32K_STABLE_THRES_V)<<(RTC_CNTL_XTAL32K_STABLE_THRES_S)) #define RTC_CNTL_XTAL32K_STABLE_THRES_V 0xF #define RTC_CNTL_XTAL32K_STABLE_THRES_S 28 /* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */ -/*description: If no clock detected for this amount of time*/ -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FF +/*description: If no clock detected for this amount of time.*/ +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FF #define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V)<<(RTC_CNTL_XTAL32K_WDT_TIMEOUT_S)) #define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0xFF #define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20 /* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */ -/*description: cycles to wait to repower on xtal 32k*/ -#define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFF +/*description: cycles to wait to repower on xtal 32k.*/ +#define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFF #define RTC_CNTL_XTAL32K_RESTART_WAIT_M ((RTC_CNTL_XTAL32K_RESTART_WAIT_V)<<(RTC_CNTL_XTAL32K_RESTART_WAIT_S)) #define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0xFFFF #define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 /* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: cycles to wait to return noral xtal 32k*/ -#define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F +/*description: cycles to wait to return noral xtal 32k.*/ +#define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F #define RTC_CNTL_XTAL32K_RETURN_WAIT_M ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S)) #define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0xF #define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 -#define RTC_CNTL_ULP_CP_TIMER_REG (DR_REG_RTCCNTL_BASE + 0x00F8) +#define RTC_CNTL_ULP_CP_TIMER_REG (DR_REG_RTCCNTL_BASE + 0xFC) /* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: ULP-coprocessor timer enable bit*/ -#define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(31)) +/*description: ULP-coprocessor timer enable bit.*/ +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(31)) #define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (BIT(31)) #define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x1 #define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 31 /* RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR : WO ;bitpos:[30] ;default: 1'd0 ; */ -/*description: ULP-coprocessor wakeup by GPIO state clear*/ -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR (BIT(30)) +/*description: ULP-coprocessor wakeup by GPIO state clear.*/ +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR (BIT(30)) #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_M (BIT(30)) #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V 0x1 #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S 30 /* RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: ULP-coprocessor wakeup by GPIO enable*/ -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA (BIT(29)) +/*description: ULP-coprocessor wakeup by GPIO enable.*/ +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA (BIT(29)) #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_M (BIT(29)) #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V 0x1 #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S 29 /* RTC_CNTL_ULP_CP_PC_INIT : R/W ;bitpos:[10:0] ;default: 11'b0 ; */ -/*description: ULP-coprocessor PC initial address*/ -#define RTC_CNTL_ULP_CP_PC_INIT 0x000007FF +/*description: ULP-coprocessor PC initial address.*/ +#define RTC_CNTL_ULP_CP_PC_INIT 0x000007FF #define RTC_CNTL_ULP_CP_PC_INIT_M ((RTC_CNTL_ULP_CP_PC_INIT_V)<<(RTC_CNTL_ULP_CP_PC_INIT_S)) #define RTC_CNTL_ULP_CP_PC_INIT_V 0x7FF #define RTC_CNTL_ULP_CP_PC_INIT_S 0 -#define RTC_CNTL_ULP_CP_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x00FC) +#define RTC_CNTL_ULP_CP_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x100) /* RTC_CNTL_ULP_CP_START_TOP : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: Write 1 to start ULP-coprocessor*/ -#define RTC_CNTL_ULP_CP_START_TOP (BIT(31)) +/*description: Write 1 to start ULP-coprocessor.*/ +#define RTC_CNTL_ULP_CP_START_TOP (BIT(31)) #define RTC_CNTL_ULP_CP_START_TOP_M (BIT(31)) #define RTC_CNTL_ULP_CP_START_TOP_V 0x1 #define RTC_CNTL_ULP_CP_START_TOP_S 31 /* RTC_CNTL_ULP_CP_FORCE_START_TOP : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: 1: ULP-coprocessor is started by SW*/ -#define RTC_CNTL_ULP_CP_FORCE_START_TOP (BIT(30)) +/*description: 1: ULP-coprocessor is started by SW.*/ +#define RTC_CNTL_ULP_CP_FORCE_START_TOP (BIT(30)) #define RTC_CNTL_ULP_CP_FORCE_START_TOP_M (BIT(30)) #define RTC_CNTL_ULP_CP_FORCE_START_TOP_V 0x1 #define RTC_CNTL_ULP_CP_FORCE_START_TOP_S 30 /* RTC_CNTL_ULP_CP_RESET : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: ulp coprocessor clk software reset*/ -#define RTC_CNTL_ULP_CP_RESET (BIT(29)) +/*description: ulp coprocessor clk software reset.*/ +#define RTC_CNTL_ULP_CP_RESET (BIT(29)) #define RTC_CNTL_ULP_CP_RESET_M (BIT(29)) #define RTC_CNTL_ULP_CP_RESET_V 0x1 #define RTC_CNTL_ULP_CP_RESET_S 29 /* RTC_CNTL_ULP_CP_CLK_FO : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: ulp coprocessor clk force on*/ -#define RTC_CNTL_ULP_CP_CLK_FO (BIT(28)) +/*description: ulp coprocessor clk force on.*/ +#define RTC_CNTL_ULP_CP_CLK_FO (BIT(28)) #define RTC_CNTL_ULP_CP_CLK_FO_M (BIT(28)) #define RTC_CNTL_ULP_CP_CLK_FO_V 0x1 #define RTC_CNTL_ULP_CP_CLK_FO_S 28 /* RTC_CNTL_ULP_CP_MEM_OFFST_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR (BIT(22)) +/*description: .*/ +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR (BIT(22)) #define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_M (BIT(22)) #define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V 0x1 #define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S 22 /* RTC_CNTL_ULP_CP_MEM_ADDR_SIZE : R/W ;bitpos:[21:11] ;default: 11'd512 ; */ -/*description: */ -#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE 0x000007FF +/*description: .*/ +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE 0x000007FF #define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_M ((RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V)<<(RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S)) #define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V 0x7FF #define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S 11 /* RTC_CNTL_ULP_CP_MEM_ADDR_INIT : R/W ;bitpos:[10:0] ;default: 11'd512 ; */ -/*description: */ -#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT 0x000007FF +/*description: .*/ +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT 0x000007FF #define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_M ((RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V)<<(RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S)) #define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V 0x7FF #define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S 0 -#define RTC_CNTL_COCPU_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0100) +#define RTC_CNTL_COCPU_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x104) /* RTC_CNTL_COCPU_CLKGATE_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_COCPU_CLKGATE_EN (BIT(27)) +/*description: .*/ +#define RTC_CNTL_COCPU_CLKGATE_EN (BIT(27)) #define RTC_CNTL_COCPU_CLKGATE_EN_M (BIT(27)) #define RTC_CNTL_COCPU_CLKGATE_EN_V 0x1 #define RTC_CNTL_COCPU_CLKGATE_EN_S 27 /* RTC_CNTL_COCPU_SW_INT_TRIGGER : WO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: trigger cocpu register interrupt*/ -#define RTC_CNTL_COCPU_SW_INT_TRIGGER (BIT(26)) +/*description: trigger cocpu register interrupt.*/ +#define RTC_CNTL_COCPU_SW_INT_TRIGGER (BIT(26)) #define RTC_CNTL_COCPU_SW_INT_TRIGGER_M (BIT(26)) #define RTC_CNTL_COCPU_SW_INT_TRIGGER_V 0x1 #define RTC_CNTL_COCPU_SW_INT_TRIGGER_S 26 /* RTC_CNTL_COCPU_DONE : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: done signal used by riscv to control timer.*/ -#define RTC_CNTL_COCPU_DONE (BIT(25)) +/*description: done signal used by riscv to control timer. .*/ +#define RTC_CNTL_COCPU_DONE (BIT(25)) #define RTC_CNTL_COCPU_DONE_M (BIT(25)) #define RTC_CNTL_COCPU_DONE_V 0x1 #define RTC_CNTL_COCPU_DONE_S 25 /* RTC_CNTL_COCPU_DONE_FORCE : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: 1: select riscv done 0: select ulp done*/ -#define RTC_CNTL_COCPU_DONE_FORCE (BIT(24)) +/*description: 1: select riscv done 0: select ulp done.*/ +#define RTC_CNTL_COCPU_DONE_FORCE (BIT(24)) #define RTC_CNTL_COCPU_DONE_FORCE_M (BIT(24)) #define RTC_CNTL_COCPU_DONE_FORCE_V 0x1 #define RTC_CNTL_COCPU_DONE_FORCE_S 24 /* RTC_CNTL_COCPU_SEL : R/W ;bitpos:[23] ;default: 1'b1 ; */ -/*description: 1: old ULP 0: new riscV*/ -#define RTC_CNTL_COCPU_SEL (BIT(23)) +/*description: 1: old ULP 0: new riscV.*/ +#define RTC_CNTL_COCPU_SEL (BIT(23)) #define RTC_CNTL_COCPU_SEL_M (BIT(23)) #define RTC_CNTL_COCPU_SEL_V 0x1 #define RTC_CNTL_COCPU_SEL_S 23 /* RTC_CNTL_COCPU_SHUT_RESET_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: to reset cocpu*/ -#define RTC_CNTL_COCPU_SHUT_RESET_EN (BIT(22)) +/*description: to reset cocpu.*/ +#define RTC_CNTL_COCPU_SHUT_RESET_EN (BIT(22)) #define RTC_CNTL_COCPU_SHUT_RESET_EN_M (BIT(22)) #define RTC_CNTL_COCPU_SHUT_RESET_EN_V 0x1 #define RTC_CNTL_COCPU_SHUT_RESET_EN_S 22 /* RTC_CNTL_COCPU_SHUT_2_CLK_DIS : R/W ;bitpos:[21:14] ;default: 8'd40 ; */ -/*description: time from shut cocpu to disable clk*/ -#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS 0x000000FF +/*description: time from shut cocpu to disable clk.*/ +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS 0x000000FF #define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_M ((RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V)<<(RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S)) #define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V 0xFF #define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S 14 /* RTC_CNTL_COCPU_SHUT : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: to shut cocpu*/ -#define RTC_CNTL_COCPU_SHUT (BIT(13)) +/*description: to shut cocpu.*/ +#define RTC_CNTL_COCPU_SHUT (BIT(13)) #define RTC_CNTL_COCPU_SHUT_M (BIT(13)) #define RTC_CNTL_COCPU_SHUT_V 0x1 #define RTC_CNTL_COCPU_SHUT_S 13 /* RTC_CNTL_COCPU_START_2_INTR_EN : R/W ;bitpos:[12:7] ;default: 6'd16 ; */ -/*description: time from start cocpu to give start interrupt*/ -#define RTC_CNTL_COCPU_START_2_INTR_EN 0x0000003F +/*description: time from start cocpu to give start interrupt.*/ +#define RTC_CNTL_COCPU_START_2_INTR_EN 0x0000003F #define RTC_CNTL_COCPU_START_2_INTR_EN_M ((RTC_CNTL_COCPU_START_2_INTR_EN_V)<<(RTC_CNTL_COCPU_START_2_INTR_EN_S)) #define RTC_CNTL_COCPU_START_2_INTR_EN_V 0x3F #define RTC_CNTL_COCPU_START_2_INTR_EN_S 7 /* RTC_CNTL_COCPU_START_2_RESET_DIS : R/W ;bitpos:[6:1] ;default: 6'd8 ; */ -/*description: time from start cocpu to pull down reset*/ -#define RTC_CNTL_COCPU_START_2_RESET_DIS 0x0000003F +/*description: time from start cocpu to pull down reset.*/ +#define RTC_CNTL_COCPU_START_2_RESET_DIS 0x0000003F #define RTC_CNTL_COCPU_START_2_RESET_DIS_M ((RTC_CNTL_COCPU_START_2_RESET_DIS_V)<<(RTC_CNTL_COCPU_START_2_RESET_DIS_S)) #define RTC_CNTL_COCPU_START_2_RESET_DIS_V 0x3F #define RTC_CNTL_COCPU_START_2_RESET_DIS_S 1 /* RTC_CNTL_COCPU_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: cocpu clk force on*/ -#define RTC_CNTL_COCPU_CLK_FO (BIT(0)) +/*description: cocpu clk force on.*/ +#define RTC_CNTL_COCPU_CLK_FO (BIT(0)) #define RTC_CNTL_COCPU_CLK_FO_M (BIT(0)) #define RTC_CNTL_COCPU_CLK_FO_V 0x1 #define RTC_CNTL_COCPU_CLK_FO_S 0 -#define RTC_CNTL_TOUCH_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x0104) +#define RTC_CNTL_TOUCH_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x108) /* RTC_CNTL_TOUCH_MEAS_NUM : R/W ;bitpos:[31:16] ;default: 16'h1000 ; */ -/*description: the meas length (in 8MHz)*/ -#define RTC_CNTL_TOUCH_MEAS_NUM 0x0000FFFF +/*description: the meas length (in 8MHz).*/ +#define RTC_CNTL_TOUCH_MEAS_NUM 0x0000FFFF #define RTC_CNTL_TOUCH_MEAS_NUM_M ((RTC_CNTL_TOUCH_MEAS_NUM_V)<<(RTC_CNTL_TOUCH_MEAS_NUM_S)) #define RTC_CNTL_TOUCH_MEAS_NUM_V 0xFFFF #define RTC_CNTL_TOUCH_MEAS_NUM_S 16 /* RTC_CNTL_TOUCH_SLEEP_CYCLES : R/W ;bitpos:[15:0] ;default: 16'h100 ; */ -/*description: sleep cycles for timer*/ -#define RTC_CNTL_TOUCH_SLEEP_CYCLES 0x0000FFFF +/*description: sleep cycles for timer.*/ +#define RTC_CNTL_TOUCH_SLEEP_CYCLES 0x0000FFFF #define RTC_CNTL_TOUCH_SLEEP_CYCLES_M ((RTC_CNTL_TOUCH_SLEEP_CYCLES_V)<<(RTC_CNTL_TOUCH_SLEEP_CYCLES_S)) #define RTC_CNTL_TOUCH_SLEEP_CYCLES_V 0xFFFF #define RTC_CNTL_TOUCH_SLEEP_CYCLES_S 0 -#define RTC_CNTL_TOUCH_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x0108) +#define RTC_CNTL_TOUCH_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x10C) /* RTC_CNTL_TOUCH_CLKGATE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: touch clock enable*/ -#define RTC_CNTL_TOUCH_CLKGATE_EN (BIT(31)) +/*description: touch clock enable.*/ +#define RTC_CNTL_TOUCH_CLKGATE_EN (BIT(31)) #define RTC_CNTL_TOUCH_CLKGATE_EN_M (BIT(31)) #define RTC_CNTL_TOUCH_CLKGATE_EN_V 0x1 #define RTC_CNTL_TOUCH_CLKGATE_EN_S 31 /* RTC_CNTL_TOUCH_CLK_FO : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: touch clock force on*/ -#define RTC_CNTL_TOUCH_CLK_FO (BIT(30)) +/*description: touch clock force on.*/ +#define RTC_CNTL_TOUCH_CLK_FO (BIT(30)) #define RTC_CNTL_TOUCH_CLK_FO_M (BIT(30)) #define RTC_CNTL_TOUCH_CLK_FO_V 0x1 #define RTC_CNTL_TOUCH_CLK_FO_S 30 /* RTC_CNTL_TOUCH_RESET : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: reset upgrade touch*/ -#define RTC_CNTL_TOUCH_RESET (BIT(29)) +/*description: reset upgrade touch.*/ +#define RTC_CNTL_TOUCH_RESET (BIT(29)) #define RTC_CNTL_TOUCH_RESET_M (BIT(29)) #define RTC_CNTL_TOUCH_RESET_V 0x1 #define RTC_CNTL_TOUCH_RESET_S 29 /* RTC_CNTL_TOUCH_TIMER_FORCE_DONE : R/W ;bitpos:[28:27] ;default: 2'b0 ; */ -/*description: force touch timer done*/ -#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE 0x00000003 +/*description: force touch timer done.*/ +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE 0x00000003 #define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_M ((RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V)<<(RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S)) #define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V 0x3 #define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S 27 /* RTC_CNTL_TOUCH_SLP_CYC_DIV : R/W ;bitpos:[26:25] ;default: 2'd0 ; */ -/*description: when a touch pad is active*/ -#define RTC_CNTL_TOUCH_SLP_CYC_DIV 0x00000003 +/*description: when a touch pad is active.*/ +#define RTC_CNTL_TOUCH_SLP_CYC_DIV 0x00000003 #define RTC_CNTL_TOUCH_SLP_CYC_DIV_M ((RTC_CNTL_TOUCH_SLP_CYC_DIV_V)<<(RTC_CNTL_TOUCH_SLP_CYC_DIV_S)) #define RTC_CNTL_TOUCH_SLP_CYC_DIV_V 0x3 #define RTC_CNTL_TOUCH_SLP_CYC_DIV_S 25 /* RTC_CNTL_TOUCH_XPD_WAIT : R/W ;bitpos:[24:17] ;default: 8'h4 ; */ -/*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/ -#define RTC_CNTL_TOUCH_XPD_WAIT 0x000000FF +/*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD.*/ +#define RTC_CNTL_TOUCH_XPD_WAIT 0x000000FF #define RTC_CNTL_TOUCH_XPD_WAIT_M ((RTC_CNTL_TOUCH_XPD_WAIT_V)<<(RTC_CNTL_TOUCH_XPD_WAIT_S)) #define RTC_CNTL_TOUCH_XPD_WAIT_V 0xFF #define RTC_CNTL_TOUCH_XPD_WAIT_S 17 /* RTC_CNTL_TOUCH_START_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: 1: to start touch fsm by SW*/ -#define RTC_CNTL_TOUCH_START_FORCE (BIT(16)) +/*description: 1: to start touch fsm by SW.*/ +#define RTC_CNTL_TOUCH_START_FORCE (BIT(16)) #define RTC_CNTL_TOUCH_START_FORCE_M (BIT(16)) #define RTC_CNTL_TOUCH_START_FORCE_V 0x1 #define RTC_CNTL_TOUCH_START_FORCE_S 16 /* RTC_CNTL_TOUCH_START_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: 1: start touch fsm*/ -#define RTC_CNTL_TOUCH_START_EN (BIT(15)) +/*description: 1: start touch fsm.*/ +#define RTC_CNTL_TOUCH_START_EN (BIT(15)) #define RTC_CNTL_TOUCH_START_EN_M (BIT(15)) #define RTC_CNTL_TOUCH_START_EN_V 0x1 #define RTC_CNTL_TOUCH_START_EN_S 15 /* RTC_CNTL_TOUCH_START_FSM_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ -/*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm*/ -#define RTC_CNTL_TOUCH_START_FSM_EN (BIT(14)) +/*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm.*/ +#define RTC_CNTL_TOUCH_START_FSM_EN (BIT(14)) #define RTC_CNTL_TOUCH_START_FSM_EN_M (BIT(14)) #define RTC_CNTL_TOUCH_START_FSM_EN_V 0x1 #define RTC_CNTL_TOUCH_START_FSM_EN_S 14 /* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: touch timer enable bit*/ -#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(13)) +/*description: touch timer enable bit.*/ +#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(13)) #define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (BIT(13)) #define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x1 #define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 13 /* RTC_CNTL_TOUCH_DBIAS : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: 1:use self bias 0:use bandgap bias*/ -#define RTC_CNTL_TOUCH_DBIAS (BIT(12)) +/*description: 1:use self bias 0:use bandgap bias.*/ +#define RTC_CNTL_TOUCH_DBIAS (BIT(12)) #define RTC_CNTL_TOUCH_DBIAS_M (BIT(12)) #define RTC_CNTL_TOUCH_DBIAS_V 0x1 #define RTC_CNTL_TOUCH_DBIAS_S 12 /* RTC_CNTL_TOUCH_REFC : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ -/*description: TOUCH pad0 reference cap*/ -#define RTC_CNTL_TOUCH_REFC 0x00000007 +/*description: TOUCH pad0 reference cap.*/ +#define RTC_CNTL_TOUCH_REFC 0x00000007 #define RTC_CNTL_TOUCH_REFC_M ((RTC_CNTL_TOUCH_REFC_V)<<(RTC_CNTL_TOUCH_REFC_S)) #define RTC_CNTL_TOUCH_REFC_V 0x7 #define RTC_CNTL_TOUCH_REFC_S 9 /* RTC_CNTL_TOUCH_XPD_BIAS : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: TOUCH_XPD_BIAS*/ -#define RTC_CNTL_TOUCH_XPD_BIAS (BIT(8)) +/*description: TOUCH_XPD_BIAS.*/ +#define RTC_CNTL_TOUCH_XPD_BIAS (BIT(8)) #define RTC_CNTL_TOUCH_XPD_BIAS_M (BIT(8)) #define RTC_CNTL_TOUCH_XPD_BIAS_V 0x1 #define RTC_CNTL_TOUCH_XPD_BIAS_S 8 /* RTC_CNTL_TOUCH_DREFH : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ -/*description: TOUCH_DREFH*/ -#define RTC_CNTL_TOUCH_DREFH 0x00000003 +/*description: TOUCH_DREFH.*/ +#define RTC_CNTL_TOUCH_DREFH 0x00000003 #define RTC_CNTL_TOUCH_DREFH_M ((RTC_CNTL_TOUCH_DREFH_V)<<(RTC_CNTL_TOUCH_DREFH_S)) #define RTC_CNTL_TOUCH_DREFH_V 0x3 #define RTC_CNTL_TOUCH_DREFH_S 6 /* RTC_CNTL_TOUCH_DREFL : R/W ;bitpos:[5:4] ;default: 2'b00 ; */ -/*description: TOUCH_DREFL*/ -#define RTC_CNTL_TOUCH_DREFL 0x00000003 +/*description: TOUCH_DREFL.*/ +#define RTC_CNTL_TOUCH_DREFL 0x00000003 #define RTC_CNTL_TOUCH_DREFL_M ((RTC_CNTL_TOUCH_DREFL_V)<<(RTC_CNTL_TOUCH_DREFL_S)) #define RTC_CNTL_TOUCH_DREFL_V 0x3 #define RTC_CNTL_TOUCH_DREFL_S 4 /* RTC_CNTL_TOUCH_DRANGE : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ -/*description: TOUCH_DRANGE*/ -#define RTC_CNTL_TOUCH_DRANGE 0x00000003 +/*description: TOUCH_DRANGE.*/ +#define RTC_CNTL_TOUCH_DRANGE 0x00000003 #define RTC_CNTL_TOUCH_DRANGE_M ((RTC_CNTL_TOUCH_DRANGE_V)<<(RTC_CNTL_TOUCH_DRANGE_S)) #define RTC_CNTL_TOUCH_DRANGE_V 0x3 #define RTC_CNTL_TOUCH_DRANGE_S 2 -#define RTC_CNTL_TOUCH_SCAN_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x010C) +#define RTC_CNTL_TOUCH_SCAN_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x110) /* RTC_CNTL_TOUCH_OUT_RING : R/W ;bitpos:[31:28] ;default: 4'hf ; */ -/*description: select out ring pad*/ -#define RTC_CNTL_TOUCH_OUT_RING 0x0000000F +/*description: select out ring pad.*/ +#define RTC_CNTL_TOUCH_OUT_RING 0x0000000F #define RTC_CNTL_TOUCH_OUT_RING_M ((RTC_CNTL_TOUCH_OUT_RING_V)<<(RTC_CNTL_TOUCH_OUT_RING_S)) #define RTC_CNTL_TOUCH_OUT_RING_V 0xF #define RTC_CNTL_TOUCH_OUT_RING_S 28 /* RTC_CNTL_TOUCH_BUFDRV : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ -/*description: touch7 buffer driver strength*/ -#define RTC_CNTL_TOUCH_BUFDRV 0x00000007 +/*description: touch7 buffer driver strength.*/ +#define RTC_CNTL_TOUCH_BUFDRV 0x00000007 #define RTC_CNTL_TOUCH_BUFDRV_M ((RTC_CNTL_TOUCH_BUFDRV_V)<<(RTC_CNTL_TOUCH_BUFDRV_S)) #define RTC_CNTL_TOUCH_BUFDRV_V 0x7 #define RTC_CNTL_TOUCH_BUFDRV_S 25 /* RTC_CNTL_TOUCH_SCAN_PAD_MAP : R/W ;bitpos:[24:10] ;default: 15'h0 ; */ -/*description: touch scan mode pad enable map*/ -#define RTC_CNTL_TOUCH_SCAN_PAD_MAP 0x00007FFF +/*description: touch scan mode pad enable map.*/ +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP 0x00007FFF #define RTC_CNTL_TOUCH_SCAN_PAD_MAP_M ((RTC_CNTL_TOUCH_SCAN_PAD_MAP_V)<<(RTC_CNTL_TOUCH_SCAN_PAD_MAP_S)) #define RTC_CNTL_TOUCH_SCAN_PAD_MAP_V 0x7FFF #define RTC_CNTL_TOUCH_SCAN_PAD_MAP_S 10 /* RTC_CNTL_TOUCH_SHIELD_PAD_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: touch pad14 will be used as shield*/ -#define RTC_CNTL_TOUCH_SHIELD_PAD_EN (BIT(9)) +/*description: touch pad14 will be used as shield.*/ +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN (BIT(9)) #define RTC_CNTL_TOUCH_SHIELD_PAD_EN_M (BIT(9)) #define RTC_CNTL_TOUCH_SHIELD_PAD_EN_V 0x1 #define RTC_CNTL_TOUCH_SHIELD_PAD_EN_S 9 /* RTC_CNTL_TOUCH_INACTIVE_CONNECTION : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: inactive touch pads connect to 1: gnd 0: HighZ*/ -#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION (BIT(8)) +/*description: inactive touch pads connect to 1: gnd 0: HighZ.*/ +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_M (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V 0x1 #define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S 8 /* RTC_CNTL_TOUCH_DENOISE_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: touch pad0 will be used to de-noise*/ -#define RTC_CNTL_TOUCH_DENOISE_EN (BIT(2)) +/*description: touch pad0 will be used to de-noise.*/ +#define RTC_CNTL_TOUCH_DENOISE_EN (BIT(2)) #define RTC_CNTL_TOUCH_DENOISE_EN_M (BIT(2)) #define RTC_CNTL_TOUCH_DENOISE_EN_V 0x1 #define RTC_CNTL_TOUCH_DENOISE_EN_S 2 /* RTC_CNTL_TOUCH_DENOISE_RES : R/W ;bitpos:[1:0] ;default: 2'd2 ; */ -/*description: De-noise resolution: 12/10/8/4 bit*/ -#define RTC_CNTL_TOUCH_DENOISE_RES 0x00000003 +/*description: De-noise resolution: 12/10/8/4 bit.*/ +#define RTC_CNTL_TOUCH_DENOISE_RES 0x00000003 #define RTC_CNTL_TOUCH_DENOISE_RES_M ((RTC_CNTL_TOUCH_DENOISE_RES_V)<<(RTC_CNTL_TOUCH_DENOISE_RES_S)) #define RTC_CNTL_TOUCH_DENOISE_RES_V 0x3 #define RTC_CNTL_TOUCH_DENOISE_RES_S 0 -#define RTC_CNTL_TOUCH_SLP_THRES_REG (DR_REG_RTCCNTL_BASE + 0x0110) -/* RTC_CNTL_TOUCH_SLP_PAD : R/W ;bitpos:[31:27] ;default: 4'hF ; */ -/*description: */ -#define RTC_CNTL_TOUCH_SLP_PAD 0x0000001F +#define RTC_CNTL_TOUCH_SLP_THRES_REG (DR_REG_RTCCNTL_BASE + 0x114) +/* RTC_CNTL_TOUCH_SLP_PAD : R/W ;bitpos:[31:27] ;default: 4'hf ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_SLP_PAD 0x0000001F #define RTC_CNTL_TOUCH_SLP_PAD_M ((RTC_CNTL_TOUCH_SLP_PAD_V)<<(RTC_CNTL_TOUCH_SLP_PAD_S)) #define RTC_CNTL_TOUCH_SLP_PAD_V 0x1F #define RTC_CNTL_TOUCH_SLP_PAD_S 27 /* RTC_CNTL_TOUCH_SLP_APPROACH_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: sleep pad approach function enable*/ -#define RTC_CNTL_TOUCH_SLP_APPROACH_EN (BIT(26)) +/*description: sleep pad approach function enable.*/ +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN (BIT(26)) #define RTC_CNTL_TOUCH_SLP_APPROACH_EN_M (BIT(26)) #define RTC_CNTL_TOUCH_SLP_APPROACH_EN_V 0x1 #define RTC_CNTL_TOUCH_SLP_APPROACH_EN_S 26 /* RTC_CNTL_TOUCH_SLP_TH : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: the threshold for sleep touch pad*/ -#define RTC_CNTL_TOUCH_SLP_TH 0x003FFFFF +/*description: the threshold for sleep touch pad.*/ +#define RTC_CNTL_TOUCH_SLP_TH 0x003FFFFF #define RTC_CNTL_TOUCH_SLP_TH_M ((RTC_CNTL_TOUCH_SLP_TH_V)<<(RTC_CNTL_TOUCH_SLP_TH_S)) #define RTC_CNTL_TOUCH_SLP_TH_V 0x3FFFFF #define RTC_CNTL_TOUCH_SLP_TH_S 0 -#define RTC_CNTL_TOUCH_APPROACH_REG (DR_REG_RTCCNTL_BASE + 0x0114) +#define RTC_CNTL_TOUCH_APPROACH_REG (DR_REG_RTCCNTL_BASE + 0x118) /* RTC_CNTL_TOUCH_APPROACH_MEAS_TIME : R/W ;bitpos:[31:24] ;default: 8'd80 ; */ -/*description: approach pads total meas times*/ -#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME 0x000000FF +/*description: approach pads total meas times.*/ +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME 0x000000FF #define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_M ((RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V)<<(RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S)) #define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V 0xFF #define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S 24 /* RTC_CNTL_TOUCH_SLP_CHANNEL_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */ -/*description: clear touch slp channel*/ -#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR (BIT(23)) +/*description: clear touch slp channel.*/ +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR (BIT(23)) #define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_M (BIT(23)) #define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V 0x1 #define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S 23 -#define RTC_CNTL_TOUCH_FILTER_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0118) +#define RTC_CNTL_TOUCH_FILTER_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x11C) /* RTC_CNTL_TOUCH_FILTER_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: touch filter enable*/ -#define RTC_CNTL_TOUCH_FILTER_EN (BIT(31)) +/*description: touch filter enable.*/ +#define RTC_CNTL_TOUCH_FILTER_EN (BIT(31)) #define RTC_CNTL_TOUCH_FILTER_EN_M (BIT(31)) #define RTC_CNTL_TOUCH_FILTER_EN_V 0x1 #define RTC_CNTL_TOUCH_FILTER_EN_S 31 /* RTC_CNTL_TOUCH_FILTER_MODE : R/W ;bitpos:[30:28] ;default: 3'd1 ; */ -/*description: 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter*/ -#define RTC_CNTL_TOUCH_FILTER_MODE 0x00000007 +/*description: 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter.*/ +#define RTC_CNTL_TOUCH_FILTER_MODE 0x00000007 #define RTC_CNTL_TOUCH_FILTER_MODE_M ((RTC_CNTL_TOUCH_FILTER_MODE_V)<<(RTC_CNTL_TOUCH_FILTER_MODE_S)) #define RTC_CNTL_TOUCH_FILTER_MODE_V 0x7 #define RTC_CNTL_TOUCH_FILTER_MODE_S 28 /* RTC_CNTL_TOUCH_DEBOUNCE : R/W ;bitpos:[27:25] ;default: 3'd3 ; */ -/*description: debounce counter*/ -#define RTC_CNTL_TOUCH_DEBOUNCE 0x00000007 +/*description: debounce counter.*/ +#define RTC_CNTL_TOUCH_DEBOUNCE 0x00000007 #define RTC_CNTL_TOUCH_DEBOUNCE_M ((RTC_CNTL_TOUCH_DEBOUNCE_V)<<(RTC_CNTL_TOUCH_DEBOUNCE_S)) #define RTC_CNTL_TOUCH_DEBOUNCE_V 0x7 #define RTC_CNTL_TOUCH_DEBOUNCE_S 25 /* RTC_CNTL_TOUCH_HYSTERESIS : R/W ;bitpos:[24:23] ;default: 2'd1 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_HYSTERESIS 0x00000003 +/*description: .*/ +#define RTC_CNTL_TOUCH_HYSTERESIS 0x00000003 #define RTC_CNTL_TOUCH_HYSTERESIS_M ((RTC_CNTL_TOUCH_HYSTERESIS_V)<<(RTC_CNTL_TOUCH_HYSTERESIS_S)) #define RTC_CNTL_TOUCH_HYSTERESIS_V 0x3 #define RTC_CNTL_TOUCH_HYSTERESIS_S 23 /* RTC_CNTL_TOUCH_NOISE_THRES : R/W ;bitpos:[22:21] ;default: 2'd1 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_NOISE_THRES 0x00000003 +/*description: .*/ +#define RTC_CNTL_TOUCH_NOISE_THRES 0x00000003 #define RTC_CNTL_TOUCH_NOISE_THRES_M ((RTC_CNTL_TOUCH_NOISE_THRES_V)<<(RTC_CNTL_TOUCH_NOISE_THRES_S)) #define RTC_CNTL_TOUCH_NOISE_THRES_V 0x3 #define RTC_CNTL_TOUCH_NOISE_THRES_S 21 /* RTC_CNTL_TOUCH_NEG_NOISE_THRES : R/W ;bitpos:[20:19] ;default: 2'd1 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_NEG_NOISE_THRES 0x00000003 +/*description: .*/ +#define RTC_CNTL_TOUCH_NEG_NOISE_THRES 0x00000003 #define RTC_CNTL_TOUCH_NEG_NOISE_THRES_M ((RTC_CNTL_TOUCH_NEG_NOISE_THRES_V)<<(RTC_CNTL_TOUCH_NEG_NOISE_THRES_S)) #define RTC_CNTL_TOUCH_NEG_NOISE_THRES_V 0x3 #define RTC_CNTL_TOUCH_NEG_NOISE_THRES_S 19 /* RTC_CNTL_TOUCH_NEG_NOISE_LIMIT : R/W ;bitpos:[18:15] ;default: 4'd5 ; */ -/*description: negative threshold counter limit*/ -#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT 0x0000000F +/*description: negative threshold counter limit.*/ +#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT 0x0000000F #define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_M ((RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V)<<(RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S)) #define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V 0xF #define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S 15 /* RTC_CNTL_TOUCH_JITTER_STEP : R/W ;bitpos:[14:11] ;default: 4'd1 ; */ -/*description: touch jitter step*/ -#define RTC_CNTL_TOUCH_JITTER_STEP 0x0000000F +/*description: touch jitter step.*/ +#define RTC_CNTL_TOUCH_JITTER_STEP 0x0000000F #define RTC_CNTL_TOUCH_JITTER_STEP_M ((RTC_CNTL_TOUCH_JITTER_STEP_V)<<(RTC_CNTL_TOUCH_JITTER_STEP_S)) #define RTC_CNTL_TOUCH_JITTER_STEP_V 0xF #define RTC_CNTL_TOUCH_JITTER_STEP_S 11 /* RTC_CNTL_TOUCH_SMOOTH_LVL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_SMOOTH_LVL 0x00000003 +/*description: .*/ +#define RTC_CNTL_TOUCH_SMOOTH_LVL 0x00000003 #define RTC_CNTL_TOUCH_SMOOTH_LVL_M ((RTC_CNTL_TOUCH_SMOOTH_LVL_V)<<(RTC_CNTL_TOUCH_SMOOTH_LVL_S)) #define RTC_CNTL_TOUCH_SMOOTH_LVL_V 0x3 #define RTC_CNTL_TOUCH_SMOOTH_LVL_S 9 /* RTC_CNTL_TOUCH_BYPASS_NOISE_THRES : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES (BIT(8)) +/*description: .*/ +#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES (BIT(8)) #define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_M (BIT(8)) #define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_V 0x1 #define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_S 8 /* RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES (BIT(7)) +/*description: .*/ +#define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES (BIT(7)) #define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_M (BIT(7)) #define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_V 0x1 #define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_S 7 -#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x011C) +#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x120) +/* RTC_CNTL_SW_HW_USB_PHY_SEL : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_SW_HW_USB_PHY_SEL (BIT(20)) +#define RTC_CNTL_SW_HW_USB_PHY_SEL_M (BIT(20)) +#define RTC_CNTL_SW_HW_USB_PHY_SEL_V 0x1 +#define RTC_CNTL_SW_HW_USB_PHY_SEL_S 20 +/* RTC_CNTL_SW_USB_PHY_SEL : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_SW_USB_PHY_SEL (BIT(19)) +#define RTC_CNTL_SW_USB_PHY_SEL_M (BIT(19)) +#define RTC_CNTL_SW_USB_PHY_SEL_V 0x1 +#define RTC_CNTL_SW_USB_PHY_SEL_S 19 /* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) +/*description: .*/ +#define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) #define RTC_CNTL_IO_MUX_RESET_DISABLE_M (BIT(18)) #define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x1 #define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 /* RTC_CNTL_USB_RESET_DISABLE : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_RESET_DISABLE (BIT(17)) +/*description: .*/ +#define RTC_CNTL_USB_RESET_DISABLE (BIT(17)) #define RTC_CNTL_USB_RESET_DISABLE_M (BIT(17)) #define RTC_CNTL_USB_RESET_DISABLE_V 0x1 #define RTC_CNTL_USB_RESET_DISABLE_S 17 /* RTC_CNTL_USB_TX_EN_OVERRIDE : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_TX_EN_OVERRIDE (BIT(16)) +/*description: .*/ +#define RTC_CNTL_USB_TX_EN_OVERRIDE (BIT(16)) #define RTC_CNTL_USB_TX_EN_OVERRIDE_M (BIT(16)) #define RTC_CNTL_USB_TX_EN_OVERRIDE_V 0x1 #define RTC_CNTL_USB_TX_EN_OVERRIDE_S 16 /* RTC_CNTL_USB_TX_EN : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_TX_EN (BIT(15)) +/*description: .*/ +#define RTC_CNTL_USB_TX_EN (BIT(15)) #define RTC_CNTL_USB_TX_EN_M (BIT(15)) #define RTC_CNTL_USB_TX_EN_V 0x1 #define RTC_CNTL_USB_TX_EN_S 15 /* RTC_CNTL_USB_TXP : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_TXP (BIT(14)) +/*description: .*/ +#define RTC_CNTL_USB_TXP (BIT(14)) #define RTC_CNTL_USB_TXP_M (BIT(14)) #define RTC_CNTL_USB_TXP_V 0x1 #define RTC_CNTL_USB_TXP_S 14 /* RTC_CNTL_USB_TXM : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_TXM (BIT(13)) +/*description: .*/ +#define RTC_CNTL_USB_TXM (BIT(13)) #define RTC_CNTL_USB_TXM_M (BIT(13)) #define RTC_CNTL_USB_TXM_V 0x1 #define RTC_CNTL_USB_TXM_S 13 /* RTC_CNTL_USB_PAD_ENABLE : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_PAD_ENABLE (BIT(12)) +/*description: .*/ +#define RTC_CNTL_USB_PAD_ENABLE (BIT(12)) #define RTC_CNTL_USB_PAD_ENABLE_M (BIT(12)) #define RTC_CNTL_USB_PAD_ENABLE_V 0x1 #define RTC_CNTL_USB_PAD_ENABLE_S 12 /* RTC_CNTL_USB_PAD_ENABLE_OVERRIDE : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE (BIT(11)) +/*description: .*/ +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE (BIT(11)) #define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_M (BIT(11)) #define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V 0x1 #define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S 11 /* RTC_CNTL_USB_PULLUP_VALUE : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_PULLUP_VALUE (BIT(10)) +/*description: .*/ +#define RTC_CNTL_USB_PULLUP_VALUE (BIT(10)) #define RTC_CNTL_USB_PULLUP_VALUE_M (BIT(10)) #define RTC_CNTL_USB_PULLUP_VALUE_V 0x1 #define RTC_CNTL_USB_PULLUP_VALUE_S 10 /* RTC_CNTL_USB_DM_PULLDOWN : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_DM_PULLDOWN (BIT(9)) +/*description: .*/ +#define RTC_CNTL_USB_DM_PULLDOWN (BIT(9)) #define RTC_CNTL_USB_DM_PULLDOWN_M (BIT(9)) #define RTC_CNTL_USB_DM_PULLDOWN_V 0x1 #define RTC_CNTL_USB_DM_PULLDOWN_S 9 /* RTC_CNTL_USB_DM_PULLUP : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_DM_PULLUP (BIT(8)) +/*description: .*/ +#define RTC_CNTL_USB_DM_PULLUP (BIT(8)) #define RTC_CNTL_USB_DM_PULLUP_M (BIT(8)) #define RTC_CNTL_USB_DM_PULLUP_V 0x1 #define RTC_CNTL_USB_DM_PULLUP_S 8 /* RTC_CNTL_USB_DP_PULLDOWN : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_DP_PULLDOWN (BIT(7)) +/*description: .*/ +#define RTC_CNTL_USB_DP_PULLDOWN (BIT(7)) #define RTC_CNTL_USB_DP_PULLDOWN_M (BIT(7)) #define RTC_CNTL_USB_DP_PULLDOWN_V 0x1 #define RTC_CNTL_USB_DP_PULLDOWN_S 7 /* RTC_CNTL_USB_DP_PULLUP : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_DP_PULLUP (BIT(6)) +/*description: .*/ +#define RTC_CNTL_USB_DP_PULLUP (BIT(6)) #define RTC_CNTL_USB_DP_PULLUP_M (BIT(6)) #define RTC_CNTL_USB_DP_PULLUP_V 0x1 #define RTC_CNTL_USB_DP_PULLUP_S 6 /* RTC_CNTL_USB_PAD_PULL_OVERRIDE : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_PAD_PULL_OVERRIDE (BIT(5)) +/*description: .*/ +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE (BIT(5)) #define RTC_CNTL_USB_PAD_PULL_OVERRIDE_M (BIT(5)) #define RTC_CNTL_USB_PAD_PULL_OVERRIDE_V 0x1 #define RTC_CNTL_USB_PAD_PULL_OVERRIDE_S 5 /* RTC_CNTL_USB_VREF_OVERRIDE : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_VREF_OVERRIDE (BIT(4)) +/*description: .*/ +#define RTC_CNTL_USB_VREF_OVERRIDE (BIT(4)) #define RTC_CNTL_USB_VREF_OVERRIDE_M (BIT(4)) #define RTC_CNTL_USB_VREF_OVERRIDE_V 0x1 #define RTC_CNTL_USB_VREF_OVERRIDE_S 4 /* RTC_CNTL_USB_VREFL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_VREFL 0x00000003 +/*description: .*/ +#define RTC_CNTL_USB_VREFL 0x00000003 #define RTC_CNTL_USB_VREFL_M ((RTC_CNTL_USB_VREFL_V)<<(RTC_CNTL_USB_VREFL_S)) #define RTC_CNTL_USB_VREFL_V 0x3 #define RTC_CNTL_USB_VREFL_S 2 /* RTC_CNTL_USB_VREFH : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: */ -#define RTC_CNTL_USB_VREFH 0x00000003 +/*description: .*/ +#define RTC_CNTL_USB_VREFH 0x00000003 #define RTC_CNTL_USB_VREFH_M ((RTC_CNTL_USB_VREFH_V)<<(RTC_CNTL_USB_VREFH_S)) #define RTC_CNTL_USB_VREFH_V 0x3 #define RTC_CNTL_USB_VREFH_S 0 -#define RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0120) +#define RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x124) /* RTC_CNTL_TOUCH_TIMEOUT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_TIMEOUT_EN (BIT(22)) +/*description: .*/ +#define RTC_CNTL_TOUCH_TIMEOUT_EN (BIT(22)) #define RTC_CNTL_TOUCH_TIMEOUT_EN_M (BIT(22)) #define RTC_CNTL_TOUCH_TIMEOUT_EN_V 0x1 #define RTC_CNTL_TOUCH_TIMEOUT_EN_S 22 /* RTC_CNTL_TOUCH_TIMEOUT_NUM : R/W ;bitpos:[21:0] ;default: 22'h3fffff ; */ -/*description: */ -#define RTC_CNTL_TOUCH_TIMEOUT_NUM 0x003FFFFF +/*description: .*/ +#define RTC_CNTL_TOUCH_TIMEOUT_NUM 0x003FFFFF #define RTC_CNTL_TOUCH_TIMEOUT_NUM_M ((RTC_CNTL_TOUCH_TIMEOUT_NUM_V)<<(RTC_CNTL_TOUCH_TIMEOUT_NUM_S)) #define RTC_CNTL_TOUCH_TIMEOUT_NUM_V 0x3FFFFF #define RTC_CNTL_TOUCH_TIMEOUT_NUM_S 0 -#define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x0124) +#define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x128) /* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[17:0] ;default: 18'd0 ; */ -/*description: sleep reject cause*/ -#define RTC_CNTL_REJECT_CAUSE 0x0003FFFF +/*description: sleep reject cause.*/ +#define RTC_CNTL_REJECT_CAUSE 0x0003FFFF #define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) #define RTC_CNTL_REJECT_CAUSE_V 0x3FFFF #define RTC_CNTL_REJECT_CAUSE_S 0 -#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x0128) +#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x12C) /* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) +/*description: .*/ +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (BIT(0)) #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x1 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 -#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x012C) +#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x130) /* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */ -/*description: sleep wakeup cause*/ -#define RTC_CNTL_WAKEUP_CAUSE 0x0001FFFF +/*description: sleep wakeup cause.*/ +#define RTC_CNTL_WAKEUP_CAUSE 0x0001FFFF #define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) #define RTC_CNTL_WAKEUP_CAUSE_V 0x1FFFF #define RTC_CNTL_WAKEUP_CAUSE_S 0 -#define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x0130) +#define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x134) /* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */ -/*description: sleep cycles for ULP-coprocessor timer*/ -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF +/*description: sleep cycles for ULP-coprocessor timer.*/ +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S)) #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0xFFFFFF #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 -#define RTC_CNTL_INT_ENA_W1TS_REG (DR_REG_RTCCNTL_BASE + 0x0134) +#define RTC_CNTL_INT_ENA_RTC_W1TS_REG (DR_REG_RTCCNTL_BASE + 0x138) /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS (BIT(20)) +/*description: .*/ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_M (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S 20 /* RTC_CNTL_GLITCH_DET_INT_ENA_W1TS : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: enbale gitch det interrupt*/ -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS (BIT(19)) +/*description: enbale gitch det interrupt.*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S 19 /* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: enable touch timeout interrupt*/ -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS (BIT(18)) +/*description: enable touch timeout interrupt.*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_M (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_S 18 /* RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: enable cocpu trap interrupt*/ -#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS (BIT(17)) +/*description: enable cocpu trap interrupt.*/ +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_M (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_S 17 /* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: enable xtal32k_dead interrupt*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS (BIT(16)) +/*description: enable xtal32k_dead interrupt.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_M (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S 16 /* RTC_CNTL_SWD_INT_ENA_W1TS : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: enable super watch dog interrupt*/ -#define RTC_CNTL_SWD_INT_ENA_W1TS (BIT(15)) +/*description: enable super watch dog interrupt.*/ +#define RTC_CNTL_SWD_INT_ENA_W1TS (BIT(15)) #define RTC_CNTL_SWD_INT_ENA_W1TS_M (BIT(15)) #define RTC_CNTL_SWD_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_SWD_INT_ENA_W1TS_S 15 /* RTC_CNTL_SARADC2_INT_ENA_W1TS : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: enable saradc2 interrupt*/ -#define RTC_CNTL_SARADC2_INT_ENA_W1TS (BIT(14)) +/*description: enable saradc2 interrupt.*/ +#define RTC_CNTL_SARADC2_INT_ENA_W1TS (BIT(14)) #define RTC_CNTL_SARADC2_INT_ENA_W1TS_M (BIT(14)) #define RTC_CNTL_SARADC2_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_SARADC2_INT_ENA_W1TS_S 14 /* RTC_CNTL_COCPU_INT_ENA_W1TS : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: enable riscV cocpu interrupt*/ -#define RTC_CNTL_COCPU_INT_ENA_W1TS (BIT(13)) +/*description: enable riscV cocpu interrupt.*/ +#define RTC_CNTL_COCPU_INT_ENA_W1TS (BIT(13)) #define RTC_CNTL_COCPU_INT_ENA_W1TS_M (BIT(13)) #define RTC_CNTL_COCPU_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_COCPU_INT_ENA_W1TS_S 13 /* RTC_CNTL_TSENS_INT_ENA_W1TS : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: enable tsens interrupt*/ -#define RTC_CNTL_TSENS_INT_ENA_W1TS (BIT(12)) +/*description: enable tsens interrupt.*/ +#define RTC_CNTL_TSENS_INT_ENA_W1TS (BIT(12)) #define RTC_CNTL_TSENS_INT_ENA_W1TS_M (BIT(12)) #define RTC_CNTL_TSENS_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_TSENS_INT_ENA_W1TS_S 12 /* RTC_CNTL_SARADC1_INT_ENA_W1TS : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: enable saradc1 interrupt*/ -#define RTC_CNTL_SARADC1_INT_ENA_W1TS (BIT(11)) +/*description: enable saradc1 interrupt.*/ +#define RTC_CNTL_SARADC1_INT_ENA_W1TS (BIT(11)) #define RTC_CNTL_SARADC1_INT_ENA_W1TS_M (BIT(11)) #define RTC_CNTL_SARADC1_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_SARADC1_INT_ENA_W1TS_S 11 /* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: enable RTC main timer interrupt*/ -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS (BIT(10)) +/*description: enable RTC main timer interrupt.*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S 10 /* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: enable brown out interrupt*/ -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS (BIT(9)) +/*description: enable brown out interrupt.*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S 9 /* RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: enable touch inactive interrupt*/ -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS (BIT(8)) +/*description: enable touch inactive interrupt.*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_M (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_S 8 /* RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: enable touch active interrupt*/ -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS (BIT(7)) +/*description: enable touch active interrupt.*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_M (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_S 7 /* RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: enable touch done interrupt*/ -#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS (BIT(6)) +/*description: enable touch done interrupt.*/ +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_M (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_S 6 /* RTC_CNTL_ULP_CP_INT_ENA_W1TS : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: enable ULP-coprocessor interrupt*/ -#define RTC_CNTL_ULP_CP_INT_ENA_W1TS (BIT(5)) +/*description: enable ULP-coprocessor interrupt.*/ +#define RTC_CNTL_ULP_CP_INT_ENA_W1TS (BIT(5)) #define RTC_CNTL_ULP_CP_INT_ENA_W1TS_M (BIT(5)) #define RTC_CNTL_ULP_CP_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_ULP_CP_INT_ENA_W1TS_S 5 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: enable touch scan done interrupt*/ -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS (BIT(4)) +/*description: enable touch scan done interrupt.*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_M (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_S 4 /* RTC_CNTL_WDT_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: enable RTC WDT interrupt*/ -#define RTC_CNTL_WDT_INT_ENA_W1TS (BIT(3)) +/*description: enable RTC WDT interrupt.*/ +#define RTC_CNTL_WDT_INT_ENA_W1TS (BIT(3)) #define RTC_CNTL_WDT_INT_ENA_W1TS_M (BIT(3)) #define RTC_CNTL_WDT_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_WDT_INT_ENA_W1TS_S 3 /* RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: enable SDIO idle interrupt*/ -#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS (BIT(2)) +/*description: enable SDIO idle interrupt.*/ +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_M (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_S 2 /* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: enable sleep reject interrupt*/ -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS (BIT(1)) +/*description: enable sleep reject interrupt.*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S 1 /* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: enable sleep wakeup interrupt*/ -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS (BIT(0)) +/*description: enable sleep wakeup interrupt.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S 0 -#define RTC_CNTL_INT_ENA_W1TC_REG (DR_REG_RTCCNTL_BASE + 0x0138) +#define RTC_CNTL_INT_ENA_RTC_W1TC_REG (DR_REG_RTCCNTL_BASE + 0x13C) /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC (BIT(20)) +/*description: .*/ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_M (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S 20 /* RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: enbale gitch det interrupt*/ -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC (BIT(19)) +/*description: enbale gitch det interrupt.*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S 19 /* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: enable touch timeout interrupt*/ -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC (BIT(18)) +/*description: enable touch timeout interrupt.*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_M (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_S 18 /* RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: enable cocpu trap interrupt*/ -#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC (BIT(17)) +/*description: enable cocpu trap interrupt.*/ +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_M (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_S 17 /* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: enable xtal32k_dead interrupt*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC (BIT(16)) +/*description: enable xtal32k_dead interrupt.*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_M (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S 16 /* RTC_CNTL_SWD_INT_ENA_W1TC : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: enable super watch dog interrupt*/ -#define RTC_CNTL_SWD_INT_ENA_W1TC (BIT(15)) +/*description: enable super watch dog interrupt.*/ +#define RTC_CNTL_SWD_INT_ENA_W1TC (BIT(15)) #define RTC_CNTL_SWD_INT_ENA_W1TC_M (BIT(15)) #define RTC_CNTL_SWD_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_SWD_INT_ENA_W1TC_S 15 /* RTC_CNTL_SARADC2_INT_ENA_W1TC : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: enable saradc2 interrupt*/ -#define RTC_CNTL_SARADC2_INT_ENA_W1TC (BIT(14)) +/*description: enable saradc2 interrupt.*/ +#define RTC_CNTL_SARADC2_INT_ENA_W1TC (BIT(14)) #define RTC_CNTL_SARADC2_INT_ENA_W1TC_M (BIT(14)) #define RTC_CNTL_SARADC2_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_SARADC2_INT_ENA_W1TC_S 14 /* RTC_CNTL_COCPU_INT_ENA_W1TC : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: enable riscV cocpu interrupt*/ -#define RTC_CNTL_COCPU_INT_ENA_W1TC (BIT(13)) +/*description: enable riscV cocpu interrupt.*/ +#define RTC_CNTL_COCPU_INT_ENA_W1TC (BIT(13)) #define RTC_CNTL_COCPU_INT_ENA_W1TC_M (BIT(13)) #define RTC_CNTL_COCPU_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_COCPU_INT_ENA_W1TC_S 13 /* RTC_CNTL_TSENS_INT_ENA_W1TC : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: enable tsens interrupt*/ -#define RTC_CNTL_TSENS_INT_ENA_W1TC (BIT(12)) +/*description: enable tsens interrupt.*/ +#define RTC_CNTL_TSENS_INT_ENA_W1TC (BIT(12)) #define RTC_CNTL_TSENS_INT_ENA_W1TC_M (BIT(12)) #define RTC_CNTL_TSENS_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_TSENS_INT_ENA_W1TC_S 12 /* RTC_CNTL_SARADC1_INT_ENA_W1TC : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: enable saradc1 interrupt*/ -#define RTC_CNTL_SARADC1_INT_ENA_W1TC (BIT(11)) +/*description: enable saradc1 interrupt.*/ +#define RTC_CNTL_SARADC1_INT_ENA_W1TC (BIT(11)) #define RTC_CNTL_SARADC1_INT_ENA_W1TC_M (BIT(11)) #define RTC_CNTL_SARADC1_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_SARADC1_INT_ENA_W1TC_S 11 /* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: enable RTC main timer interrupt*/ -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC (BIT(10)) +/*description: enable RTC main timer interrupt.*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S 10 /* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: enable brown out interrupt*/ -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC (BIT(9)) +/*description: enable brown out interrupt.*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S 9 /* RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: enable touch inactive interrupt*/ -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC (BIT(8)) +/*description: enable touch inactive interrupt.*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_M (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_S 8 /* RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: enable touch active interrupt*/ -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC (BIT(7)) +/*description: enable touch active interrupt.*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_M (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_S 7 /* RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: enable touch done interrupt*/ -#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC (BIT(6)) +/*description: enable touch done interrupt.*/ +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_M (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_S 6 /* RTC_CNTL_ULP_CP_INT_ENA_W1TC : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: enable ULP-coprocessor interrupt*/ -#define RTC_CNTL_ULP_CP_INT_ENA_W1TC (BIT(5)) +/*description: enable ULP-coprocessor interrupt.*/ +#define RTC_CNTL_ULP_CP_INT_ENA_W1TC (BIT(5)) #define RTC_CNTL_ULP_CP_INT_ENA_W1TC_M (BIT(5)) #define RTC_CNTL_ULP_CP_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_ULP_CP_INT_ENA_W1TC_S 5 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: enable touch scan done interrupt*/ -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC (BIT(4)) +/*description: enable touch scan done interrupt.*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_M (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_S 4 /* RTC_CNTL_WDT_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: enable RTC WDT interrupt*/ -#define RTC_CNTL_WDT_INT_ENA_W1TC (BIT(3)) +/*description: enable RTC WDT interrupt.*/ +#define RTC_CNTL_WDT_INT_ENA_W1TC (BIT(3)) #define RTC_CNTL_WDT_INT_ENA_W1TC_M (BIT(3)) #define RTC_CNTL_WDT_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_WDT_INT_ENA_W1TC_S 3 /* RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: enable SDIO idle interrupt*/ -#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC (BIT(2)) +/*description: enable SDIO idle interrupt.*/ +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_M (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_S 2 /* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: enable sleep reject interrupt*/ -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC (BIT(1)) +/*description: enable sleep reject interrupt.*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S 1 /* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: enable sleep wakeup interrupt*/ -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC (BIT(0)) +/*description: enable sleep wakeup interrupt.*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S 0 -#define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x013c) -/* RTC_CNTL_RETENTION_WAIT : R/W ;bitpos:[31:27] ;default: 5'd20 ; */ -/*description: wait cycles for rention operation*/ -#define RTC_CNTL_RETENTION_WAIT 0x0000001F +#define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x140) +/* RTC_CNTL_RETENTION_WAIT : R/W ;bitpos:[31:25] ;default: 7'd20 ; */ +/*description: wait cycles for rention operation.*/ +#define RTC_CNTL_RETENTION_WAIT 0x0000007F #define RTC_CNTL_RETENTION_WAIT_M ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S)) -#define RTC_CNTL_RETENTION_WAIT_V 0x1F -#define RTC_CNTL_RETENTION_WAIT_S 27 -/* RTC_CNTL_RETENTION_EN : R/W ;bitpos:[26] ;default: 1'd0 ; */ -/*description: */ -#define RTC_CNTL_RETENTION_EN (BIT(26)) -#define RTC_CNTL_RETENTION_EN_M (BIT(26)) +#define RTC_CNTL_RETENTION_WAIT_V 0x7F +#define RTC_CNTL_RETENTION_WAIT_S 25 +/* RTC_CNTL_RETENTION_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: .*/ +#define RTC_CNTL_RETENTION_EN (BIT(24)) +#define RTC_CNTL_RETENTION_EN_M (BIT(24)) #define RTC_CNTL_RETENTION_EN_V 0x1 -#define RTC_CNTL_RETENTION_EN_S 26 -/* RTC_CNTL_RETENTION_CLKOFF_WAIT : R/W ;bitpos:[25:22] ;default: 4'd3 ; */ -/*description: */ -#define RTC_CNTL_RETENTION_CLKOFF_WAIT 0x0000000F +#define RTC_CNTL_RETENTION_EN_S 24 +/* RTC_CNTL_RETENTION_CLKOFF_WAIT : R/W ;bitpos:[23:20] ;default: 4'd3 ; */ +/*description: .*/ +#define RTC_CNTL_RETENTION_CLKOFF_WAIT 0x0000000F #define RTC_CNTL_RETENTION_CLKOFF_WAIT_M ((RTC_CNTL_RETENTION_CLKOFF_WAIT_V)<<(RTC_CNTL_RETENTION_CLKOFF_WAIT_S)) #define RTC_CNTL_RETENTION_CLKOFF_WAIT_V 0xF -#define RTC_CNTL_RETENTION_CLKOFF_WAIT_S 22 -/* RTC_CNTL_RETENTION_DONE_WAIT : R/W ;bitpos:[21:19] ;default: 3'd2 ; */ -/*description: */ -#define RTC_CNTL_RETENTION_DONE_WAIT 0x00000007 +#define RTC_CNTL_RETENTION_CLKOFF_WAIT_S 20 +/* RTC_CNTL_RETENTION_DONE_WAIT : R/W ;bitpos:[19:17] ;default: 3'd2 ; */ +/*description: .*/ +#define RTC_CNTL_RETENTION_DONE_WAIT 0x00000007 #define RTC_CNTL_RETENTION_DONE_WAIT_M ((RTC_CNTL_RETENTION_DONE_WAIT_V)<<(RTC_CNTL_RETENTION_DONE_WAIT_S)) #define RTC_CNTL_RETENTION_DONE_WAIT_V 0x7 -#define RTC_CNTL_RETENTION_DONE_WAIT_S 19 -/* RTC_CNTL_RETENTION_CLK_SEL : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define RTC_CNTL_RETENTION_CLK_SEL (BIT(18)) -#define RTC_CNTL_RETENTION_CLK_SEL_M (BIT(18)) +#define RTC_CNTL_RETENTION_DONE_WAIT_S 17 +/* RTC_CNTL_RETENTION_CLK_SEL : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_RETENTION_CLK_SEL (BIT(16)) +#define RTC_CNTL_RETENTION_CLK_SEL_M (BIT(16)) #define RTC_CNTL_RETENTION_CLK_SEL_V 0x1 -#define RTC_CNTL_RETENTION_CLK_SEL_S 18 +#define RTC_CNTL_RETENTION_CLK_SEL_S 16 +/* RTC_CNTL_RETENTION_TARGET : R/W ;bitpos:[15:14] ;default: 2'b0 ; */ +/*description: .*/ +#define RTC_CNTL_RETENTION_TARGET 0x00000003 +#define RTC_CNTL_RETENTION_TARGET_M ((RTC_CNTL_RETENTION_TARGET_V)<<(RTC_CNTL_RETENTION_TARGET_S)) +#define RTC_CNTL_RETENTION_TARGET_V 0x3 +#define RTC_CNTL_RETENTION_TARGET_S 14 +/* RTC_CNTL_RETENTION_TAG_MODE : R/W ;bitpos:[13:10] ;default: 4'd0 ; */ +/*description: .*/ +#define RTC_CNTL_RETENTION_TAG_MODE 0x0000000F +#define RTC_CNTL_RETENTION_TAG_MODE_M ((RTC_CNTL_RETENTION_TAG_MODE_V)<<(RTC_CNTL_RETENTION_TAG_MODE_S)) +#define RTC_CNTL_RETENTION_TAG_MODE_V 0xF +#define RTC_CNTL_RETENTION_TAG_MODE_S 10 -#define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0140) +#define RTC_CNTL_PG_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x144) +/* RTC_CNTL_POWER_GLITCH_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_POWER_GLITCH_EN (BIT(31)) +#define RTC_CNTL_POWER_GLITCH_EN_M (BIT(31)) +#define RTC_CNTL_POWER_GLITCH_EN_V 0x1 +#define RTC_CNTL_POWER_GLITCH_EN_S 31 +/* RTC_CNTL_POWER_GLITCH_EFUSE_SEL : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: select use analog fib signal.*/ +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL (BIT(30)) +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_M (BIT(30)) +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V 0x1 +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S 30 +/* RTC_CNTL_POWER_GLITCH_FORCE_PU : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_POWER_GLITCH_FORCE_PU (BIT(29)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PU_M (BIT(29)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PU_V 0x1 +#define RTC_CNTL_POWER_GLITCH_FORCE_PU_S 29 +/* RTC_CNTL_POWER_GLITCH_FORCE_PD : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_POWER_GLITCH_FORCE_PD (BIT(28)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PD_M (BIT(28)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PD_V 0x1 +#define RTC_CNTL_POWER_GLITCH_FORCE_PD_S 28 +/* RTC_CNTL_POWER_GLITCH_DSENSE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */ +/*description: .*/ +#define RTC_CNTL_POWER_GLITCH_DSENSE 0x00000003 +#define RTC_CNTL_POWER_GLITCH_DSENSE_M ((RTC_CNTL_POWER_GLITCH_DSENSE_V)<<(RTC_CNTL_POWER_GLITCH_DSENSE_S)) +#define RTC_CNTL_POWER_GLITCH_DSENSE_V 0x3 +#define RTC_CNTL_POWER_GLITCH_DSENSE_S 26 + +#define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x148) /* RTC_CNTL_FIB_SEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ -/*description: select use analog fib signal*/ -#define RTC_CNTL_FIB_SEL 0x00000007 +/*description: .*/ +#define RTC_CNTL_FIB_SEL 0x00000007 #define RTC_CNTL_FIB_SEL_M ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S)) #define RTC_CNTL_FIB_SEL_V 0x7 #define RTC_CNTL_FIB_SEL_S 0 -#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x0144) -/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2010090 ; */ -/*description: */ -#define RTC_CNTL_CNTL_DATE 0x0FFFFFFF -#define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S)) -#define RTC_CNTL_CNTL_DATE_V 0xFFFFFFF -#define RTC_CNTL_CNTL_DATE_S 0 +#define RTC_CNTL_TOUCH_DAC_REG (DR_REG_RTCCNTL_BASE + 0x14C) +/* RTC_CNTL_TOUCH_PAD0_DAC : R/W ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD0_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD0_DAC_M ((RTC_CNTL_TOUCH_PAD0_DAC_V)<<(RTC_CNTL_TOUCH_PAD0_DAC_S)) +#define RTC_CNTL_TOUCH_PAD0_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD0_DAC_S 29 +/* RTC_CNTL_TOUCH_PAD1_DAC : R/W ;bitpos:[28:26] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD1_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD1_DAC_M ((RTC_CNTL_TOUCH_PAD1_DAC_V)<<(RTC_CNTL_TOUCH_PAD1_DAC_S)) +#define RTC_CNTL_TOUCH_PAD1_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD1_DAC_S 26 +/* RTC_CNTL_TOUCH_PAD2_DAC : R/W ;bitpos:[25:23] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD2_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD2_DAC_M ((RTC_CNTL_TOUCH_PAD2_DAC_V)<<(RTC_CNTL_TOUCH_PAD2_DAC_S)) +#define RTC_CNTL_TOUCH_PAD2_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD2_DAC_S 23 +/* RTC_CNTL_TOUCH_PAD3_DAC : R/W ;bitpos:[22:20] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD3_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD3_DAC_M ((RTC_CNTL_TOUCH_PAD3_DAC_V)<<(RTC_CNTL_TOUCH_PAD3_DAC_S)) +#define RTC_CNTL_TOUCH_PAD3_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD3_DAC_S 20 +/* RTC_CNTL_TOUCH_PAD4_DAC : R/W ;bitpos:[19:17] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD4_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD4_DAC_M ((RTC_CNTL_TOUCH_PAD4_DAC_V)<<(RTC_CNTL_TOUCH_PAD4_DAC_S)) +#define RTC_CNTL_TOUCH_PAD4_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD4_DAC_S 17 +/* RTC_CNTL_TOUCH_PAD5_DAC : R/W ;bitpos:[16:14] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD5_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD5_DAC_M ((RTC_CNTL_TOUCH_PAD5_DAC_V)<<(RTC_CNTL_TOUCH_PAD5_DAC_S)) +#define RTC_CNTL_TOUCH_PAD5_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD5_DAC_S 14 +/* RTC_CNTL_TOUCH_PAD6_DAC : R/W ;bitpos:[13:11] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD6_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD6_DAC_M ((RTC_CNTL_TOUCH_PAD6_DAC_V)<<(RTC_CNTL_TOUCH_PAD6_DAC_S)) +#define RTC_CNTL_TOUCH_PAD6_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD6_DAC_S 11 +/* RTC_CNTL_TOUCH_PAD7_DAC : R/W ;bitpos:[10:8] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD7_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD7_DAC_M ((RTC_CNTL_TOUCH_PAD7_DAC_V)<<(RTC_CNTL_TOUCH_PAD7_DAC_S)) +#define RTC_CNTL_TOUCH_PAD7_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD7_DAC_S 8 +/* RTC_CNTL_TOUCH_PAD8_DAC : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD8_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD8_DAC_M ((RTC_CNTL_TOUCH_PAD8_DAC_V)<<(RTC_CNTL_TOUCH_PAD8_DAC_S)) +#define RTC_CNTL_TOUCH_PAD8_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD8_DAC_S 5 +/* RTC_CNTL_TOUCH_PAD9_DAC : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD9_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD9_DAC_M ((RTC_CNTL_TOUCH_PAD9_DAC_V)<<(RTC_CNTL_TOUCH_PAD9_DAC_S)) +#define RTC_CNTL_TOUCH_PAD9_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD9_DAC_S 2 + +#define RTC_CNTL_TOUCH_DAC1_REG (DR_REG_RTCCNTL_BASE + 0x150) +/* RTC_CNTL_TOUCH_PAD10_DAC : R/W ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD10_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD10_DAC_M ((RTC_CNTL_TOUCH_PAD10_DAC_V)<<(RTC_CNTL_TOUCH_PAD10_DAC_S)) +#define RTC_CNTL_TOUCH_PAD10_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD10_DAC_S 29 +/* RTC_CNTL_TOUCH_PAD11_DAC : R/W ;bitpos:[28:26] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD11_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD11_DAC_M ((RTC_CNTL_TOUCH_PAD11_DAC_V)<<(RTC_CNTL_TOUCH_PAD11_DAC_S)) +#define RTC_CNTL_TOUCH_PAD11_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD11_DAC_S 26 +/* RTC_CNTL_TOUCH_PAD12_DAC : R/W ;bitpos:[25:23] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD12_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD12_DAC_M ((RTC_CNTL_TOUCH_PAD12_DAC_V)<<(RTC_CNTL_TOUCH_PAD12_DAC_S)) +#define RTC_CNTL_TOUCH_PAD12_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD12_DAC_S 23 +/* RTC_CNTL_TOUCH_PAD13_DAC : R/W ;bitpos:[22:20] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD13_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD13_DAC_M ((RTC_CNTL_TOUCH_PAD13_DAC_V)<<(RTC_CNTL_TOUCH_PAD13_DAC_S)) +#define RTC_CNTL_TOUCH_PAD13_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD13_DAC_S 20 +/* RTC_CNTL_TOUCH_PAD14_DAC : R/W ;bitpos:[19:17] ;default: 3'd0 ; */ +/*description: .*/ +#define RTC_CNTL_TOUCH_PAD14_DAC 0x00000007 +#define RTC_CNTL_TOUCH_PAD14_DAC_M ((RTC_CNTL_TOUCH_PAD14_DAC_V)<<(RTC_CNTL_TOUCH_PAD14_DAC_S)) +#define RTC_CNTL_TOUCH_PAD14_DAC_V 0x7 +#define RTC_CNTL_TOUCH_PAD14_DAC_S 17 + +#define RTC_CNTL_COCPU_DISABLE_REG (DR_REG_RTCCNTL_BASE + 0x154) +/* RTC_CNTL_DISABLE_RTC_CPU : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define RTC_CNTL_DISABLE_RTC_CPU (BIT(31)) +#define RTC_CNTL_DISABLE_RTC_CPU_M (BIT(31)) +#define RTC_CNTL_DISABLE_RTC_CPU_V 0x1 +#define RTC_CNTL_DISABLE_RTC_CPU_S 31 + +#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x1FC) +/* RTC_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101271 ; */ +/*description: .*/ +#define RTC_CNTL_DATE 0x0FFFFFFF +#define RTC_CNTL_DATE_M ((RTC_CNTL_DATE_V)<<(RTC_CNTL_DATE_S)) +#define RTC_CNTL_DATE_V 0xFFFFFFF +#define RTC_CNTL_DATE_S 0 + #ifdef __cplusplus } diff --git a/components/soc/esp32s3/include/soc/rtc_cntl_struct.h b/components/soc/esp32s3/include/soc/rtc_cntl_struct.h index e2fe8b0a18..608eea67f6 100644 --- a/components/soc/esp32s3/include/soc/rtc_cntl_struct.h +++ b/components/soc/esp32s3/include/soc/rtc_cntl_struct.h @@ -13,9 +13,12 @@ // limitations under the License. #ifndef _SOC_RTC_CNTL_STRUCT_H_ #define _SOC_RTC_CNTL_STRUCT_H_ + + #ifdef __cplusplus extern "C" { #endif +#include "soc.h" typedef volatile struct { union { @@ -149,8 +152,8 @@ typedef volatile struct { uint32_t glitch_rst_en: 1; uint32_t reserved21: 1; /*PLLA force power down*/ uint32_t sar_i2c_pu: 1; /*PLLA force power up*/ - uint32_t plla_force_pd: 1; /*PLLA force power down*/ - uint32_t plla_force_pu: 1; /*PLLA force power up*/ + uint32_t analog_top_iso_sleep: 1; /*PLLA force power down*/ + uint32_t analog_top_iso_monitor: 1; /*PLLA force power up*/ uint32_t bbpll_cal_slp_start: 1; /*start BBPLL calibration during sleep*/ uint32_t pvtmon_pu: 1; /*1: PVTMON power up*/ uint32_t txrf_i2c_pu: 1; /*1: TXRF_I2C power up*/ @@ -358,24 +361,27 @@ typedef volatile struct { } sdio_act_conf; union { struct { - uint32_t reserved0: 3; - uint32_t ck8m_div_sel_vld: 1; /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/ - uint32_t ck8m_div: 2; /*CK8M_D256_OUT divider. 00: div128*/ - uint32_t enb_ck8m: 1; /*disable CK8M and CK8M_D256_OUT*/ - uint32_t enb_ck8m_div: 1; /*1: CK8M_D256_OUT is actually CK8M*/ - uint32_t dig_xtal32k_en: 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ - uint32_t dig_clk8m_d256_en: 1; /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ - uint32_t dig_clk8m_en: 1; /*enable CK8M for digital core (no relationship with RTC core)*/ - uint32_t reserved11: 1; - uint32_t ck8m_div_sel: 3; /*divider = reg_ck8m_div_sel + 1*/ - uint32_t xtal_force_nogating: 1; /*XTAL force no gating during sleep*/ - uint32_t ck8m_force_nogating: 1; /*CK8M force no gating during sleep*/ - uint32_t ck8m_dfreq: 8; /*CK8M_DFREQ*/ - uint32_t ck8m_force_pd: 1; /*CK8M force power down*/ - uint32_t ck8m_force_pu: 1; /*CK8M force power up*/ - uint32_t reserved27: 2; - uint32_t fast_clk_rtc_sel: 1; /*fast_clk_rtc sel. 0: XTAL div 4*/ - uint32_t ana_clk_rtc_sel: 2; + uint32_t reserved0: 1; + uint32_t efuse_clk_force_gating: 1; + uint32_t efuse_clk_force_nogating: 1; + uint32_t ck8m_div_sel_vld: 1; /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/ + uint32_t ck8m_div: 2; /*CK8M_D256_OUT divider. 00: div128*/ + uint32_t enb_ck8m: 1; /*disable CK8M and CK8M_D256_OUT*/ + uint32_t enb_ck8m_div: 1; /*1: CK8M_D256_OUT is actually CK8M*/ + uint32_t dig_xtal32k_en: 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ + uint32_t dig_clk8m_d256_en: 1; /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ + uint32_t dig_clk8m_en: 1; /*enable CK8M for digital core (no relationship with RTC core)*/ + uint32_t reserved11: 1; + uint32_t ck8m_div_sel: 3; /*divider = reg_ck8m_div_sel + 1*/ + uint32_t xtal_force_nogating: 1; /*XTAL force no gating during sleep*/ + uint32_t ck8m_force_nogating: 1; /*CK8M force no gating during sleep*/ + uint32_t ck8m_dfreq: 8; /*CK8M_DFREQ*/ + uint32_t ck8m_force_pd: 1; /*CK8M force power down*/ + uint32_t ck8m_force_pu: 1; /*CK8M force power up*/ + uint32_t xtal_global_force_gating: 1; + uint32_t xtal_global_force_nogating: 1; + uint32_t fast_clk_rtc_sel: 1; /*fast_clk_rtc sel. 0: XTAL div 4*/ + uint32_t ana_clk_rtc_sel: 2; }; uint32_t val; } clk_conf; @@ -465,6 +471,16 @@ typedef volatile struct { }; uint32_t val; } rtc_pwc; + union { + struct { + uint32_t rtculator_drv_b_monitor : 6; + uint32_t rtculator_drv_b_slp : 6; + uint32_t dg_vdd_drv_b_slp : 8; + uint32_t dg_vdd_drv_b_monitor : 8; + uint32_t reserved28 : 4; + }; + uint32_t val; + } regulator_drv_ctrl; union { struct { uint32_t reserved0: 3; @@ -822,7 +838,9 @@ typedef volatile struct { uint32_t usb_tx_en_override: 1; uint32_t usb_reset_disable: 1; uint32_t io_mux_reset_disable: 1; - uint32_t reserved19: 13; + uint32_t sw_usb_phy_sel: 1; + uint32_t sw_hw_usb_phy_sel: 1; + uint32_t reserved21: 11; }; uint32_t val; } usb_conf; @@ -918,26 +936,114 @@ typedef volatile struct { } int_ena_w1tc; union { struct { - uint32_t reserved0: 18; - uint32_t retention_clk_sel: 1; - uint32_t retention_done_wait: 3; - uint32_t retention_clkoff_wait: 4; - uint32_t retention_en: 1; - uint32_t retention_wait: 5; /*wait cycles for rention operation*/ + uint32_t reserved0 : 10; + uint32_t retention_tag_mode : 4; + uint32_t retention_target : 2; + uint32_t retention_clk_sel : 1; + uint32_t retention_done_wait : 3; + uint32_t retention_clkoff_wait : 4; + uint32_t retention_en : 1; + uint32_t retention_wait : 7; /*wait cycles for rention operation*/ }; uint32_t val; } retention_ctrl; union { struct { - uint32_t rtc_fib_sel: 3; /*select use analog fib signal*/ - uint32_t reserved3: 29; + uint32_t reserved0 : 26; + uint32_t power_glitch_dsense : 2; + uint32_t power_glitch_force_pd : 1; + uint32_t power_glitch_force_pu : 1; + uint32_t power_glitch_efuse_sel : 1; /*select use analog fib signal*/ + uint32_t power_glitch_en : 1; + }; + uint32_t val; + } pg_ctrl; + union { + struct { + uint32_t rtc_fib_sel : 3; + uint32_t reserved3 : 29; }; uint32_t val; } fib_sel; union { struct { - uint32_t date: 28; - uint32_t reserved28: 4; + uint32_t reserved0 : 2; + uint32_t touch_pad9_dac : 3; + uint32_t touch_pad8_dac : 3; + uint32_t touch_pad7_dac : 3; + uint32_t touch_pad6_dac : 3; + uint32_t touch_pad5_dac : 3; + uint32_t touch_pad4_dac : 3; + uint32_t touch_pad3_dac : 3; + uint32_t touch_pad2_dac : 3; + uint32_t touch_pad1_dac : 3; + uint32_t touch_pad0_dac : 3; + }; + uint32_t val; + } touch_dac; + union { + struct { + uint32_t reserved0 : 17; + uint32_t touch_pad14_dac : 3; + uint32_t touch_pad13_dac : 3; + uint32_t touch_pad12_dac : 3; + uint32_t touch_pad11_dac : 3; + uint32_t touch_pad10_dac : 3; + }; + uint32_t val; + } touch_dac1; + union { + struct { + uint32_t reserved0 : 31; + uint32_t disable_rtc_cpu : 1; + }; + uint32_t val; + } cocpu_disable; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + union { + struct { + uint32_t date : 28; + uint32_t reserved28 : 4; }; uint32_t val; } date; diff --git a/components/soc/esp32s3/include/soc/system_reg.h b/components/soc/esp32s3/include/soc/system_reg.h index e1bc980152..6dbae10346 100644 --- a/components/soc/esp32s3/include/soc/system_reg.h +++ b/components/soc/esp32s3/include/soc/system_reg.h @@ -102,71 +102,7 @@ extern "C" { #define SYSTEM_CPUPERIOD_SEL_V 0x3 #define SYSTEM_CPUPERIOD_SEL_S 0 -#define SYSTEM_JTAG_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x14) -/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: .*/ -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S)) -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S 0 - -#define SYSTEM_JTAG_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x18) -/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: .*/ -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S)) -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S 0 - -#define SYSTEM_JTAG_CTRL_2_REG (DR_REG_SYSTEM_BASE + 0x1C) -/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: .*/ -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S)) -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S 0 - -#define SYSTEM_JTAG_CTRL_3_REG (DR_REG_SYSTEM_BASE + 0x20) -/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: .*/ -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S)) -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S 0 - -#define SYSTEM_JTAG_CTRL_4_REG (DR_REG_SYSTEM_BASE + 0x24) -/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: .*/ -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S)) -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S 0 - -#define SYSTEM_JTAG_CTRL_5_REG (DR_REG_SYSTEM_BASE + 0x28) -/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: .*/ -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S)) -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S 0 - -#define SYSTEM_JTAG_CTRL_6_REG (DR_REG_SYSTEM_BASE + 0x2C) -/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: .*/ -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S)) -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S 0 - -#define SYSTEM_JTAG_CTRL_7_REG (DR_REG_SYSTEM_BASE + 0x30) -/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: .*/ -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V)<<(SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S)) -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V 0xFFFFFFFF -#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S 0 - -#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x34) +#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x14) /* SYSTEM_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ /*description: .*/ #define SYSTEM_LSLP_MEM_PD_MASK (BIT(0)) @@ -174,7 +110,7 @@ extern "C" { #define SYSTEM_LSLP_MEM_PD_MASK_V 0x1 #define SYSTEM_LSLP_MEM_PD_MASK_S 0 -#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x38) +#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x18) /* SYSTEM_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */ /*description: .*/ #define SYSTEM_SPI4_CLK_EN (BIT(31)) @@ -368,7 +304,7 @@ extern "C" { #define SYSTEM_TIMERS_CLK_EN_V 0x1 #define SYSTEM_TIMERS_CLK_EN_S 0 -#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x3C) +#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x1C) /* SYSTEM_USB_DEVICE_CLK_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ /*description: .*/ #define SYSTEM_USB_DEVICE_CLK_EN (BIT(10)) @@ -436,7 +372,7 @@ extern "C" { #define SYSTEM_PERI_BACKUP_CLK_EN_V 0x1 #define SYSTEM_PERI_BACKUP_CLK_EN_S 0 -#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x40) +#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x20) /* SYSTEM_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */ /*description: .*/ #define SYSTEM_SPI4_RST (BIT(31)) @@ -630,7 +566,7 @@ extern "C" { #define SYSTEM_TIMERS_RST_V 0x1 #define SYSTEM_TIMERS_RST_S 0 -#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x44) +#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x24) /* SYSTEM_USB_DEVICE_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ /*description: .*/ #define SYSTEM_USB_DEVICE_RST (BIT(10)) @@ -698,7 +634,7 @@ extern "C" { #define SYSTEM_PERI_BACKUP_RST_V 0x1 #define SYSTEM_PERI_BACKUP_RST_S 0 -#define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x48) +#define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x28) /* SYSTEM_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */ /*description: .*/ #define SYSTEM_BT_LPCK_DIV_NUM 0x00000FFF @@ -706,7 +642,7 @@ extern "C" { #define SYSTEM_BT_LPCK_DIV_NUM_V 0xFFF #define SYSTEM_BT_LPCK_DIV_NUM_S 0 -#define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x4C) +#define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x2C) /* SYSTEM_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ /*description: .*/ #define SYSTEM_LPCLK_RTC_EN (BIT(28)) @@ -750,7 +686,7 @@ extern "C" { #define SYSTEM_BT_LPCK_DIV_B_V 0xFFF #define SYSTEM_BT_LPCK_DIV_B_S 0 -#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x50) +#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x30) /* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: .*/ #define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0)) @@ -758,7 +694,7 @@ extern "C" { #define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x1 #define SYSTEM_CPU_INTR_FROM_CPU_0_S 0 -#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x54) +#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x34) /* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: .*/ #define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0)) @@ -766,7 +702,7 @@ extern "C" { #define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x1 #define SYSTEM_CPU_INTR_FROM_CPU_1_S 0 -#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x58) +#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x38) /* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: .*/ #define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0)) @@ -774,7 +710,7 @@ extern "C" { #define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x1 #define SYSTEM_CPU_INTR_FROM_CPU_2_S 0 -#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x5C) +#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x3C) /* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: .*/ #define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0)) @@ -782,7 +718,7 @@ extern "C" { #define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x1 #define SYSTEM_CPU_INTR_FROM_CPU_3_S 0 -#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x60) +#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x40) /* SYSTEM_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */ /*description: .*/ #define SYSTEM_RSA_MEM_FORCE_PD (BIT(2)) @@ -802,7 +738,7 @@ extern "C" { #define SYSTEM_RSA_MEM_PD_V 0x1 #define SYSTEM_RSA_MEM_PD_S 0 -#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x64) +#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x44) /* SYSTEM_EDMA_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ /*description: .*/ #define SYSTEM_EDMA_RESET (BIT(1)) @@ -816,7 +752,7 @@ extern "C" { #define SYSTEM_EDMA_CLK_ON_V 0x1 #define SYSTEM_EDMA_CLK_ON_S 0 -#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x68) +#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x48) /* SYSTEM_DCACHE_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */ /*description: .*/ #define SYSTEM_DCACHE_RESET (BIT(3)) @@ -842,7 +778,7 @@ extern "C" { #define SYSTEM_ICACHE_CLK_ON_V 0x1 #define SYSTEM_ICACHE_CLK_ON_S 0 -#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x6C) +#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x4C) /* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */ /*description: .*/ #define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) @@ -868,7 +804,7 @@ extern "C" { #define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x1 #define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0 -#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x70) +#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x50) /* SYSTEM_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */ /*description: .*/ #define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31)) @@ -894,7 +830,7 @@ extern "C" { #define SYSTEM_RTC_MEM_CRC_START_V 0x1 #define SYSTEM_RTC_MEM_CRC_START_S 8 -#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x74) +#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x54) /* SYSTEM_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: .*/ #define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFF @@ -902,7 +838,7 @@ extern "C" { #define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFF #define SYSTEM_RTC_MEM_CRC_RES_S 0 -#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x78) +#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x58) /* SYSTEM_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */ /*description: .*/ #define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1)) @@ -916,7 +852,7 @@ extern "C" { #define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x1 #define SYSTEM_REDUNDANT_ECO_DRIVE_S 0 -#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x7C) +#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x5C) /* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ /*description: .*/ #define SYSTEM_CLK_EN (BIT(0)) @@ -924,7 +860,7 @@ extern "C" { #define SYSTEM_CLK_EN_V 0x1 #define SYSTEM_CLK_EN_S 0 -#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x80) +#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x60) /* SYSTEM_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */ /*description: .*/ #define SYSTEM_CLK_DIV_EN (BIT(19)) @@ -950,7 +886,7 @@ extern "C" { #define SYSTEM_PRE_DIV_CNT_V 0x3FF #define SYSTEM_PRE_DIV_CNT_S 0 -#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x84) +#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x64) /* SYSTEM_MEM_VT_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ /*description: .*/ #define SYSTEM_MEM_VT_SEL 0x00000003 @@ -982,7 +918,7 @@ extern "C" { #define SYSTEM_MEM_PATH_LEN_V 0xF #define SYSTEM_MEM_PATH_LEN_S 0 -#define SYSTEM_COMB_PVT_LVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x88) +#define SYSTEM_COMB_PVT_LVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x68) /* SYSTEM_COMB_PVT_MONITOR_EN_LVT : R/W ;bitpos:[6] ;default: 1'b0 ; */ /*description: .*/ #define SYSTEM_COMB_PVT_MONITOR_EN_LVT (BIT(6)) @@ -1002,7 +938,7 @@ extern "C" { #define SYSTEM_COMB_PATH_LEN_LVT_V 0x1F #define SYSTEM_COMB_PATH_LEN_LVT_S 0 -#define SYSTEM_COMB_PVT_NVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x8C) +#define SYSTEM_COMB_PVT_NVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x6C) /* SYSTEM_COMB_PVT_MONITOR_EN_NVT : R/W ;bitpos:[6] ;default: 1'b0 ; */ /*description: .*/ #define SYSTEM_COMB_PVT_MONITOR_EN_NVT (BIT(6)) @@ -1022,7 +958,7 @@ extern "C" { #define SYSTEM_COMB_PATH_LEN_NVT_V 0x1F #define SYSTEM_COMB_PATH_LEN_NVT_S 0 -#define SYSTEM_COMB_PVT_HVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x90) +#define SYSTEM_COMB_PVT_HVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x70) /* SYSTEM_COMB_PVT_MONITOR_EN_HVT : R/W ;bitpos:[6] ;default: 1'b0 ; */ /*description: .*/ #define SYSTEM_COMB_PVT_MONITOR_EN_HVT (BIT(6)) @@ -1042,7 +978,7 @@ extern "C" { #define SYSTEM_COMB_PATH_LEN_HVT_V 0x1F #define SYSTEM_COMB_PATH_LEN_HVT_S 0 -#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x94) +#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x74) /* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: .*/ #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 0x0000FFFF @@ -1050,7 +986,7 @@ extern "C" { #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V 0xFFFF #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S 0 -#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x98) +#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x78) /* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: .*/ #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 0x0000FFFF @@ -1058,7 +994,7 @@ extern "C" { #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V 0xFFFF #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S 0 -#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x9C) +#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x7C) /* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: .*/ #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 0x0000FFFF @@ -1066,7 +1002,7 @@ extern "C" { #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V 0xFFFF #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S 0 -#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0xA0) +#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x80) /* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: .*/ #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 0x0000FFFF @@ -1074,7 +1010,7 @@ extern "C" { #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V 0xFFFF #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S 0 -#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0xA4) +#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x84) /* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: .*/ #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 0x0000FFFF @@ -1082,7 +1018,7 @@ extern "C" { #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V 0xFFFF #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S 0 -#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0xA8) +#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x88) /* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: .*/ #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 0x0000FFFF @@ -1090,7 +1026,7 @@ extern "C" { #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V 0xFFFF #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S 0 -#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0xAC) +#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x8C) /* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: .*/ #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 0x0000FFFF @@ -1098,7 +1034,7 @@ extern "C" { #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V 0xFFFF #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S 0 -#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0xB0) +#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x90) /* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: .*/ #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 0x0000FFFF @@ -1106,7 +1042,7 @@ extern "C" { #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V 0xFFFF #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S 0 -#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0xB4) +#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x94) /* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: .*/ #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 0x0000FFFF @@ -1114,7 +1050,7 @@ extern "C" { #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V 0xFFFF #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S 0 -#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0xB8) +#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x98) /* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: .*/ #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 0x0000FFFF @@ -1122,7 +1058,7 @@ extern "C" { #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V 0xFFFF #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S 0 -#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0xBC) +#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x9C) /* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: .*/ #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 0x0000FFFF @@ -1130,7 +1066,7 @@ extern "C" { #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V 0xFFFF #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S 0 -#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0xC0) +#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0xA0) /* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: .*/ #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 0x0000FFFF @@ -1139,13 +1075,14 @@ extern "C" { #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S 0 #define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0xFFC) -/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012230 ; */ +/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101220 ; */ /*description: .*/ #define SYSTEM_DATE 0x0FFFFFFF #define SYSTEM_DATE_M ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S)) #define SYSTEM_DATE_V 0xFFFFFFF #define SYSTEM_DATE_S 0 + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s3/include/soc/system_struct.h b/components/soc/esp32s3/include/soc/system_struct.h index a5d3dd4b4e..4c29c2fad4 100644 --- a/components/soc/esp32s3/include/soc/system_struct.h +++ b/components/soc/esp32s3/include/soc/system_struct.h @@ -59,14 +59,6 @@ typedef volatile struct { }; uint32_t val; } cpu_per_conf; - uint32_t jtag_ctrl_0; - uint32_t jtag_ctrl_1; - uint32_t jtag_ctrl_2; - uint32_t jtag_ctrl_3; - uint32_t jtag_ctrl_4; - uint32_t jtag_ctrl_5; - uint32_t jtag_ctrl_6; - uint32_t jtag_ctrl_7; union { struct { uint32_t lslp_mem_pd_mask : 1; @@ -428,6 +420,14 @@ typedef volatile struct { }; uint32_t val; } comb_pvt_err_hvt_site3; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; uint32_t reserved_c4; uint32_t reserved_c8; uint32_t reserved_cc;