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efuse: Adds ERR_RST_ENABLE efuse for C3 and S3

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Closes https://github.com/espressif/esp-idf/issues/8357
This commit is contained in:
KonstantinKondrashov 2022-02-28 21:16:24 +08:00
parent f47023f8c2
commit 1979c68e82
5 changed files with 45 additions and 15 deletions
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11
components/efuse/esp32c3/esp_efuse_table.c
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@ -9,7 +9,7 @@
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table 357feb63f27b95519accb97200d894a7
// md5_digest_table 6614a99de35023cf9ba3849a2b80e9e7
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -311,6 +311,10 @@ static const esp_efuse_desc_t SECURE_VERSION[] = {
{EFUSE_BLK0, 142, 16}, // Secure version for anti-rollback,
};
static const esp_efuse_desc_t ERR_RST_ENABLE[] = {
{EFUSE_BLK0, 159, 1}, // Use BLOCK0 to check error record registers,
};
static const esp_efuse_desc_t MAC_FACTORY[] = {
{EFUSE_BLK1, 40, 8}, // Factory MAC addr [0],
{EFUSE_BLK1, 32, 8}, // Factory MAC addr [1],
@ -858,6 +862,11 @@ const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ERR_RST_ENABLE[] = {
&ERR_RST_ENABLE[0], // Use BLOCK0 to check error record registers
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
&MAC_FACTORY[0], // Factory MAC addr [0]
&MAC_FACTORY[1], // Factory MAC addr [1]

1
components/efuse/esp32c3/esp_efuse_table.csv
View File

@ -95,6 +95,7 @@
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.
FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot
SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback
ERR_RST_ENABLE, EFUSE_BLK0, 159, 1, Use BLOCK0 to check error record registers, 0 - without check.
# EFUSE_RD_REPEAT_DATA4_REG #

Can't render this file because it contains an unexpected character in line 7 and column 87.

3
components/efuse/esp32c3/include/esp_efuse_table.h
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@ -9,7 +9,7 @@ extern "C" {
#endif
// md5_digest_table 357feb63f27b95519accb97200d894a7
// md5_digest_table 6614a99de35023cf9ba3849a2b80e9e7
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -90,6 +90,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_ERR_RST_ENABLE[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];

42
components/soc/esp32c3/include/soc/efuse_reg.h
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@ -256,11 +256,17 @@ extern "C" {
#define EFUSE_KEY_PURPOSE_2_S 0
#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x010)
/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31:30] ;default: 2'h0 ; */
/* EFUSE_ERR_RST_ENABLE : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: Use BLOCK0 to check error record registers, 0 - without check.*/
#define EFUSE_ERR_RST_ENABLE (BIT(31))
#define EFUSE_ERR_RST_ENABLE_M (BIT(31))
#define EFUSE_ERR_RST_ENABLE_V 0x1
#define EFUSE_ERR_RST_ENABLE_S 31
/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[30] ;default: 1'h0 ; */
/*description: Reserved (used for four backups method).*/
#define EFUSE_RPT4_RESERVED1 0x00000003
#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S))
#define EFUSE_RPT4_RESERVED1_V 0x3
#define EFUSE_RPT4_RESERVED1 (BIT(30))
#define EFUSE_RPT4_RESERVED1_M (BIT(30))
#define EFUSE_RPT4_RESERVED1_V 0x1
#define EFUSE_RPT4_RESERVED1_S 30
/* EFUSE_SECURE_VERSION : R/W ;bitpos:[29:14] ;default: 16'h0 ; */
/*description: Secure version (used by ESP-IDF anti-rollback feature).*/
@ -609,11 +615,17 @@ extern "C" {
#define EFUSE_KEY_PURPOSE_2_S 0
#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x03C)
/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31:30] ;default: 2'h0 ; */
/* EFUSE_ERR_RST_ENABLE : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: Use BLOCK0 to check error record registers, 0 - without check.*/
#define EFUSE_ERR_RST_ENABLE (BIT(31))
#define EFUSE_ERR_RST_ENABLE_M (BIT(31))
#define EFUSE_ERR_RST_ENABLE_V 0x1
#define EFUSE_ERR_RST_ENABLE_S 31
/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[30] ;default: 1'h0 ; */
/*description: Reserved.*/
#define EFUSE_RPT4_RESERVED1 0x00000003
#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S))
#define EFUSE_RPT4_RESERVED1_V 0x3
#define EFUSE_RPT4_RESERVED1 (BIT(30))
#define EFUSE_RPT4_RESERVED1_M (BIT(30))
#define EFUSE_RPT4_RESERVED1_V 0x1
#define EFUSE_RPT4_RESERVED1_S 30
/* EFUSE_SECURE_VERSION : RO ;bitpos:[29:14] ;default: 16'h0 ; */
/*description: The value of SECURE_VERSION.*/
@ -1561,11 +1573,17 @@ extern "C" {
#define EFUSE_KEY_PURPOSE_2_ERR_S 0
#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */
/* EFUSE_ERR_RST_ENABLE_ERR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: Use BLOCK0 to check error record registers, 0 - without check.*/
#define EFUSE_ERR_RST_ENABLE_ERR (BIT(31))
#define EFUSE_ERR_RST_ENABLE_ERR_M (BIT(31))
#define EFUSE_ERR_RST_ENABLE_ERR_V 0x1
#define EFUSE_ERR_RST_ENABLE_ERR_S 31
/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[30] ;default: 1'h0 ; */
/*description: Reserved.*/
#define EFUSE_RPT4_RESERVED1_ERR 0x00000003
#define EFUSE_RPT4_RESERVED1_ERR_M ((EFUSE_RPT4_RESERVED1_ERR_V)<<(EFUSE_RPT4_RESERVED1_ERR_S))
#define EFUSE_RPT4_RESERVED1_ERR_V 0x3
#define EFUSE_RPT4_RESERVED1_ERR (BIT(30))
#define EFUSE_RPT4_RESERVED1_ERR_M (BIT(30))
#define EFUSE_RPT4_RESERVED1_ERR_V 0x1
#define EFUSE_RPT4_RESERVED1_ERR_S 30
/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[29:14] ;default: 16'h0 ; */
/*description: If any bit in SECURE_VERSION is 1 then it indicates a programming error.*/

3
components/soc/esp32c3/include/soc/efuse_struct.h
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@ -165,7 +165,8 @@ typedef volatile struct efuse_dev_s {
uint32_t rpt4_reserved7: 5; /*Reserved.*/
uint32_t force_send_resume: 1; /*The value of FORCE_SEND_RESUME.*/
uint32_t secure_version: 16; /*The value of SECURE_VERSION.*/
uint32_t rpt4_reserved1: 2; /*Reserved.*/
uint32_t rpt4_reserved1: 1; /*Reserved.*/
uint32_t err_rst_enable: 1; /*Use BLOCK0 to check error record registers, 0 - without check.*/
};
uint32_t val;
} rd_repeat_data3;