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support dcache 64Byte and 16k

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This commit is contained in:
gaoxiaojie 2020-10-10 16:22:49 +08:00 committed by Marius Vikhammer
parent f7137254e9
commit 191a494e08
3 changed files with 34 additions and 12 deletions
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6
components/esp32s3/Kconfig
View File

@ -108,7 +108,8 @@ menu "ESP32S3-Specific"
config ESP32S3_DATA_CACHE_SIZE
hex
default 0x4000 if ESP32S3_DATA_CACHE_16KB
# For 16KB the actual configuration is 32kb cache, but 16kb will be reserved for heap at startup
default 0x8000 if ESP32S3_DATA_CACHE_16KB
default 0x8000 if ESP32S3_DATA_CACHE_32KB
default 0x10000 if ESP32S3_DATA_CACHE_64KB
@ -140,12 +141,15 @@ menu "ESP32S3-Specific"
depends on ESP32S3_DATA_CACHE_16KB || ESP32S3_DATA_CACHE_32KB
config ESP32S3_DATA_CACHE_LINE_32B
bool "32 Bytes"
config ESP32S3_DATA_CACHE_LINE_64B
bool "64 Bytes"
endchoice
config ESP32S3_DATA_CACHE_LINE_SIZE
int
default 16 if ESP32S3_DATA_CACHE_LINE_16B
default 32 if ESP32S3_DATA_CACHE_LINE_32B
default 64 if ESP32S3_DATA_CACHE_LINE_64B
config ESP32S3_DATA_CACHE_WRAP
bool "Enable data cache wrap mode"

31
components/esp_system/port/cpu_start.c
View File

@ -359,10 +359,14 @@ void IRAM_ATTR call_start_cpu0(void)
#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
/* Configure the Cache MMU size for instruction and rodata in flash. */
extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size);
extern int _rodata_reserved_start, _rodata_reserved_end;
extern int _rodata_reserved_start;
uint32_t rodata_reserved_start_align = (uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1);
uint32_t cache_mmu_irom_size = ((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) * sizeof(uint32_t);
#if CONFIG_IDF_TARGET_ESP32S3
extern int _rodata_reserved_end;
uint32_t cache_mmu_drom_size = (((uint32_t)&_rodata_reserved_end - rodata_reserved_start_align + MMU_PAGE_SIZE - 1)/MMU_PAGE_SIZE)*sizeof(uint32_t);
#endif
Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
#endif // CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
@ -439,8 +443,6 @@ void IRAM_ATTR call_start_cpu0(void)
}
#endif
static int s_instr_flash2spiram_off = 0;
static int s_rodata_flash2spiram_off = 0;
#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
extern void instruction_flash_page_info_init(void);
instruction_flash_page_info_init();
@ -453,15 +455,22 @@ void IRAM_ATTR call_start_cpu0(void)
#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
extern void esp_spiram_enable_instruction_access(void);
esp_spiram_enable_instruction_access();
s_instr_flash2spiram_off = instruction_flash2spiram_offset();
#endif
#if CONFIG_SPIRAM_RODATA
extern void esp_spiram_enable_rodata_access(void);
esp_spiram_enable_rodata_access();
s_rodata_flash2spiram_off = rodata_flash2spiram_offset();
#endif
#if CONFIG_IDF_TARGET_ESP32S3
int s_instr_flash2spiram_off = 0;
int s_rodata_flash2spiram_off = 0;
#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
s_instr_flash2spiram_off = instruction_flash2spiram_offset();
#endif
#if CONFIG_SPIRAM_RODATA
s_rodata_flash2spiram_off = rodata_flash2spiram_offset();
#endif
extern void Cache_Set_IDROM_MMU_Info(uint32_t instr_page_num, uint32_t rodata_page_num, uint32_t rodata_start, uint32_t rodata_end, int i_off, int ro_off);
Cache_Set_IDROM_MMU_Info(cache_mmu_irom_size/sizeof(uint32_t), \
cache_mmu_drom_size/sizeof(uint32_t), \
@ -471,18 +480,24 @@ void IRAM_ATTR call_start_cpu0(void)
s_rodata_flash2spiram_off);
#endif
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S2_DATA_CACHE_WRAP
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S2_DATA_CACHE_WRAP || \
CONFIG_ESP32S3_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S3_DATA_CACHE_WRAP
uint32_t icache_wrap_enable = 0, dcache_wrap_enable = 0;
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S3_INSTRUCTION_CACHE_WRAP
icache_wrap_enable = 1;
#endif
#if CONFIG_ESP32S2_DATA_CACHE_WRAP
#if CONFIG_ESP32S2_DATA_CACHE_WRAP || CONFIG_ESP32S3_DATA_CACHE_WRAP
dcache_wrap_enable = 1;
#endif
extern void esp_enable_cache_wrap(uint32_t icache_wrap_enable, uint32_t dcache_wrap_enable);
esp_enable_cache_wrap(icache_wrap_enable, dcache_wrap_enable);
#endif
#if CONFIG_ESP32S3_DATA_CACHE_16KB
Cache_Invalidate_DCache_All();
Cache_Occupy_Addr(SOC_DROM_LOW, 0x4000);
#endif
#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
memset(&_ext_ram_bss_start, 0, (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start));
#endif

9
components/heap/port/esp32s3/memory_layout.c
View File

@ -44,6 +44,8 @@ const soc_memory_type_desc_t soc_memory_types[] = {
{ "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
// Type 4: SPI SRAM data
{ "SPIRAM", { MALLOC_CAP_SPIRAM | MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT}, false, false},
// Type 5: DRAM which is not DMA accesible
{ "NON_DMA_DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT, 0 }, false, false},
};
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
@ -69,11 +71,12 @@ const soc_memory_region_t soc_memory_regions[] = {
{ 0x3FCC0000, 0x10000, 2, 0x403B0000}, //Level 6, IDRAM, can be used as trace memroy
{ 0x3FCD0000, 0x10000, 2, 0x403C0000}, //Level 7, IDRAM, can be used as trace memroy
{ 0x3FCE0000, 0x10000, 1, 0}, //Level 8, IDRAM, can be used as trace memroy, contains stacks used by startup flow, recycled by heap allocator in app_main task
#if CONFIG_ESP32S3_DATA_CACHE_16KB
{ 0x3FCF0000, 0xC000, 0, 0}, //Level 9, DRAM
#elif CONFIG_ESP32S3_DATA_CACHE_32KB
#if CONFIG_ESP32S3_DATA_CACHE_16KB || CONFIG_ESP32S3_DATA_CACHE_32KB
{ 0x3FCF0000, 0x8000, 0, 0}, //Level 9, DRAM
#endif
#if CONFIG_ESP32S3_DATA_CACHE_16KB
{ 0x3C000000, 0x4000, 5, 0}
#endif
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ 0x50000000, 0x2000, 4, 0}, //Fast RTC memory
#endif