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Merge branch 'fix/spi_clk_div_repaire' into 'master'

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fix(spi_master): fix P4 clock src divider calc and 8bit support

See merge request espressif/esp-idf!28699
This commit is contained in:
Wan Lei 2024-01-29 12:34:52 +08:00
commit 18df8fbc9b
2 changed files with 6 additions and 3 deletions
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5
components/esp_driver_spi/src/gpspi/spi_master.c
View File

@ -381,13 +381,12 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa
.src_freq_hz = clock_source_hz,
.exp_freq_hz = dev_config->clock_speed_hz * 2, //we have (hs_clk = 2*mst_clk), calc hs_clk first
.round_opt = HAL_DIV_ROUND,
.min_integ = 1,
.max_integ = SPI_LL_CLK_SRC_PRE_DIV_MAX / 2,
};
hal_utils_calc_clk_div_integer(&clk_cfg, &clock_source_div);
}
clock_source_div *= 2; //convert to mst_clk function divider
if (clock_source_div > SPI_LL_CLK_SRC_PRE_DIV_MAX) {
clock_source_div = SPI_LL_CLK_SRC_PRE_DIV_MAX;
}
clock_source_hz /= clock_source_div; //actual freq enter to SPI peripheral
#else
SPI_CHECK((dev_config->clock_speed_hz > 0) && (dev_config->clock_speed_hz <= clock_source_hz), "invalid sclk speed", ESP_ERR_INVALID_ARG);

4
components/hal/esp32p4/include/hal/spi_ll.h
View File

@ -692,12 +692,16 @@ static inline void spi_ll_master_set_line_mode(spi_dev_t *hw, spi_line_mode_t li
hw->user.val &= ~SPI_LL_ONE_LINE_USER_MASK;
hw->ctrl.fcmd_dual = (line_mode.cmd_lines == 2);
hw->ctrl.fcmd_quad = (line_mode.cmd_lines == 4);
hw->ctrl.fcmd_oct = (line_mode.cmd_lines == 8);
hw->ctrl.faddr_dual = (line_mode.addr_lines == 2);
hw->ctrl.faddr_quad = (line_mode.addr_lines == 4);
hw->ctrl.faddr_oct = (line_mode.addr_lines == 8);
hw->ctrl.fread_dual = (line_mode.data_lines == 2);
hw->user.fwrite_dual = (line_mode.data_lines == 2);
hw->ctrl.fread_quad = (line_mode.data_lines == 4);
hw->user.fwrite_quad = (line_mode.data_lines == 4);
hw->ctrl.fread_oct = (line_mode.data_lines == 8);
hw->user.fwrite_oct = (line_mode.data_lines == 8);
}
/**