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Fix function prototypes

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This commit is contained in:
Angus Gratton 2019-08-12 12:06:07 +10:00 committed by Angus Gratton
parent c47e1756f8
commit 18c5cfadae
46 changed files with 189 additions and 189 deletions
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4
components/bootloader_support/src/esp32s2beta/flash_encrypt.c
View File

@ -31,7 +31,7 @@ static const char *TAG = "flash_encrypt";
/* Static functions for stages of flash encryption */
static esp_err_t initialise_flash_encryption(void);
static esp_err_t encrypt_flash_contents(uint32_t flash_crypt_cnt, bool flash_crypt_wr_dis);
static esp_err_t encrypt_bootloader();
static esp_err_t encrypt_bootloader(void);
static esp_err_t encrypt_and_load_partition_table(esp_partition_info_t *partition_table, int *num_partitions);
static esp_err_t encrypt_partition(int index, const esp_partition_info_t *partition);
@ -184,7 +184,7 @@ static esp_err_t encrypt_flash_contents(uint32_t spi_boot_crypt_cnt, bool flash_
return ESP_OK;
}
static esp_err_t encrypt_bootloader()
static esp_err_t encrypt_bootloader(void)
{
esp_err_t err;
uint32_t image_length;

2
components/bt/host/nimble/nimble

@ -1 +1 @@
Subproject commit 7600a6f60308c77fec755a024d51ab2fb7d11553
Subproject commit 4839d84f61296b7d7479350ebb92908b0fdb1329

24
components/driver/esp32s2beta/rtc_touchpad.c
View File

@ -187,13 +187,13 @@ esp_err_t touch_pad_io_init(touch_pad_t touch_num)
return ESP_OK;
}
esp_err_t touch_pad_wait_init_done()
esp_err_t touch_pad_wait_init_done(void)
{
// TODO
return ESP_FAIL;
}
esp_err_t touch_pad_fsm_start()
esp_err_t touch_pad_fsm_start(void)
{
RTC_TOUCH_ENTER_CRITICAL();
RTCCNTL.touch_ctrl2.touch_clkgate_en = 1; //enable touch clock for FSM. or force enable.
@ -202,7 +202,7 @@ esp_err_t touch_pad_fsm_start()
return ESP_OK;
}
esp_err_t touch_pad_fsm_stop()
esp_err_t touch_pad_fsm_stop(void)
{
RTC_TOUCH_ENTER_CRITICAL();
RTCCNTL.touch_ctrl2.touch_start_en = 0; //stop touch fsm
@ -338,7 +338,7 @@ esp_err_t touch_pad_intr_disable(touch_pad_intr_mask_t int_mask)
return ESP_OK;
}
uint32_t touch_pad_intr_status_get_mask()
uint32_t touch_pad_intr_status_get_mask(void)
{
return ((REG_READ(RTC_CNTL_INT_ST_REG) >> (RTC_CNTL_TOUCH_DONE_INT_ST_S)) & TOUCH_PAD_INTR_MASK_ALL);
}
@ -354,7 +354,7 @@ esp_err_t touch_pad_config(touch_pad_t touch_num)
return ESP_OK;
}
esp_err_t touch_pad_init()
esp_err_t touch_pad_init(void)
{
if (rtc_touch_mux == NULL) {
rtc_touch_mux = xSemaphoreCreateMutex();
@ -372,7 +372,7 @@ esp_err_t touch_pad_init()
return ESP_OK;
}
esp_err_t touch_pad_deinit()
esp_err_t touch_pad_deinit(void)
{
RTC_MODULE_CHECK(rtc_touch_mux != NULL, "Touch pad not initialized", ESP_FAIL);
xSemaphoreTake(rtc_touch_mux, portMAX_DELAY);
@ -451,7 +451,7 @@ esp_err_t touch_pad_filter_get_config(touch_filter_config_t *filter_info)
return ESP_OK;
}
esp_err_t touch_pad_filter_enable()
esp_err_t touch_pad_filter_enable(void)
{
RTC_TOUCH_ENTER_CRITICAL();
RTCCNTL.touch_filter_ctrl.touch_filter_en = 1;
@ -459,7 +459,7 @@ esp_err_t touch_pad_filter_enable()
return ESP_OK;
}
esp_err_t touch_pad_filter_disable()
esp_err_t touch_pad_filter_disable(void)
{
RTC_TOUCH_ENTER_CRITICAL();
RTCCNTL.touch_filter_ctrl.touch_filter_en = 0;
@ -467,7 +467,7 @@ esp_err_t touch_pad_filter_disable()
return ESP_OK;
}
esp_err_t touch_pad_denoise_enable()
esp_err_t touch_pad_denoise_enable(void)
{
RTC_TOUCH_ENTER_CRITICAL();
RTCCNTL.touch_scan_ctrl.touch_scan_pad_map &= ~(BIT(TOUCH_DENOISE_CHANNEL));
@ -476,7 +476,7 @@ esp_err_t touch_pad_denoise_enable()
return ESP_OK;
}
esp_err_t touch_pad_denoise_disable()
esp_err_t touch_pad_denoise_disable(void)
{
RTC_TOUCH_ENTER_CRITICAL();
RTCCNTL.touch_scan_ctrl.touch_denoise_en = 0;
@ -532,7 +532,7 @@ esp_err_t touch_pad_waterproof_get_config(touch_pad_waterproof_t *waterproof)
return ESP_OK;
}
esp_err_t touch_pad_waterproof_enable()
esp_err_t touch_pad_waterproof_enable(void)
{
touch_pad_io_init(TOUCH_SHIELD_CHANNEL);
RTC_TOUCH_ENTER_CRITICAL();
@ -542,7 +542,7 @@ esp_err_t touch_pad_waterproof_enable()
return ESP_OK;
}
esp_err_t touch_pad_waterproof_disable()
esp_err_t touch_pad_waterproof_disable(void)
{
RTC_TOUCH_ENTER_CRITICAL();
RTCCNTL.touch_scan_ctrl.touch_shield_pad_en = 0;

2
components/driver/include/driver/rtc_io.h
View File

@ -340,7 +340,7 @@ esp_err_t rtc_gpio_sleep_mode_disable(gpio_num_t gpio_num);
* Force hold signal is enabled before going into deep sleep for pins which
* are used for EXT1 wakeup.
*/
esp_err_t rtc_gpio_force_hold_all();
esp_err_t rtc_gpio_force_hold_all(void);
#endif
#ifdef __cplusplus

22
components/driver/include/driver/touch_pad.h
View File

@ -732,14 +732,14 @@ esp_err_t touch_pad_filter_delete(void);
* @return
* - ESP_OK on success
*/
esp_err_t touch_pad_fsm_start();
esp_err_t touch_pad_fsm_start(void);
/**
* @brief Stop touch sensor FSM.
* @return
* - ESP_OK on success
*/
esp_err_t touch_pad_fsm_stop();
esp_err_t touch_pad_fsm_stop(void);
/**
* @brief Set touch sensor measurement and sleep time
@ -859,7 +859,7 @@ esp_err_t touch_pad_config(touch_pad_t touch_num);
* @return
* - ESP_OK Success
*/
esp_err_t touch_pad_reset();
esp_err_t touch_pad_reset(void);
/**
* @brief Check touch sensor measurement status.
@ -878,7 +878,7 @@ bool touch_pad_meas_is_done(void);
* @return
* - touch channel number
*/
touch_pad_t touch_pad_get_scan_curr();
touch_pad_t touch_pad_get_scan_curr(void);
/**
* @brief Get the touch sensor interrupt status mask. usually used in ISR to decide interrupt type.
@ -886,7 +886,7 @@ touch_pad_t touch_pad_get_scan_curr();
* @return
* - touch intrrupt bit
*/
uint32_t touch_pad_intr_status_get_mask();
uint32_t touch_pad_intr_status_get_mask(void);
/**
* @brief Enable touch sensor interrupt.
@ -984,7 +984,7 @@ esp_err_t touch_pad_filter_get_config(touch_filter_config_t *filter_info);
* @return
* - ESP_OK Success
*/
esp_err_t touch_pad_filter_enable();
esp_err_t touch_pad_filter_enable(void);
/**
* @brief diaable touch sensor filter and detection algorithm.
@ -992,7 +992,7 @@ esp_err_t touch_pad_filter_enable();
* @return
* - ESP_OK Success
*/
esp_err_t touch_pad_filter_disable();
esp_err_t touch_pad_filter_disable(void);
/**
* @brief set parameter of denoise pad (TOUCH_PAD_NUM0).
@ -1025,14 +1025,14 @@ esp_err_t touch_pad_denoise_get_config(touch_pad_denoise_t *denoise);
* @return
* - ESP_OK Success
*/
esp_err_t touch_pad_denoise_enable();
esp_err_t touch_pad_denoise_enable(void);
/**
* @brief disable denoise function.
* @return
* - ESP_OK Success
*/
esp_err_t touch_pad_denoise_disable();
esp_err_t touch_pad_denoise_disable(void);
/**
* @brief get denoise measure value (TOUCH_PAD_NUM0).
@ -1073,7 +1073,7 @@ esp_err_t touch_pad_waterproof_get_config(touch_pad_waterproof_t *waterproof);
* @return
* - ESP_OK Success
*/
esp_err_t touch_pad_waterproof_enable();
esp_err_t touch_pad_waterproof_enable(void);
/**
* @brief Enable parameter of waterproof function.
@ -1085,7 +1085,7 @@ esp_err_t touch_pad_waterproof_enable();
* @return
* - ESP_OK Success
*/
esp_err_t touch_pad_waterproof_disable();
esp_err_t touch_pad_waterproof_disable(void);
/**
* @brief Set parameter of proximity channel. Three proximity sensing channels can be set.

4
components/esp32s2beta/brownout.c
View File

@ -31,7 +31,7 @@
#define BROWNOUT_DET_LVL 0
#endif //CONFIG_ESP32S2_BROWNOUT_DET_LVL
static void rtc_brownout_isr_handler()
static void rtc_brownout_isr_handler(void *arg)
{
/* Normally RTC ISR clears the interrupt flag after the application-supplied
* handler returns. Since restart is called here, the flag needs to be
@ -46,7 +46,7 @@ static void rtc_brownout_isr_handler()
esp_restart_noos();
}
void esp_brownout_init()
void esp_brownout_init(void)
{
// TODO: implement brownout threshold configuration for esp32s2beta - IDF-751

4
components/esp32s2beta/cache_err_int.c
View File

@ -32,7 +32,7 @@
#include "sdkconfig.h"
#include "esp32s2beta/dport_access.h"
void esp_cache_err_int_init()
void esp_cache_err_int_init(void)
{
uint32_t core_id = xPortGetCoreID();
ESP_INTR_DISABLE(ETS_CACHEERR_INUM);
@ -64,7 +64,7 @@ void esp_cache_err_int_init()
ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
}
int IRAM_ATTR esp_cache_err_get_cpuid()
int IRAM_ATTR esp_cache_err_get_cpuid(void)
{
return PRO_CPU_NUM;
}

2
components/esp32s2beta/clk.c
View File

@ -169,7 +169,7 @@ static void select_rtc_slow_clk(rtc_slow_freq_t slow_clk)
esp_clk_slowclk_cal_set(cal_val);
}
void rtc_clk_select_rtc_slow_clk()
void rtc_clk_select_rtc_slow_clk(void)
{
select_rtc_slow_clk(RTC_SLOW_FREQ_32K_XTAL);
}

4
components/esp32s2beta/cpu_start.c
View File

@ -106,7 +106,7 @@ static bool s_spiram_okay=true;
* and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
*/
void IRAM_ATTR call_start_cpu0()
void IRAM_ATTR call_start_cpu0(void)
{
RESET_REASON rst_reas;
@ -347,7 +347,7 @@ void start_cpu0_default(void)
}
#ifdef CONFIG_COMPILER_CXX_EXCEPTIONS
size_t __cxx_eh_arena_size_get()
size_t __cxx_eh_arena_size_get(void)
{
return CONFIG_COMPILER_CXX_EXCEPTIONS_EMG_POOL_SIZE;
}

4
components/esp32s2beta/crosscore_int.c
View File

@ -46,7 +46,7 @@ static volatile uint32_t reason[ portNUM_PROCESSORS ];
ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
the ISR will cause it to switch _away_ from it. portYIELD_FROM_ISR will probably just schedule the task again, but have to check that.
*/
static inline void IRAM_ATTR esp_crosscore_isr_handle_yield()
static inline void IRAM_ATTR esp_crosscore_isr_handle_yield(void)
{
portYIELD_FROM_ISR();
}
@ -82,7 +82,7 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) {
//Initialize the crosscore interrupt on this core. Call this once
//on each active core.
void esp_crosscore_int_init() {
void esp_crosscore_int_init(void) {
portENTER_CRITICAL(&reason_spinlock);
reason[xPortGetCoreID()]=0;
portEXIT_CRITICAL(&reason_spinlock);

2
components/esp32s2beta/esp_clk_internal.h
View File

@ -41,4 +41,4 @@ void esp_perip_clk_init(void);
/* Selects an external clock source (32 kHz) for RTC.
* Only internal use in unit test.
*/
void rtc_clk_select_rtc_slow_clk();
void rtc_clk_select_rtc_slow_clk(void);

14
components/esp32s2beta/esp_timer_esp32s2beta.c
View File

@ -151,7 +151,7 @@ portMUX_TYPE s_time_update_lock = portMUX_INITIALIZER_UNLOCKED;
#define TIMER_IS_AFTER_OVERFLOW(a) (ALARM_OVERFLOW_VAL < (a) && (a) <= FRC_TIMER_LOAD_VALUE(1))
// Check if timer overflow has happened (but was not handled by ISR yet)
static inline bool IRAM_ATTR timer_overflow_happened()
static inline bool IRAM_ATTR timer_overflow_happened(void)
{
if (s_overflow_happened) {
return true;
@ -177,17 +177,17 @@ static inline void IRAM_ATTR timer_count_reload(void)
REG_WRITE(FRC_TIMER_LOAD_REG(1), REG_READ(FRC_TIMER_COUNT_REG(1)) - ALARM_OVERFLOW_VAL);
}
void esp_timer_impl_lock()
void esp_timer_impl_lock(void)
{
portENTER_CRITICAL(&s_time_update_lock);
}
void esp_timer_impl_unlock()
void esp_timer_impl_unlock(void)
{
portEXIT_CRITICAL(&s_time_update_lock);
}
uint64_t IRAM_ATTR esp_timer_impl_get_time()
uint64_t IRAM_ATTR esp_timer_impl_get_time(void)
{
uint32_t timer_val;
uint64_t time_base;
@ -372,7 +372,7 @@ esp_err_t esp_timer_impl_init(intr_handler_t alarm_handler)
return ESP_OK;
}
void esp_timer_impl_deinit()
void esp_timer_impl_deinit(void)
{
esp_intr_disable(s_timer_interrupt_handle);
@ -387,13 +387,13 @@ void esp_timer_impl_deinit()
// FIXME: This value is safe for 80MHz APB frequency.
// Should be modified to depend on clock frequency.
uint64_t IRAM_ATTR esp_timer_impl_get_min_period_us()
uint64_t IRAM_ATTR esp_timer_impl_get_min_period_us(void)
{
return 50;
}
#ifdef ESP_TIMER_DYNAMIC_OVERFLOW_VAL
uint32_t esp_timer_impl_get_overflow_val()
uint32_t esp_timer_impl_get_overflow_val(void)
{
return s_alarm_overflow_val;
}

2
components/esp32s2beta/include/esp32s2beta/brownout.h
View File

@ -16,6 +16,6 @@
#ifndef __ESP_BROWNOUT_H
#define __ESP_BROWNOUT_H
void esp_brownout_init();
void esp_brownout_init(void);
#endif

4
components/esp32s2beta/include/esp32s2beta/cache_err_int.h
View File

@ -20,7 +20,7 @@
* to interrupt input number ETS_CACHEERR_INUM (see soc/soc.h). It is called
* from the startup code.
*/
void esp_cache_err_int_init();
void esp_cache_err_int_init(void);
/**
@ -30,4 +30,4 @@ void esp_cache_err_int_init();
* - APP_CPU_NUM, if APP_CPU has caused cache IA interrupt
* - (-1) otherwise
*/
int esp_cache_err_get_cpuid();
int esp_cache_err_get_cpuid(void);

4
components/esp32s2beta/include/esp32s2beta/clk.h
View File

@ -28,7 +28,7 @@
*
* @return the calibration value obtained using rtc_clk_cal, at startup time
*/
uint32_t esp_clk_slowclk_cal_get();
uint32_t esp_clk_slowclk_cal_get(void);
/**
* @brief Update the calibration value of RTC slow clock
@ -72,4 +72,4 @@ int esp_clk_apb_freq(void);
*
* @return Value or RTC counter, expressed in microseconds
*/
uint64_t esp_clk_rtc_time();
uint64_t esp_clk_rtc_time(void);

12
components/esp32s2beta/include/esp32s2beta/spiram.h
View File

@ -26,7 +26,7 @@
*
* @return ESP_OK on success
*/
esp_err_t esp_spiram_init();
esp_err_t esp_spiram_init(void);
/**
* @brief Configure Cache/MMU for access to external SPI RAM.
@ -37,7 +37,7 @@ esp_err_t esp_spiram_init();
*
* @attention this function must be called with flash cache disabled.
*/
void esp_spiram_init_cache();
void esp_spiram_init_cache(void);
/**
@ -48,13 +48,13 @@ void esp_spiram_init_cache();
*
* @return true on success, false on failed memory test
*/
bool esp_spiram_test();
bool esp_spiram_test(void);
/**
* @brief Add the initialized SPI RAM to the heap allocator.
*/
esp_err_t esp_spiram_add_to_heapalloc();
esp_err_t esp_spiram_add_to_heapalloc(void);
/**
@ -62,7 +62,7 @@ esp_err_t esp_spiram_add_to_heapalloc();
*
* @return Size in bytes, or 0 if no external RAM chip support compiled in.
*/
size_t esp_spiram_get_size();
size_t esp_spiram_get_size(void);
/**
@ -72,7 +72,7 @@ size_t esp_spiram_get_size();
*
* This is meant for use from within the SPI flash code.
*/
void esp_spiram_writeback_cache();
void esp_spiram_writeback_cache(void);

4
components/esp32s2beta/include/esp_clk.h
View File

@ -28,7 +28,7 @@
*
* @return the calibration value obtained using rtc_clk_cal, at startup time
*/
uint32_t esp_clk_slowclk_cal_get();
uint32_t esp_clk_slowclk_cal_get(void);
/**
* @brief Update the calibration value of RTC slow clock
@ -72,4 +72,4 @@ int esp_clk_apb_freq(void);
*
* @return Value or RTC counter, expressed in microseconds
*/
uint64_t esp_clk_rtc_time();
uint64_t esp_clk_rtc_time(void);

4
components/esp32s2beta/include/esp_intr_alloc.h
View File

@ -281,13 +281,13 @@ esp_err_t esp_intr_set_in_iram(intr_handle_t handle, bool is_in_iram);
/**
* @brief Disable interrupts that aren't specifically marked as running from IRAM
*/
void esp_intr_noniram_disable();
void esp_intr_noniram_disable(void);
/**
* @brief Re-enable interrupts disabled by esp_intr_noniram_disable
*/
void esp_intr_noniram_enable();
void esp_intr_noniram_enable(void);
/**@}*/

14
components/esp32s2beta/include/esp_sleep.h
View File

@ -94,7 +94,7 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source);
* - ESP_OK on success
* - ESP_ERR_INVALID_STATE if ULP co-processor is not enabled or if wakeup triggers conflict
*/
esp_err_t esp_sleep_enable_ulp_wakeup();
esp_err_t esp_sleep_enable_ulp_wakeup(void);
/**
* @brief Enable wakeup by timer
@ -120,7 +120,7 @@ esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us);
* - ESP_OK on success
* - ESP_ERR_INVALID_STATE if wakeup triggers conflict
*/
esp_err_t esp_sleep_enable_touchpad_wakeup();
esp_err_t esp_sleep_enable_touchpad_wakeup(void);
/**
* @brief Get the touch pad which caused wakeup
@ -129,7 +129,7 @@ esp_err_t esp_sleep_enable_touchpad_wakeup();
*
* @return touch pad which caused wakeup
*/
touch_pad_t esp_sleep_get_touchpad_wakeup_status();
touch_pad_t esp_sleep_get_touchpad_wakeup_status(void);
/**
* @brief Enable wakeup using a pin
@ -197,7 +197,7 @@ esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t mask, esp_sleep_ext1_wakeup_mode
*
* @return bit mask, if GPIOn caused wakeup, BIT(n) will be set
*/
uint64_t esp_sleep_get_ext1_wakeup_status();
uint64_t esp_sleep_get_ext1_wakeup_status(void);
/**
* @brief Set power down mode for an RTC power domain in sleep mode
@ -218,7 +218,7 @@ esp_err_t esp_sleep_pd_config(esp_sleep_pd_domain_t domain,
*
* This function does not return.
*/
void esp_deep_sleep_start() __attribute__((noreturn));
void esp_deep_sleep_start(void) __attribute__((noreturn));
/**
* @brief Enter light sleep with the configured wakeup options
@ -227,7 +227,7 @@ void esp_deep_sleep_start() __attribute__((noreturn));
* - ESP_OK on success (returned after wakeup)
* - ESP_ERR_INVALID_STATE if WiFi or BT is not stopped
*/
esp_err_t esp_light_sleep_start();
esp_err_t esp_light_sleep_start(void);
/**
* @brief Enter deep-sleep mode
@ -269,7 +269,7 @@ void system_deep_sleep(uint64_t time_in_us) __attribute__((noreturn, deprecated)
*
* @return wakeup cause, or ESP_DEEP_SLEEP_WAKEUP_UNDEFINED if reset happened for reason other than deep sleep wakeup
*/
esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause();
esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void);
/**

12
components/esp32s2beta/include/esp_spiram.h
View File

@ -25,7 +25,7 @@
*
* @return ESP_OK on success
*/
esp_err_t esp_spiram_init();
esp_err_t esp_spiram_init(void);
/**
* @brief Configure Cache/MMU for access to external SPI RAM.
@ -36,7 +36,7 @@ esp_err_t esp_spiram_init();
*
* @attention this function must be called with flash cache disabled.
*/
void esp_spiram_init_cache();
void esp_spiram_init_cache(void);
/**
@ -47,13 +47,13 @@ void esp_spiram_init_cache();
*
* @return true on success, false on failed memory test
*/
bool esp_spiram_test();
bool esp_spiram_test(void);
/**
* @brief Add the initialized SPI RAM to the heap allocator.
*/
esp_err_t esp_spiram_add_to_heapalloc();
esp_err_t esp_spiram_add_to_heapalloc(void);
/**
@ -61,7 +61,7 @@ esp_err_t esp_spiram_add_to_heapalloc();
*
* @return Size in bytes, or 0 if no external RAM chip support compiled in.
*/
size_t esp_spiram_get_size();
size_t esp_spiram_get_size(void);
/**
@ -71,7 +71,7 @@ size_t esp_spiram_get_size();
*
* This is meant for use from within the SPI flash code.
*/
void esp_spiram_writeback_cache();
void esp_spiram_writeback_cache(void);

4
components/esp32s2beta/int_wdt.c
View File

@ -70,7 +70,7 @@ static void IRAM_ATTR tick_hook(void) {
#endif
void esp_int_wdt_init() {
void esp_int_wdt_init(void) {
periph_module_enable(PERIPH_TIMG1_MODULE);
TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
TIMERG1.wdt_config0.sys_reset_length=7; //3.2uS
@ -90,7 +90,7 @@ void esp_int_wdt_init() {
timer_group_intr_enable(TIMER_GROUP_1, TIMG_WDT_INT_ENA_M);
}
void esp_int_wdt_cpu_init()
void esp_int_wdt_cpu_init(void)
{
esp_register_freertos_tick_hook_for_cpu(tick_hook, xPortGetCoreID());
ESP_INTR_DISABLE(WDT_INT_NUM);

4
components/esp32s2beta/intr_alloc.c
View File

@ -841,7 +841,7 @@ esp_err_t IRAM_ATTR esp_intr_disable(intr_handle_t handle)
}
void IRAM_ATTR esp_intr_noniram_disable()
void IRAM_ATTR esp_intr_noniram_disable(void)
{
int oldint;
int cpu=xPortGetCoreID();
@ -860,7 +860,7 @@ void IRAM_ATTR esp_intr_noniram_disable()
non_iram_int_disabled[cpu]=oldint&non_iram_int_mask[cpu];
}
void IRAM_ATTR esp_intr_noniram_enable()
void IRAM_ATTR esp_intr_noniram_enable(void)
{
int cpu=xPortGetCoreID();
int intmask=non_iram_int_disabled[cpu];

20
components/esp32s2beta/panic.c
View File

@ -125,7 +125,7 @@ void __attribute__((weak)) vApplicationStackOverflowHook( TaskHandle_t xTask, s
static bool abort_called;
static __attribute__((noreturn)) inline void invoke_abort()
static __attribute__((noreturn)) inline void invoke_abort(void)
{
abort_called = true;
#if CONFIG_ESP32_APPTRACE_ENABLE
@ -144,7 +144,7 @@ static __attribute__((noreturn)) inline void invoke_abort()
}
}
void abort()
void abort(void)
{
#if !CONFIG_ESP32S2_PANIC_SILENT_REBOOT
ets_printf("abort() was called at PC 0x%08x on core %d\r\n", (intptr_t)__builtin_return_address(0) - 3, xPortGetCoreID());
@ -169,11 +169,11 @@ static const char *edesc[] = {
#define NUM_EDESCS (sizeof(edesc) / sizeof(char *))
static void commonErrorHandler(XtExcFrame *frame);
static inline void disableAllWdts();
static inline void disableAllWdts(void);
//The fact that we've panic'ed probably means the other CPU is now running wild, possibly
//messing up the serial output, so we stall it here.
static void haltOtherCore()
static void haltOtherCore(void)
{
esp_cpu_stall( xPortGetCoreID() == 0 ? 1 : 0 );
}
@ -349,7 +349,7 @@ void xt_unhandled_exception(XtExcFrame *frame)
all watchdogs except the timer group 0 watchdog, and it reconfigures that to reset the chip after
one second.
*/
static void reconfigureAllWdts()
static void reconfigureAllWdts(void)
{
TIMERG0.wdt_wprotect = TIMG_WDT_WKEY_VALUE;
TIMERG0.wdt_feed = 1;
@ -369,7 +369,7 @@ static void reconfigureAllWdts()
/*
This disables all the watchdogs for when we call the gdbstub.
*/
static inline void disableAllWdts()
static inline void disableAllWdts(void)
{
TIMERG0.wdt_wprotect = TIMG_WDT_WKEY_VALUE;
TIMERG0.wdt_config0.en = 0;
@ -379,7 +379,7 @@ static inline void disableAllWdts()
TIMERG1.wdt_wprotect = 0;
}
static void esp_panic_wdt_start()
static void esp_panic_wdt_start(void)
{
if (REG_GET_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN)) {
return;
@ -396,7 +396,7 @@ static void esp_panic_wdt_start()
WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, 0);
}
void esp_panic_wdt_stop()
void esp_panic_wdt_stop(void)
{
WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE);
WRITE_PERI_REG(RTC_CNTL_WDTFEED_REG, 1);
@ -405,9 +405,9 @@ void esp_panic_wdt_stop()
WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, 0);
}
static void esp_panic_dig_reset() __attribute__((noreturn));
static void esp_panic_dig_reset(void) __attribute__((noreturn));
static void esp_panic_dig_reset()
static void esp_panic_dig_reset(void)
{
// make sure all the panic handler output is sent from UART FIFO
uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);

18
components/esp32s2beta/pm_esp32s2beta.c
View File

@ -146,9 +146,9 @@ static const char* s_mode_names[] = {
static const char* TAG = "pm_esp32";
static void update_ccompare();
static void update_ccompare(void);
static void do_switch(pm_mode_t new_mode);
static void leave_idle();
static void leave_idle(void);
static void on_freq_update(uint32_t old_ticks_per_us, uint32_t ticks_per_us);
@ -242,7 +242,7 @@ esp_err_t esp_pm_configure(const void* vconfig)
return ESP_OK;
}
static pm_mode_t IRAM_ATTR get_lowest_allowed_mode()
static pm_mode_t IRAM_ATTR get_lowest_allowed_mode(void)
{
/* TODO: optimize using ffs/clz */
if (s_mode_mask >= BIT(PM_MODE_CPU_MAX)) {
@ -413,7 +413,7 @@ static void IRAM_ATTR do_switch(pm_mode_t new_mode)
* would happen without the frequency change.
* Assumes that the new_frequency = old_frequency * s_ccount_mul / s_ccount_div.
*/
static void IRAM_ATTR update_ccompare()
static void IRAM_ATTR update_ccompare(void)
{
uint32_t ccount = XTHAL_GET_CCOUNT();
uint32_t ccompare = XTHAL_GET_CCOMPARE(XT_TIMER_INDEX);
@ -427,7 +427,7 @@ static void IRAM_ATTR update_ccompare()
}
}
static void IRAM_ATTR leave_idle()
static void IRAM_ATTR leave_idle(void)
{
int core_id = xPortGetCoreID();
if (s_core_idle[core_id]) {
@ -437,7 +437,7 @@ static void IRAM_ATTR leave_idle()
}
}
void esp_pm_impl_idle_hook()
void esp_pm_impl_idle_hook(void)
{
int core_id = xPortGetCoreID();
uint32_t state = portENTER_CRITICAL_NESTED();
@ -449,7 +449,7 @@ void esp_pm_impl_idle_hook()
ESP_PM_TRACE_ENTER(IDLE, core_id);
}
void esp_pm_impl_waiti()
void esp_pm_impl_waiti(void)
{
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
int core_id = xPortGetCoreID();
@ -467,7 +467,7 @@ void esp_pm_impl_waiti()
#endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
}
void IRAM_ATTR esp_pm_impl_isr_hook()
void IRAM_ATTR esp_pm_impl_isr_hook(void)
{
int core_id = xPortGetCoreID();
ESP_PM_TRACE_ENTER(ISR_HOOK, core_id);
@ -563,7 +563,7 @@ void esp_pm_impl_dump_stats(FILE* out)
}
#endif // WITH_PROFILING
void esp_pm_impl_init()
void esp_pm_impl_init(void)
{
s_cpu_freq_to_ticks[RTC_CPU_FREQ_XTAL] = rtc_clk_xtal_freq_get();
#ifdef CONFIG_PM_TRACE

2
components/esp32s2beta/pm_trace.c
View File

@ -30,7 +30,7 @@ static const int DRAM_ATTR s_trace_io[] = {
BIT(27), BIT(27), // ESP_PM_TRACE_SLEEP
};
void esp_pm_trace_init()
void esp_pm_trace_init(void)
{
for (size_t i = 0; i < sizeof(s_trace_io)/sizeof(s_trace_io[0]); ++i) {
int io = __builtin_ffs(s_trace_io[i]);

36
components/esp32s2beta/sleep_modes.c
View File

@ -87,10 +87,10 @@ static _lock_t lock_rtc_memory_crc;
static const char* TAG = "sleep";
static uint32_t get_power_down_flags();
static void ext0_wakeup_prepare();
static void ext1_wakeup_prepare();
static void timer_wakeup_prepare();
static uint32_t get_power_down_flags(void);
static void ext0_wakeup_prepare(void);
static void ext1_wakeup_prepare(void);
static void timer_wakeup_prepare(void);
/* Wake from deep sleep stub
See esp_deepsleep.h esp_wake_deep_sleep() comments for details.
@ -133,7 +133,7 @@ void esp_deep_sleep(uint64_t time_in_us)
esp_deep_sleep_start();
}
static void IRAM_ATTR suspend_uarts()
static void IRAM_ATTR suspend_uarts(void)
{
for (int i = 0; i < 2; ++i) {
REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF);
@ -141,7 +141,7 @@ static void IRAM_ATTR suspend_uarts()
}
}
static void IRAM_ATTR resume_uarts()
static void IRAM_ATTR resume_uarts(void)
{
for (int i = 0; i < 2; ++i) {
REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF);
@ -192,7 +192,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
return result;
}
void IRAM_ATTR esp_deep_sleep_start()
void IRAM_ATTR esp_deep_sleep_start(void)
{
// record current RTC time
s_config.rtc_ticks_at_sleep_start = rtc_time_get();
@ -230,7 +230,7 @@ static void rtc_wdt_enable(int time_ms)
WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, 0);
}
static void rtc_wdt_disable()
static void rtc_wdt_disable(void)
{
WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE);
WRITE_PERI_REG(RTC_CNTL_WDTFEED_REG, 1);
@ -268,7 +268,7 @@ static esp_err_t esp_light_sleep_inner(uint32_t pd_flags,
return err;
}
esp_err_t esp_light_sleep_start()
esp_err_t esp_light_sleep_start(void)
{
static portMUX_TYPE light_sleep_lock = portMUX_INITIALIZER_UNLOCKED;
portENTER_CRITICAL(&light_sleep_lock);
@ -367,7 +367,7 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source)
return ESP_OK;
}
esp_err_t esp_sleep_enable_ulp_wakeup()
esp_err_t esp_sleep_enable_ulp_wakeup(void)
{
return ESP_ERR_NOT_SUPPORTED;
}
@ -379,7 +379,7 @@ esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us)
return ESP_OK;
}
static void timer_wakeup_prepare()
static void timer_wakeup_prepare(void)
{
uint32_t period = esp_clk_slowclk_cal_get();
int64_t sleep_duration = (int64_t) s_config.sleep_duration - (int64_t) s_config.sleep_time_adjustment;
@ -391,7 +391,7 @@ static void timer_wakeup_prepare()
rtc_sleep_set_wakeup_time(s_config.rtc_ticks_at_sleep_start + rtc_count_delta);
}
esp_err_t esp_sleep_enable_touchpad_wakeup()
esp_err_t esp_sleep_enable_touchpad_wakeup(void)
{
if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN)) {
ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0");
@ -401,7 +401,7 @@ esp_err_t esp_sleep_enable_touchpad_wakeup()
return ESP_OK;
}
touch_pad_t esp_sleep_get_touchpad_wakeup_status()
touch_pad_t esp_sleep_get_touchpad_wakeup_status(void)
{
if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_TOUCHPAD) {
return TOUCH_PAD_MAX;
@ -430,7 +430,7 @@ esp_err_t esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level)
return ESP_OK;
}
static void ext0_wakeup_prepare()
static void ext0_wakeup_prepare(void)
{
int rtc_gpio_num = s_config.ext0_rtc_gpio_num;
// Set GPIO to be used for wakeup
@ -472,7 +472,7 @@ esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t mask, esp_sleep_ext1_wakeup_mode
return ESP_OK;
}
static void ext1_wakeup_prepare()
static void ext1_wakeup_prepare(void)
{
// Configure all RTC IOs selected as ext1 wakeup inputs
uint32_t rtc_gpio_mask = s_config.ext1_rtc_gpio_mask;
@ -508,7 +508,7 @@ static void ext1_wakeup_prepare()
s_config.ext1_trigger_mode, RTC_CNTL_EXT_WAKEUP1_LV_S);
}
uint64_t esp_sleep_get_ext1_wakeup_status()
uint64_t esp_sleep_get_ext1_wakeup_status(void)
{
if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_EXT1) {
return 0;
@ -529,7 +529,7 @@ uint64_t esp_sleep_get_ext1_wakeup_status()
return gpio_mask;
}
esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause()
esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void)
{
if (rtc_get_reset_reason(0) != DEEPSLEEP_RESET) {
return ESP_SLEEP_WAKEUP_UNDEFINED;
@ -561,7 +561,7 @@ esp_err_t esp_sleep_pd_config(esp_sleep_pd_domain_t domain,
return ESP_OK;
}
static uint32_t get_power_down_flags()
static uint32_t get_power_down_flags(void)
{
// Where needed, convert AUTO options to ON. Later interpret AUTO as OFF.

16
components/esp32s2beta/spiram.c
View File

@ -68,7 +68,7 @@ static bool spiram_inited=false;
true when RAM seems OK, false when test fails. WARNING: Do not run this before the 2nd cpu has been
initialized (in a two-core system) or after the heap allocator has taken ownership of the memory.
*/
bool esp_spiram_test()
bool esp_spiram_test(void)
{
volatile int *spiram=(volatile int*)(SOC_EXTRAM_DATA_HIGH - CONFIG_SPIRAM_SIZE);
size_t p;
@ -128,7 +128,7 @@ bool esp_spiram_test()
#define SPIRAM_MID_BIG_SIZE_MAP_SIZE DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE
void IRAM_ATTR esp_spiram_init_cache()
void IRAM_ATTR esp_spiram_init_cache(void)
{
Cache_Suspend_DCache();
/* map the address from SPIRAM end to the start, map the address in order: DRAM1, DRAM1, DPORT, DBUS3 */
@ -175,12 +175,12 @@ static uint32_t page0_page = 0xffff;
static uint32_t instrcution_in_spiram = 0;
static uint32_t rodata_in_spiram = 0;
uint32_t esp_spiram_instruction_access_enabled()
uint32_t esp_spiram_instruction_access_enabled(void)
{
return instrcution_in_spiram;
}
uint32_t esp_spiram_rodata_access_enabled()
uint32_t esp_spiram_rodata_access_enabled(void)
{
return rodata_in_spiram;
}
@ -233,7 +233,7 @@ esp_err_t esp_spiram_enable_rodata_access(void)
return ESP_OK;
}
esp_err_t esp_spiram_init()
esp_err_t esp_spiram_init(void)
{
esp_err_t r;
r = psram_enable(PSRAM_SPEED, PSRAM_MODE);
@ -256,7 +256,7 @@ esp_err_t esp_spiram_init()
}
esp_err_t esp_spiram_add_to_heapalloc()
esp_err_t esp_spiram_add_to_heapalloc(void)
{
uint32_t size_for_flash = (pages_for_flash << 16);
ESP_EARLY_LOGI(TAG, "Adding pool of %dK of external SPI memory to heap allocator", (CONFIG_SPIRAM_SIZE - (pages_for_flash << 16))/1024);
@ -319,7 +319,7 @@ esp_err_t esp_spiram_reserve_dma_pool(size_t size) {
return heap_caps_add_region_with_caps(caps, (intptr_t) dma_heap, (intptr_t) dma_heap+size-1);
}
size_t esp_spiram_get_size()
size_t esp_spiram_get_size(void)
{
return CONFIG_SPIRAM_SIZE;
}
@ -328,7 +328,7 @@ size_t esp_spiram_get_size()
Before flushing the cache, if psram is enabled as a memory-mapped thing, we need to write back the data in the cache to the psram first,
otherwise it will get lost. For now, we just read 64/128K of random PSRAM memory to do this.
*/
void IRAM_ATTR esp_spiram_writeback_cache()
void IRAM_ATTR esp_spiram_writeback_cache(void)
{
extern void Cache_WriteBack_All(void);
int cache_was_disabled=0;

2
components/esp32s2beta/spiram_psram.c
View File

@ -698,7 +698,7 @@ static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode)
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPICLK_U, FUNC_SPICLK_SPICLK);
}
psram_size_t psram_get_size()
psram_size_t psram_get_size(void)
{
if (PSRAM_IS_32MBIT_VER0(s_psram_id)) {
return PSRAM_SIZE_32MBITS;

2
components/esp32s2beta/spiram_psram.h
View File

@ -53,7 +53,7 @@ typedef enum {
* - PSRAM_SIZE_MAX if psram not enabled or not valid
* - PSRAM size
*/
psram_size_t psram_get_size();
psram_size_t psram_get_size(void);
/**
* @brief psram cache enable function

6
components/esp32s2beta/system_api.c
View File

@ -44,7 +44,7 @@ static uint8_t base_mac_addr[6] = { 0 };
#define SHUTDOWN_HANDLERS_NO 2
static shutdown_handler_t shutdown_handlers[SHUTDOWN_HANDLERS_NO];
void system_init()
void system_init(void)
{
}
@ -227,7 +227,7 @@ esp_err_t esp_unregister_shutdown_handler(shutdown_handler_t handler)
return ESP_ERR_INVALID_STATE;
}
void esp_restart_noos() __attribute__ ((noreturn));
void esp_restart_noos(void) __attribute__ ((noreturn));
void IRAM_ATTR esp_restart(void)
{
@ -248,7 +248,7 @@ void IRAM_ATTR esp_restart(void)
* core are already stopped. Stalls other core, resets hardware,
* triggers restart.
*/
void IRAM_ATTR esp_restart_noos()
void IRAM_ATTR esp_restart_noos(void)
{
// Disable interrupts
xt_ints_off(0xFFFFFFFF);

8
components/esp32s2beta/task_wdt.c
View File

@ -102,7 +102,7 @@ static twdt_task_t *find_task_in_twdt_list(TaskHandle_t handle, bool *all_reset)
* Resets the hardware timer and has_reset flags of each task on the list.
* Called within critical
*/
static void reset_hw_timer()
static void reset_hw_timer(void)
{
//All tasks have reset; time to reset the hardware timer.
TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
@ -214,7 +214,7 @@ esp_err_t esp_task_wdt_init(uint32_t timeout, bool panic)
return ESP_OK;
}
esp_err_t esp_task_wdt_deinit()
esp_err_t esp_task_wdt_deinit(void)
{
portENTER_CRITICAL(&twdt_spinlock);
//TWDT must already be initialized
@ -282,7 +282,7 @@ esp_err_t esp_task_wdt_add(TaskHandle_t handle)
return ESP_OK;
}
esp_err_t esp_task_wdt_reset()
esp_err_t esp_task_wdt_reset(void)
{
portENTER_CRITICAL(&twdt_spinlock);
//TWDT must already be initialized
@ -370,7 +370,7 @@ esp_err_t esp_task_wdt_status(TaskHandle_t handle)
return ESP_ERR_NOT_FOUND;
}
void esp_task_wdt_feed()
void esp_task_wdt_feed(void)
{
portENTER_CRITICAL(&twdt_spinlock);
//Return immediately if TWDT has not been initialized

12
components/esp_rom/include/esp32s2beta/rom/cache.h
View File

@ -798,7 +798,7 @@ void Cache_Resume_DCache(uint32_t autoload);
*
* @return None
*/
void Cache_Drom0_Source_ICache();
void Cache_Drom0_Source_ICache(void);
/**
* @brief Make Drom0 bus access from DCache.
@ -807,7 +807,7 @@ void Cache_Drom0_Source_ICache();
*
* @return None
*/
void Cache_Drom0_Source_DCache();
void Cache_Drom0_Source_DCache(void);
/**
* @brief Return if Drom0 bus access from ICache.
@ -816,7 +816,7 @@ void Cache_Drom0_Source_DCache();
*
* @return uint32_t: 0 for no, other for yes
*/
uint32_t Cache_Drom0_Using_ICache();
uint32_t Cache_Drom0_Using_ICache(void);
/**
* @brief Return if Drom0 bus access from DCache.
@ -825,7 +825,7 @@ uint32_t Cache_Drom0_Using_ICache();
*
* @return uint32_t: 0 for no, other for yes
*/
uint32_t Cache_Drom0_Using_DCache();
uint32_t Cache_Drom0_Using_DCache(void);
/**
* @brief Get ICache cache line size
@ -834,7 +834,7 @@ uint32_t Cache_Drom0_Using_DCache();
*
* @return uint32_t: 16, 32, 64 Byte
*/
uint32_t Cache_Get_ICache_Line_Size();
uint32_t Cache_Get_ICache_Line_Size(void);
/**
* @brief Get DCache cache line size
@ -843,7 +843,7 @@ uint32_t Cache_Get_ICache_Line_Size();
*
* @return uint32_t: 16, 32, 64 Byte
*/
uint32_t Cache_Get_DCache_Line_Size();
uint32_t Cache_Get_DCache_Line_Size(void);
/**
* @brief Set default mode from boot.

4
components/esp_rom/include/esp32s2beta/rom/spi_flash.h
View File

@ -511,8 +511,8 @@ typedef esp_rom_spiflash_result_t SpiFlashOpResult;
SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, const void* data, uint32_t len);
SpiFlashOpResult SPI_Encrypt_Write_Dest(SpiEncryptDest dest, uint32_t flash_addr, const void* data, uint32_t len);
void SPI_Write_Encrypt_Enable();
void SPI_Write_Encrypt_Disable();
void SPI_Write_Encrypt_Enable(void);
void SPI_Write_Encrypt_Disable(void);
/** @brief Wait until SPI flash write operation is complete
*

2
components/esp_rom/include/esp32s2beta/rom/tbconsole.h
View File

@ -18,7 +18,7 @@
extern "C" {
#endif
void start_tb_console();
void start_tb_console(void);
#ifdef __cplusplus
}

2
components/soc/esp32s2beta/cpu_util.c
View File

@ -50,7 +50,7 @@ void IRAM_ATTR esp_cpu_reset(int cpu_id)
cpu_id == 0 ? RTC_CNTL_SW_PROCPU_RST_M : RTC_CNTL_SW_APPCPU_RST_M);
}
bool IRAM_ATTR esp_cpu_in_ocd_debug_mode()
bool IRAM_ATTR esp_cpu_in_ocd_debug_mode(void)
{
#if CONFIG_ESP32S2_DEBUG_OCDAWARE
int dcr;

8
components/soc/esp32s2beta/include/soc/cpu.h
View File

@ -29,7 +29,7 @@
/** @brief Read current stack pointer address
*
*/
static inline void *get_sp()
static inline void *get_sp(void)
{
void *sp;
asm volatile ("mov %0, sp;" : "=r" (sp));
@ -51,7 +51,7 @@ static inline void cpu_write_itlb(unsigned vpn, unsigned attr)
asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr));
}
static inline void cpu_init_memctl()
static inline void cpu_init_memctl(void)
{
#if XCHAL_ERRATUM_572
#error "Shouldn't have this errata or need this call on esp32s2beta"
@ -69,7 +69,7 @@ static inline void cpu_init_memctl()
* 15 — no access, raise exception
*/
static inline void cpu_configure_region_protection()
static inline void cpu_configure_region_protection(void)
{
const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000};
for (int i = 0; i < sizeof(pages_to_protect)/sizeof(pages_to_protect[0]); ++i) {
@ -106,7 +106,7 @@ void esp_cpu_reset(int cpu_id);
* @note If "Make exception and panic handlers JTAG/OCD aware"
* is disabled, this function always returns false.
*/
bool esp_cpu_in_ocd_debug_mode();
bool esp_cpu_in_ocd_debug_mode(void);
/**
* @brief Convert the PC register value to its true address

28
components/soc/esp32s2beta/include/soc/rtc.h
View File

@ -163,7 +163,7 @@ void rtc_clk_init(rtc_clk_config_t cfg);
*
* @return XTAL frequency, one of rtc_xtal_freq_t
*/
rtc_xtal_freq_t rtc_clk_xtal_freq_get();
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
/**
* @brief Update XTAL frequency
@ -185,7 +185,7 @@ void rtc_clk_32k_enable(bool en);
* @brief Get the state of 32k XTAL oscillator
* @return true if 32k XTAL oscillator has been enabled
*/
bool rtc_clk_32k_enabled();
bool rtc_clk_32k_enabled(void);
/**
* @brief Enable 32k oscillator, configuring it for fast startup time.
@ -221,13 +221,13 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en);
* @brief Get the state of 8 MHz internal oscillator
* @return true if the oscillator is enabled
*/
bool rtc_clk_8m_enabled();
bool rtc_clk_8m_enabled(void);
/**
* @brief Get the state of /256 divider which is applied to 8MHz clock
* @return true if the divided output is enabled
*/
bool rtc_clk_8md256_enabled();
bool rtc_clk_8md256_enabled(void);
/**
* @brief Enable or disable APLL
@ -257,7 +257,7 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq);
* @brief Get the RTC_SLOW_CLK source
* @return currently selected clock source (one of rtc_slow_freq_t values)
*/
rtc_slow_freq_t rtc_clk_slow_freq_get();
rtc_slow_freq_t rtc_clk_slow_freq_get(void);
/**
* @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
@ -271,7 +271,7 @@ rtc_slow_freq_t rtc_clk_slow_freq_get();
*
* @return RTC_SLOW_CLK frequency, in Hz
*/
uint32_t rtc_clk_slow_freq_get_hz();
uint32_t rtc_clk_slow_freq_get_hz(void);
/**
* @brief Select source for RTC_FAST_CLK
@ -283,7 +283,7 @@ void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq);
* @brief Get the RTC_FAST_CLK source
* @return currently selected clock source (one of rtc_fast_freq_t values)
*/
rtc_fast_freq_t rtc_clk_fast_freq_get();
rtc_fast_freq_t rtc_clk_fast_freq_get(void);
/**
* @brief Switch CPU frequency
@ -327,7 +327,7 @@ void rtc_clk_cpu_freq_set_fast(rtc_cpu_freq_t cpu_freq);
*
* @return CPU frequency (one of rtc_cpu_freq_t values)
*/
rtc_cpu_freq_t rtc_clk_cpu_freq_get();
rtc_cpu_freq_t rtc_clk_cpu_freq_get(void);
/**
* @brief Get corresponding frequency value for rtc_cpu_freq_t enum value
@ -362,7 +362,7 @@ void rtc_clk_apb_freq_update(uint32_t apb_freq);
* @brief Get the current stored APB frequency.
* @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz.
*/
uint32_t rtc_clk_apb_freq_get();
uint32_t rtc_clk_apb_freq_get(void);
#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
@ -421,11 +421,11 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
*
* @return current value of RTC counter
*/
uint64_t rtc_time_get();
uint64_t rtc_time_get(void);
uint64_t rtc_light_slp_time_get();
uint64_t rtc_light_slp_time_get(void);
uint64_t rtc_deep_slp_time_get();
uint64_t rtc_deep_slp_time_get(void);
/**
* @brief Busy loop until next RTC_SLOW_CLK cycle
@ -434,7 +434,7 @@ uint64_t rtc_deep_slp_time_get();
* In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
* one RTC_SLOW_CLK cycle later.
*/
void rtc_clk_wait_for_slow_cycle();
void rtc_clk_wait_for_slow_cycle(void);
/**
* @brief Power down flags for rtc_sleep_pd function
@ -647,7 +647,7 @@ typedef struct {
* Otherwise, use default values and the level of MTDI bootstrapping pin.
* @return currently used VDDSDIO configuration
*/
rtc_vddsdio_config_t rtc_vddsdio_get_config();
rtc_vddsdio_config_t rtc_vddsdio_get_config(void);
/**
* Set new VDDSDIO configuration using RTC registers.

24
components/soc/esp32s2beta/rtc_clk.c
View File

@ -176,7 +176,7 @@ void rtc_clk_32k_bootstrap(uint32_t cycle)
CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_RTC_EN);
}
bool rtc_clk_32k_enabled()
bool rtc_clk_32k_enabled(void)
{
uint32_t xtal_conf = READ_PERI_REG(RTC_CNTL_EXT_XTL_CONF_REG);
/* If xtal xpd is controlled by software */
@ -211,12 +211,12 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
}
}
bool rtc_clk_8m_enabled()
bool rtc_clk_8m_enabled(void)
{
return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0;
}
bool rtc_clk_8md256_enabled()
bool rtc_clk_8md256_enabled(void)
{
return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
}
@ -278,12 +278,12 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
ets_delay_us(DELAY_SLOW_CLK_SWITCH);
}
rtc_slow_freq_t rtc_clk_slow_freq_get()
rtc_slow_freq_t rtc_clk_slow_freq_get(void)
{
return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
}
uint32_t rtc_clk_slow_freq_get_hz()
uint32_t rtc_clk_slow_freq_get_hz(void)
{
switch(rtc_clk_slow_freq_get()) {
case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K;
@ -299,7 +299,7 @@ void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq)
ets_delay_us(DELAY_FAST_CLK_SWITCH);
}
rtc_fast_freq_t rtc_clk_fast_freq_get()
rtc_fast_freq_t rtc_clk_fast_freq_get(void)
{
return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL);
}
@ -446,7 +446,7 @@ void rtc_clk_bbpll_set(rtc_xtal_freq_t xtal_freq, rtc_pll_t pll_freq)
/**
* Switch to XTAL frequency. Does not disable the PLL.
*/
static void rtc_clk_cpu_freq_to_xtal()
static void rtc_clk_cpu_freq_to_xtal(void)
{
rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
ets_update_cpu_frequency(xtal_freq);
@ -586,7 +586,7 @@ void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq)
s_cur_freq = cpu_freq;
}
rtc_cpu_freq_t rtc_clk_cpu_freq_get()
rtc_cpu_freq_t rtc_clk_cpu_freq_get(void)
{
uint32_t soc_clk_sel = REG_GET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL);
switch (soc_clk_sel) {
@ -681,7 +681,7 @@ static uint32_t clk_val_to_reg_val(uint32_t val) {
return (val & UINT16_MAX) | ((val & UINT16_MAX) << 16);
}
rtc_xtal_freq_t rtc_clk_xtal_freq_get()
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
{
/* We may have already written XTAL value into RTC_XTAL_FREQ_REG */
uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
@ -697,7 +697,7 @@ void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
WRITE_PERI_REG(RTC_XTAL_FREQ_REG, clk_val_to_reg_val(xtal_freq));
}
static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate()
static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void)
{
/* Enable 8M/256 clock if needed */
const bool clk_8m_enabled = rtc_clk_8m_enabled();
@ -738,7 +738,7 @@ void rtc_clk_apb_freq_update(uint32_t apb_freq)
WRITE_PERI_REG(RTC_APB_FREQ_REG, clk_val_to_reg_val(apb_freq >> 12));
}
uint32_t rtc_clk_apb_freq_get()
uint32_t rtc_clk_apb_freq_get(void)
{
uint32_t freq_hz = reg_val_to_clk_val(READ_PERI_REG(RTC_APB_FREQ_REG)) << 12;
// round to the nearest MHz
@ -848,4 +848,4 @@ void rtc_clk_init(rtc_clk_config_t cfg)
/* Name used in libphy.a:phy_chip_v7.o
* TODO: update the library to use rtc_clk_xtal_freq_get
*/
rtc_xtal_freq_t rtc_get_xtal() __attribute__((alias("rtc_clk_xtal_freq_get")));
rtc_xtal_freq_t rtc_get_xtal(void) __attribute__((alias("rtc_clk_xtal_freq_get")));

2
components/soc/esp32s2beta/rtc_init.c
View File

@ -184,7 +184,7 @@ void rtc_init(rtc_config_t cfg)
}
#endif
rtc_vddsdio_config_t rtc_vddsdio_get_config()
rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
{
rtc_vddsdio_config_t result;
uint32_t sdio_conf_reg = REG_READ(RTC_CNTL_SDIO_CONF_REG);

8
components/soc/esp32s2beta/rtc_pm.c
View File

@ -31,14 +31,14 @@ typedef enum{
/* These MAC-related functions are defined in the closed source part of
* RTC library
*/
extern void pm_mac_init();
extern int pm_check_mac_idle();
extern void pm_mac_deinit();
extern void pm_mac_init(void);
extern int pm_check_mac_idle(void);
extern void pm_mac_deinit(void);
/* This sleep-related function is called from the closed source part of RTC
* library.
*/
pm_sw_reject_t pm_set_sleep_mode(pm_sleep_mode_t sleep_mode, void(*pmac_save_params)())
pm_sw_reject_t pm_set_sleep_mode(pm_sleep_mode_t sleep_mode, void(*pmac_save_params)(void))
{
(void) pmac_save_params; /* unused */

8
components/soc/esp32s2beta/rtc_time.c
View File

@ -126,7 +126,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT;
}
uint64_t rtc_time_get()
uint64_t rtc_time_get(void)
{
SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
while (GET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_VALID) == 0) {
@ -138,7 +138,7 @@ uint64_t rtc_time_get()
return t;
}
uint64_t rtc_light_slp_time_get()
uint64_t rtc_light_slp_time_get(void)
{
uint64_t t_wake = READ_PERI_REG(RTC_CNTL_TIME_LOW0_REG);
t_wake |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH0_REG)) << 32;
@ -147,7 +147,7 @@ uint64_t rtc_light_slp_time_get()
return (t_wake - t_slp);
}
uint64_t rtc_deep_slp_time_get()
uint64_t rtc_deep_slp_time_get(void)
{
uint64_t t_slp = READ_PERI_REG(RTC_CNTL_TIME_LOW1_REG);
t_slp |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH1_REG)) << 32;
@ -155,7 +155,7 @@ uint64_t rtc_deep_slp_time_get()
return (t_wake - t_slp);
}
void rtc_clk_wait_for_slow_cycle() //This function may not by useful any more
void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
{
SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE);
while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) {

2
components/soc/esp32s2beta/test/test_rtc_clk.c
View File

@ -137,7 +137,7 @@ TEST_CASE("Test fast switching between PLL and XTAL", "[rtc_clk]")
#define COUNT_TEST 3
#define TIMEOUT_TEST_MS (5 + CONFIG_ESP32_RTC_CLK_CAL_CYCLES / 16)
void stop_rtc_external_quartz(){
void stop_rtc_external_quartz(void){
const uint8_t pin_32 = 32;
const uint8_t pin_33 = 33;
const uint8_t mask_32 = (1 << (pin_32 - 32));

4
components/spi_flash/esp32/flash_ops_esp32.c
View File

@ -16,7 +16,7 @@
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/cache.h"
static inline void IRAM_ATTR spi_flash_guard_start()
static inline void IRAM_ATTR spi_flash_guard_start(void)
{
const spi_flash_guard_funcs_t *ops = spi_flash_guard_get();
if (ops && ops->start) {
@ -24,7 +24,7 @@ static inline void IRAM_ATTR spi_flash_guard_start()
}
}
static inline void IRAM_ATTR spi_flash_guard_end()
static inline void IRAM_ATTR spi_flash_guard_end(void)
{
const spi_flash_guard_funcs_t *ops = spi_flash_guard_get();
if (ops && ops->end) {

4
examples/peripherals/temp_sensor_esp32s2/main/temp_sensor_main.c
View File

@ -39,14 +39,14 @@ void tempsensor_example(void *arg)
vTaskDelete(NULL);
}
void app_main()
void app_main(void)
{
xTaskCreate(tempsensor_example, "temp", 2048, NULL, 5, NULL);
}
#elif CONFIG_IDF_TARGET_ESP32
void app_main()
void app_main(void)
{
printf("ESP32 don't support temperature sensor\n");
}

2
examples/peripherals/touch_pad_interrupt/main/esp32s2beta/tp_interrupt_main.c
View File

@ -147,7 +147,7 @@ static void tp_example_read_task(void *pvParameter)
}
}
void app_main()
void app_main(void)
{
if (que_touch == NULL) {
que_touch = xQueueCreate(TOUCH_BUTTON_NUM, sizeof(touch_event_t));

2
examples/peripherals/touch_pad_read/main/esp32s2beta/tp_read_main.c
View File

@ -54,7 +54,7 @@ static void tp_example_read_task(void *pvParameter)
}
}
void app_main()
void app_main(void)
{
/* Initialize touch pad peripheral. */
touch_pad_init();