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Merge branch 'fix/unused_interrupts' into 'master'

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fix(esp_hw_ ‎support): clear reserved interrupts that are unused or not applicable anymore

Closes IDF-7821 and IDF-9428

See merge request espressif/esp-idf!29639
This commit is contained in:
Omar Chebib 2024-03-28 11:27:20 +08:00
commit 1683e9a92c
21 changed files with 404 additions and 359 deletions
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37
components/esp_hw_support/include/esp_private/esp_riscv_intr.h
View File

@ -9,6 +9,37 @@
#if CONFIG_IDF_TARGET_ARCH_RISCV
#if SOC_INT_CLIC_SUPPORTED
/**
* @brief Checks whether the given interrupt number is reserved either in the given mask or in the
* _mtvt_table, which contains the routines the CPU will jump to when an interrupt or an exception
* occurs, on RISC-V targets.
*
* @param intr_num External interrupt number to check, in range 0~32
* @param rsvd_mask Reserved interrupt mask, where bit i is 1 if interrupt i is reserved.
*
* @returns ESP_CPU_INTR_DESC_FLAG_RESVD if the interrupt is reserved, 0 else
*/
static inline uint32_t esp_riscv_intr_num_flags(int intr_num, uint32_t rsvd_mask)
{
if (rsvd_mask & BIT(intr_num)) {
return ESP_CPU_INTR_DESC_FLAG_RESVD;
}
extern intptr_t _mtvt_table[48];
extern intptr_t _interrupt_handler;
/* The first 16 entries of the array are internal interrupt, ignore them */
const intptr_t destination = _mtvt_table[16 + intr_num];
return (destination != (intptr_t)&_interrupt_handler) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0;
}
#else // !SOC_INT_CLIC_SUPPORTED
#include "esp_cpu.h"
#include "riscv/instruction_decode.h"
@ -28,9 +59,9 @@ static inline uint32_t esp_riscv_intr_num_flags(int intr_num, uint32_t rsvd_mask
return ESP_CPU_INTR_DESC_FLAG_RESVD;
}
extern int _vector_table;
extern intptr_t _vector_table[32];
extern int _interrupt_handler;
const intptr_t pc = (intptr_t)(&_vector_table + intr_num);
const intptr_t pc = (intptr_t) &_vector_table[intr_num];
/* JAL instructions are relative to the PC they are executed from. */
const intptr_t destination = pc + riscv_decode_offset_from_jal_instruction(pc);
@ -38,4 +69,6 @@ static inline uint32_t esp_riscv_intr_num_flags(int intr_num, uint32_t rsvd_mask
return (destination != (intptr_t)&_interrupt_handler) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0;
}
#endif // SOC_INT_CLIC_SUPPORTED
#endif // CONFIG_IDF_TARGET_ARCH_RISCV

7
components/esp_hw_support/intr_alloc.c
View File

@ -630,7 +630,7 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
esp_intr_disable(ret);
}
#ifdef SOC_CPU_HAS_FLEXIBLE_INTC
#if SOC_CPU_HAS_FLEXIBLE_INTC
//Extract the level from the interrupt passed flags
int level = esp_intr_flags_to_level(flags);
esp_cpu_intr_set_priority(intr, level);
@ -642,6 +642,11 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
}
#endif
#if SOC_INT_PLIC_SUPPORTED
/* Make sure the interrupt is not delegated to user mode (IDF uses machine mode only) */
RV_CLEAR_CSR(mideleg, BIT(intr));
#endif
portEXIT_CRITICAL(&spinlock);
//Fill return handle if needed, otherwise free handle.

156
components/esp_hw_support/port/esp32/esp_cpu_intr.c
View File

@ -22,20 +22,146 @@ typedef struct {
} intr_desc_t;
/**
* @brief Reserve interrupt 5 or 25 for Bluetooth BR/EDR and BLE controller.
*/
#if CONFIG_BTDM_CTRL_HLI
#define STATE_INTERRUPT_5 0
#define STATE_INTERRUPT_25 ESP_CPU_INTR_DESC_FLAG_RESVD
#else // !CONFIG_BTDM_CTRL_HLI
#define STATE_INTERRUPT_5 ESP_CPU_INTR_DESC_FLAG_RESVD
#define STATE_INTERRUPT_25 0
#endif // CONFIG_BTDM_CTRL_HLI
/**
* @brief Interrupt 1 is used by UART HCI, regardless of High-Level Interrupt (HLI) configuration
*/
#if CONFIG_BTDM_CTRL_HCI_MODE_UART_H4
#define STATE_INTERRUPT_1 ESP_CPU_INTR_DESC_FLAG_RESVD
/* Interrupt 7 being a software interrupt, it is marked as "special" if not used */
#define STATE_INTERRUPT_7 ESP_CPU_INTR_DESC_FLAG_SPECIAL
#else // !BTDM_CTRL_HCI_MODE_UART_H4
#define STATE_INTERRUPT_1 0
#define STATE_INTERRUPT_7 ESP_CPU_INTR_DESC_FLAG_RESVD
#endif // BTDM_CTRL_HCI_MODE_UART_H4
/**
* @brief Reserve the interrupts on the core where Bluetooth will run.
* The macro CONFIG_BTDM_CTRL_PINNED_TO_CORE is only defined if Bluetooth controller is enabled.
* It is set to the core where it will run.
*/
#ifdef CONFIG_BTDM_CTRL_PINNED_TO_CORE
#if CONFIG_BTDM_CTRL_PINNED_TO_CORE == 0
/* Interrupt 1 is used by Bluetooth UART HCI, check code above */
#define CORE_0_INTERRUPT_1 STATE_INTERRUPT_1
#define CORE_1_INTERRUPT_1 0
/* Interrupt 5 may be used by Bluetooth BR/EDR and BLE controller */
#define CORE_0_INTERRUPT_5 STATE_INTERRUPT_5
#define CORE_1_INTERRUPT_5 0
/* Interrupt 7 is used by Bluetooth VHCI software interrupt */
#define CORE_0_INTERRUPT_7 STATE_INTERRUPT_7
#define CORE_1_INTERRUPT_7 ESP_CPU_INTR_DESC_FLAG_SPECIAL
/* Interrupt 8 is used by Bluetooth BB */
#define CORE_0_INTERRUPT_8 ESP_CPU_INTR_DESC_FLAG_RESVD
#define CORE_1_INTERRUPT_8 0
/* Interrupt 25 may be used by Bluetooth BR/EDR and BLE controller */
#define CORE_0_INTERRUPT_25 STATE_INTERRUPT_25
#define CORE_1_INTERRUPT_25 0
#elif CONFIG_BTDM_CTRL_PINNED_TO_CORE == 1
/* Interrupt 1 is used by Bluetooth UART HCI, check code above */
#define CORE_0_INTERRUPT_1 0
#define CORE_1_INTERRUPT_1 STATE_INTERRUPT_1
/* Interrupt 5 may be used by Bluetooth BR/EDR and BLE controller */
#define CORE_0_INTERRUPT_5 0
#define CORE_1_INTERRUPT_5 STATE_INTERRUPT_5
/* Interrupt 7 is used by Bluetooth VHCI software interrupt */
#define CORE_0_INTERRUPT_7 ESP_CPU_INTR_DESC_FLAG_SPECIAL
#define CORE_1_INTERRUPT_7 STATE_INTERRUPT_7
/* Interrupt 8 is used by Bluetooth BB */
#define CORE_0_INTERRUPT_8 0
#define CORE_1_INTERRUPT_8 ESP_CPU_INTR_DESC_FLAG_RESVD
/* Interrupt 25 may be used by Bluetooth BR/EDR and BLE controller */
#define CORE_0_INTERRUPT_25 0
#define CORE_1_INTERRUPT_25 STATE_INTERRUPT_25
#endif
#else // Bluetooth not enabled
#define CORE_0_INTERRUPT_1 0
#define CORE_1_INTERRUPT_1 0
#define CORE_0_INTERRUPT_5 0
#define CORE_1_INTERRUPT_5 0
#define CORE_0_INTERRUPT_7 ESP_CPU_INTR_DESC_FLAG_SPECIAL
#define CORE_1_INTERRUPT_7 ESP_CPU_INTR_DESC_FLAG_SPECIAL
#define CORE_0_INTERRUPT_8 0
#define CORE_1_INTERRUPT_8 0
#define CORE_0_INTERRUPT_25 0
#define CORE_1_INTERRUPT_25 0
#endif
/**
* @brief The system interrupts (memory access, cache, watchdog, ...) can be allocated on either level 4 or level 5 interrupts.
* Check the configuration.
*/
#if CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5
#define CORE_0_INTERRUPT_24 0
#define CORE_1_INTERRUPT_24 0
/* If CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 is enabled, Bluetooth macros above take care of interrupt 25 */
/* Interrupt 26 reserved for T1 Watchdog, cache and memory access errors */
#define CORE_0_INTERRUPT_26 ESP_CPU_INTR_DESC_FLAG_RESVD
#define CORE_1_INTERRUPT_26 ESP_CPU_INTR_DESC_FLAG_RESVD
#define CORE_0_INTERRUPT_28 0
#define CORE_1_INTERRUPT_28 0
/* Interrupt 31 reserved for IPC ISRs */
#define CORE_0_INTERRUPT_31 ESP_CPU_INTR_DESC_FLAG_RESVD
#define CORE_1_INTERRUPT_31 ESP_CPU_INTR_DESC_FLAG_RESVD
#elif CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4
/* Interrupt reserved for T1 Watchdog, make sure it is enabled */
#if CONFIG_ESP_INT_WDT
#define CORE_0_INTERRUPT_24 ESP_CPU_INTR_DESC_FLAG_RESVD
#define CORE_1_INTERRUPT_24 ESP_CPU_INTR_DESC_FLAG_RESVD
#else // !CONFIG_ESP_INT_WDT
#define CORE_0_INTERRUPT_24 0
#define CORE_1_INTERRUPT_24 0
#endif
/* If CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 is enabled, Bluetooth HLI is not enabled for sure (guaranteed by Kconfig),
* so we can discard the macro previously defined for interrupt 25 */
#undef CORE_0_INTERRUPT_25
#undef CORE_1_INTERRUPT_25
/* Interrupt reserved for memory access and cache errors */
#define CORE_0_INTERRUPT_25 ESP_CPU_INTR_DESC_FLAG_RESVD
#define CORE_1_INTERRUPT_25 ESP_CPU_INTR_DESC_FLAG_RESVD
#define CORE_0_INTERRUPT_26 0
#define CORE_1_INTERRUPT_26 0
/* Interrupt reserved for IPC ISRs */
#define CORE_0_INTERRUPT_28 ESP_CPU_INTR_DESC_FLAG_RESVD
#define CORE_1_INTERRUPT_28 ESP_CPU_INTR_DESC_FLAG_RESVD
#define CORE_0_INTERRUPT_31 0
#define CORE_1_INTERRUPT_31 0
#endif // CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5
const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = {
/* Interrupt 0 reserved for WMAC (Wifi) */
[0] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
[1] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
/* Interrupt 1 reserved for BT/BLE Host HCI DMA when CONFIG_BTDM_CTRL_HCI_MODE_UART_H4 is enabled */
[1] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_1, CORE_1_INTERRUPT_1 } },
[2] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
[3] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
/* Interrupt 4 reserved for WBB */
[4] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } },
[5] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
/* Interrupt 5 reserved for BT/BLE Controller when Bluetooth HLI is enabled */
[5] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_5, CORE_1_INTERRUPT_5 } },
#if CONFIG_FREERTOS_CORETIMER_0
[6] = { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
#else
[6] = { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
#endif
[7] = { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
[8] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
/* Interrupt 7 reserved for Bluetooth VHCI (software interrupt) */
[7] = { 1, ESP_CPU_INTR_TYPE_NA, { CORE_0_INTERRUPT_7, CORE_1_INTERRUPT_7 } },
/* Interrupt 8 reserved for BT/BLE BB(RX/TX) */
[8] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_8, CORE_1_INTERRUPT_8 } },
[9] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
[10] = { 1, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } },
[11] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
@ -53,16 +179,22 @@ const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = {
[19] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
[20] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
[21] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
[22] = { 3, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } },
[22] = { 3, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } },
[23] = { 3, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
[24] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } },
[25] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
[26] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { 0, ESP_CPU_INTR_DESC_FLAG_RESVD } },
[27] = { 3, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
[28] = { 4, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } },
/* Interrupt 24 reserved for T1 WDT when CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 is enabled */
[24] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_24, CORE_1_INTERRUPT_24 } },
/* Interrupt 25 reserved for Memory access and cache errors when CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 is enabled
* Reserved for BT/BLE Controller when CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 is enabled */
[25] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_25, CORE_1_INTERRUPT_25 } },
/* Interrupt 26 reserved for T1 WDT, Memory access and cache errors when CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 is enabled */
[26] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_26, CORE_1_INTERRUPT_26 } },
[27] = { 3, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
/* Interrupt 28 reserved for IPC when CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 is enabled */
[28] = { 4, ESP_CPU_INTR_TYPE_EDGE, { CORE_0_INTERRUPT_28, CORE_1_INTERRUPT_28 } },
[29] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
[30] = { 4, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
[31] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
[30] = { 4, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } },
/* Interrupt 31 reserved for IPC when CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 is enabled */
[31] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_31, CORE_1_INTERRUPT_31 } },
};

5
components/esp_hw_support/port/esp32c2/esp_cpu_intr.c
View File

@ -11,11 +11,10 @@ void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_
{
/* On the ESP32-C2, interrupt:
* - 1 is for Wi-Fi
* - 5 and 8 for Bluetooth
* - 6 for "permanently disabled interrupt"
* - 6 for "permanently disabled interrupt", named INT_MUX_DISABLED_INTNO in the interrupt allocator
*/
// [TODO: IDF-2465]
const uint32_t rsvd_mask = BIT(1) | BIT(5) | BIT(6) | BIT(8);
const uint32_t rsvd_mask = BIT(1) | BIT(6);
intr_desc_ret->priority = 1;
intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;

2
components/esp_hw_support/port/esp32c3/esp_cpu_intr.c
View File

@ -12,7 +12,7 @@ void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_
/* On the ESP32-C3, interrupt:
* - 1 is for Wi-Fi
* - 5 and 8 for Bluetooth
* - 6 for "permanently disabled interrupt"
* - 6 for "permanently disabled interrupt", named INT_MUX_DISABLED_INTNO in the interrupt allocator
*/
// [TODO: IDF-2465]
const uint32_t rsvd_mask = BIT(1) | BIT(5) | BIT(6) | BIT(8);

8
components/esp_hw_support/port/esp32c5/esp_cpu_intr.c
View File

@ -12,9 +12,11 @@ void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_
/* On targets that uses CLIC as the interrupt controller, the first 16 lines (0..15) are reserved for software
* interrupts, all the other lines starting from 16 and above can be used by external peripheral.
*
* Only interrupt line 6 is reserved at the moment since it is used for disabling interrupts */
/* TODO: IDF-8655, we may need to reserve more interrupts once we have Wifi and BT */
* Reserve interrupt line 1 for the Wifi controller.
* Reserve interrupt line 6 since it is used for disabling interrupts in the interrupt allocator (INT_MUX_DISABLED_INTNO)
*/
const uint32_t rsvd_mask = BIT(1) | BIT(6);
intr_desc_ret->priority = 1;
intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;
intr_desc_ret->flags = (intr_num == 6) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0;
intr_desc_ret->flags = esp_riscv_intr_num_flags(intr_num, rsvd_mask);
}

6
components/esp_hw_support/port/esp32c6/esp_cpu_intr.c
View File

@ -11,14 +11,12 @@ void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_
{
/* On the ESP32-C6, interrupt:
* - 1 is for Wi-Fi
* - 5 and 8 for Bluetooth
* - 6 for "permanently disabled interrupt"
*
* Interrupts 0, 3, 4 and 7 are unavailable for PULP CPU.
* Interrupts 3, 4 and 7 are unavailable for PULP CPU as they are bound to Core-Local Interrupts (CLINT)
*/
// [TODO: IDF-2465]
const uint32_t rsvd_mask = BIT(0) | BIT(1) | BIT(3) | BIT(4) |
BIT(5) | BIT(6) | BIT(7) | BIT(8);
const uint32_t rsvd_mask = BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(7);
intr_desc_ret->priority = 1;
intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;

6
components/esp_hw_support/port/esp32h2/esp_cpu_intr.c
View File

@ -11,14 +11,12 @@ void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_
{
/* On the ESP32-H2, interrupt:
* - 1 is for Wi-Fi
* - 5 and 8 for Bluetooth
* - 6 for "permanently disabled interrupt"
*
* Interrupts 0, 3, 4 and 7 are unavailable for PULP CPU.
* Interrupts 3, 4 and 7 are unavailable for PULP CPU as they are bound to Core-Local Interrupts (CLINT)
*/
// [TODO: IDF-2465]
const uint32_t rsvd_mask = BIT(0) | BIT(1) | BIT(3) | BIT(4) |
BIT(5) | BIT(6) | BIT(7) | BIT(8);
const uint32_t rsvd_mask = BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(7);
intr_desc_ret->priority = 1;
intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;

7
components/esp_hw_support/port/esp32p4/esp_cpu_intr.c
View File

@ -12,8 +12,11 @@ void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_
/* On targets that uses CLIC as the interrupt controller, the first 16 lines (0..15) are reserved for software
* interrupts, all the other lines starting from 16 and above can be used by external peripheral.
*
* Only interrupt line 6 is reserved at the moment since it is used for disabling interrupts */
* Only interrupt line 6 is reserved at the moment since it is used for disabling interrupts in the
* interrupt allocator (INT_MUX_DISABLED_INTNO) */
const uint32_t rsvd_mask = BIT(6);
intr_desc_ret->priority = 1;
intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;
intr_desc_ret->flags = (intr_num == 6) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0;
intr_desc_ret->flags = esp_riscv_intr_num_flags(intr_num, rsvd_mask);
}

21
components/esp_hw_support/port/esp32s2/esp_cpu_intr.c
View File

@ -23,25 +23,28 @@ typedef struct {
const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = {
/* Interrupt 0 reserved for WMAC (Wifi) */
[0] = { 1, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD },
[1] = { 1, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD },
[1] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 },
[2] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 },
[3] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 },
/* Interrupt 4 reserved for WBB */
[4] = { 1, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD },
[5] = { 1, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD },
[5] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 },
#if CONFIG_FREERTOS_CORETIMER_0
[6] = { 1, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_RESVD },
#else
[6] = { 1, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL },
#endif
[7] = { 1, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL },
[8] = { 1, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD },
[8] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 },
[9] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 },
[10] = { 1, ESP_CPU_INTR_TYPE_EDGE, 0 },
[11] = { 3, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL },
[12] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 },
[13] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 },
[14] = { 7, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD }, // NMI
/* Interrupt 14 reserved for NMI (Non-Maskable Interrupts) */
[14] = { 7, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD },
#if CONFIG_FREERTOS_CORETIMER_1
[15] = { 3, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_RESVD },
#else
@ -53,16 +56,18 @@ const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = {
[19] = { 2, ESP_CPU_INTR_TYPE_LEVEL, 0 },
[20] = { 2, ESP_CPU_INTR_TYPE_LEVEL, 0 },
[21] = { 2, ESP_CPU_INTR_TYPE_LEVEL, 0 },
[22] = { 3, ESP_CPU_INTR_TYPE_EDGE, ESP_CPU_INTR_DESC_FLAG_RESVD },
[22] = { 3, ESP_CPU_INTR_TYPE_EDGE, 0 },
[23] = { 3, ESP_CPU_INTR_TYPE_LEVEL, 0 },
/* Interrupt 24 reserved for T1 WDT */
[24] = { 4, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD },
/* Interrupt 25 reserved for memory access errors */
[25] = { 4, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD },
[26] = { 5, ESP_CPU_INTR_TYPE_LEVEL, 0 },
[27] = { 3, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD },
[27] = { 3, ESP_CPU_INTR_TYPE_LEVEL, 0 },
[28] = { 4, ESP_CPU_INTR_TYPE_EDGE, 0 },
[29] = { 3, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL },
[30] = { 4, ESP_CPU_INTR_TYPE_EDGE, ESP_CPU_INTR_DESC_FLAG_RESVD },
[31] = { 5, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD },
[30] = { 4, ESP_CPU_INTR_TYPE_EDGE, 0 },
[31] = { 5, ESP_CPU_INTR_TYPE_LEVEL, 0 },
};

63
components/esp_hw_support/port/esp32s3/esp_cpu_intr.c
View File

@ -7,8 +7,8 @@
#include "sdkconfig.h"
#include "esp_cpu.h"
/* The ESP32-S3 uses the SysTimer for the FreeRTOS system tick, there is no need to Xtensa core interrupts,
* which will be marked as ESP_CPU_INTR_DESC_FLAG_SPECIAL */
/* The ESP32-S3 uses the SysTimer for the FreeRTOS system tick, there is no need to use Xtensa core timer interrupts,
* marked as ESP_CPU_INTR_DESC_FLAG_SPECIAL in the table below */
/**
* @brief Type defined for the table below
@ -20,21 +20,55 @@ typedef struct {
} intr_desc_t;
/**
* @brief Reserve the interrupts on the core where Bluetooth will run.
* The macro CONFIG_BT_CTRL_PINNED_TO_CORE is only defined if Bluetooth controller is enabled.
* It is set to the core where it will run.
*/
#ifdef CONFIG_BT_CTRL_PINNED_TO_CORE
#if CONFIG_BT_CTRL_PINNED_TO_CORE == 0
#define CORE_0_INTERRUPT_5 ESP_CPU_INTR_DESC_FLAG_RESVD
#define CORE_1_INTERRUPT_5 0
#define CORE_0_INTERRUPT_8 ESP_CPU_INTR_DESC_FLAG_RESVD
#define CORE_1_INTERRUPT_8 0
#elif CONFIG_BT_CTRL_PINNED_TO_CORE == 1
#define CORE_0_INTERRUPT_5 0
#define CORE_1_INTERRUPT_5 ESP_CPU_INTR_DESC_FLAG_RESVD
#define CORE_0_INTERRUPT_8 0
#define CORE_1_INTERRUPT_8 ESP_CPU_INTR_DESC_FLAG_RESVD
#endif
#else // Bluetooth not enabled
#define CORE_0_INTERRUPT_5 0
#define CORE_1_INTERRUPT_5 0
#define CORE_0_INTERRUPT_8 0
#define CORE_1_INTERRUPT_8 0
#endif
const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = {
[0] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
[1] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
/* Interrupt 0 reserved for WMAC (Wifi) */
#if CONFIG_ESP_WIFI_TASK_PINNED_TO_CORE_0
[0] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } },
#else
[0] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, ESP_CPU_INTR_DESC_FLAG_RESVD } },
#endif
[1] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
[2] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
[3] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
/* Interrupt 4 reserved for WBB */
[4] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } },
[5] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
/* Interrupt 5 reserved for BT/BLE Controller */
[5] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_5, CORE_1_INTERRUPT_5 } },
[6] = { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
[7] = { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
[8] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
/* Interrupt 8 reserved for BT/BLE Controller */
[8] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_8, CORE_1_INTERRUPT_8 } },
[9] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
[10] = { 1, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } },
[11] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
[12] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
[13] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
/* Interrupt 14 reserved for NMI (Non-Maskable Interrupts) */
[14] = { 7, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, // NMI
[15] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
[16] = { 5, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
@ -43,16 +77,19 @@ const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = {
[19] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
[20] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
[21] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
[22] = { 3, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } },
[22] = { 3, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } },
[23] = { 3, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
[24] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } },
/* Interrupt 24 reserved for T1 WDT */
[24] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
/* Interrupt 25 reserved for memory access and cache errors */
[25] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
[26] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { 0, ESP_CPU_INTR_DESC_FLAG_RESVD } },
[27] = { 3, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
[28] = { 4, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } },
[26] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
[27] = { 3, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
/* Interrupt 28 reserved for IPC */
[28] = { 4, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
[29] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } },
[30] = { 4, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
[31] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } },
[30] = { 4, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } },
[31] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } },
};

91
components/soc/esp32/include/soc/soc.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -219,51 +219,12 @@
// Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x3ffe3f20
#if CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5
//interrupt cpu using table, Please see the core-isa.h
/*************************************************************************************************************
* Intr num Level Type PRO CPU usage APP CPU uasge
* 0 1 extern level WMAC Reserved
* 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA
* 2 1 extern level
* 3 1 extern level
* 4 1 extern level WBB
* 5 1 extern level
* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
* 7 1 software BT/BLE VHCI BT/BLE VHCI
* 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX)
* 9 1 extern level
* 10 1 extern edge
* 11 3 profiling
* 12 1 extern level
* 13 1 extern level
* 14 7 nmi Reserved Reserved
* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3)
* 16 5 timer Reserved Reserved
* 17 1 extern level
* 18 1 extern level
* 19 2 extern level
* 20 2 extern level
* 21 2 extern level
* 22 3 extern edge
* 23 3 extern level
* 24 4 extern level
* 25 4 extern level BT/BLE Controller BT/BLE Controller
* 26 5 extern level TG1_WDT & CACHEERR
* 27 3 extern level Reserved Reserved
* 28 4 extern edge
* 29 3 software BT/BLE hli BT/BLE hli
* 30 4 extern edge Reserved Reserved
* 31 5 extern level IPC_ISR IPC_ISR
*************************************************************************************************************
*/
//CPU0 Interrupt number reserved, not touch this.
#define ETS_WMAC_INUM 0
#define ETS_BT_HOST_INUM 1
#define ETS_WBB_INUM 4
#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
#define ETS_FRC1_INUM 22
#if CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5
#define ETS_T1_WDT_CACHEERR_INUM 26
#define ETS_T1_WDT_INUM ETS_T1_WDT_CACHEERR_INUM
#define ETS_MEMACCESS_ERR_INUM ETS_T1_WDT_CACHEERR_INUM
@ -273,50 +234,6 @@
#elif CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4
//interrupt cpu using table, Please see the core-isa.h
/*************************************************************************************************************
* Intr num Level Type PRO CPU usage APP CPU uasge
* 0 1 extern level WMAC Reserved
* 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA
* 2 1 extern level
* 3 1 extern level
* 4 1 extern level WBB
* 5 1 extern level BT/BLE Controller BT/BLE Controller
* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
* 7 1 software BT/BLE VHCI BT/BLE VHCI
* 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX)
* 9 1 extern level
* 10 1 extern edge
* 11 3 profiling
* 12 1 extern level
* 13 1 extern level
* 14 7 nmi Reserved Reserved
* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3)
* 16 5 timer
* 17 1 extern level
* 18 1 extern level
* 19 2 extern level
* 20 2 extern level
* 21 2 extern level
* 22 3 extern edge
* 23 3 extern level
* 24 4 extern level TG1_WDT
* 25 4 extern level CACHEERR
* 26 5 extern level
* 27 3 extern level Reserved Reserved
* 28 4 extern edge IPC_ISR IPC_ISR
* 29 3 software Reserved Reserved
* 30 4 extern edge Reserved Reserved
* 31 5 extern level
*************************************************************************************************************
*/
//CPU0 Interrupt number reserved, not touch this.
#define ETS_WMAC_INUM 0
#define ETS_BT_HOST_INUM 1
#define ETS_WBB_INUM 4
#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
#define ETS_FRC1_INUM 22
#define ETS_T1_WDT_INUM 24
#define ETS_MEMACCESS_ERR_INUM 25
/* backwards compatibility only, use ETS_MEMACCESS_ERR_INUM instead*/

44
components/soc/esp32s2/include/soc/soc.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -207,50 +207,8 @@
// Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x3fffe70c
//interrupt cpu using table, Please see the core-isa.h
/*************************************************************************************************************
* Intr num Level Type PRO CPU usage
* 0 1 extern level WMAC
* 1 1 extern level BT/BLE Host HCI DMA
* 2 1 extern level
* 3 1 extern level
* 4 1 extern level WBB
* 5 1 extern level BT/BLE Controller
* 6 1 timer FreeRTOS Tick(L1)
* 7 1 software BT/BLE VHCI
* 8 1 extern level BT/BLE BB(RX/TX)
* 9 1 extern level
* 10 1 extern edge
* 11 3 profiling
* 12 1 extern level
* 13 1 extern level
* 14 7 nmi Reserved
* 15 3 timer FreeRTOS Tick(L3)
* 16 5 timer
* 17 1 extern level
* 18 1 extern level
* 19 2 extern level
* 20 2 extern level
* 21 2 extern level
* 22 3 extern edge
* 23 3 extern level
* 24 4 extern level TG1_WDT
* 25 4 extern level CACHEERR
* 26 5 extern level
* 27 3 extern level Reserved
* 28 4 extern edge Reserved
* 29 3 software Reserved
* 30 4 extern edge Reserved
* 31 5 extern level
*************************************************************************************************************
*/
//CPU0 Interrupt number reserved, not touch this.
#define ETS_WMAC_INUM 0
#define ETS_BT_HOST_INUM 1
#define ETS_WBB_INUM 4
#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
#define ETS_FRC1_INUM 22
#define ETS_T1_WDT_INUM 24
#define ETS_MEMACCESS_ERR_INUM 25

44
components/soc/esp32s3/include/soc/soc.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -224,50 +224,8 @@
#define SOC_ROM_STACK_START 0x3fceb710
#define SOC_ROM_STACK_SIZE 0x2000
//interrupt cpu using table, Please see the core-isa.h
/*************************************************************************************************************
* Intr num Level Type PRO CPU usage APP CPU uasge
* 0 1 extern level WMAC Reserved
* 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA
* 2 1 extern level
* 3 1 extern level
* 4 1 extern level WBB
* 5 1 extern level BT/BLE Controller BT/BLE Controller
* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
* 7 1 software BT/BLE VHCI BT/BLE VHCI
* 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX)
* 9 1 extern level
* 10 1 extern edge
* 11 3 profiling
* 12 1 extern level
* 13 1 extern level
* 14 7 nmi Reserved Reserved
* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3)
* 16 5 timer
* 17 1 extern level
* 18 1 extern level
* 19 2 extern level
* 20 2 extern level
* 21 2 extern level
* 22 3 extern edge
* 23 3 extern level
* 24 4 extern level TG1_WDT
* 25 4 extern level CACHEERR
* 26 5 extern level
* 27 3 extern level Reserved Reserved
* 28 4 extern edge IPC_ISR IPC_ISR
* 29 3 software Reserved Reserved
* 30 4 extern edge Reserved Reserved
* 31 5 extern level
*************************************************************************************************************
*/
//CPU0 Interrupt number reserved, not touch this.
#define ETS_WMAC_INUM 0
#define ETS_BT_HOST_INUM 1
#define ETS_WBB_INUM 4
#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
#define ETS_FRC1_INUM 22
#define ETS_T1_WDT_INUM 24
#define ETS_MEMACCESS_ERR_INUM 25
#define ETS_CACHEERR_INUM ETS_MEMACCESS_ERR_INUM

92
tools/test_apps/system/esp_intr_dump/expected_output/esp32.txt
View File

@ -1,48 +1,14 @@
CPU 0 interrupt status:
Int Level Type Status
0 1 Level Reserved
1 1 Level Reserved
2 1 Level Used: RTC_CORE
3 1 Level Used: FROM_CPU0
1 1 Level Used: RTC_CORE
2 1 Level Used: FROM_CPU0
3 1 Level Used: TG0_WDT_LEVEL
4 1 Level Reserved
5 1 Level Reserved
5 1 Level Used: UART0
6 1 Level Reserved
7 1 Level CPU-internal
8 1 Level Reserved
9 1 Level Used: TG0_WDT_LEVEL
10 1 Edge Free (not general-use)
11 3 Level CPU-internal
12 1 Level Used: UART0
13 1 Level Free
14 7 Level Reserved
15 3 Level CPU-internal
16 5 Level CPU-internal
17 1 Level Free
18 1 Level Free
19 2 Level Free
20 2 Level Free
21 2 Level Free
22 3 Edge Reserved
23 3 Level Free
24 4 Level Reserved
25 4 Level Reserved
26 5 Level Free (not general-use)
27 3 Level Reserved
28 4 Edge Free (not general-use)
29 3 Level CPU-internal
30 4 Edge Reserved
31 5 Level Reserved
CPU 1 interrupt status:
Int Level Type Status
0 1 Level Reserved
1 1 Level Reserved
2 1 Level Used: FROM_CPU1
3 1 Level Free
4 1 Level Free
5 1 Level Reserved
6 1 Level Reserved
7 1 Level CPU-internal
8 1 Level Reserved
8 1 Level Free
9 1 Level Free
10 1 Edge Free (not general-use)
11 3 Level CPU-internal
@ -58,13 +24,47 @@ CPU 1 interrupt status:
21 2 Level Free
22 3 Edge Free (not general-use)
23 3 Level Free
24 4 Level Free (not general-use)
24 4 Level Reserved
25 4 Level Reserved
26 5 Level Reserved
27 3 Level Reserved
28 4 Edge Free (not general-use)
26 5 Level Free (not general-use)
27 3 Level Free
28 4 Edge Reserved
29 3 Level CPU-internal
30 4 Edge Reserved
31 5 Level Reserved
Interrupts available for general use: 18
30 4 Edge Free (not general-use)
31 5 Level Free (not general-use)
CPU 1 interrupt status:
Int Level Type Status
0 1 Level Reserved
1 1 Level Used: FROM_CPU1
2 1 Level Free
3 1 Level Free
4 1 Level Free
5 1 Level Free
6 1 Level Reserved
7 1 Level CPU-internal
8 1 Level Free
9 1 Level Free
10 1 Edge Free (not general-use)
11 3 Level CPU-internal
12 1 Level Free
13 1 Level Free
14 7 Level Reserved
15 3 Level CPU-internal
16 5 Level CPU-internal
17 1 Level Free
18 1 Level Free
19 2 Level Free
20 2 Level Free
21 2 Level Free
22 3 Edge Free (not general-use)
23 3 Level Free
24 4 Level Reserved
25 4 Level Reserved
26 5 Level Free (not general-use)
27 3 Level Free
28 4 Edge Reserved
29 3 Level CPU-internal
30 4 Edge Free (not general-use)
31 5 Level Free (not general-use)
Interrupts available for general use: 26
Shared interrupts: 0

10
tools/test_apps/system/esp_intr_dump/expected_output/esp32c2.txt
View File

@ -5,11 +5,11 @@ CPU 0 interrupt status:
2 1 Level Used: RTC_CORE
3 1 Level Used: SYSTIMER_TARGET2_EDGE
4 1 Level Used: ETS_FROM_CPU_INTR0
5 * * Reserved
5 1 Level Used: SYSTIMER_TARGET0_EDGE
6 * * Reserved
7 1 Level Used: SYSTIMER_TARGET0_EDGE
8 * * Reserved
9 1 Level Used: UART
7 1 Level Used: UART
8 * * Free
9 * * Free
10 * * Free
11 * * Free
12 * * Free
@ -32,5 +32,5 @@ CPU 0 interrupt status:
29 * * Free
30 * * Free
31 * * Free
Interrupts available for general use: 19
Interrupts available for general use: 21
Shared interrupts: 0

14
tools/test_apps/system/esp_intr_dump/expected_output/esp32c6.txt
View File

@ -5,14 +5,14 @@ CPU 0 interrupt status:
2 1 Level Used: LP_RTC_TIMER
3 * * Reserved
4 * * Reserved
5 * * Reserved
5 1 Level Used: CPU_FROM_CPU_0
6 * * Reserved
7 * * Reserved
8 * * Reserved
9 1 Level Used: CPU_FROM_CPU_0
10 1 Level Used: SYSTIMER_TARGET0
11 1 Level Used: TG0_WDT
12 1 Level Used: UART0
8 1 Level Used: SYSTIMER_TARGET0
9 1 Level Used: TG0_WDT
10 1 Level Used: UART0
11 * * Free
12 * * Free
13 * * Free
14 * * Free
15 * * Free
@ -32,5 +32,5 @@ CPU 0 interrupt status:
29 * * Free
30 * * Free
31 * * Free
Interrupts available for general use: 16
Interrupts available for general use: 18
Shared interrupts: 0

14
tools/test_apps/system/esp_intr_dump/expected_output/esp32h2.txt
View File

@ -5,14 +5,14 @@ CPU 0 interrupt status:
2 1 Level Used: LP_RTC_TIMER
3 * * Reserved
4 * * Reserved
5 * * Reserved
5 1 Level Used: CPUFROM_CPU_0
6 * * Reserved
7 * * Reserved
8 * * Reserved
9 1 Level Used: CPUFROM_CPU_0
10 1 Level Used: SYSTIMER_TARGET0
11 1 Level Used: TG0_WDT
12 1 Level Used: UART0
8 1 Level Used: SYSTIMER_TARGET0
9 1 Level Used: TG0_WDT
10 1 Level Used: UART0
11 * * Free
12 * * Free
13 * * Free
14 * * Free
15 * * Free
@ -32,5 +32,5 @@ CPU 0 interrupt status:
29 * * Free
30 * * Free
31 * * Free
Interrupts available for general use: 16
Interrupts available for general use: 18
Shared interrupts: 0

18
tools/test_apps/system/esp_intr_dump/expected_output/esp32p4.txt
View File

@ -24,11 +24,11 @@ CPU 0 interrupt status:
21 * * Free
22 * * Free
23 * * Free
24 * * Free
25 * * Free
24 * * Reserved
25 * * Reserved
26 * * Free
27 * * Free
28 * * Free
27 * * Reserved
28 * * Reserved
29 * * Free
30 * * Free
31 * * Free
@ -58,12 +58,12 @@ CPU 1 interrupt status:
21 * * Free
22 * * Free
23 * * Free
24 * * Free
25 * * Free
24 * * Reserved
25 * * Reserved
26 * * Free
27 * * Free
28 * * Free
27 * * Reserved
28 * * Reserved
29 * * Free
30 * * Free
31 * * Free
Interrupts available for general use: 56
Interrupts available for general use: 48

24
tools/test_apps/system/esp_intr_dump/expected_output/esp32s2.txt
View File

@ -1,18 +1,18 @@
CPU 0 interrupt status:
Int Level Type Status
0 1 Level Reserved
1 1 Level Reserved
2 1 Level Used: RTC_CORE
3 1 Level Used: FROM_CPU_INTR0
1 1 Level Used: RTC_CORE
2 1 Level Used: FROM_CPU_INTR0
3 1 Level Used: TG0_WDT_LEVEL
4 1 Level Reserved
5 1 Level Reserved
5 1 Level Used: UART0
6 1 Level Reserved
7 1 Level CPU-internal
8 1 Level Reserved
9 1 Level Used: TG0_WDT_LEVEL
8 1 Level Free
9 1 Level Free
10 1 Edge Free (not general-use)
11 3 Level CPU-internal
12 1 Level Used: UART0
12 1 Level Free
13 1 Level Free
14 7 Level Reserved
15 3 Level CPU-internal
@ -22,15 +22,15 @@ CPU 0 interrupt status:
19 2 Level Free
20 2 Level Free
21 2 Level Free
22 3 Edge Reserved
22 3 Edge Free (not general-use)
23 3 Level Free
24 4 Level Reserved
25 4 Level Reserved
26 5 Level Free (not general-use)
27 3 Level Reserved
27 3 Level Free
28 4 Edge Free (not general-use)
29 3 Level CPU-internal
30 4 Edge Reserved
31 5 Level Reserved
Interrupts available for general use: 7
30 4 Edge Free (not general-use)
31 5 Level Free (not general-use)
Interrupts available for general use: 11
Shared interrupts: 0

94
tools/test_apps/system/esp_intr_dump/expected_output/esp32s3.txt
View File

@ -1,48 +1,14 @@
CPU 0 interrupt status:
Int Level Type Status
0 1 Level Reserved
1 1 Level Reserved
2 1 Level Used: RTC_CORE
3 1 Level Used: FROM_CPU_INTR0
0 1 Level Used: RTC_CORE
1 1 Level Used: FROM_CPU_INTR0
2 1 Level Used: SYSTIMER_TARGET0
3 1 Level Used: TG0_WDT_LEVEL
4 1 Level Reserved
5 1 Level Reserved
5 1 Level Used: UART0
6 1 Level CPU-internal
7 1 Level CPU-internal
8 1 Level Reserved
9 1 Level Used: SYSTIMER_TARGET0
10 1 Edge Free (not general-use)
11 3 Level CPU-internal
12 1 Level Used: TG0_WDT_LEVEL
13 1 Level Used: UART0
14 7 Level Reserved
15 3 Level CPU-internal
16 5 Level CPU-internal
17 1 Level Free
18 1 Level Free
19 2 Level Free
20 2 Level Free
21 2 Level Free
22 3 Edge Reserved
23 3 Level Free
24 4 Level Reserved
25 4 Level Reserved
26 5 Level Free (not general-use)
27 3 Level Reserved
28 4 Edge Free (not general-use)
29 3 Level CPU-internal
30 4 Edge Reserved
31 5 Level Reserved
CPU 1 interrupt status:
Int Level Type Status
0 1 Level Reserved
1 1 Level Reserved
2 1 Level Used: FROM_CPU_INTR1
3 1 Level Used: SYSTIMER_TARGET1
4 1 Level Free
5 1 Level Reserved
6 1 Level CPU-internal
7 1 Level CPU-internal
8 1 Level Reserved
8 1 Level Free
9 1 Level Free
10 1 Edge Free (not general-use)
11 3 Level CPU-internal
@ -58,13 +24,47 @@ CPU 1 interrupt status:
21 2 Level Free
22 3 Edge Free (not general-use)
23 3 Level Free
24 4 Level Free (not general-use)
24 4 Level Reserved
25 4 Level Reserved
26 5 Level Reserved
27 3 Level Reserved
28 4 Edge Free (not general-use)
26 5 Level Free (not general-use)
27 3 Level Free
28 4 Edge Reserved
29 3 Level CPU-internal
30 4 Edge Reserved
31 5 Level Reserved
Interrupts available for general use: 16
30 4 Edge Free (not general-use)
31 5 Level Free (not general-use)
CPU 1 interrupt status:
Int Level Type Status
0 1 Level Reserved
1 1 Level Used: FROM_CPU_INTR1
2 1 Level Used: SYSTIMER_TARGET1
3 1 Level Free
4 1 Level Free
5 1 Level Free
6 1 Level CPU-internal
7 1 Level CPU-internal
8 1 Level Free
9 1 Level Free
10 1 Edge Free (not general-use)
11 3 Level CPU-internal
12 1 Level Free
13 1 Level Free
14 7 Level Reserved
15 3 Level CPU-internal
16 5 Level CPU-internal
17 1 Level Free
18 1 Level Free
19 2 Level Free
20 2 Level Free
21 2 Level Free
22 3 Edge Free (not general-use)
23 3 Level Free
24 4 Level Reserved
25 4 Level Reserved
26 5 Level Free (not general-use)
27 3 Level Free
28 4 Edge Reserved
29 3 Level CPU-internal
30 4 Edge Free (not general-use)
31 5 Level Free (not general-use)
Interrupts available for general use: 25
Shared interrupts: 0