diff --git a/.codespellrc b/.codespellrc
index 42f363c725..c9cdd4c7cd 100644
--- a/.codespellrc
+++ b/.codespellrc
@@ -1,4 +1,4 @@
 [codespell]
 skip = build,*.yuv,components/fatfs/src/*,alice.txt,*.rgb
-ignore-words-list = ser,dout,rsource,fram,inout,shs,ans,aci,unstall,unstalling
+ignore-words-list = ser,dout,rsource,fram,inout,shs,ans,aci,unstall,unstalling,hart
 write-changes = true
diff --git a/components/riscv/include/riscv/csr.h b/components/riscv/include/riscv/csr.h
index 833a32b72f..580aa46ccc 100644
--- a/components/riscv/include/riscv/csr.h
+++ b/components/riscv/include/riscv/csr.h
@@ -78,7 +78,7 @@ extern "C" {
     do {                                                                           \
         ESP_STATIC_ASSERT(__builtin_popcount((SIZE)) == 1, "Size must be a power of 2"); \
         ESP_STATIC_ASSERT((ADDR) % ((SIZE)) == 0, "Addr must be aligned to size"); \
-        RV_WRITE_CSR((CSR_PMAADDR0) + (ENTRY), ((ADDR) | ((SIZE >> 1) - 1)) >> 2); \
+        RV_WRITE_CSR((CSR_PMAADDR0) + (ENTRY), ((ADDR) | (((SIZE) >> 1) - 1)) >> 2); \
         RV_WRITE_CSR((CSR_PMACFG0) + (ENTRY), CFG);                                \
     } while (0)
 
@@ -119,7 +119,7 @@ extern "C" {
      generate specific assembly instructions.
    - ADDR is the address to write to the PMPADDRx register. Note this is the unshifted address.
    - CFG is the configuration value to write to the correct CFG entry register. Note that
-     the macro only sets bits in the CFG register, so it sould be zeroed already.
+     the macro only sets bits in the CFG register, so it should be zeroed already.
 */
 #define PMP_ENTRY_SET(ENTRY, ADDR, CFG) do {  \
     RV_WRITE_CSR((CSR_PMPADDR0) + (ENTRY), (ADDR) >> (PMP_SHIFT));    \