diff --git a/components/hal/esp32s3/include/hal/clk_tree_ll.h b/components/hal/esp32s3/include/hal/clk_tree_ll.h index 9d042d0525..3e26d80e77 100644 --- a/components/hal/esp32s3/include/hal/clk_tree_ll.h +++ b/components/hal/esp32s3/include/hal/clk_tree_ll.h @@ -311,7 +311,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32 uint8_t dr3; uint8_t dchgp; uint8_t dcur; - uint8_t dbias; + uint8_t dbias = 3; if (pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) { /* Configure 480M PLL */ @@ -323,7 +323,6 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32 dr3 = 0; dchgp = 5; dcur = 3; - dbias = 2; break; case SOC_XTAL_FREQ_32M: div_ref = 1; @@ -332,7 +331,6 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32 dr3 = 1; dchgp = 4; dcur = 0; - dbias = 2; break; default: div_ref = 0; @@ -341,7 +339,6 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32 dr3 = 0; dchgp = 5; dcur = 3; - dbias = 2; break; } REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6B); @@ -355,7 +352,6 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32 dr3 = 0; dchgp = 5; dcur = 3; - dbias = 2; break; case SOC_XTAL_FREQ_32M: div_ref = 1; @@ -364,7 +360,6 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32 dr3 = 0; dchgp = 5; dcur = 3; - dbias = 2; break; default: div_ref = 0; @@ -373,7 +368,6 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32 dr3 = 0; dchgp = 5; dcur = 3; - dbias = 2; break; } REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69);