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feat(soc): Update efuse related soc_caps for c61 and c5 (MP/beta3)
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@ -288,7 +288,7 @@ esp_err_t esp_efuse_write_key(esp_efuse_block_t block, esp_efuse_purpose_t purpo
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purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 ||
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purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 ||
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purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 ||
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purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 ||
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#endif
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#endif
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#if SOC_ECDSA_SUPPORTED
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#if SOC_EFUSE_ECDSA_KEY
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purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
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purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
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#endif
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#endif
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purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY)) {
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purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY)) {
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@ -303,7 +303,7 @@ esp_err_t esp_efuse_write_key(esp_efuse_block_t block, esp_efuse_purpose_t purpo
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purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 ||
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purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 ||
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purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 ||
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purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 ||
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#endif //#ifdef SOC_EFUSE_SUPPORT_XTS_AES_256_KEYS
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#endif //#ifdef SOC_EFUSE_SUPPORT_XTS_AES_256_KEYS
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#if SOC_ECDSA_SUPPORTED
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#if SOC_EFUSE_ECDSA_KEY
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purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
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purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
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#endif
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#endif
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#if SOC_KEY_MANAGER_SUPPORTED
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#if SOC_KEY_MANAGER_SUPPORTED
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@ -1,5 +1,5 @@
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/*
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/*
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* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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@ -63,7 +63,7 @@ TEST_CASE("Test efuse API blocks burning XTS and ECDSA keys into BLOCK9", "[efus
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purpose = ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2;
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purpose = ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2;
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TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_efuse_write_key(EFUSE_BLK9, purpose, &key, sizeof(key)));
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TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_efuse_write_key(EFUSE_BLK9, purpose, &key, sizeof(key)));
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#endif
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#endif
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#if SOC_ECDSA_SUPPORTED
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#if SOC_EFUSE_ECDSA_KEY
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purpose = ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY;
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purpose = ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY;
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TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_efuse_write_key(EFUSE_BLK9, purpose, &key, sizeof(key)));
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TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_efuse_write_key(EFUSE_BLK9, purpose, &key, sizeof(key)));
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#endif
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#endif
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@ -90,7 +90,7 @@ static esp_err_t s_check_key(esp_efuse_block_t num_key, void* wr_key)
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purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 ||
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purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 ||
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purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 ||
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purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 ||
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#endif
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#endif
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#if SOC_ECDSA_SUPPORTED
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#if SOC_EFUSE_ECDSA_KEY
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purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
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purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
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#endif
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#endif
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purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL ||
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purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL ||
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@ -169,7 +169,7 @@ TEST_CASE("Test esp_efuse_write_key for virt mode", "[efuse]")
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purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 ||
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purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 ||
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purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 ||
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purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 ||
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#endif //#ifdef SOC_EFUSE_SUPPORT_XTS_AES_256_KEYS
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#endif //#ifdef SOC_EFUSE_SUPPORT_XTS_AES_256_KEYS
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#if SOC_ECDSA_SUPPORTED
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#if SOC_EFUSE_ECDSA_KEY
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purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
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purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
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#endif
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#endif
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purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY)) {
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purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY)) {
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@ -204,7 +204,7 @@ TEST_CASE("Test 1 esp_efuse_write_key for FPGA", "[efuse]")
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esp_efuse_purpose_t purpose [] = {
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esp_efuse_purpose_t purpose [] = {
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ESP_EFUSE_KEY_PURPOSE_USER,
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ESP_EFUSE_KEY_PURPOSE_USER,
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#if SOC_ECDSA_SUPPORTED
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#if SOC_EFUSE_ECDSA_KEY
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ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY,
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ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY,
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#else
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#else
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ESP_EFUSE_KEY_PURPOSE_RESERVED,
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ESP_EFUSE_KEY_PURPOSE_RESERVED,
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@ -47,7 +47,7 @@ IRAM_ATTR bool efuse_hal_flash_encryption_enabled(void)
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return enabled;
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return enabled;
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}
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}
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#if SOC_ECDSA_SUPPORTED
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#if SOC_EFUSE_ECDSA_KEY
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void efuse_hal_set_ecdsa_key(int efuse_blk)
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void efuse_hal_set_ecdsa_key(int efuse_blk)
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{
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{
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efuse_ll_set_ecdsa_key_blk(efuse_blk);
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efuse_ll_set_ecdsa_key_blk(efuse_blk);
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@ -84,6 +84,16 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(
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return (uint32_t)0;
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return (uint32_t)0;
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}
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}
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__attribute__((always_inline)) static inline uint32_t efuse_ll_get_ecdsa_key_blk(void)
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{
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return EFUSE0.conf.cfg_ecdsa_blk;
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}
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__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(int efuse_blk)
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{
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EFUSE0.conf.cfg_ecdsa_blk = efuse_blk;
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}
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/******************* eFuse control functions *************************/
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/******************* eFuse control functions *************************/
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__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void)
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__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void)
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@ -137,6 +147,11 @@ __attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint1
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EFUSE0.wr_tim_conf2.pwr_off_num = value;
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EFUSE0.wr_tim_conf2.pwr_off_num = value;
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}
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}
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__attribute__((always_inline)) static inline void efuse_ll_rs_bypass_update(void)
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{
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EFUSE0.wr_tim_conf0_rs_bypass.update = 1;
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}
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/******************* eFuse control functions *************************/
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/******************* eFuse control functions *************************/
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#ifdef __cplusplus
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#ifdef __cplusplus
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@ -61,7 +61,7 @@ uint32_t efuse_hal_get_major_chip_version(void);
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*/
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*/
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uint32_t efuse_hal_get_minor_chip_version(void);
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uint32_t efuse_hal_get_minor_chip_version(void);
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#if SOC_ECDSA_SUPPORTED
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#if SOC_EFUSE_ECDSA_KEY
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/**
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/**
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* @brief Set the efuse block that should be used as ECDSA private key
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* @brief Set the efuse block that should be used as ECDSA private key
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*
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*
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@ -571,6 +571,10 @@ config SOC_TIMER_GROUP_TOTAL_TIMERS
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int
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int
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default 2
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default 2
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config SOC_EFUSE_ECDSA_KEY
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bool
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default y
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config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
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config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
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int
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int
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default 3
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default 3
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@ -463,7 +463,7 @@
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// #define SOC_EFUSE_DIS_DIRECT_BOOT 1
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// #define SOC_EFUSE_DIS_DIRECT_BOOT 1
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// #define SOC_EFUSE_SOFT_DIS_JTAG 1
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// #define SOC_EFUSE_SOFT_DIS_JTAG 1
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// #define SOC_EFUSE_DIS_ICACHE 1
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// #define SOC_EFUSE_DIS_ICACHE 1
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// #define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES key purpose not supported for this block
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#define SOC_EFUSE_ECDSA_KEY 1
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/*-------------------------- Secure Boot CAPS----------------------------*/
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/*-------------------------- Secure Boot CAPS----------------------------*/
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// #define SOC_SECURE_BOOT_V2_RSA 1
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// #define SOC_SECURE_BOOT_V2_RSA 1
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@ -351,6 +351,10 @@ config SOC_TIMER_GROUP_TOTAL_TIMERS
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int
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int
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default 2
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default 2
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config SOC_EFUSE_ECDSA_KEY
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bool
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default y
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config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
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config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
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int
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int
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default 3
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default 3
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@ -458,7 +458,7 @@
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// #define SOC_EFUSE_DIS_DIRECT_BOOT 1
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// #define SOC_EFUSE_DIS_DIRECT_BOOT 1
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// #define SOC_EFUSE_SOFT_DIS_JTAG 1
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// #define SOC_EFUSE_SOFT_DIS_JTAG 1
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// #define SOC_EFUSE_DIS_ICACHE 1
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// #define SOC_EFUSE_DIS_ICACHE 1
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// #define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES key purpose not supported for this block
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#define SOC_EFUSE_ECDSA_KEY 1
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/*-------------------------- Secure Boot CAPS----------------------------*/
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/*-------------------------- Secure Boot CAPS----------------------------*/
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// #define SOC_SECURE_BOOT_V2_RSA 1
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// #define SOC_SECURE_BOOT_V2_RSA 1
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@ -795,7 +795,7 @@ config SOC_EFUSE_DIS_ICACHE
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bool
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bool
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default y
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default y
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config SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK
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config SOC_EFUSE_ECDSA_KEY
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bool
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bool
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default y
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default y
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@ -452,7 +452,7 @@
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#define SOC_EFUSE_DIS_DIRECT_BOOT 1
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#define SOC_EFUSE_DIS_DIRECT_BOOT 1
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#define SOC_EFUSE_SOFT_DIS_JTAG 0
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#define SOC_EFUSE_SOFT_DIS_JTAG 0
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#define SOC_EFUSE_DIS_ICACHE 1
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#define SOC_EFUSE_DIS_ICACHE 1
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#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES key purpose not supported for this block
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#define SOC_EFUSE_ECDSA_KEY 1
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/*-------------------------- Secure Boot CAPS----------------------------*/
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/*-------------------------- Secure Boot CAPS----------------------------*/
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#define SOC_SECURE_BOOT_V2_RSA 0
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#define SOC_SECURE_BOOT_V2_RSA 0
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@ -1171,6 +1171,10 @@ config SOC_EFUSE_ECDSA_USE_HARDWARE_K
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bool
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bool
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default y
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default y
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config SOC_EFUSE_ECDSA_KEY
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bool
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default y
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config SOC_SECURE_BOOT_V2_RSA
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config SOC_SECURE_BOOT_V2_RSA
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bool
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bool
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default y
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default y
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@ -458,6 +458,7 @@
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#define SOC_EFUSE_DIS_ICACHE 1
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#define SOC_EFUSE_DIS_ICACHE 1
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#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES and ECDSA key purposes not supported for this block
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#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES and ECDSA key purposes not supported for this block
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#define SOC_EFUSE_ECDSA_USE_HARDWARE_K 1 // Force use hardware TRNG supplied K for ECDSA
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#define SOC_EFUSE_ECDSA_USE_HARDWARE_K 1 // Force use hardware TRNG supplied K for ECDSA
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#define SOC_EFUSE_ECDSA_KEY 1
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/*-------------------------- Secure Boot CAPS----------------------------*/
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/*-------------------------- Secure Boot CAPS----------------------------*/
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#define SOC_SECURE_BOOT_V2_RSA 1
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#define SOC_SECURE_BOOT_V2_RSA 1
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@ -1423,6 +1423,10 @@ config SOC_EFUSE_DIS_DOWNLOAD_MSPI
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bool
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bool
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default y
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default y
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config SOC_EFUSE_ECDSA_KEY
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bool
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default y
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config SOC_SECURE_BOOT_V2_RSA
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config SOC_SECURE_BOOT_V2_RSA
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bool
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bool
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default y
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default y
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@ -562,6 +562,7 @@
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#define SOC_EFUSE_SOFT_DIS_JTAG 1
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#define SOC_EFUSE_SOFT_DIS_JTAG 1
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/* Capability to disable the MSPI access in download mode */
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/* Capability to disable the MSPI access in download mode */
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#define SOC_EFUSE_DIS_DOWNLOAD_MSPI 1
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#define SOC_EFUSE_DIS_DOWNLOAD_MSPI 1
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#define SOC_EFUSE_ECDSA_KEY 1
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/*-------------------------- Secure Boot CAPS----------------------------*/
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/*-------------------------- Secure Boot CAPS----------------------------*/
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#define SOC_SECURE_BOOT_V2_RSA 1
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#define SOC_SECURE_BOOT_V2_RSA 1
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