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feat(soc): Update efuse related soc_caps for c61 and c5 (MP/beta3)

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Konstantin Kondrashov 2024-05-08 15:17:02 +03:00 committed by Marius Vikhammer
parent 7e5ab45fbb
commit 14d93dea75
15 changed files with 46 additions and 13 deletions
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4
components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c
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@ -288,7 +288,7 @@ esp_err_t esp_efuse_write_key(esp_efuse_block_t block, esp_efuse_purpose_t purpo
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 ||
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 ||
#endif
#if SOC_ECDSA_SUPPORTED
#if SOC_EFUSE_ECDSA_KEY
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
#endif
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY)) {
@ -303,7 +303,7 @@ esp_err_t esp_efuse_write_key(esp_efuse_block_t block, esp_efuse_purpose_t purpo
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 ||
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 ||
#endif //#ifdef SOC_EFUSE_SUPPORT_XTS_AES_256_KEYS
#if SOC_ECDSA_SUPPORTED
#if SOC_EFUSE_ECDSA_KEY
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
#endif
#if SOC_KEY_MANAGER_SUPPORTED

10
components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -63,7 +63,7 @@ TEST_CASE("Test efuse API blocks burning XTS and ECDSA keys into BLOCK9", "[efus
purpose = ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2;
TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_efuse_write_key(EFUSE_BLK9, purpose, &key, sizeof(key)));
#endif
#if SOC_ECDSA_SUPPORTED
#if SOC_EFUSE_ECDSA_KEY
purpose = ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY;
TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_efuse_write_key(EFUSE_BLK9, purpose, &key, sizeof(key)));
#endif
@ -90,7 +90,7 @@ static esp_err_t s_check_key(esp_efuse_block_t num_key, void* wr_key)
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 ||
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 ||
#endif
#if SOC_ECDSA_SUPPORTED
#if SOC_EFUSE_ECDSA_KEY
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
#endif
purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL ||
@ -169,7 +169,7 @@ TEST_CASE("Test esp_efuse_write_key for virt mode", "[efuse]")
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 ||
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 ||
#endif //#ifdef SOC_EFUSE_SUPPORT_XTS_AES_256_KEYS
#if SOC_ECDSA_SUPPORTED
#if SOC_EFUSE_ECDSA_KEY
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
#endif
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY)) {
@ -204,7 +204,7 @@ TEST_CASE("Test 1 esp_efuse_write_key for FPGA", "[efuse]")
esp_efuse_purpose_t purpose [] = {
ESP_EFUSE_KEY_PURPOSE_USER,
#if SOC_ECDSA_SUPPORTED
#if SOC_EFUSE_ECDSA_KEY
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY,
#else
ESP_EFUSE_KEY_PURPOSE_RESERVED,

2
components/hal/efuse_hal.c
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@ -47,7 +47,7 @@ IRAM_ATTR bool efuse_hal_flash_encryption_enabled(void)
return enabled;
}
#if SOC_ECDSA_SUPPORTED
#if SOC_EFUSE_ECDSA_KEY
void efuse_hal_set_ecdsa_key(int efuse_blk)
{
efuse_ll_set_ecdsa_key_blk(efuse_blk);

15
components/hal/esp32c61/include/hal/efuse_ll.h
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@ -84,6 +84,16 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(
return (uint32_t)0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_ecdsa_key_blk(void)
{
return EFUSE0.conf.cfg_ecdsa_blk;
}
__attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(int efuse_blk)
{
EFUSE0.conf.cfg_ecdsa_blk = efuse_blk;
}
/******************* eFuse control functions *************************/
__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void)
@ -137,6 +147,11 @@ __attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint1
EFUSE0.wr_tim_conf2.pwr_off_num = value;
}
__attribute__((always_inline)) static inline void efuse_ll_rs_bypass_update(void)
{
EFUSE0.wr_tim_conf0_rs_bypass.update = 1;
}
/******************* eFuse control functions *************************/
#ifdef __cplusplus

2
components/hal/include/hal/efuse_hal.h
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@ -61,7 +61,7 @@ uint32_t efuse_hal_get_major_chip_version(void);
*/
uint32_t efuse_hal_get_minor_chip_version(void);
#if SOC_ECDSA_SUPPORTED
#if SOC_EFUSE_ECDSA_KEY
/**
* @brief Set the efuse block that should be used as ECDSA private key
*

4
components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in
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@ -571,6 +571,10 @@ config SOC_TIMER_GROUP_TOTAL_TIMERS
int
default 2
config SOC_EFUSE_ECDSA_KEY
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
int
default 3

2
components/soc/esp32c5/beta3/include/soc/soc_caps.h
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@ -463,7 +463,7 @@
// #define SOC_EFUSE_DIS_DIRECT_BOOT 1
// #define SOC_EFUSE_SOFT_DIS_JTAG 1
// #define SOC_EFUSE_DIS_ICACHE 1
// #define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES key purpose not supported for this block
#define SOC_EFUSE_ECDSA_KEY 1
/*-------------------------- Secure Boot CAPS----------------------------*/
// #define SOC_SECURE_BOOT_V2_RSA 1

4
components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
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@ -351,6 +351,10 @@ config SOC_TIMER_GROUP_TOTAL_TIMERS
int
default 2
config SOC_EFUSE_ECDSA_KEY
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
int
default 3

2
components/soc/esp32c5/mp/include/soc/soc_caps.h
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@ -458,7 +458,7 @@
// #define SOC_EFUSE_DIS_DIRECT_BOOT 1
// #define SOC_EFUSE_SOFT_DIS_JTAG 1
// #define SOC_EFUSE_DIS_ICACHE 1
// #define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES key purpose not supported for this block
#define SOC_EFUSE_ECDSA_KEY 1
/*-------------------------- Secure Boot CAPS----------------------------*/
// #define SOC_SECURE_BOOT_V2_RSA 1

2
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
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@ -795,7 +795,7 @@ config SOC_EFUSE_DIS_ICACHE
bool
default y
config SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK
config SOC_EFUSE_ECDSA_KEY
bool
default y

2
components/soc/esp32c61/include/soc/soc_caps.h
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@ -452,7 +452,7 @@
#define SOC_EFUSE_DIS_DIRECT_BOOT 1
#define SOC_EFUSE_SOFT_DIS_JTAG 0
#define SOC_EFUSE_DIS_ICACHE 1
#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES key purpose not supported for this block
#define SOC_EFUSE_ECDSA_KEY 1
/*-------------------------- Secure Boot CAPS----------------------------*/
#define SOC_SECURE_BOOT_V2_RSA 0

4
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
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@ -1171,6 +1171,10 @@ config SOC_EFUSE_ECDSA_USE_HARDWARE_K
bool
default y
config SOC_EFUSE_ECDSA_KEY
bool
default y
config SOC_SECURE_BOOT_V2_RSA
bool
default y

1
components/soc/esp32h2/include/soc/soc_caps.h
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@ -458,6 +458,7 @@
#define SOC_EFUSE_DIS_ICACHE 1
#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES and ECDSA key purposes not supported for this block
#define SOC_EFUSE_ECDSA_USE_HARDWARE_K 1 // Force use hardware TRNG supplied K for ECDSA
#define SOC_EFUSE_ECDSA_KEY 1
/*-------------------------- Secure Boot CAPS----------------------------*/
#define SOC_SECURE_BOOT_V2_RSA 1

4
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
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@ -1423,6 +1423,10 @@ config SOC_EFUSE_DIS_DOWNLOAD_MSPI
bool
default y
config SOC_EFUSE_ECDSA_KEY
bool
default y
config SOC_SECURE_BOOT_V2_RSA
bool
default y

1
components/soc/esp32p4/include/soc/soc_caps.h
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@ -562,6 +562,7 @@
#define SOC_EFUSE_SOFT_DIS_JTAG 1
/* Capability to disable the MSPI access in download mode */
#define SOC_EFUSE_DIS_DOWNLOAD_MSPI 1
#define SOC_EFUSE_ECDSA_KEY 1
/*-------------------------- Secure Boot CAPS----------------------------*/
#define SOC_SECURE_BOOT_V2_RSA 1